library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;

library UNISIM;
use UNISIM.vcomponents.all;


entity tmds_phy_artix7 is
    port (
        reset      : in  std_logic;
        pix_clk    : in  std_logic;
        phy_clk    : in  std_logic;
        din        : in  std_logic_vector(9 downto 0);
        b          : in  natural;
        tmds_out_p : out std_logic;
        tmds_out_n : out std_logic
        );
end tmds_phy_artix7;


architecture beh of tmds_phy_artix7 is

    signal ld : std_logic_vector(9 downto 0);
    signal sr : std_logic_vector(9 downto 0);

    signal s : std_logic;

begin


    process(pix_clk)
    begin
        if rising_edge(pix_clk) then
            ld <= din;
        end if;
    end process;


-- Using ODDR
--   process(phy_clk)
--   begin
--      if rising_edge(phy_clk) then 
--       if b=0 then
--              sr<= ld;
--         else
--            sr(7 downto 0) <= sr  (9 downto 2);
--         end if;
--      end if;
--   end process;
--
--ODDR_inst : ODDR
--generic map(
--   DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
--   INIT => '0',   -- Initial value for Q port ('1' or '0')
--   SRTYPE => "ASYNC") -- Reset Type ("ASYNC" or "SYNC")
--port map (
--   Q => s,   -- 1-bit DDR output
--   C => phy_clk,    -- 1-bit clock input
--   CE => '1',  -- 1-bit clock enable input
--   D1 => sr(0),  -- 1-bit data input (positive edge)
--   D2 => sr(1),  -- 1-bit data input (negative edge)
--   R => '0',    -- 1-bit reset input
--   S => '0'     -- 1-bit set input
--);


-- Using a shift register
    process(phy_clk)
    begin
        if rising_edge(phy_clk) then
            if b = 0 then
                sr <= ld;
            else
                sr(8 downto 0) <= sr (9 downto 1);
                s              <=sr(0);
            end if;
        end if;
    end process;



    od : OBUFDS port map (O => tmds_out_p, OB => tmds_out_n, I => s);

end beh;