library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;

entity tmds_output is
    port (
        sys_rst_n   : in std_logic;
        pclk_locked : in std_logic;
        pclk        : in std_logic;
        pclk_x2     : in std_logic;
        pclk_phy    : in std_logic;

        r_p10 : in std_logic_vector(9 downto 0);
        g_p10 : in std_logic_vector(9 downto 0);
        b_p10 : in std_logic_vector(9 downto 0);
        c_p10 : in std_logic_vector(9 downto 0);


        tmds_c_out_p : out std_logic;
        tmds_c_out_n : out std_logic;
        tmds_r_out_p : out std_logic;
        tmds_r_out_n : out std_logic;
        tmds_g_out_p : out std_logic;
        tmds_g_out_n : out std_logic;
        tmds_b_out_p : out std_logic;
        tmds_b_out_n : out std_logic
        );
end tmds_output;


architecture beh of tmds_output is

    signal b : natural := 0;

begin



    process (pclk_phy, b, sys_rst_n)
    begin
        if sys_rst_n = '0' then
            b <= 0;
        elsif rising_edge(pclk_phy) then
            if b = 4 then
                b <= 0;
            else
                b <= b+1;
            end if;
        end if;
    end process;


    phy_c : entity work.tmds_phy_cyclone4
        port map (
            sys_rst_n  => sys_rst_n,
            pclk_phy   => pclk_phy,
            b          => b,
            din        => c_p10,
            tmds_out_p => tmds_c_out_p,
            tmds_out_n => tmds_c_out_n
            );

    phy_r : entity work.tmds_phy_cyclone4
        port map (
            sys_rst_n  => sys_rst_n,
            pclk_phy   => pclk_phy,
            b          => b,
            din        => r_p10,
            tmds_out_p => tmds_r_out_p,
            tmds_out_n => tmds_r_out_n
            );


    phy_g : entity work.tmds_phy_cyclone4
        port map (
            sys_rst_n  => sys_rst_n,
            pclk_phy   => pclk_phy,
            b          => b,
            din        => g_p10,
            tmds_out_p => tmds_g_out_p,
            tmds_out_n => tmds_g_out_n
            );


    phy_b : entity work.tmds_phy_cyclone4
        port map (
            sys_rst_n  => sys_rst_n,
            pclk_phy   => pclk_phy,
            b          => b,
            din        => b_p10,
            tmds_out_p => tmds_b_out_p,
            tmds_out_n => tmds_b_out_n
            );

end beh;