library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;


entity tmds_encode is
    port (
        sys_rst_n : in std_logic;
        pclk      : in std_logic;

        r_in  : in std_logic_vector(7 downto 0);
        g_in  : in std_logic_vector(7 downto 0);
        b_in  : in std_logic_vector(7 downto 0);
        hsync : in std_logic;
        vsync : in std_logic;
        blank : in std_logic;


        r_p10 : out std_logic_vector(9 downto 0);
        g_p10 : out std_logic_vector(9 downto 0);
        b_p10 : out std_logic_vector(9 downto 0);
        c_p10 : out std_logic_vector(9 downto 0)

        );
end tmds_encode;


architecture beh of tmds_encode is
    signal ctrl : std_logic_vector(1 downto 0);

begin

    c_p10 <= "1111100000";

    ctrl <= vsync & hsync;


    enc_r : entity work.tmds_encoder
        port map (
            sys_rst_n => sys_rst_n,
            clk       => pclk,
            ctrl      => ctrl,
            blank     => blank,
            din       => r_in,
            dout      => r_p10
            );

    enc_g : entity work.tmds_encoder
        port map (
            sys_rst_n => sys_rst_n,
            clk       => pclk,
            ctrl      => "11",
            blank     => blank,
            din       => g_in,
            dout      => g_p10
            );



    enc_b : entity work.tmds_encoder
        port map (
            sys_rst_n => sys_rst_n,
            clk       => pclk,
            ctrl      => "11",
            blank     => blank,
            din       => b_in,
            dout      => b_p10
            );


end beh;