library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; use work.all; entity kbd_uarts is port ( s_axi_aclk : in std_logic; s_axi_aresetn : in std_logic; s_axi_arvalid : in std_logic; s_axi_awvalid : in std_logic; s_axi_bready : in std_logic; s_axi_rready : in std_logic; s_axi_wlast : in std_logic; s_axi_wvalid : in std_logic; s_axi_arid : in std_logic_vector (11 downto 0); s_axi_awid : in std_logic_vector (11 downto 0); s_axi_arburst : in std_logic_vector (1 downto 0); s_axi_arlock : in std_logic_vector (1 downto 0); s_axi_arsize : in std_logic_vector (2 downto 0); s_axi_awburst : in std_logic_vector (1 downto 0); s_axi_awlock : in std_logic_vector (1 downto 0); s_axi_awsize : in std_logic_vector (2 downto 0); s_axi_arprot : in std_logic_vector (2 downto 0); s_axi_awprot : in std_logic_vector (2 downto 0); s_axi_araddr : in std_logic_vector (31 downto 0); s_axi_awaddr : in std_logic_vector (31 downto 0); s_axi_wdata : in std_logic_vector (31 downto 0); s_axi_arcache : in std_logic_vector (3 downto 0); s_axi_arlen : in std_logic_vector (3 downto 0); s_axi_arqos : in std_logic_vector (3 downto 0); s_axi_awcache : in std_logic_vector (3 downto 0); s_axi_awlen : in std_logic_vector (3 downto 0); s_axi_awqos : in std_logic_vector (3 downto 0); s_axi_wstrb : in std_logic_vector (3 downto 0); s_axi_arready : out std_logic; s_axi_awready : out std_logic; s_axi_bvalid : out std_logic; s_axi_rlast : out std_logic; s_axi_rvalid : out std_logic; s_axi_wready : out std_logic; s_axi_bid : out std_logic_vector (11 downto 0); s_axi_rid : out std_logic_vector (11 downto 0); s_axi_bresp : out std_logic_vector (1 downto 0); s_axi_rresp : out std_logic_vector (1 downto 0); s_axi_rdata : out std_logic_vector (31 downto 0); u0_tx : out std_logic; u0_rx : in std_logic; u0_int : out std_logic; u1_tx : out std_logic; u1_rx : in std_logic; u1_int : out std_logic ); end kbd_uarts; architecture Behavioural of kbd_uarts is signal m_axi_awaddr : std_logic_vector (31 downto 0); signal m_axi_awprot : std_logic_vector (2 downto 0); signal m_axi_awvalid : std_logic; signal m_axi_awready : std_logic; signal m_axi_wdata : std_logic_vector (31 downto 0); signal m_axi_wstrb : std_logic_vector (3 downto 0); signal m_axi_wvalid : std_logic; signal m_axi_wready : std_logic; signal m_axi_bresp : std_logic_vector (1 downto 0); signal m_axi_bvalid : std_logic; signal m_axi_bready : std_logic; signal m_axi_araddr : std_logic_vector (31 downto 0); signal m_axi_arprot : std_logic_vector (2 downto 0); signal m_axi_arvalid : std_logic; signal m_axi_arready : std_logic; signal m_axi_rdata : std_logic_vector (31 downto 0); signal m_axi_rresp : std_logic_vector (1 downto 0); signal m_axi_rvalid : std_logic; signal m_axi_rready : std_logic; signal uc_axi_awaddr : std_logic_vector (63 downto 0); signal uc_axi_awprot : std_logic_vector (5 downto 0); signal uc_axi_awvalid : std_logic_vector (1 downto 0); signal uc_axi_awready : std_logic_vector (1 downto 0); signal uc_axi_wdata : std_logic_vector (63 downto 0); signal uc_axi_wstrb : std_logic_vector (7 downto 0); signal uc_axi_wvalid : std_logic_vector (1 downto 0); signal uc_axi_wready : std_logic_vector (1 downto 0); signal uc_axi_bresp : std_logic_vector (3 downto 0); signal uc_axi_bvalid : std_logic_vector (1 downto 0); signal uc_axi_bready : std_logic_vector (1 downto 0); signal uc_axi_araddr : std_logic_vector (63 downto 0); signal uc_axi_arprot : std_logic_vector (5 downto 0); signal uc_axi_arvalid : std_logic_vector (1 downto 0); signal uc_axi_arready : std_logic_vector (1 downto 0); signal uc_axi_rdata : std_logic_vector (63 downto 0); signal uc_axi_rresp : std_logic_vector (3 downto 0); signal uc_axi_rvalid : std_logic_vector (1 downto 0); signal uc_axi_rready : std_logic_vector (1 downto 0); begin axi_protocol_converter_0_i : entity work.axi_protocol_converter_0 port map ( aclk => s_axi_aclk, aresetn => s_axi_aresetn, s_axi_arvalid => s_axi_arvalid, s_axi_awvalid => s_axi_awvalid, s_axi_bready => s_axi_bready, s_axi_rready => s_axi_rready, s_axi_wlast => s_axi_wlast, s_axi_wvalid => s_axi_wvalid, s_axi_arid => s_axi_arid, s_axi_awid => s_axi_awid, s_axi_arburst => s_axi_arburst, s_axi_arlock => s_axi_arlock, s_axi_arsize => s_axi_arsize, s_axi_awburst => s_axi_awburst, s_axi_awlock => s_axi_awlock, s_axi_awsize => s_axi_awsize, s_axi_arprot => s_axi_arprot, s_axi_awprot => s_axi_awprot, s_axi_araddr => s_axi_araddr, s_axi_awaddr => s_axi_awaddr, s_axi_wdata => s_axi_wdata, s_axi_arcache => s_axi_arcache, s_axi_arlen => s_axi_arlen, s_axi_arqos => s_axi_arqos, s_axi_awcache => s_axi_awcache, s_axi_awlen => s_axi_awlen, s_axi_awqos => s_axi_awqos, s_axi_wstrb => s_axi_wstrb, s_axi_arready => s_axi_arready, s_axi_awready => s_axi_awready, s_axi_bvalid => s_axi_bvalid, s_axi_rlast => s_axi_rlast, s_axi_rvalid => s_axi_rvalid, s_axi_wready => s_axi_wready, s_axi_bid => s_axi_bid, s_axi_rid => s_axi_rid, s_axi_bresp => s_axi_bresp, s_axi_rresp => s_axi_rresp, s_axi_rdata => s_axi_rdata, m_axi_awaddr => m_axi_awaddr, m_axi_awprot => m_axi_awprot, m_axi_awvalid => m_axi_awvalid, m_axi_awready => m_axi_awready, m_axi_wdata => m_axi_wdata, m_axi_wstrb => m_axi_wstrb, m_axi_wvalid => m_axi_wvalid, m_axi_wready => m_axi_wready, m_axi_bresp => m_axi_bresp, m_axi_bvalid => m_axi_bvalid, m_axi_bready => m_axi_bready, m_axi_araddr => m_axi_araddr, m_axi_arprot => m_axi_arprot, m_axi_arvalid => m_axi_arvalid, m_axi_arready => m_axi_arready, m_axi_rdata => m_axi_rdata, m_axi_rresp => m_axi_rresp, m_axi_rvalid => m_axi_rvalid, m_axi_rready => m_axi_rready ); axi_crossbar_0_i : entity work.axi_crossbar_0 port map ( aclk => s_axi_aclk, aresetn => s_axi_aresetn, s_axi_awaddr => m_axi_awaddr, s_axi_awprot => m_axi_awprot, s_axi_awvalid => m_axi_awvalid, s_axi_awready => m_axi_awready, s_axi_wdata => m_axi_wdata, s_axi_wstrb => m_axi_wstrb, s_axi_wvalid => m_axi_wvalid, s_axi_wready => m_axi_wready, s_axi_bresp => m_axi_bresp, s_axi_bvalid => m_axi_bvalid, s_axi_bready => m_axi_bready, s_axi_araddr => m_axi_araddr, s_axi_arprot => m_axi_arprot, s_axi_arvalid => m_axi_arvalid, s_axi_arready => m_axi_arready, s_axi_rdata => m_axi_rdata, s_axi_rresp => m_axi_rresp, s_axi_rvalid => m_axi_rvalid, s_axi_rready => m_axi_rready, m_axi_awaddr => uc_axi_awaddr, m_axi_awprot => uc_axi_awprot, m_axi_awvalid => uc_axi_awvalid, m_axi_awready => uc_axi_awready, m_axi_wdata => uc_axi_wdata, m_axi_wstrb => uc_axi_wstrb, m_axi_wvalid => uc_axi_wvalid, m_axi_wready => uc_axi_wready, m_axi_bresp => uc_axi_bresp, m_axi_bvalid => uc_axi_bvalid, m_axi_bready => uc_axi_bready, m_axi_araddr => uc_axi_araddr, m_axi_arprot => uc_axi_arprot, m_axi_arvalid => uc_axi_arvalid, m_axi_arready => uc_axi_arready, m_axi_rdata => uc_axi_rdata, m_axi_rresp => uc_axi_rresp, m_axi_rvalid => uc_axi_rvalid, m_axi_rready => uc_axi_rready ); -- JMM we dont gate the interrupt with out1 axi_uart16550_0_i0 : entity work.axi_uart16550_0 port map ( s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_awaddr => uc_axi_awaddr(12 downto 0), s_axi_awvalid => uc_axi_awvalid(0), s_axi_awready => uc_axi_awready(0), s_axi_wdata => uc_axi_wdata(31 downto 0), s_axi_wstrb => uc_axi_wstrb (3 downto 0), s_axi_wvalid => uc_axi_wvalid(0), s_axi_wready => uc_axi_wready(0), s_axi_bresp => uc_axi_bresp(1 downto 0), s_axi_bvalid => uc_axi_bvalid(0), s_axi_bready => uc_axi_bready(0), s_axi_araddr => uc_axi_araddr(12 downto 0), s_axi_arvalid => uc_axi_arvalid(0), s_axi_arready => uc_axi_arready(0), s_axi_rdata => uc_axi_rdata(31 downto 0), s_axi_rresp => uc_axi_rresp(1 downto 0), s_axi_rvalid => uc_axi_rvalid(0), s_axi_rready => uc_axi_rready(0), ip2intc_irpt => u0_int, freeze => '0', sin => u0_rx, sout => u0_tx, ctsn => '0', dcdn => '0', dsrn => '0', rin => '1' -- baudoutn : out STD_LOGIC; -- ctsn : in STD_LOGIC; -- dcdn : in STD_LOGIC; -- ddis : out STD_LOGIC; -- dsrn : in STD_LOGIC; -- dtrn : out STD_LOGIC; -- out1n : out STD_LOGIC; -- out2n : out STD_LOGIC; -- rin : in STD_LOGIC; -- rtsn : out STD_LOGIC; -- rxrdyn : out STD_LOGIC; -- txrdyn : out STD_LOGIC; ); axi_uart16550_0_i1 : entity work.axi_uart16550_0 port map ( s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_awaddr => uc_axi_awaddr(44 downto 32), s_axi_awvalid => uc_axi_awvalid(1), s_axi_awready => uc_axi_awready(1), s_axi_wdata => uc_axi_wdata(63 downto 32), s_axi_wstrb => uc_axi_wstrb (7 downto 4), s_axi_wvalid => uc_axi_wvalid(1), s_axi_wready => uc_axi_wready(1), s_axi_bresp => uc_axi_bresp(3 downto 2), s_axi_bvalid => uc_axi_bvalid(1), s_axi_bready => uc_axi_bready(1), s_axi_araddr => uc_axi_araddr(44 downto 32), s_axi_arvalid => uc_axi_arvalid(1), s_axi_arready => uc_axi_arready(1), s_axi_rdata => uc_axi_rdata(63 downto 32), s_axi_rresp => uc_axi_rresp(3 downto 2), s_axi_rvalid => uc_axi_rvalid(1), s_axi_rready => uc_axi_rready(1), ip2intc_irpt => u1_int, freeze => '0', sin => u1_rx, sout => u1_tx, ctsn => '0', dcdn => '0', dsrn => '0', rin => '1' -- baudoutn : out STD_LOGIC; -- ctsn : in STD_LOGIC; -- dcdn : in STD_LOGIC; -- ddis : out STD_LOGIC; -- dsrn : in STD_LOGIC; -- dtrn : out STD_LOGIC; -- out1n : out STD_LOGIC; -- out2n : out STD_LOGIC; -- rin : in STD_LOGIC; -- rtsn : out STD_LOGIC; -- rxrdyn : out STD_LOGIC; -- txrdyn : out STD_LOGIC; ); end Behavioural;