library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; use work.all; entity fb_ram is Port ( clka : in STD_LOGIC; ena : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 3 downto 0 ); addra : in STD_LOGIC_VECTOR ( 15 downto 0 ); dina : in STD_LOGIC_VECTOR ( 31 downto 0 ); douta : out STD_LOGIC_VECTOR ( 31 downto 0 ); clkb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 3 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 15 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 31 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 31 downto 0 ) ); end fb_ram; architecture Behavioural of fb_ram is type t_d is array (0 to 3) of std_logic_vector(2 downto 0); signal s_dina:t_d; signal s_dinb:t_d; signal s_douta:t_d; signal s_doutb:t_d; begin   g_fbram: for i in 0 to 3 generate s_dina(i)(2) <= dina((8*i)+7); s_dina(i)(1) <= dina((8*i)+4); s_dina(i)(0) <= dina((8*i)+1); douta((8*i)+7) <= s_douta(i)(2); douta((8*i)+6) <= s_douta(i)(2); douta((8*i)+5) <= s_douta(i)(2); douta((8*i)+4) <= s_douta(i)(1); douta((8*i)+3) <= s_douta(i)(1); douta((8*i)+2) <= s_douta(i)(1); douta((8*i)+1) <= s_douta(i)(0); douta((8*i)+0) <= s_douta(i)(0); s_dinb(i)(2) <= dinb((8*i)+7); s_dinb(i)(1) <= dinb((8*i)+4); s_dinb(i)(0) <= dinb((8*i)+1); doutb((8*i)+7) <= s_doutb(i)(2); doutb((8*i)+6) <= s_doutb(i)(2); doutb((8*i)+5) <= s_doutb(i)(2); doutb((8*i)+4) <= s_doutb(i)(1); doutb((8*i)+3) <= s_doutb(i)(1); doutb((8*i)+2) <= s_doutb(i)(1); doutb((8*i)+1) <= s_doutb(i)(0); doutb((8*i)+0) <= s_doutb(i)(0); fb_ram_i : entity work.blk_mem_gen_1 port map ( clka => clka, ena => ena, wea => wea(i), addra => addra, dina => s_dina(i), douta => s_douta(i), clkb => clkb, web => web(0), addrb => addrb, dinb => s_dinb(i), doutb => s_doutb(i) ); end generate; end Behavioural;