library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.all;

entity fb_hw is
    generic (
        addr_width : integer := 17
        );
    port (
        s_axi_aclk    : in  std_logic;
        s_axi_aresetn : in  std_logic;
        s_axi_awid    : in  std_logic_vector (11 downto 0);
        s_axi_awaddr  : in  std_logic_vector (31 downto 0);
        s_axi_awlen   : in  std_logic_vector (3 downto 0);
        s_axi_awsize  : in  std_logic_vector (2 downto 0);
        s_axi_awburst : in  std_logic_vector (1 downto 0);
        s_axi_awlock  : in  std_logic_vector(1 downto 0);
        s_axi_awcache : in  std_logic_vector (3 downto 0);
        s_axi_awprot  : in  std_logic_vector (2 downto 0);
        s_axi_awvalid : in  std_logic;
        s_axi_awready : out std_logic;
        s_axi_wdata   : in  std_logic_vector (31 downto 0);
        s_axi_wstrb   : in  std_logic_vector (3 downto 0);
        s_axi_wlast   : in  std_logic;
        s_axi_wvalid  : in  std_logic;
        s_axi_wready  : out std_logic;
        s_axi_bid     : out std_logic_vector (11 downto 0);
        s_axi_bresp   : out std_logic_vector (1 downto 0);
        s_axi_bvalid  : out std_logic;
        s_axi_bready  : in  std_logic;
        s_axi_arid    : in  std_logic_vector (11 downto 0);
        s_axi_araddr  : in  std_logic_vector (31 downto 0);
        s_axi_arlen   : in  std_logic_vector (3 downto 0);
        s_axi_arsize  : in  std_logic_vector (2 downto 0);
        s_axi_arburst : in  std_logic_vector (1 downto 0);
        s_axi_arlock  : in  std_logic_vector(1 downto 0);
        s_axi_arcache : in  std_logic_vector (3 downto 0);
        s_axi_arprot  : in  std_logic_vector (2 downto 0);
        s_axi_arvalid : in  std_logic;
        s_axi_arready : out std_logic;
        s_axi_rid     : out std_logic_vector (11 downto 0);
        s_axi_rdata   : out std_logic_vector (31 downto 0);
        s_axi_rresp   : out std_logic_vector (1 downto 0);
        s_axi_rlast   : out std_logic;
        s_axi_rvalid  : out std_logic;
        s_axi_rready  : in  std_logic;

        overlay_clk  : in  std_logic;
        overlay_addr : in  std_logic_vector(addr_width-1 downto 0);
        overlay_gate : out std_logic;
        overlay_r    : out std_logic_vector(7 downto 0);
        overlay_g    : out std_logic_vector(7 downto 0);
        overlay_b    : out std_logic_vector(7 downto 0)



        );
end fb_hw;
architecture Behavioural of fb_hw is


    type t_palette is array (0 to 15) of std_logic_vector(7 downto 0);
    constant r_lut : t_palette := (
        x"00", x"00", x"00", x"00", x"AA", x"AA", x"AA", x"AA",
        x"55", x"55", x"55", x"55", x"FF", x"FF", x"FF", x"FF"
        );
    constant g_lut : t_palette := (
        x"00", x"00", x"AA", x"AA", x"00", x"00", x"55", x"AA",
        x"55", x"55", x"FF", x"FF", x"55", x"55", x"FF", x"FF"
        );
    constant b_lut : t_palette := (
        x"00", x"AA", x"00", x"AA", x"00", x"AA", x"00", x"AA",
        x"55", x"FF", x"55", x"FF", x"55", x"FF", x"55", x"FF"
        );


    signal overlay_demux_p : integer;
    signal overlay_demux   : integer;
    signal overlay_data    : integer;


    signal fb_ps_clk    : std_logic;
    signal fb_ps_en     : std_logic;
    signal fb_ps_we     : std_logic_vector (3 downto 0);
    signal fb_ps_addr   : std_logic_vector (19 downto 0);
    signal fb_ps_wrdata : std_logic_vector (31 downto 0);
    signal fb_ps_rddata : std_logic_vector (31 downto 0);

    signal fb_pl_addr   : std_logic_vector (14 downto 0);
    signal fb_pl_rddata : std_logic_vector (31 downto 0);

begin

    fb_ram0 : entity work.blk_mem_gen_1
        port map (
            clka  => fb_ps_clk,
            ena   => fb_ps_en,
            wea   => fb_ps_we,
            addra => fb_ps_addr (16 downto 2),
            dina  => fb_ps_wrdata,
            douta => fb_ps_rddata,
            clkb  => overlay_clk,
            web   => "0000",
            addrb => fb_pl_addr,
            dinb  => x"00000000",
            doutb => fb_pl_rddata
            );



    fb_pl_addr <= overlay_addr(17 downto 3);

    process (overlay_clk)
    begin
        if rising_edge(overlay_clk) then
            overlay_demux_p <= to_integer(unsigned(overlay_addr(2 downto 0)))*4;
            overlay_demux   <= overlay_demux_p;
        end if;
    end process;

    overlay_data <= to_integer(unsigned(fb_pl_rddata(overlay_demux+3 downto overlay_demux)));

    overlay_gate <= '0' when overlay_data = 0 else '1';
    overlay_r    <= r_lut(overlay_data);
    overlay_g    <= g_lut(overlay_data);
    overlay_b    <= b_lut(overlay_data);


    axi_bram_ctrl_0_i : entity work.axi_bram_ctrl_0
        port map (
            s_axi_aclk    => s_axi_aclk,
            s_axi_aresetn => s_axi_aresetn,

            s_axi_awid    => s_axi_awid,
            s_axi_awaddr  => s_axi_awaddr(19 downto 0),
            s_axi_awlen   => s_axi_awlen,
            s_axi_awsize  => s_axi_awsize,
            s_axi_awburst => s_axi_awburst,
            s_axi_awlock  => s_axi_awlock(0),
            s_axi_awcache => s_axi_awcache,
            s_axi_awprot  => s_axi_awprot,
            s_axi_awvalid => s_axi_awvalid,
            s_axi_awready => s_axi_awready,
            s_axi_wdata   => s_axi_wdata,
            s_axi_wstrb   => s_axi_wstrb,
            s_axi_wlast   => s_axi_wlast,
            s_axi_wvalid  => s_axi_wvalid,
            s_axi_wready  => s_axi_wready,
            s_axi_bid     => s_axi_bid,
            s_axi_bresp   => s_axi_bresp,
            s_axi_bvalid  => s_axi_bvalid,
            s_axi_bready  => s_axi_bready,
            s_axi_arid    => s_axi_arid,
            s_axi_araddr  => s_axi_araddr(19 downto 0),
            s_axi_arlen   => s_axi_arlen,
            s_axi_arsize  => s_axi_arsize,
            s_axi_arburst => s_axi_arburst,
            s_axi_arlock  => s_axi_arlock(0),
            s_axi_arcache => s_axi_arcache,
            s_axi_arprot  => s_axi_arprot,
            s_axi_arvalid => s_axi_arvalid,
            s_axi_arready => s_axi_arready,
            s_axi_rid     => s_axi_rid,
            s_axi_rdata   => s_axi_rdata,
            s_axi_rresp   => s_axi_rresp,
            s_axi_rlast   => s_axi_rlast,
            s_axi_rvalid  => s_axi_rvalid,
            s_axi_rready  => s_axi_rready,

            bram_clk_a    => fb_ps_clk,
            bram_en_a     => fb_ps_en,
            bram_we_a     => fb_ps_we,
            bram_addr_a   => fb_ps_addr,
            bram_wrdata_a => fb_ps_wrdata,
            bram_rddata_a => fb_ps_rddata

            );


end Behavioural;