# "Normal" constraints file- not early not late set_property PACKAGE_PIN U18 [get_ports {eth0_clk_o}] set_property PACKAGE_PIN U15 [get_ports {eth0_gmii_tx_clk_i}] set_property PACKAGE_PIN W19 [get_ports {eth0_gmii_tx_en_o[0]}] set_property PACKAGE_PIN W18 [get_ports {eth0_gmii_txd_o[0]}] set_property PACKAGE_PIN Y18 [get_ports {eth0_gmii_txd_o[1]}] set_property PACKAGE_PIN V18 [get_ports {eth0_gmii_txd_o[2]}] set_property PACKAGE_PIN Y19 [get_ports {eth0_gmii_txd_o[3]}] set_property PACKAGE_PIN U14 [get_ports {eth0_gmii_rx_clk_i}] set_property PACKAGE_PIN W16 [get_ports {eth0_gmii_rx_dv_i}] set_property PACKAGE_PIN Y16 [get_ports {eth0_gmii_rxd_i[0]}] set_property PACKAGE_PIN V16 [get_ports {eth0_gmii_rxd_i[1]}] set_property PACKAGE_PIN V17 [get_ports {eth0_gmii_rxd_i[2]}] set_property PACKAGE_PIN Y17 [get_ports {eth0_gmii_rxd_i[3]}] set_property PACKAGE_PIN W15 [get_ports {eth0_mdio_mdc_o}] set_property PACKAGE_PIN Y14 [get_ports {eth0_mdio_mdio_io}] set_property IOSTANDARD LVCMOS33 [get_ports eth0_*] set_property PACKAGE_PIN W13 [get_ports {green_led}] set_property PACKAGE_PIN W14 [get_ports {red_led}] set_property IOSTANDARD LVCMOS33 [get_ports *_led] #set_property IOSTANDARD LVCMOS33 [get_ports clk_50m] #set_property PACKAGE_PIN R4 [get_ports clk_50m] #set_property PACKAGE_PIN T1 [get_ports {led_1}] #set_property IOSTANDARD LVCMOS33 [get_ports {led_1}] set_property PACKAGE_PIN G19 [get_ports {hdmi_r_p}]; #data2-5 set_property PACKAGE_PIN G20 [get_ports {hdmi_r_n}]; #data2-7 set_property PACKAGE_PIN K19 [get_ports {hdmi_g_p}]; #data2-13 set_property PACKAGE_PIN J19 [get_ports {hdmi_g_n}]; #data2-9 set_property PACKAGE_PIN L19 [get_ports {hdmi_b_p}]; #data2-16 set_property PACKAGE_PIN L20 [get_ports {hdmi_b_n}]; #data2-18 set_property PACKAGE_PIN L16 [get_ports {hdmi_c_p}]; #data2-15 set_property PACKAGE_PIN L17 [get_ports {hdmi_c_n}]; #data2-20 set_property IOSTANDARD TMDS_33 [get_ports {hdmi_c_p}] set_property IOSTANDARD TMDS_33 [get_ports {hdmi_c_n}] set_property IOSTANDARD TMDS_33 [get_ports {hdmi_r_p}] set_property IOSTANDARD TMDS_33 [get_ports {hdmi_r_n}] set_property IOSTANDARD TMDS_33 [get_ports {hdmi_g_p}] set_property IOSTANDARD TMDS_33 [get_ports {hdmi_g_n}] set_property IOSTANDARD TMDS_33 [get_ports {hdmi_b_p}] set_property IOSTANDARD TMDS_33 [get_ports {hdmi_b_n}] ##set_property DRIVE 16 [get_ports {hdmi_c_p}] ##set_property DRIVE 16 [get_ports {hdmi_c_n}] ##set_property DRIVE 16 [get_ports {hdmi_r_p}] ##set_property DRIVE 16 [get_ports {hdmi_r_n}] ##set_property DRIVE 16 [get_ports {hdmi_g_p}] ##set_property DRIVE 16 [get_ports {hdmi_g_n}] ##set_property DRIVE 16 [get_ports {hdmi_b_p}] # set_property PACKAGE_PIN H20 [get_ports {hdmi_vcc}]; #data2-8 set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_vcc}] # # ##set_property PACKAGE_PIN P20 [get_ports rxd] ##set_property PACKAGE_PIN T20 [get_ports txd] ##set_property IOSTANDARD LVCMOS33 [get_ports rxd] ##set_property IOSTANDARD LVCMOS33 [get_ports txd] # ##set_property PACKAGE_PIN T3 [get_ports key] ##set_property IOSTANDARD LVCMOS33 [get_ports key] # set_property PACKAGE_PIN A20 [get_ports {video[0]}]; #data1-5 set_property PACKAGE_PIN B19 [get_ports {video[1]}]; #data1-7 set_property PACKAGE_PIN C20 [get_ports {video[2]}]; #data1-9 set_property PACKAGE_PIN H17 [get_ports {video[3]}]; #data1-11 set_property PACKAGE_PIN D20 [get_ports {video[4]}]; #data1-13 set_property PACKAGE_PIN H18 [get_ports {video[5]}]; #data1-15 set_property PACKAGE_PIN F20 [get_ports {video[6]}]; #data1-17 set_property PACKAGE_PIN F19 [get_ports {video[7]}]; #data1-19 # set_property IOSTANDARD LVCMOS33 [get_ports {video[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {video[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {video[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {video[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {video[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {video[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {video[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {video[7]}] # set_property PACKAGE_PIN H16 [get_ports {pclk_in}]; #data1-6 set_property PACKAGE_PIN D18 [get_ports {vsync_in}]; #data1-14 set_property PACKAGE_PIN D19 [get_ports {hsync_in}]; #data1-16 # #set_property PACKAGE_PIN P16 [get_ports {r_out}] #set_property PACKAGE_PIN V18 [get_ports {g_out}] #set_property PACKAGE_PIN P15 [get_ports {b_out}] #set_property PACKAGE_PIN P14 [get_ports {i_clk_out}] #set_property PACKAGE_PIN V17 [get_ports {hsync_out}] #set_property PACKAGE_PIN N13 [get_ports {vsync_out}] # # set_property IOSTANDARD LVCMOS33 [get_ports {pclk_in}] set_property IOSTANDARD LVCMOS33 [get_ports {vsync_in}] set_property IOSTANDARD LVCMOS33 [get_ports {hsync_in}] #set_property IOSTANDARD LVCMOS33 [get_ports {r_out}] #set_property IOSTANDARD LVCMOS33 [get_ports {g_out}] #set_property IOSTANDARD LVCMOS33 [get_ports {b_out}] #set_property IOSTANDARD LVCMOS33 [get_ports {i_clk_out}] #set_property IOSTANDARD LVCMOS33 [get_ports {hsync_out}] #set_property IOSTANDARD LVCMOS33 [get_ports {vsync_out}] # #set_property PACKAGE_PIN AA18 [get_ports {sys_rst_n}] #set_property IOSTANDARD LVCMOS33 [get_ports {sys_rst_n}] #set_property PULLTYPE PULLUP [get_ports {sys_rst_n}] # #create_clock -period 20.000 -name pcie_clkin [get_ports clk_50m] ##set_false_path -from [get_ports pci_exp_rst_n] # set_false_path -from [get_clocks clk_out4_mmcm_0] -to [get_clocks clk_out1_mmcm_0] ############################################################################### # Additional design / project settings ############################################################################### # Power down on overtemp set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN ENABLE [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] set_property BITSTREAM.CONFIG.USERID 32'hf00dbabe [current_design] set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design]