library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity delay is
    generic (stages : natural := 2);
    port (clk : in  std_logic;
          i   : in  std_logic;
          o   : out std_logic);
end delay;

architecture Behavioral of delay is
    signal flipflops : std_logic_vector(stages-1 downto 0) := (others => '0');
begin

    o <= flipflops(flipflops'high);

    clk_proc : process(clk, flipflops, i)
    begin
        if rising_edge(clk) then
            flipflops <= flipflops(flipflops'high-1 downto 0) & i;
        end if;
    end process;

end Behavioral;