From bc24ae901b74c5b673837d7f83423c1f7aa45c29 Mon Sep 17 00:00:00 2001 From: James McKenzie Date: Fri, 18 Apr 2025 12:37:26 +0100 Subject: fish --- ...27\266\345\272\217\346\240\207\345\207\206.pdf" | Bin 0 -> 1086239 bytes .../examples/09_vga/vga/doc/vga_colorbar.vsdx | Bin 0 -> 262875 bytes .../09_vga/vga/quartus_prj/PLLJ_PLLSPE_INFO.txt | 5 + .../vga/quartus_prj/ip_core/clk_gen/clk_gen.ppf | 11 + .../vga/quartus_prj/ip_core/clk_gen/clk_gen.qip | 6 + .../vga/quartus_prj/ip_core/clk_gen/clk_gen.v | 320 +++ .../vga/quartus_prj/ip_core/clk_gen/clk_gen_bb.v | 210 ++ .../vga/quartus_prj/ip_core/clk_gen/clk_gen_inst.v | 6 + .../ip_core/clk_gen/greybox_tmp/cbx_args.txt | 61 + .../simulation/modelsim/vga_colorbar.sft | 6 + .../simulation/modelsim/vga_colorbar.vo | 2833 ++++++++++++++++++++ .../modelsim/vga_colorbar_8_1200mv_0c_slow.vo | 2833 ++++++++++++++++++++ .../modelsim/vga_colorbar_8_1200mv_0c_v_slow.sdo | 2108 +++++++++++++++ .../modelsim/vga_colorbar_8_1200mv_85c_slow.vo | 2833 ++++++++++++++++++++ .../modelsim/vga_colorbar_8_1200mv_85c_v_slow.sdo | 2108 +++++++++++++++ .../modelsim/vga_colorbar_min_1200mv_0c_fast.vo | 2833 ++++++++++++++++++++ .../modelsim/vga_colorbar_min_1200mv_0c_v_fast.sdo | 2108 +++++++++++++++ .../simulation/modelsim/vga_colorbar_modelsim.xrf | 166 ++ .../simulation/modelsim/vga_colorbar_v.sdo | 2108 +++++++++++++++ .../09_vga/vga/quartus_prj/vga_colorbar.qpf | 30 + .../09_vga/vga/quartus_prj/vga_colorbar.qsf | 99 + .../09_vga/vga/quartus_prj/vga_colorbar.qws | Bin 0 -> 613 bytes .../examples/09_vga/vga/rtl/vga_colorbar.v | 84 + smh-ac415-fpga/examples/09_vga/vga/rtl/vga_ctrl.v | 113 + smh-ac415-fpga/examples/09_vga/vga/rtl/vga_pic.v | 79 + .../examples/09_vga/vga/sim/tb_vga_colorbar.v | 65 + .../examples/09_vga/vga/sim/tb_vga_ctrl.v | 88 + ...56\236\351\252\214\347\216\260\350\261\241.txt" | 5 + 28 files changed, 21118 insertions(+) create mode 100644 "smh-ac415-fpga/examples/09_vga/vga/doc/VESA VGA\346\227\266\345\272\217\346\240\207\345\207\206.pdf" create mode 100644 smh-ac415-fpga/examples/09_vga/vga/doc/vga_colorbar.vsdx create mode 100644 smh-ac415-fpga/examples/09_vga/vga/quartus_prj/PLLJ_PLLSPE_INFO.txt create mode 100644 smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen.ppf create mode 100644 smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen.qip create mode 100644 smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen.v create mode 100644 smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen_bb.v create mode 100644 smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen_inst.v create mode 100644 smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/greybox_tmp/cbx_args.txt create mode 100644 smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar.sft create mode 100644 smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar.vo create mode 100644 smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_0c_slow.vo create mode 100644 smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_0c_v_slow.sdo create mode 100644 smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_85c_slow.vo create mode 100644 smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_85c_v_slow.sdo create mode 100644 smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_min_1200mv_0c_fast.vo create mode 100644 smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_min_1200mv_0c_v_fast.sdo create mode 100644 smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_modelsim.xrf create mode 100644 smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_v.sdo create mode 100644 smh-ac415-fpga/examples/09_vga/vga/quartus_prj/vga_colorbar.qpf create mode 100644 smh-ac415-fpga/examples/09_vga/vga/quartus_prj/vga_colorbar.qsf create mode 100644 smh-ac415-fpga/examples/09_vga/vga/quartus_prj/vga_colorbar.qws create mode 100644 smh-ac415-fpga/examples/09_vga/vga/rtl/vga_colorbar.v create mode 100644 smh-ac415-fpga/examples/09_vga/vga/rtl/vga_ctrl.v create mode 100644 smh-ac415-fpga/examples/09_vga/vga/rtl/vga_pic.v create mode 100644 smh-ac415-fpga/examples/09_vga/vga/sim/tb_vga_colorbar.v create mode 100644 smh-ac415-fpga/examples/09_vga/vga/sim/tb_vga_ctrl.v create mode 100644 "smh-ac415-fpga/examples/09_vga/\345\256\236\351\252\214\347\216\260\350\261\241.txt" (limited to 'smh-ac415-fpga/examples/09_vga') diff --git "a/smh-ac415-fpga/examples/09_vga/vga/doc/VESA VGA\346\227\266\345\272\217\346\240\207\345\207\206.pdf" "b/smh-ac415-fpga/examples/09_vga/vga/doc/VESA VGA\346\227\266\345\272\217\346\240\207\345\207\206.pdf" new file mode 100644 index 0000000..b0b4015 Binary files /dev/null and "b/smh-ac415-fpga/examples/09_vga/vga/doc/VESA VGA\346\227\266\345\272\217\346\240\207\345\207\206.pdf" differ diff --git a/smh-ac415-fpga/examples/09_vga/vga/doc/vga_colorbar.vsdx b/smh-ac415-fpga/examples/09_vga/vga/doc/vga_colorbar.vsdx new file mode 100644 index 0000000..99486d0 Binary files /dev/null and b/smh-ac415-fpga/examples/09_vga/vga/doc/vga_colorbar.vsdx differ diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/PLLJ_PLLSPE_INFO.txt b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/PLLJ_PLLSPE_INFO.txt new file mode 100644 index 0000000..790cae7 --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/PLLJ_PLLSPE_INFO.txt @@ -0,0 +1,5 @@ +PLL_Name clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|pll1 +PLLJITTER 30 +PLLSPEmax 84 +PLLSPEmin -53 + diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen.ppf b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen.ppf new file mode 100644 index 0000000..30a8de7 --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen.ppf @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen.qip b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen.qip new file mode 100644 index 0000000..433e305 --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clk_gen.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen.ppf"] diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen.v b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen.v new file mode 100644 index 0000000..9bf99ee --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen.v @@ -0,0 +1,320 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: clk_gen.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.0 Build 156 04/24/2013 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module clk_gen ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire sub_wire0; + wire [4:0] sub_wire1; + wire [0:0] sub_wire5 = 1'h0; + wire locked = sub_wire0; + wire [0:0] sub_wire2 = sub_wire1[0:0]; + wire c0 = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire4), + .locked (sub_wire0), + .clk (sub_wire1), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 2, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 1, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 20000, + altpll_component.intended_device_family = "Cyclone IV E", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clk_gen", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_gen.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen_bb.v b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen_bb.v new file mode 100644 index 0000000..1892505 --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen_bb.v @@ -0,0 +1,210 @@ +// megafunction wizard: %ALTPLL%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: clk_gen.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.0 Build 156 04/24/2013 SJ Full Version +// ************************************************************ + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module clk_gen ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_gen.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen_inst.v b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen_inst.v new file mode 100644 index 0000000..9d75f00 --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen_inst.v @@ -0,0 +1,6 @@ +clk_gen clk_gen_inst ( + .areset ( areset_sig ), + .inclk0 ( inclk0_sig ), + .c0 ( c0_sig ), + .locked ( locked_sig ) + ); diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/greybox_tmp/cbx_args.txt b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..0eb724d --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/greybox_tmp/cbx_args.txt @@ -0,0 +1,61 @@ +BANDWIDTH_TYPE=AUTO +CLK0_DIVIDE_BY=2 +CLK0_DUTY_CYCLE=50 +CLK0_MULTIPLY_BY=1 +CLK0_PHASE_SHIFT=0 +COMPENSATE_CLOCK=CLK0 +INCLK0_INPUT_FREQUENCY=20000 +INTENDED_DEVICE_FAMILY="Cyclone IV E" +LPM_TYPE=altpll +OPERATION_MODE=NORMAL +PLL_TYPE=AUTO +PORT_ACTIVECLOCK=PORT_UNUSED +PORT_ARESET=PORT_USED +PORT_CLKBAD0=PORT_UNUSED +PORT_CLKBAD1=PORT_UNUSED +PORT_CLKLOSS=PORT_UNUSED +PORT_CLKSWITCH=PORT_UNUSED +PORT_CONFIGUPDATE=PORT_UNUSED +PORT_FBIN=PORT_UNUSED +PORT_INCLK0=PORT_USED +PORT_INCLK1=PORT_UNUSED +PORT_LOCKED=PORT_USED +PORT_PFDENA=PORT_UNUSED +PORT_PHASECOUNTERSELECT=PORT_UNUSED +PORT_PHASEDONE=PORT_UNUSED +PORT_PHASESTEP=PORT_UNUSED +PORT_PHASEUPDOWN=PORT_UNUSED +PORT_PLLENA=PORT_UNUSED +PORT_SCANACLR=PORT_UNUSED +PORT_SCANCLK=PORT_UNUSED +PORT_SCANCLKENA=PORT_UNUSED +PORT_SCANDATA=PORT_UNUSED +PORT_SCANDATAOUT=PORT_UNUSED +PORT_SCANDONE=PORT_UNUSED +PORT_SCANREAD=PORT_UNUSED +PORT_SCANWRITE=PORT_UNUSED +PORT_clk0=PORT_USED +PORT_clk1=PORT_UNUSED +PORT_clk2=PORT_UNUSED +PORT_clk3=PORT_UNUSED +PORT_clk4=PORT_UNUSED +PORT_clk5=PORT_UNUSED +PORT_clkena0=PORT_UNUSED +PORT_clkena1=PORT_UNUSED +PORT_clkena2=PORT_UNUSED +PORT_clkena3=PORT_UNUSED +PORT_clkena4=PORT_UNUSED +PORT_clkena5=PORT_UNUSED +PORT_extclk0=PORT_UNUSED +PORT_extclk1=PORT_UNUSED +PORT_extclk2=PORT_UNUSED +PORT_extclk3=PORT_UNUSED +SELF_RESET_ON_LOSS_LOCK=OFF +WIDTH_CLOCK=5 +DEVICE_FAMILY="Cyclone IV E" +CBX_AUTO_BLACKBOX=ALL +areset +inclk +inclk +clk +locked diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar.sft b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar.sft new file mode 100644 index 0000000..57ef981 --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar.sft @@ -0,0 +1,6 @@ +set tool_name "ModelSim (Verilog)" +set corner_file_list { + {{"Slow -8 1.2V 85 Model"} {vga_colorbar_8_1200mv_85c_slow.vo vga_colorbar_8_1200mv_85c_v_slow.sdo}} + {{"Slow -8 1.2V 0 Model"} {vga_colorbar_8_1200mv_0c_slow.vo vga_colorbar_8_1200mv_0c_v_slow.sdo}} + {{"Fast -M 1.2V 0 Model"} {vga_colorbar_min_1200mv_0c_fast.vo vga_colorbar_min_1200mv_0c_v_fast.sdo}} +} diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar.vo b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar.vo new file mode 100644 index 0000000..31317fc --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar.vo @@ -0,0 +1,2833 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 04:42:20" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module vga_colorbar ( + sys_clk, + sys_rst_n, + hsync, + vsync, + rgb); +input sys_clk; +input sys_rst_n; +output hsync; +output vsync; +output [15:0] rgb; + +// Design Ports Information +// hsync => Location: PIN_AA18, I/O Standard: 2.5 V, Current Strength: Default +// vsync => Location: PIN_AB17, I/O Standard: 2.5 V, Current Strength: Default +// rgb[0] => Location: PIN_AB18, I/O Standard: 2.5 V, Current Strength: Default +// rgb[1] => Location: PIN_AA19, I/O Standard: 2.5 V, Current Strength: Default +// rgb[2] => Location: PIN_AB19, I/O Standard: 2.5 V, Current Strength: Default +// rgb[3] => Location: PIN_Y21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[4] => Location: PIN_W19, I/O Standard: 2.5 V, Current Strength: Default +// rgb[5] => Location: PIN_W20, I/O Standard: 2.5 V, Current Strength: Default +// rgb[6] => Location: PIN_U21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[7] => Location: PIN_U22, I/O Standard: 2.5 V, Current Strength: Default +// rgb[8] => Location: PIN_N20, I/O Standard: 2.5 V, Current Strength: Default +// rgb[9] => Location: PIN_N21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[10] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[11] => Location: PIN_M22, I/O Standard: 2.5 V, Current Strength: Default +// rgb[12] => Location: PIN_L21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[13] => Location: PIN_L22, I/O Standard: 2.5 V, Current Strength: Default +// rgb[14] => Location: PIN_K21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[15] => Location: PIN_J21, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("vga_colorbar_v.sdo"); +// synopsys translate_on + +wire \vga_ctrl_inst|Add0~4_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ; +wire \vga_ctrl_inst|Add1~0_combout ; +wire \vga_ctrl_inst|Add1~2_combout ; +wire \vga_ctrl_inst|Add1~4_combout ; +wire \vga_ctrl_inst|Add1~6_combout ; +wire \vga_ctrl_inst|Add1~8_combout ; +wire \vga_ctrl_inst|Add1~10_combout ; +wire \vga_ctrl_inst|Add1~12_combout ; +wire \vga_ctrl_inst|Add1~16_combout ; +wire \vga_ctrl_inst|Equal0~0_combout ; +wire \vga_ctrl_inst|cnt_v[8]~3_combout ; +wire \vga_pic_inst|pix_data[4]~5_combout ; +wire \vga_pic_inst|pix_data~8_combout ; +wire \vga_pic_inst|pix_data~15_combout ; +wire \vga_pic_inst|pix_data~17_combout ; +wire \sys_clk~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \vga_ctrl_inst|Add0~0_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \sys_rst_n~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ; +wire \rst_n~0_combout ; +wire \rst_n~0clkctrl_outclk ; +wire \vga_ctrl_inst|Add0~1 ; +wire \vga_ctrl_inst|Add0~3 ; +wire \vga_ctrl_inst|Add0~5 ; +wire \vga_ctrl_inst|Add0~6_combout ; +wire \vga_ctrl_inst|Add0~7 ; +wire \vga_ctrl_inst|Add0~8_combout ; +wire \vga_ctrl_inst|Add0~9 ; +wire \vga_ctrl_inst|Add0~11 ; +wire \vga_ctrl_inst|Add0~12_combout ; +wire \vga_ctrl_inst|Add0~13 ; +wire \vga_ctrl_inst|Add0~14_combout ; +wire \vga_ctrl_inst|Add0~15 ; +wire \vga_ctrl_inst|Add0~16_combout ; +wire \vga_ctrl_inst|Add0~17 ; +wire \vga_ctrl_inst|Add0~18_combout ; +wire \vga_ctrl_inst|cnt_h~1_combout ; +wire \vga_ctrl_inst|Add0~10_combout ; +wire \vga_ctrl_inst|cnt_h~0_combout ; +wire \vga_ctrl_inst|Equal0~2_combout ; +wire \vga_ctrl_inst|Add0~2_combout ; +wire \vga_ctrl_inst|Equal0~1_combout ; +wire \vga_ctrl_inst|Equal0~3_combout ; +wire \vga_ctrl_inst|cnt_h~2_combout ; +wire \vga_ctrl_inst|LessThan2~0_combout ; +wire \vga_ctrl_inst|LessThan0~0_combout ; +wire \vga_ctrl_inst|cnt_v[0]~9_combout ; +wire \vga_ctrl_inst|cnt_v[2]~8_combout ; +wire \vga_ctrl_inst|cnt_v[4]~6_combout ; +wire \vga_ctrl_inst|always1~1_combout ; +wire \vga_ctrl_inst|cnt_v[1]~0_combout ; +wire \vga_ctrl_inst|always1~2_combout ; +wire \vga_ctrl_inst|cnt_v[3]~7_combout ; +wire \vga_ctrl_inst|LessThan6~0_combout ; +wire \vga_ctrl_inst|cnt_v[5]~2_combout ; +wire \vga_ctrl_inst|Add1~1 ; +wire \vga_ctrl_inst|Add1~3 ; +wire \vga_ctrl_inst|Add1~5 ; +wire \vga_ctrl_inst|Add1~7 ; +wire \vga_ctrl_inst|Add1~9 ; +wire \vga_ctrl_inst|Add1~11 ; +wire \vga_ctrl_inst|Add1~13 ; +wire \vga_ctrl_inst|Add1~14_combout ; +wire \vga_ctrl_inst|cnt_v[7]~4_combout ; +wire \vga_ctrl_inst|Add1~15 ; +wire \vga_ctrl_inst|Add1~17 ; +wire \vga_ctrl_inst|Add1~18_combout ; +wire \vga_ctrl_inst|cnt_v[9]~1_combout ; +wire \vga_ctrl_inst|cnt_v[6]~5_combout ; +wire \vga_ctrl_inst|always1~0_combout ; +wire \vga_ctrl_inst|LessThan1~0_combout ; +wire \vga_ctrl_inst|LessThan6~1_combout ; +wire \vga_ctrl_inst|pix_data_req~1_combout ; +wire \vga_ctrl_inst|pix_data_req~2_combout ; +wire \vga_ctrl_inst|LessThan2~1_combout ; +wire \vga_ctrl_inst|rgb_valid~0_combout ; +wire \vga_ctrl_inst|Add2~1_cout ; +wire \vga_ctrl_inst|Add2~3_cout ; +wire \vga_ctrl_inst|Add2~5_cout ; +wire \vga_ctrl_inst|Add2~7_cout ; +wire \vga_ctrl_inst|Add2~9_cout ; +wire \vga_ctrl_inst|Add2~11 ; +wire \vga_ctrl_inst|Add2~12_combout ; +wire \vga_ctrl_inst|Add2~10_combout ; +wire \vga_pic_inst|LessThan14~0_combout ; +wire \vga_ctrl_inst|Add2~13 ; +wire \vga_ctrl_inst|Add2~15 ; +wire \vga_ctrl_inst|Add2~16_combout ; +wire \vga_ctrl_inst|Add2~14_combout ; +wire \vga_pic_inst|LessThan6~0_combout ; +wire \vga_ctrl_inst|pix_data_req~0_combout ; +wire \vga_ctrl_inst|LessThan4~0_combout ; +wire \vga_ctrl_inst|pix_data_req~3_combout ; +wire \vga_ctrl_inst|pix_data_req~4_combout ; +wire \vga_pic_inst|pix_data~4_combout ; +wire \vga_pic_inst|pix_data~9_combout ; +wire \vga_pic_inst|LessThan17~0_combout ; +wire \vga_pic_inst|pix_data~6_combout ; +wire \vga_pic_inst|pix_data[4]~10_combout ; +wire \vga_pic_inst|pix_data~11_combout ; +wire \vga_pic_inst|pix_data~12_combout ; +wire \vga_pic_inst|pix_data~13_combout ; +wire \vga_ctrl_inst|rgb[0]~0_combout ; +wire \vga_pic_inst|pix_data[4]~7_combout ; +wire \vga_pic_inst|pix_data~16_combout ; +wire \vga_ctrl_inst|rgb[1]~1_combout ; +wire \vga_pic_inst|pix_data~25_combout ; +wire \vga_ctrl_inst|rgb[5]~2_combout ; +wire \vga_pic_inst|pix_data~18_combout ; +wire \vga_pic_inst|pix_data~14_combout ; +wire \vga_pic_inst|pix_data~26_combout ; +wire \vga_pic_inst|pix_data~19_combout ; +wire \vga_ctrl_inst|rgb[7]~3_combout ; +wire \vga_pic_inst|LessThan2~2_combout ; +wire \vga_pic_inst|pix_data~20_combout ; +wire \vga_pic_inst|pix_data~21_combout ; +wire \vga_ctrl_inst|rgb[10]~4_combout ; +wire \vga_pic_inst|pix_data~22_combout ; +wire \vga_pic_inst|pix_data~23_combout ; +wire \vga_ctrl_inst|rgb[11]~5_combout ; +wire \vga_pic_inst|pix_data~24_combout ; +wire \vga_ctrl_inst|rgb[12]~6_combout ; +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk ; +wire [9:0] \vga_ctrl_inst|cnt_v ; +wire [9:0] \vga_ctrl_inst|cnt_h ; +wire [15:0] \vga_pic_inst|pix_data ; + +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ; + +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [3] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [4] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [4]; + +// Location: LCCOMB_X35_Y23_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~4 ( +// Equation(s): +// \vga_ctrl_inst|Add0~4_combout = (\vga_ctrl_inst|cnt_h [2] & (\vga_ctrl_inst|Add0~3 $ (GND))) # (!\vga_ctrl_inst|cnt_h [2] & (!\vga_ctrl_inst|Add0~3 & VCC)) +// \vga_ctrl_inst|Add0~5 = CARRY((\vga_ctrl_inst|cnt_h [2] & !\vga_ctrl_inst|Add0~3 )) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~3 ), + .combout(\vga_ctrl_inst|Add0~4_combout ), + .cout(\vga_ctrl_inst|Add0~5 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~4 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: PLL_2 +cycloneive_pll \clk_gen_inst|altpll_component|auto_generated|pll1 ( + .areset(!\sys_rst_n~input_o ), + .pfdena(vcc), + .fbin(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\sys_clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_high = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_low = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_divide_by = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_multiply_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .n = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pll_compensation_delay = 6891; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~0 ( +// Equation(s): +// \vga_ctrl_inst|Add1~0_combout = \vga_ctrl_inst|cnt_v [0] $ (VCC) +// \vga_ctrl_inst|Add1~1 = CARRY(\vga_ctrl_inst|cnt_v [0]) + + .dataa(\vga_ctrl_inst|cnt_v [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\vga_ctrl_inst|Add1~0_combout ), + .cout(\vga_ctrl_inst|Add1~1 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~0 .lut_mask = 16'h55AA; +defparam \vga_ctrl_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~2 ( +// Equation(s): +// \vga_ctrl_inst|Add1~2_combout = (\vga_ctrl_inst|cnt_v [1] & (!\vga_ctrl_inst|Add1~1 )) # (!\vga_ctrl_inst|cnt_v [1] & ((\vga_ctrl_inst|Add1~1 ) # (GND))) +// \vga_ctrl_inst|Add1~3 = CARRY((!\vga_ctrl_inst|Add1~1 ) # (!\vga_ctrl_inst|cnt_v [1])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [1]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~1 ), + .combout(\vga_ctrl_inst|Add1~2_combout ), + .cout(\vga_ctrl_inst|Add1~3 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~2 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~4 ( +// Equation(s): +// \vga_ctrl_inst|Add1~4_combout = (\vga_ctrl_inst|cnt_v [2] & (\vga_ctrl_inst|Add1~3 $ (GND))) # (!\vga_ctrl_inst|cnt_v [2] & (!\vga_ctrl_inst|Add1~3 & VCC)) +// \vga_ctrl_inst|Add1~5 = CARRY((\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|Add1~3 )) + + .dataa(\vga_ctrl_inst|cnt_v [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~3 ), + .combout(\vga_ctrl_inst|Add1~4_combout ), + .cout(\vga_ctrl_inst|Add1~5 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~4 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~6 ( +// Equation(s): +// \vga_ctrl_inst|Add1~6_combout = (\vga_ctrl_inst|cnt_v [3] & (!\vga_ctrl_inst|Add1~5 )) # (!\vga_ctrl_inst|cnt_v [3] & ((\vga_ctrl_inst|Add1~5 ) # (GND))) +// \vga_ctrl_inst|Add1~7 = CARRY((!\vga_ctrl_inst|Add1~5 ) # (!\vga_ctrl_inst|cnt_v [3])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~5 ), + .combout(\vga_ctrl_inst|Add1~6_combout ), + .cout(\vga_ctrl_inst|Add1~7 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~6 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~8 ( +// Equation(s): +// \vga_ctrl_inst|Add1~8_combout = (\vga_ctrl_inst|cnt_v [4] & (\vga_ctrl_inst|Add1~7 $ (GND))) # (!\vga_ctrl_inst|cnt_v [4] & (!\vga_ctrl_inst|Add1~7 & VCC)) +// \vga_ctrl_inst|Add1~9 = CARRY((\vga_ctrl_inst|cnt_v [4] & !\vga_ctrl_inst|Add1~7 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [4]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~7 ), + .combout(\vga_ctrl_inst|Add1~8_combout ), + .cout(\vga_ctrl_inst|Add1~9 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~8 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~10 ( +// Equation(s): +// \vga_ctrl_inst|Add1~10_combout = (\vga_ctrl_inst|cnt_v [5] & (!\vga_ctrl_inst|Add1~9 )) # (!\vga_ctrl_inst|cnt_v [5] & ((\vga_ctrl_inst|Add1~9 ) # (GND))) +// \vga_ctrl_inst|Add1~11 = CARRY((!\vga_ctrl_inst|Add1~9 ) # (!\vga_ctrl_inst|cnt_v [5])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [5]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~9 ), + .combout(\vga_ctrl_inst|Add1~10_combout ), + .cout(\vga_ctrl_inst|Add1~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~10 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~12 ( +// Equation(s): +// \vga_ctrl_inst|Add1~12_combout = (\vga_ctrl_inst|cnt_v [6] & (\vga_ctrl_inst|Add1~11 $ (GND))) # (!\vga_ctrl_inst|cnt_v [6] & (!\vga_ctrl_inst|Add1~11 & VCC)) +// \vga_ctrl_inst|Add1~13 = CARRY((\vga_ctrl_inst|cnt_v [6] & !\vga_ctrl_inst|Add1~11 )) + + .dataa(\vga_ctrl_inst|cnt_v [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~11 ), + .combout(\vga_ctrl_inst|Add1~12_combout ), + .cout(\vga_ctrl_inst|Add1~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~12 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N26 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~16 ( +// Equation(s): +// \vga_ctrl_inst|Add1~16_combout = (\vga_ctrl_inst|cnt_v [8] & (\vga_ctrl_inst|Add1~15 $ (GND))) # (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|Add1~15 & VCC)) +// \vga_ctrl_inst|Add1~17 = CARRY((\vga_ctrl_inst|cnt_v [8] & !\vga_ctrl_inst|Add1~15 )) + + .dataa(\vga_ctrl_inst|cnt_v [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~15 ), + .combout(\vga_ctrl_inst|Add1~16_combout ), + .cout(\vga_ctrl_inst|Add1~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~16 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y23_N13 +dffeas \vga_ctrl_inst|cnt_v[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[8]~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[8] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~0 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~0_combout = (\vga_ctrl_inst|cnt_h [8] & \vga_ctrl_inst|cnt_h [9]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~0 .lut_mask = 16'hCC00; +defparam \vga_ctrl_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N13 +dffeas \vga_ctrl_inst|cnt_h[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [2]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[2] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N12 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[8]~3 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[8]~3_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~16_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [8])))) + + .dataa(\vga_ctrl_inst|Add1~16_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [8]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[8]~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[8]~3 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[8]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data[4]~5 ( +// Equation(s): +// \vga_pic_inst|pix_data[4]~5_combout = (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~16_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|pix_data_req~4_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~16_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4]~5 .lut_mask = 16'h00CC; +defparam \vga_pic_inst|pix_data[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~8 ( +// Equation(s): +// \vga_pic_inst|pix_data~8_combout = (\vga_ctrl_inst|Add2~16_combout ) # (((\vga_ctrl_inst|Add2~14_combout ) # (!\vga_ctrl_inst|pix_data_req~4_combout )) # (!\vga_ctrl_inst|Add2~10_combout )) + + .dataa(\vga_ctrl_inst|Add2~16_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~8 .lut_mask = 16'hFBFF; +defparam \vga_pic_inst|pix_data~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N10 +cycloneive_lcell_comb \vga_pic_inst|pix_data~15 ( +// Equation(s): +// \vga_pic_inst|pix_data~15_combout = (\vga_pic_inst|pix_data[4]~5_combout & (\vga_pic_inst|pix_data~11_combout & ((!\vga_pic_inst|pix_data[4]~10_combout )))) # (!\vga_pic_inst|pix_data[4]~5_combout & (((\vga_pic_inst|pix_data~14_combout )))) + + .dataa(\vga_pic_inst|pix_data~11_combout ), + .datab(\vga_pic_inst|pix_data~14_combout ), + .datac(\vga_pic_inst|pix_data[4]~10_combout ), + .datad(\vga_pic_inst|pix_data[4]~5_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~15_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~15 .lut_mask = 16'h0ACC; +defparam \vga_pic_inst|pix_data~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~17 ( +// Equation(s): +// \vga_pic_inst|pix_data~17_combout = (\vga_ctrl_inst|Add2~12_combout & (!\vga_ctrl_inst|Add2~14_combout )) # (!\vga_ctrl_inst|Add2~12_combout & (\vga_ctrl_inst|Add2~14_combout & !\vga_ctrl_inst|Add2~10_combout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~17_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~17 .lut_mask = 16'h0C3C; +defparam \vga_pic_inst|pix_data~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOOBUF_X35_Y0_N30 +cycloneive_io_obuf \hsync~output ( + .i(!\vga_ctrl_inst|LessThan0~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(hsync), + .obar()); +// synopsys translate_off +defparam \hsync~output .bus_hold = "false"; +defparam \hsync~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X28_Y0_N2 +cycloneive_io_obuf \vsync~output ( + .i(!\vga_ctrl_inst|LessThan1~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(vsync), + .obar()); +// synopsys translate_off +defparam \vsync~output .bus_hold = "false"; +defparam \vsync~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X32_Y0_N2 +cycloneive_io_obuf \rgb[0]~output ( + .i(\vga_ctrl_inst|rgb[0]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[0]), + .obar()); +// synopsys translate_off +defparam \rgb[0]~output .bus_hold = "false"; +defparam \rgb[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X35_Y0_N23 +cycloneive_io_obuf \rgb[1]~output ( + .i(\vga_ctrl_inst|rgb[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[1]), + .obar()); +// synopsys translate_off +defparam \rgb[1]~output .bus_hold = "false"; +defparam \rgb[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X35_Y0_N16 +cycloneive_io_obuf \rgb[2]~output ( + .i(\vga_ctrl_inst|rgb[0]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[2]), + .obar()); +// synopsys translate_off +defparam \rgb[2]~output .bus_hold = "false"; +defparam \rgb[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y4_N9 +cycloneive_io_obuf \rgb[3]~output ( + .i(\vga_ctrl_inst|rgb[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[3]), + .obar()); +// synopsys translate_off +defparam \rgb[3]~output .bus_hold = "false"; +defparam \rgb[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y3_N9 +cycloneive_io_obuf \rgb[4]~output ( + .i(\vga_ctrl_inst|rgb[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[4]), + .obar()); +// synopsys translate_off +defparam \rgb[4]~output .bus_hold = "false"; +defparam \rgb[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y3_N16 +cycloneive_io_obuf \rgb[5]~output ( + .i(\vga_ctrl_inst|rgb[5]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[5]), + .obar()); +// synopsys translate_off +defparam \rgb[5]~output .bus_hold = "false"; +defparam \rgb[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y8_N2 +cycloneive_io_obuf \rgb[6]~output ( + .i(\vga_ctrl_inst|rgb[5]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[6]), + .obar()); +// synopsys translate_off +defparam \rgb[6]~output .bus_hold = "false"; +defparam \rgb[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y8_N9 +cycloneive_io_obuf \rgb[7]~output ( + .i(\vga_ctrl_inst|rgb[7]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[7]), + .obar()); +// synopsys translate_off +defparam \rgb[7]~output .bus_hold = "false"; +defparam \rgb[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y12_N16 +cycloneive_io_obuf \rgb[8]~output ( + .i(\vga_ctrl_inst|rgb[5]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[8]), + .obar()); +// synopsys translate_off +defparam \rgb[8]~output .bus_hold = "false"; +defparam \rgb[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y13_N9 +cycloneive_io_obuf \rgb[9]~output ( + .i(\vga_ctrl_inst|rgb[7]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[9]), + .obar()); +// synopsys translate_off +defparam \rgb[9]~output .bus_hold = "false"; +defparam \rgb[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y14_N23 +cycloneive_io_obuf \rgb[10]~output ( + .i(\vga_ctrl_inst|rgb[10]~4_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[10]), + .obar()); +// synopsys translate_off +defparam \rgb[10]~output .bus_hold = "false"; +defparam \rgb[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y13_N2 +cycloneive_io_obuf \rgb[11]~output ( + .i(\vga_ctrl_inst|rgb[11]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[11]), + .obar()); +// synopsys translate_off +defparam \rgb[11]~output .bus_hold = "false"; +defparam \rgb[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y18_N16 +cycloneive_io_obuf \rgb[12]~output ( + .i(\vga_ctrl_inst|rgb[12]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[12]), + .obar()); +// synopsys translate_off +defparam \rgb[12]~output .bus_hold = "false"; +defparam \rgb[12]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y18_N23 +cycloneive_io_obuf \rgb[13]~output ( + .i(\vga_ctrl_inst|rgb[11]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[13]), + .obar()); +// synopsys translate_off +defparam \rgb[13]~output .bus_hold = "false"; +defparam \rgb[13]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y19_N9 +cycloneive_io_obuf \rgb[14]~output ( + .i(\vga_ctrl_inst|rgb[12]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[14]), + .obar()); +// synopsys translate_off +defparam \rgb[14]~output .bus_hold = "false"; +defparam \rgb[14]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y20_N23 +cycloneive_io_obuf \rgb[15]~output ( + .i(\vga_ctrl_inst|rgb[12]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[15]), + .obar()); +// synopsys translate_off +defparam \rgb[15]~output .bus_hold = "false"; +defparam \rgb[15]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~0 ( +// Equation(s): +// \vga_ctrl_inst|Add0~0_combout = \vga_ctrl_inst|cnt_h [0] $ (VCC) +// \vga_ctrl_inst|Add0~1 = CARRY(\vga_ctrl_inst|cnt_h [0]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\vga_ctrl_inst|Add0~0_combout ), + .cout(\vga_ctrl_inst|Add0~1 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~0 .lut_mask = 16'h33CC; +defparam \vga_ctrl_inst|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y3_N0 +cycloneive_lcell_comb \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X35_Y3_N1 +dffeas \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .d(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y3_N10 +cycloneive_lcell_comb \rst_n~0 ( +// Equation(s): +// \rst_n~0_combout = ((!\sys_rst_n~input_o ) # (!\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q )) # (!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ) + + .dataa(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .datac(\sys_rst_n~input_o ), + .datad(gnd), + .cin(gnd), + .combout(\rst_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \rst_n~0 .lut_mask = 16'h7F7F; +defparam \rst_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G16 +cycloneive_clkctrl \rst_n~0clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~0_combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~0clkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~0clkctrl .clock_type = "global clock"; +defparam \rst_n~0clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X35_Y23_N9 +dffeas \vga_ctrl_inst|cnt_h[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[0] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~2 ( +// Equation(s): +// \vga_ctrl_inst|Add0~2_combout = (\vga_ctrl_inst|cnt_h [1] & (!\vga_ctrl_inst|Add0~1 )) # (!\vga_ctrl_inst|cnt_h [1] & ((\vga_ctrl_inst|Add0~1 ) # (GND))) +// \vga_ctrl_inst|Add0~3 = CARRY((!\vga_ctrl_inst|Add0~1 ) # (!\vga_ctrl_inst|cnt_h [1])) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~1 ), + .combout(\vga_ctrl_inst|Add0~2_combout ), + .cout(\vga_ctrl_inst|Add0~3 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~2 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~6 ( +// Equation(s): +// \vga_ctrl_inst|Add0~6_combout = (\vga_ctrl_inst|cnt_h [3] & (!\vga_ctrl_inst|Add0~5 )) # (!\vga_ctrl_inst|cnt_h [3] & ((\vga_ctrl_inst|Add0~5 ) # (GND))) +// \vga_ctrl_inst|Add0~7 = CARRY((!\vga_ctrl_inst|Add0~5 ) # (!\vga_ctrl_inst|cnt_h [3])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [3]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~5 ), + .combout(\vga_ctrl_inst|Add0~6_combout ), + .cout(\vga_ctrl_inst|Add0~7 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~6 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N15 +dffeas \vga_ctrl_inst|cnt_h[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [3]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[3] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~8 ( +// Equation(s): +// \vga_ctrl_inst|Add0~8_combout = (\vga_ctrl_inst|cnt_h [4] & (\vga_ctrl_inst|Add0~7 $ (GND))) # (!\vga_ctrl_inst|cnt_h [4] & (!\vga_ctrl_inst|Add0~7 & VCC)) +// \vga_ctrl_inst|Add0~9 = CARRY((\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|Add0~7 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [4]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~7 ), + .combout(\vga_ctrl_inst|Add0~8_combout ), + .cout(\vga_ctrl_inst|Add0~9 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~8 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N17 +dffeas \vga_ctrl_inst|cnt_h[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[4] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~10 ( +// Equation(s): +// \vga_ctrl_inst|Add0~10_combout = (\vga_ctrl_inst|cnt_h [5] & (!\vga_ctrl_inst|Add0~9 )) # (!\vga_ctrl_inst|cnt_h [5] & ((\vga_ctrl_inst|Add0~9 ) # (GND))) +// \vga_ctrl_inst|Add0~11 = CARRY((!\vga_ctrl_inst|Add0~9 ) # (!\vga_ctrl_inst|cnt_h [5])) + + .dataa(\vga_ctrl_inst|cnt_h [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~9 ), + .combout(\vga_ctrl_inst|Add0~10_combout ), + .cout(\vga_ctrl_inst|Add0~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~10 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~12 ( +// Equation(s): +// \vga_ctrl_inst|Add0~12_combout = (\vga_ctrl_inst|cnt_h [6] & (\vga_ctrl_inst|Add0~11 $ (GND))) # (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|Add0~11 & VCC)) +// \vga_ctrl_inst|Add0~13 = CARRY((\vga_ctrl_inst|cnt_h [6] & !\vga_ctrl_inst|Add0~11 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~11 ), + .combout(\vga_ctrl_inst|Add0~12_combout ), + .cout(\vga_ctrl_inst|Add0~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~12 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N21 +dffeas \vga_ctrl_inst|cnt_h[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [6]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[6] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~14 ( +// Equation(s): +// \vga_ctrl_inst|Add0~14_combout = (\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Add0~13 )) # (!\vga_ctrl_inst|cnt_h [7] & ((\vga_ctrl_inst|Add0~13 ) # (GND))) +// \vga_ctrl_inst|Add0~15 = CARRY((!\vga_ctrl_inst|Add0~13 ) # (!\vga_ctrl_inst|cnt_h [7])) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~13 ), + .combout(\vga_ctrl_inst|Add0~14_combout ), + .cout(\vga_ctrl_inst|Add0~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~14 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N23 +dffeas \vga_ctrl_inst|cnt_h[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [7]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[7] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N24 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~16 ( +// Equation(s): +// \vga_ctrl_inst|Add0~16_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|Add0~15 $ (GND))) # (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|Add0~15 & VCC)) +// \vga_ctrl_inst|Add0~17 = CARRY((\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|Add0~15 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~15 ), + .combout(\vga_ctrl_inst|Add0~16_combout ), + .cout(\vga_ctrl_inst|Add0~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~16 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N26 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~18 ( +// Equation(s): +// \vga_ctrl_inst|Add0~18_combout = \vga_ctrl_inst|Add0~17 $ (\vga_ctrl_inst|cnt_h [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(\vga_ctrl_inst|Add0~17 ), + .combout(\vga_ctrl_inst|Add0~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~18 .lut_mask = 16'h0FF0; +defparam \vga_ctrl_inst|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~1 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~1_combout = (!\vga_ctrl_inst|Equal0~3_combout & \vga_ctrl_inst|Add0~18_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|Add0~18_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~1 .lut_mask = 16'h3030; +defparam \vga_ctrl_inst|cnt_h~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N1 +dffeas \vga_ctrl_inst|cnt_h[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[9] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N24 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~0 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~0_combout = (\vga_ctrl_inst|Add0~10_combout & !\vga_ctrl_inst|Equal0~3_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add0~10_combout ), + .datac(\vga_ctrl_inst|Equal0~3_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~0 .lut_mask = 16'h0C0C; +defparam \vga_ctrl_inst|cnt_h~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y23_N25 +dffeas \vga_ctrl_inst|cnt_h[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [5]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[5] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N30 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~2 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~2_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|cnt_h [9] & (!\vga_ctrl_inst|cnt_h [5] & !\vga_ctrl_inst|cnt_h [6]))) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(\vga_ctrl_inst|cnt_h [9]), + .datac(\vga_ctrl_inst|cnt_h [5]), + .datad(\vga_ctrl_inst|cnt_h [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~2 .lut_mask = 16'h0008; +defparam \vga_ctrl_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N11 +dffeas \vga_ctrl_inst|cnt_h[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [1]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[1] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N28 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~1 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~1_combout = (\vga_ctrl_inst|cnt_h [2] & (\vga_ctrl_inst|cnt_h [3] & (\vga_ctrl_inst|cnt_h [0] & \vga_ctrl_inst|cnt_h [1]))) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(\vga_ctrl_inst|cnt_h [3]), + .datac(\vga_ctrl_inst|cnt_h [0]), + .datad(\vga_ctrl_inst|cnt_h [1]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~1 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~3 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~3_combout = (\vga_ctrl_inst|cnt_h [4] & (\vga_ctrl_inst|Equal0~2_combout & (\vga_ctrl_inst|Equal0~1_combout & !\vga_ctrl_inst|cnt_h [7]))) + + .dataa(\vga_ctrl_inst|cnt_h [4]), + .datab(\vga_ctrl_inst|Equal0~2_combout ), + .datac(\vga_ctrl_inst|Equal0~1_combout ), + .datad(\vga_ctrl_inst|cnt_h [7]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~3 .lut_mask = 16'h0080; +defparam \vga_ctrl_inst|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~2 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~2_combout = (\vga_ctrl_inst|Add0~16_combout & !\vga_ctrl_inst|Equal0~3_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add0~16_combout ), + .datac(\vga_ctrl_inst|Equal0~3_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~2 .lut_mask = 16'h0C0C; +defparam \vga_ctrl_inst|cnt_h~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N3 +dffeas \vga_ctrl_inst|cnt_h[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[8] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N4 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan2~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan2~0_combout = (!\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|cnt_h [9]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan2~0 .lut_mask = 16'h0033; +defparam \vga_ctrl_inst|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan0~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan0~0_combout = (\vga_ctrl_inst|cnt_h [7]) # (((\vga_ctrl_inst|cnt_h [6] & \vga_ctrl_inst|cnt_h [5])) # (!\vga_ctrl_inst|LessThan2~0_combout )) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(\vga_ctrl_inst|LessThan2~0_combout ), + .datad(\vga_ctrl_inst|cnt_h [5]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan0~0 .lut_mask = 16'hEFAF; +defparam \vga_ctrl_inst|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N28 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[0]~9 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[0]~9_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~0_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [0])))) + + .dataa(\vga_ctrl_inst|Add1~0_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [0]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[0]~9 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N29 +dffeas \vga_ctrl_inst|cnt_v[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[0]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[0] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N4 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[2]~8 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[2]~8_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~4_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [2])))) + + .dataa(\vga_ctrl_inst|Add1~4_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[2]~8 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N5 +dffeas \vga_ctrl_inst|cnt_v[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[2]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [2]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[2] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[4]~6 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[4]~6_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~8_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [4])))) + + .dataa(\vga_ctrl_inst|Add1~8_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [4]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[4]~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[4]~6 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[4]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N1 +dffeas \vga_ctrl_inst|cnt_v[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[4]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[4] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|always1~1 ( +// Equation(s): +// \vga_ctrl_inst|always1~1_combout = (\vga_ctrl_inst|cnt_v [9] & (\vga_ctrl_inst|cnt_v [3] & (\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|cnt_v [4]))) + + .dataa(\vga_ctrl_inst|cnt_v [9]), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|cnt_v [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~1 .lut_mask = 16'h0080; +defparam \vga_ctrl_inst|always1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[1]~0 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[1]~0_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~2_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [1])))) + + .dataa(\vga_ctrl_inst|Add1~2_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [1]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[1]~0 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N17 +dffeas \vga_ctrl_inst|cnt_v[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[1]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [1]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[1] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|always1~2 ( +// Equation(s): +// \vga_ctrl_inst|always1~2_combout = (\vga_ctrl_inst|always1~0_combout & (!\vga_ctrl_inst|cnt_v [0] & (\vga_ctrl_inst|always1~1_combout & !\vga_ctrl_inst|cnt_v [1]))) + + .dataa(\vga_ctrl_inst|always1~0_combout ), + .datab(\vga_ctrl_inst|cnt_v [0]), + .datac(\vga_ctrl_inst|always1~1_combout ), + .datad(\vga_ctrl_inst|cnt_v [1]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~2 .lut_mask = 16'h0020; +defparam \vga_ctrl_inst|always1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[3]~7 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[3]~7_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~6_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [3])))) + + .dataa(\vga_ctrl_inst|Add1~6_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [3]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[3]~7 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N3 +dffeas \vga_ctrl_inst|cnt_v[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[3]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [3]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[3] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan6~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan6~0_combout = (!\vga_ctrl_inst|cnt_v [3] & (!\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|cnt_v [4])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|cnt_v [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan6~0 .lut_mask = 16'h0003; +defparam \vga_ctrl_inst|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[5]~2 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[5]~2_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~10_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [5])))) + + .dataa(\vga_ctrl_inst|Add1~10_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [5]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[5]~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[5]~2 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[5]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N19 +dffeas \vga_ctrl_inst|cnt_v[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[5]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [5]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[5] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N24 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~14 ( +// Equation(s): +// \vga_ctrl_inst|Add1~14_combout = (\vga_ctrl_inst|cnt_v [7] & (!\vga_ctrl_inst|Add1~13 )) # (!\vga_ctrl_inst|cnt_v [7] & ((\vga_ctrl_inst|Add1~13 ) # (GND))) +// \vga_ctrl_inst|Add1~15 = CARRY((!\vga_ctrl_inst|Add1~13 ) # (!\vga_ctrl_inst|cnt_v [7])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [7]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~13 ), + .combout(\vga_ctrl_inst|Add1~14_combout ), + .cout(\vga_ctrl_inst|Add1~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~14 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[7]~4 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[7]~4_combout = (\vga_ctrl_inst|Equal0~3_combout & (!\vga_ctrl_inst|always1~2_combout & (\vga_ctrl_inst|Add1~14_combout ))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [7])))) + + .dataa(\vga_ctrl_inst|always1~2_combout ), + .datab(\vga_ctrl_inst|Add1~14_combout ), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[7]~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[7]~4 .lut_mask = 16'h44F0; +defparam \vga_ctrl_inst|cnt_v[7]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y24_N3 +dffeas \vga_ctrl_inst|cnt_v[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[7]~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [7]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[7] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N28 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~18 ( +// Equation(s): +// \vga_ctrl_inst|Add1~18_combout = \vga_ctrl_inst|Add1~17 $ (\vga_ctrl_inst|cnt_v [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_v [9]), + .cin(\vga_ctrl_inst|Add1~17 ), + .combout(\vga_ctrl_inst|Add1~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~18 .lut_mask = 16'h0FF0; +defparam \vga_ctrl_inst|Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[9]~1 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[9]~1_combout = (\vga_ctrl_inst|Equal0~3_combout & (!\vga_ctrl_inst|always1~2_combout & (\vga_ctrl_inst|Add1~18_combout ))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [9])))) + + .dataa(\vga_ctrl_inst|always1~2_combout ), + .datab(\vga_ctrl_inst|Add1~18_combout ), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[9]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[9]~1 .lut_mask = 16'h44F0; +defparam \vga_ctrl_inst|cnt_v[9]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y24_N1 +dffeas \vga_ctrl_inst|cnt_v[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[9]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[9] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N4 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[6]~5 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[6]~5_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~12_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [6])))) + + .dataa(\vga_ctrl_inst|Add1~12_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [6]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[6]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[6]~5 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[6]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y24_N5 +dffeas \vga_ctrl_inst|cnt_v[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[6]~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [6]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[6] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|always1~0 ( +// Equation(s): +// \vga_ctrl_inst|always1~0_combout = (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|cnt_v [5] & (!\vga_ctrl_inst|cnt_v [7] & !\vga_ctrl_inst|cnt_v [6]))) + + .dataa(\vga_ctrl_inst|cnt_v [8]), + .datab(\vga_ctrl_inst|cnt_v [5]), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|cnt_v [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~0 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan1~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan1~0_combout = ((\vga_ctrl_inst|cnt_v [1]) # ((\vga_ctrl_inst|cnt_v [9]) # (!\vga_ctrl_inst|always1~0_combout ))) # (!\vga_ctrl_inst|LessThan6~0_combout ) + + .dataa(\vga_ctrl_inst|LessThan6~0_combout ), + .datab(\vga_ctrl_inst|cnt_v [1]), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(\vga_ctrl_inst|always1~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan1~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan1~0 .lut_mask = 16'hFDFF; +defparam \vga_ctrl_inst|LessThan1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan6~1 ( +// Equation(s): +// \vga_ctrl_inst|LessThan6~1_combout = (!\vga_ctrl_inst|cnt_v [1]) # (!\vga_ctrl_inst|cnt_v [0]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [0]), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_v [1]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan6~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan6~1 .lut_mask = 16'h33FF; +defparam \vga_ctrl_inst|LessThan6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N30 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~1 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~1_combout = (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|cnt_v [9] & (!\vga_ctrl_inst|cnt_v [7] & !\vga_ctrl_inst|cnt_v [6]))) + + .dataa(\vga_ctrl_inst|cnt_v [8]), + .datab(\vga_ctrl_inst|cnt_v [9]), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|cnt_v [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~1 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|pix_data_req~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N24 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~2 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~2_combout = (\vga_ctrl_inst|LessThan6~0_combout & ((\vga_ctrl_inst|LessThan6~1_combout & (\vga_ctrl_inst|pix_data_req~1_combout )) # (!\vga_ctrl_inst|LessThan6~1_combout & ((\vga_ctrl_inst|always1~0_combout ))))) # +// (!\vga_ctrl_inst|LessThan6~0_combout & (((\vga_ctrl_inst|always1~0_combout )))) + + .dataa(\vga_ctrl_inst|LessThan6~0_combout ), + .datab(\vga_ctrl_inst|LessThan6~1_combout ), + .datac(\vga_ctrl_inst|pix_data_req~1_combout ), + .datad(\vga_ctrl_inst|always1~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~2 .lut_mask = 16'hF780; +defparam \vga_ctrl_inst|pix_data_req~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N28 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan2~1 ( +// Equation(s): +// \vga_ctrl_inst|LessThan2~1_combout = (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|cnt_h [5])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(\vga_ctrl_inst|cnt_h [4]), + .datad(\vga_ctrl_inst|cnt_h [5]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan2~1 .lut_mask = 16'h0003; +defparam \vga_ctrl_inst|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|rgb_valid~0 ( +// Equation(s): +// \vga_ctrl_inst|rgb_valid~0_combout = (\vga_ctrl_inst|Equal0~0_combout & (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|LessThan2~0_combout & \vga_ctrl_inst|LessThan2~1_combout ))) # (!\vga_ctrl_inst|Equal0~0_combout & (((\vga_ctrl_inst|cnt_h [7] & +// !\vga_ctrl_inst|LessThan2~1_combout )) # (!\vga_ctrl_inst|LessThan2~0_combout ))) + + .dataa(\vga_ctrl_inst|Equal0~0_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|LessThan2~0_combout ), + .datad(\vga_ctrl_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb_valid~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb_valid~0 .lut_mask = 16'h0745; +defparam \vga_ctrl_inst|rgb_valid~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~1 ( +// Equation(s): +// \vga_ctrl_inst|Add2~1_cout = CARRY((\vga_ctrl_inst|cnt_h [1] & \vga_ctrl_inst|cnt_h [0])) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(\vga_ctrl_inst|cnt_h [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\vga_ctrl_inst|Add2~1_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~1 .lut_mask = 16'h0088; +defparam \vga_ctrl_inst|Add2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~3 ( +// Equation(s): +// \vga_ctrl_inst|Add2~3_cout = CARRY((!\vga_ctrl_inst|Add2~1_cout ) # (!\vga_ctrl_inst|cnt_h [2])) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~1_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~3_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~3 .lut_mask = 16'h005F; +defparam \vga_ctrl_inst|Add2~3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~5 ( +// Equation(s): +// \vga_ctrl_inst|Add2~5_cout = CARRY((\vga_ctrl_inst|cnt_h [3] & !\vga_ctrl_inst|Add2~3_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~3_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~5_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~5 .lut_mask = 16'h000A; +defparam \vga_ctrl_inst|Add2~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~7 ( +// Equation(s): +// \vga_ctrl_inst|Add2~7_cout = CARRY((!\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|Add2~5_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~5_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~7_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~7 .lut_mask = 16'h0005; +defparam \vga_ctrl_inst|Add2~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~9 ( +// Equation(s): +// \vga_ctrl_inst|Add2~9_cout = CARRY((\vga_ctrl_inst|cnt_h [5]) # (!\vga_ctrl_inst|Add2~7_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~7_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~9_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~9 .lut_mask = 16'h00AF; +defparam \vga_ctrl_inst|Add2~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~10 ( +// Equation(s): +// \vga_ctrl_inst|Add2~10_combout = (\vga_ctrl_inst|cnt_h [6] & (\vga_ctrl_inst|Add2~9_cout & VCC)) # (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|Add2~9_cout )) +// \vga_ctrl_inst|Add2~11 = CARRY((!\vga_ctrl_inst|cnt_h [6] & !\vga_ctrl_inst|Add2~9_cout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~9_cout ), + .combout(\vga_ctrl_inst|Add2~10_combout ), + .cout(\vga_ctrl_inst|Add2~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~10 .lut_mask = 16'hC303; +defparam \vga_ctrl_inst|Add2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~12 ( +// Equation(s): +// \vga_ctrl_inst|Add2~12_combout = (\vga_ctrl_inst|cnt_h [7] & (\vga_ctrl_inst|Add2~11 $ (GND))) # (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Add2~11 & VCC)) +// \vga_ctrl_inst|Add2~13 = CARRY((\vga_ctrl_inst|cnt_h [7] & !\vga_ctrl_inst|Add2~11 )) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~11 ), + .combout(\vga_ctrl_inst|Add2~12_combout ), + .cout(\vga_ctrl_inst|Add2~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~12 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N24 +cycloneive_lcell_comb \vga_pic_inst|LessThan14~0 ( +// Equation(s): +// \vga_pic_inst|LessThan14~0_combout = (\vga_ctrl_inst|Add2~12_combout & \vga_ctrl_inst|Add2~10_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan14~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan14~0 .lut_mask = 16'hCC00; +defparam \vga_pic_inst|LessThan14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~14 ( +// Equation(s): +// \vga_ctrl_inst|Add2~14_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|Add2~13 & VCC)) # (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|Add2~13 )) +// \vga_ctrl_inst|Add2~15 = CARRY((!\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|Add2~13 )) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~13 ), + .combout(\vga_ctrl_inst|Add2~14_combout ), + .cout(\vga_ctrl_inst|Add2~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~14 .lut_mask = 16'hA505; +defparam \vga_ctrl_inst|Add2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~16 ( +// Equation(s): +// \vga_ctrl_inst|Add2~16_combout = \vga_ctrl_inst|cnt_h [9] $ (\vga_ctrl_inst|Add2~15 ) + + .dataa(\vga_ctrl_inst|cnt_h [9]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\vga_ctrl_inst|Add2~15 ), + .combout(\vga_ctrl_inst|Add2~16_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~16 .lut_mask = 16'h5A5A; +defparam \vga_ctrl_inst|Add2~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N2 +cycloneive_lcell_comb \vga_pic_inst|LessThan6~0 ( +// Equation(s): +// \vga_pic_inst|LessThan6~0_combout = ((\vga_pic_inst|LessThan14~0_combout ) # ((\vga_ctrl_inst|Add2~16_combout ) # (\vga_ctrl_inst|Add2~14_combout ))) # (!\vga_ctrl_inst|pix_data_req~4_combout ) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_pic_inst|LessThan14~0_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan6~0 .lut_mask = 16'hFFFD; +defparam \vga_pic_inst|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N26 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~0 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~0_combout = (!\vga_ctrl_inst|always1~0_combout & \vga_ctrl_inst|cnt_v [9]) + + .dataa(\vga_ctrl_inst|always1~0_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~0 .lut_mask = 16'h5050; +defparam \vga_ctrl_inst|pix_data_req~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N4 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan4~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan4~0_combout = (\vga_ctrl_inst|LessThan2~0_combout & (((!\vga_ctrl_inst|Equal0~1_combout & \vga_ctrl_inst|LessThan2~1_combout )) # (!\vga_ctrl_inst|cnt_h [7]))) + + .dataa(\vga_ctrl_inst|Equal0~1_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|LessThan2~0_combout ), + .datad(\vga_ctrl_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan4~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan4~0 .lut_mask = 16'h7030; +defparam \vga_ctrl_inst|LessThan4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~3 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~3_combout = ((!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Equal0~1_combout & \vga_ctrl_inst|LessThan2~1_combout ))) # (!\vga_ctrl_inst|Equal0~0_combout ) + + .dataa(\vga_ctrl_inst|Equal0~0_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|Equal0~1_combout ), + .datad(\vga_ctrl_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~3 .lut_mask = 16'h5755; +defparam \vga_ctrl_inst|pix_data_req~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~4 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~4_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (!\vga_ctrl_inst|LessThan4~0_combout & \vga_ctrl_inst|pix_data_req~3_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|LessThan4~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~4 .lut_mask = 16'h0100; +defparam \vga_ctrl_inst|pix_data_req~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N2 +cycloneive_lcell_comb \vga_pic_inst|pix_data~4 ( +// Equation(s): +// \vga_pic_inst|pix_data~4_combout = (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~12_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|pix_data_req~4_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~4 .lut_mask = 16'h00CC; +defparam \vga_pic_inst|pix_data~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~9 ( +// Equation(s): +// \vga_pic_inst|pix_data~9_combout = (\vga_pic_inst|pix_data~8_combout & ((\vga_pic_inst|LessThan6~0_combout ) # ((!\vga_ctrl_inst|Add2~14_combout & \vga_pic_inst|pix_data~4_combout )))) # (!\vga_pic_inst|pix_data~8_combout & +// (((!\vga_ctrl_inst|Add2~14_combout & \vga_pic_inst|pix_data~4_combout )))) + + .dataa(\vga_pic_inst|pix_data~8_combout ), + .datab(\vga_pic_inst|LessThan6~0_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_pic_inst|pix_data~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~9_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~9 .lut_mask = 16'h8F88; +defparam \vga_pic_inst|pix_data~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N8 +cycloneive_lcell_comb \vga_pic_inst|LessThan17~0 ( +// Equation(s): +// \vga_pic_inst|LessThan17~0_combout = (\vga_ctrl_inst|Add2~12_combout ) # ((\vga_ctrl_inst|Add2~10_combout ) # ((\vga_ctrl_inst|Add2~14_combout ) # (!\vga_ctrl_inst|pix_data_req~4_combout ))) + + .dataa(\vga_ctrl_inst|Add2~12_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan17~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan17~0 .lut_mask = 16'hFEFF; +defparam \vga_pic_inst|LessThan17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N14 +cycloneive_lcell_comb \vga_pic_inst|pix_data~6 ( +// Equation(s): +// \vga_pic_inst|pix_data~6_combout = ((\vga_pic_inst|LessThan17~0_combout & ((\vga_ctrl_inst|Add2~14_combout ) # (!\vga_pic_inst|pix_data~4_combout )))) # (!\vga_pic_inst|pix_data[4]~5_combout ) + + .dataa(\vga_pic_inst|pix_data[4]~5_combout ), + .datab(\vga_pic_inst|pix_data~4_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_pic_inst|LessThan17~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~6 .lut_mask = 16'hF755; +defparam \vga_pic_inst|pix_data~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N22 +cycloneive_lcell_comb \vga_pic_inst|pix_data[4]~10 ( +// Equation(s): +// \vga_pic_inst|pix_data[4]~10_combout = (!\vga_ctrl_inst|Add2~12_combout ) # (!\vga_ctrl_inst|Add2~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[4]~10_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4]~10 .lut_mask = 16'h0FFF; +defparam \vga_pic_inst|pix_data[4]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~11 ( +// Equation(s): +// \vga_pic_inst|pix_data~11_combout = (\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|Add2~12_combout & (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~10_combout ))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~11_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~11 .lut_mask = 16'h0080; +defparam \vga_pic_inst|pix_data~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N24 +cycloneive_lcell_comb \vga_pic_inst|pix_data~12 ( +// Equation(s): +// \vga_pic_inst|pix_data~12_combout = (\vga_pic_inst|pix_data[4]~5_combout & (((\vga_pic_inst|pix_data[4]~10_combout ) # (!\vga_pic_inst|pix_data~11_combout )))) # (!\vga_pic_inst|pix_data[4]~5_combout & (\vga_pic_inst|LessThan17~0_combout )) + + .dataa(\vga_pic_inst|pix_data[4]~5_combout ), + .datab(\vga_pic_inst|LessThan17~0_combout ), + .datac(\vga_pic_inst|pix_data[4]~10_combout ), + .datad(\vga_pic_inst|pix_data~11_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~12_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~12 .lut_mask = 16'hE4EE; +defparam \vga_pic_inst|pix_data~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N16 +cycloneive_lcell_comb \vga_pic_inst|pix_data~13 ( +// Equation(s): +// \vga_pic_inst|pix_data~13_combout = ((\vga_pic_inst|pix_data[4]~7_combout & (\vga_pic_inst|pix_data~9_combout & \vga_pic_inst|pix_data~6_combout ))) # (!\vga_pic_inst|pix_data~12_combout ) + + .dataa(\vga_pic_inst|pix_data[4]~7_combout ), + .datab(\vga_pic_inst|pix_data~9_combout ), + .datac(\vga_pic_inst|pix_data~6_combout ), + .datad(\vga_pic_inst|pix_data~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~13_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~13 .lut_mask = 16'h80FF; +defparam \vga_pic_inst|pix_data~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N17 +dffeas \vga_pic_inst|pix_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[0] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N0 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[0]~0 ( +// Equation(s): +// \vga_ctrl_inst|rgb[0]~0_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (\vga_ctrl_inst|rgb_valid~0_combout & (\vga_pic_inst|pix_data [0] & !\vga_ctrl_inst|pix_data_req~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|rgb_valid~0_combout ), + .datac(\vga_pic_inst|pix_data [0]), + .datad(\vga_ctrl_inst|pix_data_req~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[0]~0 .lut_mask = 16'h0040; +defparam \vga_ctrl_inst|rgb[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data[4]~7 ( +// Equation(s): +// \vga_pic_inst|pix_data[4]~7_combout = (!\vga_ctrl_inst|Add2~16_combout & (\vga_ctrl_inst|pix_data_req~4_combout & ((!\vga_ctrl_inst|Add2~14_combout ) # (!\vga_ctrl_inst|Add2~12_combout )))) + + .dataa(\vga_ctrl_inst|Add2~12_combout ), + .datab(\vga_ctrl_inst|Add2~14_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[4]~7_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4]~7 .lut_mask = 16'h0700; +defparam \vga_pic_inst|pix_data[4]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N18 +cycloneive_lcell_comb \vga_pic_inst|pix_data~16 ( +// Equation(s): +// \vga_pic_inst|pix_data~16_combout = (\vga_pic_inst|pix_data~15_combout ) # ((\vga_pic_inst|pix_data[4]~7_combout & (\vga_pic_inst|pix_data~9_combout & \vga_pic_inst|pix_data~6_combout ))) + + .dataa(\vga_pic_inst|pix_data~15_combout ), + .datab(\vga_pic_inst|pix_data[4]~7_combout ), + .datac(\vga_pic_inst|pix_data~9_combout ), + .datad(\vga_pic_inst|pix_data~6_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~16_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~16 .lut_mask = 16'hEAAA; +defparam \vga_pic_inst|pix_data~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N19 +dffeas \vga_pic_inst|pix_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N26 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[1]~1 ( +// Equation(s): +// \vga_ctrl_inst|rgb[1]~1_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [4]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[1]~1 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data~25 ( +// Equation(s): +// \vga_pic_inst|pix_data~25_combout = (\vga_ctrl_inst|Add2~16_combout & (((!\vga_pic_inst|LessThan17~0_combout )))) # (!\vga_ctrl_inst|Add2~16_combout & ((\vga_ctrl_inst|pix_data_req~4_combout & (\vga_pic_inst|pix_data~17_combout )) # +// (!\vga_ctrl_inst|pix_data_req~4_combout & ((!\vga_pic_inst|LessThan17~0_combout ))))) + + .dataa(\vga_pic_inst|pix_data~17_combout ), + .datab(\vga_ctrl_inst|Add2~16_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_pic_inst|LessThan17~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~25_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~25 .lut_mask = 16'h20EF; +defparam \vga_pic_inst|pix_data~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y23_N13 +dffeas \vga_pic_inst|pix_data[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[8] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N30 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[5]~2 ( +// Equation(s): +// \vga_ctrl_inst|rgb[5]~2_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [8]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [8]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[5]~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[5]~2 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[5]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N28 +cycloneive_lcell_comb \vga_pic_inst|pix_data~18 ( +// Equation(s): +// \vga_pic_inst|pix_data~18_combout = (\vga_ctrl_inst|pix_data_req~4_combout & ((\vga_ctrl_inst|Add2~14_combout & (!\vga_ctrl_inst|Add2~12_combout & !\vga_ctrl_inst|Add2~10_combout )) # (!\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|Add2~12_combout +// )))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~18 .lut_mask = 16'h4060; +defparam \vga_pic_inst|pix_data~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data~14 ( +// Equation(s): +// \vga_pic_inst|pix_data~14_combout = (!\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~12_combout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add2~14_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~14_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~14 .lut_mask = 16'h0030; +defparam \vga_pic_inst|pix_data~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N30 +cycloneive_lcell_comb \vga_pic_inst|pix_data~26 ( +// Equation(s): +// \vga_pic_inst|pix_data~26_combout = (\vga_ctrl_inst|pix_data_req~4_combout & ((\vga_ctrl_inst|Add2~16_combout & ((\vga_pic_inst|pix_data~14_combout ))) # (!\vga_ctrl_inst|Add2~16_combout & (\vga_pic_inst|pix_data~18_combout )))) # +// (!\vga_ctrl_inst|pix_data_req~4_combout & (((\vga_pic_inst|pix_data~14_combout )))) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_pic_inst|pix_data~18_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_pic_inst|pix_data~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~26_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~26 .lut_mask = 16'hFD08; +defparam \vga_pic_inst|pix_data~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data~19 ( +// Equation(s): +// \vga_pic_inst|pix_data~19_combout = (\vga_pic_inst|pix_data~26_combout & \vga_pic_inst|pix_data~6_combout ) + + .dataa(gnd), + .datab(\vga_pic_inst|pix_data~26_combout ), + .datac(gnd), + .datad(\vga_pic_inst|pix_data~6_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~19_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~19 .lut_mask = 16'hCC00; +defparam \vga_pic_inst|pix_data~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y24_N1 +dffeas \vga_pic_inst|pix_data[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[9] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[7]~3 ( +// Equation(s): +// \vga_ctrl_inst|rgb[7]~3_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [9]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[7]~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[7]~3 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[7]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N6 +cycloneive_lcell_comb \vga_pic_inst|LessThan2~2 ( +// Equation(s): +// \vga_pic_inst|LessThan2~2_combout = (\vga_pic_inst|LessThan17~0_combout ) # ((\vga_ctrl_inst|Add2~16_combout ) # (!\vga_ctrl_inst|pix_data_req~4_combout )) + + .dataa(\vga_pic_inst|LessThan17~0_combout ), + .datab(\vga_ctrl_inst|Add2~16_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan2~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan2~2 .lut_mask = 16'hEEFF; +defparam \vga_pic_inst|LessThan2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data~20 ( +// Equation(s): +// \vga_pic_inst|pix_data~20_combout = (!\vga_ctrl_inst|Add2~16_combout & (!\vga_ctrl_inst|Add2~14_combout & \vga_ctrl_inst|pix_data_req~4_combout )) + + .dataa(\vga_ctrl_inst|Add2~16_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~20_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~20 .lut_mask = 16'h0500; +defparam \vga_pic_inst|pix_data~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~21 ( +// Equation(s): +// \vga_pic_inst|pix_data~21_combout = (\vga_pic_inst|LessThan2~2_combout & ((\vga_pic_inst|pix_data~26_combout ) # ((\vga_pic_inst|pix_data~4_combout & \vga_pic_inst|pix_data~20_combout )))) + + .dataa(\vga_pic_inst|pix_data~4_combout ), + .datab(\vga_pic_inst|pix_data~26_combout ), + .datac(\vga_pic_inst|LessThan2~2_combout ), + .datad(\vga_pic_inst|pix_data~20_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~21_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~21 .lut_mask = 16'hE0C0; +defparam \vga_pic_inst|pix_data~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y24_N27 +dffeas \vga_pic_inst|pix_data[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [10]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[10] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N2 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[10]~4 ( +// Equation(s): +// \vga_ctrl_inst|rgb[10]~4_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [10]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [10]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[10]~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[10]~4 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[10]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N20 +cycloneive_lcell_comb \vga_pic_inst|pix_data~22 ( +// Equation(s): +// \vga_pic_inst|pix_data~22_combout = ((\vga_pic_inst|pix_data[4]~5_combout & (!\vga_ctrl_inst|Add2~14_combout & \vga_pic_inst|pix_data~4_combout ))) # (!\vga_pic_inst|LessThan6~0_combout ) + + .dataa(\vga_pic_inst|pix_data[4]~5_combout ), + .datab(\vga_pic_inst|LessThan6~0_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_pic_inst|pix_data~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~22_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~22 .lut_mask = 16'h3B33; +defparam \vga_pic_inst|pix_data~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N28 +cycloneive_lcell_comb \vga_pic_inst|pix_data~23 ( +// Equation(s): +// \vga_pic_inst|pix_data~23_combout = ((\vga_pic_inst|pix_data[4]~7_combout & ((\vga_pic_inst|pix_data~22_combout ) # (!\vga_pic_inst|LessThan2~2_combout )))) # (!\vga_pic_inst|pix_data~12_combout ) + + .dataa(\vga_pic_inst|LessThan2~2_combout ), + .datab(\vga_pic_inst|pix_data~12_combout ), + .datac(\vga_pic_inst|pix_data~22_combout ), + .datad(\vga_pic_inst|pix_data[4]~7_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~23_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~23 .lut_mask = 16'hF733; +defparam \vga_pic_inst|pix_data~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N29 +dffeas \vga_pic_inst|pix_data[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [13]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[11]~5 ( +// Equation(s): +// \vga_ctrl_inst|rgb[11]~5_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (\vga_pic_inst|pix_data [13] & (\vga_ctrl_inst|rgb_valid~0_combout & !\vga_ctrl_inst|pix_data_req~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_pic_inst|pix_data [13]), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[11]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[11]~5 .lut_mask = 16'h0040; +defparam \vga_ctrl_inst|rgb[11]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N30 +cycloneive_lcell_comb \vga_pic_inst|pix_data~24 ( +// Equation(s): +// \vga_pic_inst|pix_data~24_combout = (\vga_pic_inst|pix_data~15_combout ) # ((\vga_pic_inst|pix_data[4]~7_combout & ((\vga_pic_inst|pix_data~22_combout ) # (!\vga_pic_inst|LessThan2~2_combout )))) + + .dataa(\vga_pic_inst|pix_data~15_combout ), + .datab(\vga_pic_inst|pix_data[4]~7_combout ), + .datac(\vga_pic_inst|pix_data~22_combout ), + .datad(\vga_pic_inst|LessThan2~2_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~24_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~24 .lut_mask = 16'hEAEE; +defparam \vga_pic_inst|pix_data~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N31 +dffeas \vga_pic_inst|pix_data[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [15]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[15] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[12]~6 ( +// Equation(s): +// \vga_ctrl_inst|rgb[12]~6_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (\vga_pic_inst|pix_data [15] & (\vga_ctrl_inst|rgb_valid~0_combout & !\vga_ctrl_inst|pix_data_req~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_pic_inst|pix_data [15]), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[12]~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[12]~6 .lut_mask = 16'h0040; +defparam \vga_ctrl_inst|rgb[12]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +endmodule diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_0c_slow.vo b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_0c_slow.vo new file mode 100644 index 0000000..d5b549e --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_0c_slow.vo @@ -0,0 +1,2833 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 04:42:20" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module vga_colorbar ( + sys_clk, + sys_rst_n, + hsync, + vsync, + rgb); +input sys_clk; +input sys_rst_n; +output hsync; +output vsync; +output [15:0] rgb; + +// Design Ports Information +// hsync => Location: PIN_AA18, I/O Standard: 2.5 V, Current Strength: Default +// vsync => Location: PIN_AB17, I/O Standard: 2.5 V, Current Strength: Default +// rgb[0] => Location: PIN_AB18, I/O Standard: 2.5 V, Current Strength: Default +// rgb[1] => Location: PIN_AA19, I/O Standard: 2.5 V, Current Strength: Default +// rgb[2] => Location: PIN_AB19, I/O Standard: 2.5 V, Current Strength: Default +// rgb[3] => Location: PIN_Y21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[4] => Location: PIN_W19, I/O Standard: 2.5 V, Current Strength: Default +// rgb[5] => Location: PIN_W20, I/O Standard: 2.5 V, Current Strength: Default +// rgb[6] => Location: PIN_U21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[7] => Location: PIN_U22, I/O Standard: 2.5 V, Current Strength: Default +// rgb[8] => Location: PIN_N20, I/O Standard: 2.5 V, Current Strength: Default +// rgb[9] => Location: PIN_N21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[10] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[11] => Location: PIN_M22, I/O Standard: 2.5 V, Current Strength: Default +// rgb[12] => Location: PIN_L21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[13] => Location: PIN_L22, I/O Standard: 2.5 V, Current Strength: Default +// rgb[14] => Location: PIN_K21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[15] => Location: PIN_J21, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("vga_colorbar_8_1200mv_0c_v_slow.sdo"); +// synopsys translate_on + +wire \vga_ctrl_inst|Add0~4_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ; +wire \vga_ctrl_inst|Add1~0_combout ; +wire \vga_ctrl_inst|Add1~2_combout ; +wire \vga_ctrl_inst|Add1~4_combout ; +wire \vga_ctrl_inst|Add1~6_combout ; +wire \vga_ctrl_inst|Add1~8_combout ; +wire \vga_ctrl_inst|Add1~10_combout ; +wire \vga_ctrl_inst|Add1~12_combout ; +wire \vga_ctrl_inst|Add1~16_combout ; +wire \vga_ctrl_inst|Equal0~0_combout ; +wire \vga_ctrl_inst|cnt_v[8]~3_combout ; +wire \vga_pic_inst|pix_data[4]~5_combout ; +wire \vga_pic_inst|pix_data~8_combout ; +wire \vga_pic_inst|pix_data~15_combout ; +wire \vga_pic_inst|pix_data~17_combout ; +wire \sys_clk~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \vga_ctrl_inst|Add0~0_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \sys_rst_n~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ; +wire \rst_n~0_combout ; +wire \rst_n~0clkctrl_outclk ; +wire \vga_ctrl_inst|Add0~1 ; +wire \vga_ctrl_inst|Add0~3 ; +wire \vga_ctrl_inst|Add0~5 ; +wire \vga_ctrl_inst|Add0~6_combout ; +wire \vga_ctrl_inst|Add0~7 ; +wire \vga_ctrl_inst|Add0~8_combout ; +wire \vga_ctrl_inst|Add0~9 ; +wire \vga_ctrl_inst|Add0~11 ; +wire \vga_ctrl_inst|Add0~12_combout ; +wire \vga_ctrl_inst|Add0~13 ; +wire \vga_ctrl_inst|Add0~14_combout ; +wire \vga_ctrl_inst|Add0~15 ; +wire \vga_ctrl_inst|Add0~16_combout ; +wire \vga_ctrl_inst|Add0~17 ; +wire \vga_ctrl_inst|Add0~18_combout ; +wire \vga_ctrl_inst|cnt_h~1_combout ; +wire \vga_ctrl_inst|Add0~10_combout ; +wire \vga_ctrl_inst|cnt_h~0_combout ; +wire \vga_ctrl_inst|Equal0~2_combout ; +wire \vga_ctrl_inst|Add0~2_combout ; +wire \vga_ctrl_inst|Equal0~1_combout ; +wire \vga_ctrl_inst|Equal0~3_combout ; +wire \vga_ctrl_inst|cnt_h~2_combout ; +wire \vga_ctrl_inst|LessThan2~0_combout ; +wire \vga_ctrl_inst|LessThan0~0_combout ; +wire \vga_ctrl_inst|cnt_v[0]~9_combout ; +wire \vga_ctrl_inst|cnt_v[2]~8_combout ; +wire \vga_ctrl_inst|cnt_v[4]~6_combout ; +wire \vga_ctrl_inst|always1~1_combout ; +wire \vga_ctrl_inst|cnt_v[1]~0_combout ; +wire \vga_ctrl_inst|always1~2_combout ; +wire \vga_ctrl_inst|cnt_v[3]~7_combout ; +wire \vga_ctrl_inst|LessThan6~0_combout ; +wire \vga_ctrl_inst|cnt_v[5]~2_combout ; +wire \vga_ctrl_inst|Add1~1 ; +wire \vga_ctrl_inst|Add1~3 ; +wire \vga_ctrl_inst|Add1~5 ; +wire \vga_ctrl_inst|Add1~7 ; +wire \vga_ctrl_inst|Add1~9 ; +wire \vga_ctrl_inst|Add1~11 ; +wire \vga_ctrl_inst|Add1~13 ; +wire \vga_ctrl_inst|Add1~14_combout ; +wire \vga_ctrl_inst|cnt_v[7]~4_combout ; +wire \vga_ctrl_inst|Add1~15 ; +wire \vga_ctrl_inst|Add1~17 ; +wire \vga_ctrl_inst|Add1~18_combout ; +wire \vga_ctrl_inst|cnt_v[9]~1_combout ; +wire \vga_ctrl_inst|cnt_v[6]~5_combout ; +wire \vga_ctrl_inst|always1~0_combout ; +wire \vga_ctrl_inst|LessThan1~0_combout ; +wire \vga_ctrl_inst|LessThan6~1_combout ; +wire \vga_ctrl_inst|pix_data_req~1_combout ; +wire \vga_ctrl_inst|pix_data_req~2_combout ; +wire \vga_ctrl_inst|LessThan2~1_combout ; +wire \vga_ctrl_inst|rgb_valid~0_combout ; +wire \vga_ctrl_inst|Add2~1_cout ; +wire \vga_ctrl_inst|Add2~3_cout ; +wire \vga_ctrl_inst|Add2~5_cout ; +wire \vga_ctrl_inst|Add2~7_cout ; +wire \vga_ctrl_inst|Add2~9_cout ; +wire \vga_ctrl_inst|Add2~11 ; +wire \vga_ctrl_inst|Add2~12_combout ; +wire \vga_ctrl_inst|Add2~10_combout ; +wire \vga_pic_inst|LessThan14~0_combout ; +wire \vga_ctrl_inst|Add2~13 ; +wire \vga_ctrl_inst|Add2~15 ; +wire \vga_ctrl_inst|Add2~16_combout ; +wire \vga_ctrl_inst|Add2~14_combout ; +wire \vga_pic_inst|LessThan6~0_combout ; +wire \vga_ctrl_inst|pix_data_req~0_combout ; +wire \vga_ctrl_inst|LessThan4~0_combout ; +wire \vga_ctrl_inst|pix_data_req~3_combout ; +wire \vga_ctrl_inst|pix_data_req~4_combout ; +wire \vga_pic_inst|pix_data~4_combout ; +wire \vga_pic_inst|pix_data~9_combout ; +wire \vga_pic_inst|LessThan17~0_combout ; +wire \vga_pic_inst|pix_data~6_combout ; +wire \vga_pic_inst|pix_data[4]~10_combout ; +wire \vga_pic_inst|pix_data~11_combout ; +wire \vga_pic_inst|pix_data~12_combout ; +wire \vga_pic_inst|pix_data~13_combout ; +wire \vga_ctrl_inst|rgb[0]~0_combout ; +wire \vga_pic_inst|pix_data[4]~7_combout ; +wire \vga_pic_inst|pix_data~16_combout ; +wire \vga_ctrl_inst|rgb[1]~1_combout ; +wire \vga_pic_inst|pix_data~25_combout ; +wire \vga_ctrl_inst|rgb[5]~2_combout ; +wire \vga_pic_inst|pix_data~18_combout ; +wire \vga_pic_inst|pix_data~14_combout ; +wire \vga_pic_inst|pix_data~26_combout ; +wire \vga_pic_inst|pix_data~19_combout ; +wire \vga_ctrl_inst|rgb[7]~3_combout ; +wire \vga_pic_inst|LessThan2~2_combout ; +wire \vga_pic_inst|pix_data~20_combout ; +wire \vga_pic_inst|pix_data~21_combout ; +wire \vga_ctrl_inst|rgb[10]~4_combout ; +wire \vga_pic_inst|pix_data~22_combout ; +wire \vga_pic_inst|pix_data~23_combout ; +wire \vga_ctrl_inst|rgb[11]~5_combout ; +wire \vga_pic_inst|pix_data~24_combout ; +wire \vga_ctrl_inst|rgb[12]~6_combout ; +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk ; +wire [9:0] \vga_ctrl_inst|cnt_v ; +wire [9:0] \vga_ctrl_inst|cnt_h ; +wire [15:0] \vga_pic_inst|pix_data ; + +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ; + +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [3] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [4] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [4]; + +// Location: LCCOMB_X35_Y23_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~4 ( +// Equation(s): +// \vga_ctrl_inst|Add0~4_combout = (\vga_ctrl_inst|cnt_h [2] & (\vga_ctrl_inst|Add0~3 $ (GND))) # (!\vga_ctrl_inst|cnt_h [2] & (!\vga_ctrl_inst|Add0~3 & VCC)) +// \vga_ctrl_inst|Add0~5 = CARRY((\vga_ctrl_inst|cnt_h [2] & !\vga_ctrl_inst|Add0~3 )) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~3 ), + .combout(\vga_ctrl_inst|Add0~4_combout ), + .cout(\vga_ctrl_inst|Add0~5 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~4 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: PLL_2 +cycloneive_pll \clk_gen_inst|altpll_component|auto_generated|pll1 ( + .areset(!\sys_rst_n~input_o ), + .pfdena(vcc), + .fbin(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\sys_clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_high = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_low = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_divide_by = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_multiply_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .n = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pll_compensation_delay = 5989; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~0 ( +// Equation(s): +// \vga_ctrl_inst|Add1~0_combout = \vga_ctrl_inst|cnt_v [0] $ (VCC) +// \vga_ctrl_inst|Add1~1 = CARRY(\vga_ctrl_inst|cnt_v [0]) + + .dataa(\vga_ctrl_inst|cnt_v [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\vga_ctrl_inst|Add1~0_combout ), + .cout(\vga_ctrl_inst|Add1~1 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~0 .lut_mask = 16'h55AA; +defparam \vga_ctrl_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~2 ( +// Equation(s): +// \vga_ctrl_inst|Add1~2_combout = (\vga_ctrl_inst|cnt_v [1] & (!\vga_ctrl_inst|Add1~1 )) # (!\vga_ctrl_inst|cnt_v [1] & ((\vga_ctrl_inst|Add1~1 ) # (GND))) +// \vga_ctrl_inst|Add1~3 = CARRY((!\vga_ctrl_inst|Add1~1 ) # (!\vga_ctrl_inst|cnt_v [1])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [1]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~1 ), + .combout(\vga_ctrl_inst|Add1~2_combout ), + .cout(\vga_ctrl_inst|Add1~3 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~2 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~4 ( +// Equation(s): +// \vga_ctrl_inst|Add1~4_combout = (\vga_ctrl_inst|cnt_v [2] & (\vga_ctrl_inst|Add1~3 $ (GND))) # (!\vga_ctrl_inst|cnt_v [2] & (!\vga_ctrl_inst|Add1~3 & VCC)) +// \vga_ctrl_inst|Add1~5 = CARRY((\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|Add1~3 )) + + .dataa(\vga_ctrl_inst|cnt_v [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~3 ), + .combout(\vga_ctrl_inst|Add1~4_combout ), + .cout(\vga_ctrl_inst|Add1~5 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~4 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~6 ( +// Equation(s): +// \vga_ctrl_inst|Add1~6_combout = (\vga_ctrl_inst|cnt_v [3] & (!\vga_ctrl_inst|Add1~5 )) # (!\vga_ctrl_inst|cnt_v [3] & ((\vga_ctrl_inst|Add1~5 ) # (GND))) +// \vga_ctrl_inst|Add1~7 = CARRY((!\vga_ctrl_inst|Add1~5 ) # (!\vga_ctrl_inst|cnt_v [3])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~5 ), + .combout(\vga_ctrl_inst|Add1~6_combout ), + .cout(\vga_ctrl_inst|Add1~7 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~6 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~8 ( +// Equation(s): +// \vga_ctrl_inst|Add1~8_combout = (\vga_ctrl_inst|cnt_v [4] & (\vga_ctrl_inst|Add1~7 $ (GND))) # (!\vga_ctrl_inst|cnt_v [4] & (!\vga_ctrl_inst|Add1~7 & VCC)) +// \vga_ctrl_inst|Add1~9 = CARRY((\vga_ctrl_inst|cnt_v [4] & !\vga_ctrl_inst|Add1~7 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [4]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~7 ), + .combout(\vga_ctrl_inst|Add1~8_combout ), + .cout(\vga_ctrl_inst|Add1~9 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~8 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~10 ( +// Equation(s): +// \vga_ctrl_inst|Add1~10_combout = (\vga_ctrl_inst|cnt_v [5] & (!\vga_ctrl_inst|Add1~9 )) # (!\vga_ctrl_inst|cnt_v [5] & ((\vga_ctrl_inst|Add1~9 ) # (GND))) +// \vga_ctrl_inst|Add1~11 = CARRY((!\vga_ctrl_inst|Add1~9 ) # (!\vga_ctrl_inst|cnt_v [5])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [5]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~9 ), + .combout(\vga_ctrl_inst|Add1~10_combout ), + .cout(\vga_ctrl_inst|Add1~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~10 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~12 ( +// Equation(s): +// \vga_ctrl_inst|Add1~12_combout = (\vga_ctrl_inst|cnt_v [6] & (\vga_ctrl_inst|Add1~11 $ (GND))) # (!\vga_ctrl_inst|cnt_v [6] & (!\vga_ctrl_inst|Add1~11 & VCC)) +// \vga_ctrl_inst|Add1~13 = CARRY((\vga_ctrl_inst|cnt_v [6] & !\vga_ctrl_inst|Add1~11 )) + + .dataa(\vga_ctrl_inst|cnt_v [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~11 ), + .combout(\vga_ctrl_inst|Add1~12_combout ), + .cout(\vga_ctrl_inst|Add1~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~12 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N26 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~16 ( +// Equation(s): +// \vga_ctrl_inst|Add1~16_combout = (\vga_ctrl_inst|cnt_v [8] & (\vga_ctrl_inst|Add1~15 $ (GND))) # (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|Add1~15 & VCC)) +// \vga_ctrl_inst|Add1~17 = CARRY((\vga_ctrl_inst|cnt_v [8] & !\vga_ctrl_inst|Add1~15 )) + + .dataa(\vga_ctrl_inst|cnt_v [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~15 ), + .combout(\vga_ctrl_inst|Add1~16_combout ), + .cout(\vga_ctrl_inst|Add1~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~16 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y23_N13 +dffeas \vga_ctrl_inst|cnt_v[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[8]~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[8] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~0 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~0_combout = (\vga_ctrl_inst|cnt_h [8] & \vga_ctrl_inst|cnt_h [9]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~0 .lut_mask = 16'hCC00; +defparam \vga_ctrl_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N13 +dffeas \vga_ctrl_inst|cnt_h[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [2]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[2] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N12 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[8]~3 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[8]~3_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~16_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [8])))) + + .dataa(\vga_ctrl_inst|Add1~16_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [8]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[8]~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[8]~3 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[8]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data[4]~5 ( +// Equation(s): +// \vga_pic_inst|pix_data[4]~5_combout = (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~16_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|pix_data_req~4_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~16_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4]~5 .lut_mask = 16'h00CC; +defparam \vga_pic_inst|pix_data[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~8 ( +// Equation(s): +// \vga_pic_inst|pix_data~8_combout = (\vga_ctrl_inst|Add2~16_combout ) # (((\vga_ctrl_inst|Add2~14_combout ) # (!\vga_ctrl_inst|pix_data_req~4_combout )) # (!\vga_ctrl_inst|Add2~10_combout )) + + .dataa(\vga_ctrl_inst|Add2~16_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~8 .lut_mask = 16'hFBFF; +defparam \vga_pic_inst|pix_data~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N10 +cycloneive_lcell_comb \vga_pic_inst|pix_data~15 ( +// Equation(s): +// \vga_pic_inst|pix_data~15_combout = (\vga_pic_inst|pix_data[4]~5_combout & (\vga_pic_inst|pix_data~11_combout & ((!\vga_pic_inst|pix_data[4]~10_combout )))) # (!\vga_pic_inst|pix_data[4]~5_combout & (((\vga_pic_inst|pix_data~14_combout )))) + + .dataa(\vga_pic_inst|pix_data~11_combout ), + .datab(\vga_pic_inst|pix_data~14_combout ), + .datac(\vga_pic_inst|pix_data[4]~10_combout ), + .datad(\vga_pic_inst|pix_data[4]~5_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~15_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~15 .lut_mask = 16'h0ACC; +defparam \vga_pic_inst|pix_data~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~17 ( +// Equation(s): +// \vga_pic_inst|pix_data~17_combout = (\vga_ctrl_inst|Add2~12_combout & (!\vga_ctrl_inst|Add2~14_combout )) # (!\vga_ctrl_inst|Add2~12_combout & (\vga_ctrl_inst|Add2~14_combout & !\vga_ctrl_inst|Add2~10_combout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~17_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~17 .lut_mask = 16'h0C3C; +defparam \vga_pic_inst|pix_data~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOOBUF_X35_Y0_N30 +cycloneive_io_obuf \hsync~output ( + .i(!\vga_ctrl_inst|LessThan0~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(hsync), + .obar()); +// synopsys translate_off +defparam \hsync~output .bus_hold = "false"; +defparam \hsync~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X28_Y0_N2 +cycloneive_io_obuf \vsync~output ( + .i(!\vga_ctrl_inst|LessThan1~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(vsync), + .obar()); +// synopsys translate_off +defparam \vsync~output .bus_hold = "false"; +defparam \vsync~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X32_Y0_N2 +cycloneive_io_obuf \rgb[0]~output ( + .i(\vga_ctrl_inst|rgb[0]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[0]), + .obar()); +// synopsys translate_off +defparam \rgb[0]~output .bus_hold = "false"; +defparam \rgb[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X35_Y0_N23 +cycloneive_io_obuf \rgb[1]~output ( + .i(\vga_ctrl_inst|rgb[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[1]), + .obar()); +// synopsys translate_off +defparam \rgb[1]~output .bus_hold = "false"; +defparam \rgb[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X35_Y0_N16 +cycloneive_io_obuf \rgb[2]~output ( + .i(\vga_ctrl_inst|rgb[0]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[2]), + .obar()); +// synopsys translate_off +defparam \rgb[2]~output .bus_hold = "false"; +defparam \rgb[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y4_N9 +cycloneive_io_obuf \rgb[3]~output ( + .i(\vga_ctrl_inst|rgb[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[3]), + .obar()); +// synopsys translate_off +defparam \rgb[3]~output .bus_hold = "false"; +defparam \rgb[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y3_N9 +cycloneive_io_obuf \rgb[4]~output ( + .i(\vga_ctrl_inst|rgb[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[4]), + .obar()); +// synopsys translate_off +defparam \rgb[4]~output .bus_hold = "false"; +defparam \rgb[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y3_N16 +cycloneive_io_obuf \rgb[5]~output ( + .i(\vga_ctrl_inst|rgb[5]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[5]), + .obar()); +// synopsys translate_off +defparam \rgb[5]~output .bus_hold = "false"; +defparam \rgb[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y8_N2 +cycloneive_io_obuf \rgb[6]~output ( + .i(\vga_ctrl_inst|rgb[5]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[6]), + .obar()); +// synopsys translate_off +defparam \rgb[6]~output .bus_hold = "false"; +defparam \rgb[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y8_N9 +cycloneive_io_obuf \rgb[7]~output ( + .i(\vga_ctrl_inst|rgb[7]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[7]), + .obar()); +// synopsys translate_off +defparam \rgb[7]~output .bus_hold = "false"; +defparam \rgb[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y12_N16 +cycloneive_io_obuf \rgb[8]~output ( + .i(\vga_ctrl_inst|rgb[5]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[8]), + .obar()); +// synopsys translate_off +defparam \rgb[8]~output .bus_hold = "false"; +defparam \rgb[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y13_N9 +cycloneive_io_obuf \rgb[9]~output ( + .i(\vga_ctrl_inst|rgb[7]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[9]), + .obar()); +// synopsys translate_off +defparam \rgb[9]~output .bus_hold = "false"; +defparam \rgb[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y14_N23 +cycloneive_io_obuf \rgb[10]~output ( + .i(\vga_ctrl_inst|rgb[10]~4_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[10]), + .obar()); +// synopsys translate_off +defparam \rgb[10]~output .bus_hold = "false"; +defparam \rgb[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y13_N2 +cycloneive_io_obuf \rgb[11]~output ( + .i(\vga_ctrl_inst|rgb[11]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[11]), + .obar()); +// synopsys translate_off +defparam \rgb[11]~output .bus_hold = "false"; +defparam \rgb[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y18_N16 +cycloneive_io_obuf \rgb[12]~output ( + .i(\vga_ctrl_inst|rgb[12]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[12]), + .obar()); +// synopsys translate_off +defparam \rgb[12]~output .bus_hold = "false"; +defparam \rgb[12]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y18_N23 +cycloneive_io_obuf \rgb[13]~output ( + .i(\vga_ctrl_inst|rgb[11]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[13]), + .obar()); +// synopsys translate_off +defparam \rgb[13]~output .bus_hold = "false"; +defparam \rgb[13]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y19_N9 +cycloneive_io_obuf \rgb[14]~output ( + .i(\vga_ctrl_inst|rgb[12]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[14]), + .obar()); +// synopsys translate_off +defparam \rgb[14]~output .bus_hold = "false"; +defparam \rgb[14]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y20_N23 +cycloneive_io_obuf \rgb[15]~output ( + .i(\vga_ctrl_inst|rgb[12]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[15]), + .obar()); +// synopsys translate_off +defparam \rgb[15]~output .bus_hold = "false"; +defparam \rgb[15]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~0 ( +// Equation(s): +// \vga_ctrl_inst|Add0~0_combout = \vga_ctrl_inst|cnt_h [0] $ (VCC) +// \vga_ctrl_inst|Add0~1 = CARRY(\vga_ctrl_inst|cnt_h [0]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\vga_ctrl_inst|Add0~0_combout ), + .cout(\vga_ctrl_inst|Add0~1 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~0 .lut_mask = 16'h33CC; +defparam \vga_ctrl_inst|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y3_N0 +cycloneive_lcell_comb \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X35_Y3_N1 +dffeas \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .d(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y3_N10 +cycloneive_lcell_comb \rst_n~0 ( +// Equation(s): +// \rst_n~0_combout = ((!\sys_rst_n~input_o ) # (!\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q )) # (!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ) + + .dataa(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .datac(\sys_rst_n~input_o ), + .datad(gnd), + .cin(gnd), + .combout(\rst_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \rst_n~0 .lut_mask = 16'h7F7F; +defparam \rst_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G16 +cycloneive_clkctrl \rst_n~0clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~0_combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~0clkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~0clkctrl .clock_type = "global clock"; +defparam \rst_n~0clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X35_Y23_N9 +dffeas \vga_ctrl_inst|cnt_h[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[0] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~2 ( +// Equation(s): +// \vga_ctrl_inst|Add0~2_combout = (\vga_ctrl_inst|cnt_h [1] & (!\vga_ctrl_inst|Add0~1 )) # (!\vga_ctrl_inst|cnt_h [1] & ((\vga_ctrl_inst|Add0~1 ) # (GND))) +// \vga_ctrl_inst|Add0~3 = CARRY((!\vga_ctrl_inst|Add0~1 ) # (!\vga_ctrl_inst|cnt_h [1])) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~1 ), + .combout(\vga_ctrl_inst|Add0~2_combout ), + .cout(\vga_ctrl_inst|Add0~3 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~2 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~6 ( +// Equation(s): +// \vga_ctrl_inst|Add0~6_combout = (\vga_ctrl_inst|cnt_h [3] & (!\vga_ctrl_inst|Add0~5 )) # (!\vga_ctrl_inst|cnt_h [3] & ((\vga_ctrl_inst|Add0~5 ) # (GND))) +// \vga_ctrl_inst|Add0~7 = CARRY((!\vga_ctrl_inst|Add0~5 ) # (!\vga_ctrl_inst|cnt_h [3])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [3]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~5 ), + .combout(\vga_ctrl_inst|Add0~6_combout ), + .cout(\vga_ctrl_inst|Add0~7 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~6 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N15 +dffeas \vga_ctrl_inst|cnt_h[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [3]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[3] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~8 ( +// Equation(s): +// \vga_ctrl_inst|Add0~8_combout = (\vga_ctrl_inst|cnt_h [4] & (\vga_ctrl_inst|Add0~7 $ (GND))) # (!\vga_ctrl_inst|cnt_h [4] & (!\vga_ctrl_inst|Add0~7 & VCC)) +// \vga_ctrl_inst|Add0~9 = CARRY((\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|Add0~7 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [4]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~7 ), + .combout(\vga_ctrl_inst|Add0~8_combout ), + .cout(\vga_ctrl_inst|Add0~9 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~8 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N17 +dffeas \vga_ctrl_inst|cnt_h[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[4] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~10 ( +// Equation(s): +// \vga_ctrl_inst|Add0~10_combout = (\vga_ctrl_inst|cnt_h [5] & (!\vga_ctrl_inst|Add0~9 )) # (!\vga_ctrl_inst|cnt_h [5] & ((\vga_ctrl_inst|Add0~9 ) # (GND))) +// \vga_ctrl_inst|Add0~11 = CARRY((!\vga_ctrl_inst|Add0~9 ) # (!\vga_ctrl_inst|cnt_h [5])) + + .dataa(\vga_ctrl_inst|cnt_h [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~9 ), + .combout(\vga_ctrl_inst|Add0~10_combout ), + .cout(\vga_ctrl_inst|Add0~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~10 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~12 ( +// Equation(s): +// \vga_ctrl_inst|Add0~12_combout = (\vga_ctrl_inst|cnt_h [6] & (\vga_ctrl_inst|Add0~11 $ (GND))) # (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|Add0~11 & VCC)) +// \vga_ctrl_inst|Add0~13 = CARRY((\vga_ctrl_inst|cnt_h [6] & !\vga_ctrl_inst|Add0~11 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~11 ), + .combout(\vga_ctrl_inst|Add0~12_combout ), + .cout(\vga_ctrl_inst|Add0~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~12 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N21 +dffeas \vga_ctrl_inst|cnt_h[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [6]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[6] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~14 ( +// Equation(s): +// \vga_ctrl_inst|Add0~14_combout = (\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Add0~13 )) # (!\vga_ctrl_inst|cnt_h [7] & ((\vga_ctrl_inst|Add0~13 ) # (GND))) +// \vga_ctrl_inst|Add0~15 = CARRY((!\vga_ctrl_inst|Add0~13 ) # (!\vga_ctrl_inst|cnt_h [7])) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~13 ), + .combout(\vga_ctrl_inst|Add0~14_combout ), + .cout(\vga_ctrl_inst|Add0~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~14 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N23 +dffeas \vga_ctrl_inst|cnt_h[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [7]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[7] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N24 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~16 ( +// Equation(s): +// \vga_ctrl_inst|Add0~16_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|Add0~15 $ (GND))) # (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|Add0~15 & VCC)) +// \vga_ctrl_inst|Add0~17 = CARRY((\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|Add0~15 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~15 ), + .combout(\vga_ctrl_inst|Add0~16_combout ), + .cout(\vga_ctrl_inst|Add0~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~16 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N26 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~18 ( +// Equation(s): +// \vga_ctrl_inst|Add0~18_combout = \vga_ctrl_inst|Add0~17 $ (\vga_ctrl_inst|cnt_h [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(\vga_ctrl_inst|Add0~17 ), + .combout(\vga_ctrl_inst|Add0~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~18 .lut_mask = 16'h0FF0; +defparam \vga_ctrl_inst|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~1 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~1_combout = (!\vga_ctrl_inst|Equal0~3_combout & \vga_ctrl_inst|Add0~18_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|Add0~18_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~1 .lut_mask = 16'h3030; +defparam \vga_ctrl_inst|cnt_h~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N1 +dffeas \vga_ctrl_inst|cnt_h[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[9] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N24 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~0 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~0_combout = (\vga_ctrl_inst|Add0~10_combout & !\vga_ctrl_inst|Equal0~3_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add0~10_combout ), + .datac(\vga_ctrl_inst|Equal0~3_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~0 .lut_mask = 16'h0C0C; +defparam \vga_ctrl_inst|cnt_h~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y23_N25 +dffeas \vga_ctrl_inst|cnt_h[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [5]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[5] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N30 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~2 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~2_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|cnt_h [9] & (!\vga_ctrl_inst|cnt_h [5] & !\vga_ctrl_inst|cnt_h [6]))) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(\vga_ctrl_inst|cnt_h [9]), + .datac(\vga_ctrl_inst|cnt_h [5]), + .datad(\vga_ctrl_inst|cnt_h [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~2 .lut_mask = 16'h0008; +defparam \vga_ctrl_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N11 +dffeas \vga_ctrl_inst|cnt_h[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [1]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[1] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N28 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~1 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~1_combout = (\vga_ctrl_inst|cnt_h [2] & (\vga_ctrl_inst|cnt_h [3] & (\vga_ctrl_inst|cnt_h [0] & \vga_ctrl_inst|cnt_h [1]))) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(\vga_ctrl_inst|cnt_h [3]), + .datac(\vga_ctrl_inst|cnt_h [0]), + .datad(\vga_ctrl_inst|cnt_h [1]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~1 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~3 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~3_combout = (\vga_ctrl_inst|cnt_h [4] & (\vga_ctrl_inst|Equal0~2_combout & (\vga_ctrl_inst|Equal0~1_combout & !\vga_ctrl_inst|cnt_h [7]))) + + .dataa(\vga_ctrl_inst|cnt_h [4]), + .datab(\vga_ctrl_inst|Equal0~2_combout ), + .datac(\vga_ctrl_inst|Equal0~1_combout ), + .datad(\vga_ctrl_inst|cnt_h [7]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~3 .lut_mask = 16'h0080; +defparam \vga_ctrl_inst|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~2 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~2_combout = (\vga_ctrl_inst|Add0~16_combout & !\vga_ctrl_inst|Equal0~3_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add0~16_combout ), + .datac(\vga_ctrl_inst|Equal0~3_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~2 .lut_mask = 16'h0C0C; +defparam \vga_ctrl_inst|cnt_h~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N3 +dffeas \vga_ctrl_inst|cnt_h[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[8] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N4 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan2~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan2~0_combout = (!\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|cnt_h [9]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan2~0 .lut_mask = 16'h0033; +defparam \vga_ctrl_inst|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan0~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan0~0_combout = (\vga_ctrl_inst|cnt_h [7]) # (((\vga_ctrl_inst|cnt_h [6] & \vga_ctrl_inst|cnt_h [5])) # (!\vga_ctrl_inst|LessThan2~0_combout )) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(\vga_ctrl_inst|LessThan2~0_combout ), + .datad(\vga_ctrl_inst|cnt_h [5]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan0~0 .lut_mask = 16'hEFAF; +defparam \vga_ctrl_inst|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N28 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[0]~9 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[0]~9_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~0_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [0])))) + + .dataa(\vga_ctrl_inst|Add1~0_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [0]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[0]~9 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N29 +dffeas \vga_ctrl_inst|cnt_v[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[0]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[0] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N4 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[2]~8 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[2]~8_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~4_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [2])))) + + .dataa(\vga_ctrl_inst|Add1~4_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[2]~8 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N5 +dffeas \vga_ctrl_inst|cnt_v[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[2]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [2]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[2] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[4]~6 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[4]~6_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~8_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [4])))) + + .dataa(\vga_ctrl_inst|Add1~8_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [4]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[4]~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[4]~6 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[4]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N1 +dffeas \vga_ctrl_inst|cnt_v[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[4]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[4] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|always1~1 ( +// Equation(s): +// \vga_ctrl_inst|always1~1_combout = (\vga_ctrl_inst|cnt_v [9] & (\vga_ctrl_inst|cnt_v [3] & (\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|cnt_v [4]))) + + .dataa(\vga_ctrl_inst|cnt_v [9]), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|cnt_v [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~1 .lut_mask = 16'h0080; +defparam \vga_ctrl_inst|always1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[1]~0 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[1]~0_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~2_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [1])))) + + .dataa(\vga_ctrl_inst|Add1~2_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [1]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[1]~0 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N17 +dffeas \vga_ctrl_inst|cnt_v[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[1]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [1]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[1] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|always1~2 ( +// Equation(s): +// \vga_ctrl_inst|always1~2_combout = (\vga_ctrl_inst|always1~0_combout & (!\vga_ctrl_inst|cnt_v [0] & (\vga_ctrl_inst|always1~1_combout & !\vga_ctrl_inst|cnt_v [1]))) + + .dataa(\vga_ctrl_inst|always1~0_combout ), + .datab(\vga_ctrl_inst|cnt_v [0]), + .datac(\vga_ctrl_inst|always1~1_combout ), + .datad(\vga_ctrl_inst|cnt_v [1]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~2 .lut_mask = 16'h0020; +defparam \vga_ctrl_inst|always1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[3]~7 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[3]~7_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~6_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [3])))) + + .dataa(\vga_ctrl_inst|Add1~6_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [3]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[3]~7 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N3 +dffeas \vga_ctrl_inst|cnt_v[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[3]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [3]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[3] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan6~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan6~0_combout = (!\vga_ctrl_inst|cnt_v [3] & (!\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|cnt_v [4])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|cnt_v [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan6~0 .lut_mask = 16'h0003; +defparam \vga_ctrl_inst|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[5]~2 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[5]~2_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~10_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [5])))) + + .dataa(\vga_ctrl_inst|Add1~10_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [5]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[5]~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[5]~2 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[5]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N19 +dffeas \vga_ctrl_inst|cnt_v[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[5]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [5]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[5] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N24 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~14 ( +// Equation(s): +// \vga_ctrl_inst|Add1~14_combout = (\vga_ctrl_inst|cnt_v [7] & (!\vga_ctrl_inst|Add1~13 )) # (!\vga_ctrl_inst|cnt_v [7] & ((\vga_ctrl_inst|Add1~13 ) # (GND))) +// \vga_ctrl_inst|Add1~15 = CARRY((!\vga_ctrl_inst|Add1~13 ) # (!\vga_ctrl_inst|cnt_v [7])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [7]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~13 ), + .combout(\vga_ctrl_inst|Add1~14_combout ), + .cout(\vga_ctrl_inst|Add1~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~14 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[7]~4 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[7]~4_combout = (\vga_ctrl_inst|Equal0~3_combout & (!\vga_ctrl_inst|always1~2_combout & (\vga_ctrl_inst|Add1~14_combout ))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [7])))) + + .dataa(\vga_ctrl_inst|always1~2_combout ), + .datab(\vga_ctrl_inst|Add1~14_combout ), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[7]~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[7]~4 .lut_mask = 16'h44F0; +defparam \vga_ctrl_inst|cnt_v[7]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y24_N3 +dffeas \vga_ctrl_inst|cnt_v[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[7]~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [7]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[7] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N28 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~18 ( +// Equation(s): +// \vga_ctrl_inst|Add1~18_combout = \vga_ctrl_inst|Add1~17 $ (\vga_ctrl_inst|cnt_v [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_v [9]), + .cin(\vga_ctrl_inst|Add1~17 ), + .combout(\vga_ctrl_inst|Add1~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~18 .lut_mask = 16'h0FF0; +defparam \vga_ctrl_inst|Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[9]~1 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[9]~1_combout = (\vga_ctrl_inst|Equal0~3_combout & (!\vga_ctrl_inst|always1~2_combout & (\vga_ctrl_inst|Add1~18_combout ))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [9])))) + + .dataa(\vga_ctrl_inst|always1~2_combout ), + .datab(\vga_ctrl_inst|Add1~18_combout ), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[9]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[9]~1 .lut_mask = 16'h44F0; +defparam \vga_ctrl_inst|cnt_v[9]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y24_N1 +dffeas \vga_ctrl_inst|cnt_v[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[9]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[9] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N4 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[6]~5 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[6]~5_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~12_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [6])))) + + .dataa(\vga_ctrl_inst|Add1~12_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [6]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[6]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[6]~5 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[6]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y24_N5 +dffeas \vga_ctrl_inst|cnt_v[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[6]~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [6]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[6] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|always1~0 ( +// Equation(s): +// \vga_ctrl_inst|always1~0_combout = (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|cnt_v [5] & (!\vga_ctrl_inst|cnt_v [7] & !\vga_ctrl_inst|cnt_v [6]))) + + .dataa(\vga_ctrl_inst|cnt_v [8]), + .datab(\vga_ctrl_inst|cnt_v [5]), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|cnt_v [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~0 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan1~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan1~0_combout = ((\vga_ctrl_inst|cnt_v [1]) # ((\vga_ctrl_inst|cnt_v [9]) # (!\vga_ctrl_inst|always1~0_combout ))) # (!\vga_ctrl_inst|LessThan6~0_combout ) + + .dataa(\vga_ctrl_inst|LessThan6~0_combout ), + .datab(\vga_ctrl_inst|cnt_v [1]), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(\vga_ctrl_inst|always1~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan1~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan1~0 .lut_mask = 16'hFDFF; +defparam \vga_ctrl_inst|LessThan1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan6~1 ( +// Equation(s): +// \vga_ctrl_inst|LessThan6~1_combout = (!\vga_ctrl_inst|cnt_v [1]) # (!\vga_ctrl_inst|cnt_v [0]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [0]), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_v [1]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan6~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan6~1 .lut_mask = 16'h33FF; +defparam \vga_ctrl_inst|LessThan6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N30 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~1 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~1_combout = (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|cnt_v [9] & (!\vga_ctrl_inst|cnt_v [7] & !\vga_ctrl_inst|cnt_v [6]))) + + .dataa(\vga_ctrl_inst|cnt_v [8]), + .datab(\vga_ctrl_inst|cnt_v [9]), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|cnt_v [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~1 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|pix_data_req~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N24 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~2 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~2_combout = (\vga_ctrl_inst|LessThan6~0_combout & ((\vga_ctrl_inst|LessThan6~1_combout & (\vga_ctrl_inst|pix_data_req~1_combout )) # (!\vga_ctrl_inst|LessThan6~1_combout & ((\vga_ctrl_inst|always1~0_combout ))))) # +// (!\vga_ctrl_inst|LessThan6~0_combout & (((\vga_ctrl_inst|always1~0_combout )))) + + .dataa(\vga_ctrl_inst|LessThan6~0_combout ), + .datab(\vga_ctrl_inst|LessThan6~1_combout ), + .datac(\vga_ctrl_inst|pix_data_req~1_combout ), + .datad(\vga_ctrl_inst|always1~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~2 .lut_mask = 16'hF780; +defparam \vga_ctrl_inst|pix_data_req~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N28 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan2~1 ( +// Equation(s): +// \vga_ctrl_inst|LessThan2~1_combout = (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|cnt_h [5])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(\vga_ctrl_inst|cnt_h [4]), + .datad(\vga_ctrl_inst|cnt_h [5]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan2~1 .lut_mask = 16'h0003; +defparam \vga_ctrl_inst|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|rgb_valid~0 ( +// Equation(s): +// \vga_ctrl_inst|rgb_valid~0_combout = (\vga_ctrl_inst|Equal0~0_combout & (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|LessThan2~0_combout & \vga_ctrl_inst|LessThan2~1_combout ))) # (!\vga_ctrl_inst|Equal0~0_combout & (((\vga_ctrl_inst|cnt_h [7] & +// !\vga_ctrl_inst|LessThan2~1_combout )) # (!\vga_ctrl_inst|LessThan2~0_combout ))) + + .dataa(\vga_ctrl_inst|Equal0~0_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|LessThan2~0_combout ), + .datad(\vga_ctrl_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb_valid~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb_valid~0 .lut_mask = 16'h0745; +defparam \vga_ctrl_inst|rgb_valid~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~1 ( +// Equation(s): +// \vga_ctrl_inst|Add2~1_cout = CARRY((\vga_ctrl_inst|cnt_h [1] & \vga_ctrl_inst|cnt_h [0])) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(\vga_ctrl_inst|cnt_h [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\vga_ctrl_inst|Add2~1_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~1 .lut_mask = 16'h0088; +defparam \vga_ctrl_inst|Add2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~3 ( +// Equation(s): +// \vga_ctrl_inst|Add2~3_cout = CARRY((!\vga_ctrl_inst|Add2~1_cout ) # (!\vga_ctrl_inst|cnt_h [2])) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~1_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~3_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~3 .lut_mask = 16'h005F; +defparam \vga_ctrl_inst|Add2~3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~5 ( +// Equation(s): +// \vga_ctrl_inst|Add2~5_cout = CARRY((\vga_ctrl_inst|cnt_h [3] & !\vga_ctrl_inst|Add2~3_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~3_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~5_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~5 .lut_mask = 16'h000A; +defparam \vga_ctrl_inst|Add2~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~7 ( +// Equation(s): +// \vga_ctrl_inst|Add2~7_cout = CARRY((!\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|Add2~5_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~5_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~7_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~7 .lut_mask = 16'h0005; +defparam \vga_ctrl_inst|Add2~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~9 ( +// Equation(s): +// \vga_ctrl_inst|Add2~9_cout = CARRY((\vga_ctrl_inst|cnt_h [5]) # (!\vga_ctrl_inst|Add2~7_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~7_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~9_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~9 .lut_mask = 16'h00AF; +defparam \vga_ctrl_inst|Add2~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~10 ( +// Equation(s): +// \vga_ctrl_inst|Add2~10_combout = (\vga_ctrl_inst|cnt_h [6] & (\vga_ctrl_inst|Add2~9_cout & VCC)) # (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|Add2~9_cout )) +// \vga_ctrl_inst|Add2~11 = CARRY((!\vga_ctrl_inst|cnt_h [6] & !\vga_ctrl_inst|Add2~9_cout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~9_cout ), + .combout(\vga_ctrl_inst|Add2~10_combout ), + .cout(\vga_ctrl_inst|Add2~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~10 .lut_mask = 16'hC303; +defparam \vga_ctrl_inst|Add2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~12 ( +// Equation(s): +// \vga_ctrl_inst|Add2~12_combout = (\vga_ctrl_inst|cnt_h [7] & (\vga_ctrl_inst|Add2~11 $ (GND))) # (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Add2~11 & VCC)) +// \vga_ctrl_inst|Add2~13 = CARRY((\vga_ctrl_inst|cnt_h [7] & !\vga_ctrl_inst|Add2~11 )) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~11 ), + .combout(\vga_ctrl_inst|Add2~12_combout ), + .cout(\vga_ctrl_inst|Add2~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~12 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N24 +cycloneive_lcell_comb \vga_pic_inst|LessThan14~0 ( +// Equation(s): +// \vga_pic_inst|LessThan14~0_combout = (\vga_ctrl_inst|Add2~12_combout & \vga_ctrl_inst|Add2~10_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan14~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan14~0 .lut_mask = 16'hCC00; +defparam \vga_pic_inst|LessThan14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~14 ( +// Equation(s): +// \vga_ctrl_inst|Add2~14_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|Add2~13 & VCC)) # (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|Add2~13 )) +// \vga_ctrl_inst|Add2~15 = CARRY((!\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|Add2~13 )) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~13 ), + .combout(\vga_ctrl_inst|Add2~14_combout ), + .cout(\vga_ctrl_inst|Add2~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~14 .lut_mask = 16'hA505; +defparam \vga_ctrl_inst|Add2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~16 ( +// Equation(s): +// \vga_ctrl_inst|Add2~16_combout = \vga_ctrl_inst|cnt_h [9] $ (\vga_ctrl_inst|Add2~15 ) + + .dataa(\vga_ctrl_inst|cnt_h [9]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\vga_ctrl_inst|Add2~15 ), + .combout(\vga_ctrl_inst|Add2~16_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~16 .lut_mask = 16'h5A5A; +defparam \vga_ctrl_inst|Add2~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N2 +cycloneive_lcell_comb \vga_pic_inst|LessThan6~0 ( +// Equation(s): +// \vga_pic_inst|LessThan6~0_combout = ((\vga_pic_inst|LessThan14~0_combout ) # ((\vga_ctrl_inst|Add2~16_combout ) # (\vga_ctrl_inst|Add2~14_combout ))) # (!\vga_ctrl_inst|pix_data_req~4_combout ) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_pic_inst|LessThan14~0_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan6~0 .lut_mask = 16'hFFFD; +defparam \vga_pic_inst|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N26 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~0 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~0_combout = (!\vga_ctrl_inst|always1~0_combout & \vga_ctrl_inst|cnt_v [9]) + + .dataa(\vga_ctrl_inst|always1~0_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~0 .lut_mask = 16'h5050; +defparam \vga_ctrl_inst|pix_data_req~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N4 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan4~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan4~0_combout = (\vga_ctrl_inst|LessThan2~0_combout & (((!\vga_ctrl_inst|Equal0~1_combout & \vga_ctrl_inst|LessThan2~1_combout )) # (!\vga_ctrl_inst|cnt_h [7]))) + + .dataa(\vga_ctrl_inst|Equal0~1_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|LessThan2~0_combout ), + .datad(\vga_ctrl_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan4~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan4~0 .lut_mask = 16'h7030; +defparam \vga_ctrl_inst|LessThan4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~3 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~3_combout = ((!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Equal0~1_combout & \vga_ctrl_inst|LessThan2~1_combout ))) # (!\vga_ctrl_inst|Equal0~0_combout ) + + .dataa(\vga_ctrl_inst|Equal0~0_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|Equal0~1_combout ), + .datad(\vga_ctrl_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~3 .lut_mask = 16'h5755; +defparam \vga_ctrl_inst|pix_data_req~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~4 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~4_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (!\vga_ctrl_inst|LessThan4~0_combout & \vga_ctrl_inst|pix_data_req~3_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|LessThan4~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~4 .lut_mask = 16'h0100; +defparam \vga_ctrl_inst|pix_data_req~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N2 +cycloneive_lcell_comb \vga_pic_inst|pix_data~4 ( +// Equation(s): +// \vga_pic_inst|pix_data~4_combout = (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~12_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|pix_data_req~4_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~4 .lut_mask = 16'h00CC; +defparam \vga_pic_inst|pix_data~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~9 ( +// Equation(s): +// \vga_pic_inst|pix_data~9_combout = (\vga_pic_inst|pix_data~8_combout & ((\vga_pic_inst|LessThan6~0_combout ) # ((!\vga_ctrl_inst|Add2~14_combout & \vga_pic_inst|pix_data~4_combout )))) # (!\vga_pic_inst|pix_data~8_combout & +// (((!\vga_ctrl_inst|Add2~14_combout & \vga_pic_inst|pix_data~4_combout )))) + + .dataa(\vga_pic_inst|pix_data~8_combout ), + .datab(\vga_pic_inst|LessThan6~0_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_pic_inst|pix_data~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~9_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~9 .lut_mask = 16'h8F88; +defparam \vga_pic_inst|pix_data~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N8 +cycloneive_lcell_comb \vga_pic_inst|LessThan17~0 ( +// Equation(s): +// \vga_pic_inst|LessThan17~0_combout = (\vga_ctrl_inst|Add2~12_combout ) # ((\vga_ctrl_inst|Add2~10_combout ) # ((\vga_ctrl_inst|Add2~14_combout ) # (!\vga_ctrl_inst|pix_data_req~4_combout ))) + + .dataa(\vga_ctrl_inst|Add2~12_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan17~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan17~0 .lut_mask = 16'hFEFF; +defparam \vga_pic_inst|LessThan17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N14 +cycloneive_lcell_comb \vga_pic_inst|pix_data~6 ( +// Equation(s): +// \vga_pic_inst|pix_data~6_combout = ((\vga_pic_inst|LessThan17~0_combout & ((\vga_ctrl_inst|Add2~14_combout ) # (!\vga_pic_inst|pix_data~4_combout )))) # (!\vga_pic_inst|pix_data[4]~5_combout ) + + .dataa(\vga_pic_inst|pix_data[4]~5_combout ), + .datab(\vga_pic_inst|pix_data~4_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_pic_inst|LessThan17~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~6 .lut_mask = 16'hF755; +defparam \vga_pic_inst|pix_data~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N22 +cycloneive_lcell_comb \vga_pic_inst|pix_data[4]~10 ( +// Equation(s): +// \vga_pic_inst|pix_data[4]~10_combout = (!\vga_ctrl_inst|Add2~12_combout ) # (!\vga_ctrl_inst|Add2~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[4]~10_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4]~10 .lut_mask = 16'h0FFF; +defparam \vga_pic_inst|pix_data[4]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~11 ( +// Equation(s): +// \vga_pic_inst|pix_data~11_combout = (\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|Add2~12_combout & (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~10_combout ))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~11_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~11 .lut_mask = 16'h0080; +defparam \vga_pic_inst|pix_data~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N24 +cycloneive_lcell_comb \vga_pic_inst|pix_data~12 ( +// Equation(s): +// \vga_pic_inst|pix_data~12_combout = (\vga_pic_inst|pix_data[4]~5_combout & (((\vga_pic_inst|pix_data[4]~10_combout ) # (!\vga_pic_inst|pix_data~11_combout )))) # (!\vga_pic_inst|pix_data[4]~5_combout & (\vga_pic_inst|LessThan17~0_combout )) + + .dataa(\vga_pic_inst|pix_data[4]~5_combout ), + .datab(\vga_pic_inst|LessThan17~0_combout ), + .datac(\vga_pic_inst|pix_data[4]~10_combout ), + .datad(\vga_pic_inst|pix_data~11_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~12_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~12 .lut_mask = 16'hE4EE; +defparam \vga_pic_inst|pix_data~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N16 +cycloneive_lcell_comb \vga_pic_inst|pix_data~13 ( +// Equation(s): +// \vga_pic_inst|pix_data~13_combout = ((\vga_pic_inst|pix_data[4]~7_combout & (\vga_pic_inst|pix_data~9_combout & \vga_pic_inst|pix_data~6_combout ))) # (!\vga_pic_inst|pix_data~12_combout ) + + .dataa(\vga_pic_inst|pix_data[4]~7_combout ), + .datab(\vga_pic_inst|pix_data~9_combout ), + .datac(\vga_pic_inst|pix_data~6_combout ), + .datad(\vga_pic_inst|pix_data~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~13_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~13 .lut_mask = 16'h80FF; +defparam \vga_pic_inst|pix_data~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N17 +dffeas \vga_pic_inst|pix_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[0] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N0 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[0]~0 ( +// Equation(s): +// \vga_ctrl_inst|rgb[0]~0_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (\vga_ctrl_inst|rgb_valid~0_combout & (\vga_pic_inst|pix_data [0] & !\vga_ctrl_inst|pix_data_req~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|rgb_valid~0_combout ), + .datac(\vga_pic_inst|pix_data [0]), + .datad(\vga_ctrl_inst|pix_data_req~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[0]~0 .lut_mask = 16'h0040; +defparam \vga_ctrl_inst|rgb[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data[4]~7 ( +// Equation(s): +// \vga_pic_inst|pix_data[4]~7_combout = (!\vga_ctrl_inst|Add2~16_combout & (\vga_ctrl_inst|pix_data_req~4_combout & ((!\vga_ctrl_inst|Add2~14_combout ) # (!\vga_ctrl_inst|Add2~12_combout )))) + + .dataa(\vga_ctrl_inst|Add2~12_combout ), + .datab(\vga_ctrl_inst|Add2~14_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[4]~7_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4]~7 .lut_mask = 16'h0700; +defparam \vga_pic_inst|pix_data[4]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N18 +cycloneive_lcell_comb \vga_pic_inst|pix_data~16 ( +// Equation(s): +// \vga_pic_inst|pix_data~16_combout = (\vga_pic_inst|pix_data~15_combout ) # ((\vga_pic_inst|pix_data[4]~7_combout & (\vga_pic_inst|pix_data~9_combout & \vga_pic_inst|pix_data~6_combout ))) + + .dataa(\vga_pic_inst|pix_data~15_combout ), + .datab(\vga_pic_inst|pix_data[4]~7_combout ), + .datac(\vga_pic_inst|pix_data~9_combout ), + .datad(\vga_pic_inst|pix_data~6_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~16_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~16 .lut_mask = 16'hEAAA; +defparam \vga_pic_inst|pix_data~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N19 +dffeas \vga_pic_inst|pix_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N26 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[1]~1 ( +// Equation(s): +// \vga_ctrl_inst|rgb[1]~1_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [4]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[1]~1 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data~25 ( +// Equation(s): +// \vga_pic_inst|pix_data~25_combout = (\vga_ctrl_inst|Add2~16_combout & (((!\vga_pic_inst|LessThan17~0_combout )))) # (!\vga_ctrl_inst|Add2~16_combout & ((\vga_ctrl_inst|pix_data_req~4_combout & (\vga_pic_inst|pix_data~17_combout )) # +// (!\vga_ctrl_inst|pix_data_req~4_combout & ((!\vga_pic_inst|LessThan17~0_combout ))))) + + .dataa(\vga_pic_inst|pix_data~17_combout ), + .datab(\vga_ctrl_inst|Add2~16_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_pic_inst|LessThan17~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~25_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~25 .lut_mask = 16'h20EF; +defparam \vga_pic_inst|pix_data~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y23_N13 +dffeas \vga_pic_inst|pix_data[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[8] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N30 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[5]~2 ( +// Equation(s): +// \vga_ctrl_inst|rgb[5]~2_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [8]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [8]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[5]~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[5]~2 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[5]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N28 +cycloneive_lcell_comb \vga_pic_inst|pix_data~18 ( +// Equation(s): +// \vga_pic_inst|pix_data~18_combout = (\vga_ctrl_inst|pix_data_req~4_combout & ((\vga_ctrl_inst|Add2~14_combout & (!\vga_ctrl_inst|Add2~12_combout & !\vga_ctrl_inst|Add2~10_combout )) # (!\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|Add2~12_combout +// )))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~18 .lut_mask = 16'h4060; +defparam \vga_pic_inst|pix_data~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data~14 ( +// Equation(s): +// \vga_pic_inst|pix_data~14_combout = (!\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~12_combout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add2~14_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~14_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~14 .lut_mask = 16'h0030; +defparam \vga_pic_inst|pix_data~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N30 +cycloneive_lcell_comb \vga_pic_inst|pix_data~26 ( +// Equation(s): +// \vga_pic_inst|pix_data~26_combout = (\vga_ctrl_inst|pix_data_req~4_combout & ((\vga_ctrl_inst|Add2~16_combout & ((\vga_pic_inst|pix_data~14_combout ))) # (!\vga_ctrl_inst|Add2~16_combout & (\vga_pic_inst|pix_data~18_combout )))) # +// (!\vga_ctrl_inst|pix_data_req~4_combout & (((\vga_pic_inst|pix_data~14_combout )))) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_pic_inst|pix_data~18_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_pic_inst|pix_data~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~26_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~26 .lut_mask = 16'hFD08; +defparam \vga_pic_inst|pix_data~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data~19 ( +// Equation(s): +// \vga_pic_inst|pix_data~19_combout = (\vga_pic_inst|pix_data~26_combout & \vga_pic_inst|pix_data~6_combout ) + + .dataa(gnd), + .datab(\vga_pic_inst|pix_data~26_combout ), + .datac(gnd), + .datad(\vga_pic_inst|pix_data~6_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~19_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~19 .lut_mask = 16'hCC00; +defparam \vga_pic_inst|pix_data~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y24_N1 +dffeas \vga_pic_inst|pix_data[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[9] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[7]~3 ( +// Equation(s): +// \vga_ctrl_inst|rgb[7]~3_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [9]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[7]~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[7]~3 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[7]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N6 +cycloneive_lcell_comb \vga_pic_inst|LessThan2~2 ( +// Equation(s): +// \vga_pic_inst|LessThan2~2_combout = (\vga_pic_inst|LessThan17~0_combout ) # ((\vga_ctrl_inst|Add2~16_combout ) # (!\vga_ctrl_inst|pix_data_req~4_combout )) + + .dataa(\vga_pic_inst|LessThan17~0_combout ), + .datab(\vga_ctrl_inst|Add2~16_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan2~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan2~2 .lut_mask = 16'hEEFF; +defparam \vga_pic_inst|LessThan2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data~20 ( +// Equation(s): +// \vga_pic_inst|pix_data~20_combout = (!\vga_ctrl_inst|Add2~16_combout & (!\vga_ctrl_inst|Add2~14_combout & \vga_ctrl_inst|pix_data_req~4_combout )) + + .dataa(\vga_ctrl_inst|Add2~16_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~20_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~20 .lut_mask = 16'h0500; +defparam \vga_pic_inst|pix_data~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~21 ( +// Equation(s): +// \vga_pic_inst|pix_data~21_combout = (\vga_pic_inst|LessThan2~2_combout & ((\vga_pic_inst|pix_data~26_combout ) # ((\vga_pic_inst|pix_data~4_combout & \vga_pic_inst|pix_data~20_combout )))) + + .dataa(\vga_pic_inst|pix_data~4_combout ), + .datab(\vga_pic_inst|pix_data~26_combout ), + .datac(\vga_pic_inst|LessThan2~2_combout ), + .datad(\vga_pic_inst|pix_data~20_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~21_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~21 .lut_mask = 16'hE0C0; +defparam \vga_pic_inst|pix_data~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y24_N27 +dffeas \vga_pic_inst|pix_data[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [10]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[10] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N2 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[10]~4 ( +// Equation(s): +// \vga_ctrl_inst|rgb[10]~4_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [10]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [10]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[10]~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[10]~4 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[10]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N20 +cycloneive_lcell_comb \vga_pic_inst|pix_data~22 ( +// Equation(s): +// \vga_pic_inst|pix_data~22_combout = ((\vga_pic_inst|pix_data[4]~5_combout & (!\vga_ctrl_inst|Add2~14_combout & \vga_pic_inst|pix_data~4_combout ))) # (!\vga_pic_inst|LessThan6~0_combout ) + + .dataa(\vga_pic_inst|pix_data[4]~5_combout ), + .datab(\vga_pic_inst|LessThan6~0_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_pic_inst|pix_data~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~22_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~22 .lut_mask = 16'h3B33; +defparam \vga_pic_inst|pix_data~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N28 +cycloneive_lcell_comb \vga_pic_inst|pix_data~23 ( +// Equation(s): +// \vga_pic_inst|pix_data~23_combout = ((\vga_pic_inst|pix_data[4]~7_combout & ((\vga_pic_inst|pix_data~22_combout ) # (!\vga_pic_inst|LessThan2~2_combout )))) # (!\vga_pic_inst|pix_data~12_combout ) + + .dataa(\vga_pic_inst|LessThan2~2_combout ), + .datab(\vga_pic_inst|pix_data~12_combout ), + .datac(\vga_pic_inst|pix_data~22_combout ), + .datad(\vga_pic_inst|pix_data[4]~7_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~23_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~23 .lut_mask = 16'hF733; +defparam \vga_pic_inst|pix_data~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N29 +dffeas \vga_pic_inst|pix_data[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [13]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[11]~5 ( +// Equation(s): +// \vga_ctrl_inst|rgb[11]~5_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (\vga_pic_inst|pix_data [13] & (\vga_ctrl_inst|rgb_valid~0_combout & !\vga_ctrl_inst|pix_data_req~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_pic_inst|pix_data [13]), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[11]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[11]~5 .lut_mask = 16'h0040; +defparam \vga_ctrl_inst|rgb[11]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N30 +cycloneive_lcell_comb \vga_pic_inst|pix_data~24 ( +// Equation(s): +// \vga_pic_inst|pix_data~24_combout = (\vga_pic_inst|pix_data~15_combout ) # ((\vga_pic_inst|pix_data[4]~7_combout & ((\vga_pic_inst|pix_data~22_combout ) # (!\vga_pic_inst|LessThan2~2_combout )))) + + .dataa(\vga_pic_inst|pix_data~15_combout ), + .datab(\vga_pic_inst|pix_data[4]~7_combout ), + .datac(\vga_pic_inst|pix_data~22_combout ), + .datad(\vga_pic_inst|LessThan2~2_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~24_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~24 .lut_mask = 16'hEAEE; +defparam \vga_pic_inst|pix_data~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N31 +dffeas \vga_pic_inst|pix_data[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [15]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[15] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[12]~6 ( +// Equation(s): +// \vga_ctrl_inst|rgb[12]~6_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (\vga_pic_inst|pix_data [15] & (\vga_ctrl_inst|rgb_valid~0_combout & !\vga_ctrl_inst|pix_data_req~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_pic_inst|pix_data [15]), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[12]~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[12]~6 .lut_mask = 16'h0040; +defparam \vga_ctrl_inst|rgb[12]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +endmodule diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_0c_v_slow.sdo b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_0c_v_slow.sdo new file mode 100644 index 0000000..56cf675 --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_0c_v_slow.sdo @@ -0,0 +1,2108 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE15F23C8, +// with speed grade 8, core voltage 1.2V, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "vga_colorbar") + (DATE "06/02/2023 04:42:20") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (414:414:414)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (3921:3921:3921) (3921:3921:3921)) + (PORT inclk[0] (2063:2063:2063) (2063:2063:2063)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (930:930:930) (857:857:857)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (936:936:936) (846:846:846)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (946:946:946) (850:850:850)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT datab (976:976:976) (871:871:871)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~8) + (DELAY + (ABSOLUTE + (PORT datab (553:553:553) (535:535:535)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~10) + (DELAY + (ABSOLUTE + (PORT datab (928:928:928) (836:836:836)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (539:539:539)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (860:860:860)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1630:1630:1630)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT datab (376:376:376) (436:436:436)) + (PORT datad (318:318:318) (383:383:383)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[8\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (702:702:702)) + (PORT datab (854:854:854) (735:735:735)) + (PORT datad (295:295:295) (323:323:323)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[4\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (1192:1192:1192) (1014:1014:1014)) + (PORT datad (897:897:897) (776:776:776)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1125:1125:1125) (953:953:953)) + (PORT datab (944:944:944) (799:799:799)) + (PORT datac (901:901:901) (814:814:814)) + (PORT datad (1146:1146:1146) (972:972:972)) + (IOPATH dataa combout (349:349:349) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~15) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (714:714:714)) + (PORT datab (502:502:502) (440:440:440)) + (PORT datac (233:233:233) (251:251:251)) + (PORT datad (253:253:253) (275:275:275)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~17) + (DELAY + (ABSOLUTE + (PORT datab (324:324:324) (343:343:343)) + (PORT datac (833:833:833) (685:685:685)) + (PORT datad (272:272:272) (289:289:289)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (788:788:788) (813:813:813)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2044:2044:2044) (2012:2012:2012)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE hsync\~output) + (DELAY + (ABSOLUTE + (PORT i (1890:1890:1890) (2195:2195:2195)) + (IOPATH i o (2832:2832:2832) (2912:2912:2912)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE vsync\~output) + (DELAY + (ABSOLUTE + (PORT i (1656:1656:1656) (1999:1999:1999)) + (IOPATH i o (2842:2842:2842) (2922:2922:2922)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2831:2831:2831) (2423:2423:2423)) + (IOPATH i o (2912:2912:2912) (2832:2832:2832)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2775:2775:2775) (2366:2366:2366)) + (IOPATH i o (2922:2922:2922) (2842:2842:2842)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3072:3072:3072) (2605:2605:2605)) + (IOPATH i o (2922:2922:2922) (2842:2842:2842)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3427:3427:3427) (2865:2865:2865)) + (IOPATH i o (3043:3043:3043) (2991:2991:2991)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3421:3421:3421) (2863:2863:2863)) + (IOPATH i o (3023:3023:3023) (2971:2971:2971)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1488:1488:1488) (1307:1307:1307)) + (IOPATH i o (3023:3023:3023) (2971:2971:2971)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1531:1531:1531) (1319:1319:1319)) + (IOPATH i o (3023:3023:3023) (2971:2971:2971)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2076:2076:2076) (1758:1758:1758)) + (IOPATH i o (3033:3033:3033) (2981:2981:2981)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1883:1883:1883) (1625:1625:1625)) + (IOPATH i o (2993:2993:2993) (2941:2941:2941)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1877:1877:1877) (1595:1595:1595)) + (IOPATH i o (3013:3013:3013) (2961:2961:2961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1823:1823:1823) (1522:1522:1522)) + (IOPATH i o (3003:3003:3003) (2951:2951:2951)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1783:1783:1783) (1502:1502:1502)) + (IOPATH i o (3003:3003:3003) (2951:2951:2951)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1438:1438:1438) (1189:1189:1189)) + (IOPATH i o (3013:3013:3013) (2961:2961:2961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[13\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1456:1456:1456) (1192:1192:1192)) + (IOPATH i o (3003:3003:3003) (2951:2951:2951)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[14\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1057:1057:1057) (866:866:866)) + (IOPATH i o (3013:3013:3013) (2961:2961:2961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[15\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1090:1090:1090) (891:891:891)) + (IOPATH i o (3003:3003:3003) (2951:2951:2951)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT datab (346:346:346) (403:403:403)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (748:748:748) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (2611:2611:2611) (2849:2849:2849)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4061:4061:4061) (3964:3964:3964)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rst_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1998:1998:1998) (2217:2217:2217)) + (PORT datab (316:316:316) (370:370:370)) + (PORT datac (3330:3330:3330) (3369:3369:3369)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (301:301:301) (283:283:283)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~0clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2132:2132:2132) (1906:1906:1906)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (410:410:410)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (348:348:348) (406:406:406)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (395:395:395)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (788:788:788)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datab (347:347:347) (405:405:405)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (381:381:381) (442:442:442)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datad (326:326:326) (392:392:392)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~1) + (DELAY + (ABSOLUTE + (PORT datab (841:841:841) (693:693:693)) + (PORT datac (229:229:229) (244:244:244)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~0) + (DELAY + (ABSOLUTE + (PORT datab (783:783:783) (625:625:625)) + (PORT datac (249:249:249) (266:266:266)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1632:1632:1632)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (596:596:596)) + (PORT datab (366:366:366) (429:429:429)) + (PORT datac (839:839:839) (745:745:745)) + (PORT datad (306:306:306) (366:366:366)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (415:415:415)) + (PORT datab (348:348:348) (406:406:406)) + (PORT datac (306:306:306) (372:372:372)) + (PORT datad (308:308:308) (368:368:368)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (778:778:778)) + (PORT datab (732:732:732) (605:605:605)) + (PORT datac (711:711:711) (589:589:589)) + (PORT datad (892:892:892) (802:802:802)) + (IOPATH dataa combout (394:394:394) (400:400:400)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~2) + (DELAY + (ABSOLUTE + (PORT datab (270:270:270) (277:277:277)) + (PORT datac (799:799:799) (659:659:659)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan2\~0) + (DELAY + (ABSOLUTE + (PORT datab (375:375:375) (435:435:435)) + (PORT datad (317:317:317) (382:382:382)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (750:750:750)) + (PORT datab (904:904:904) (785:785:785)) + (PORT datac (753:753:753) (626:626:626)) + (PORT datad (304:304:304) (363:363:363)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (831:831:831) (712:712:712)) + (PORT datab (858:858:858) (739:739:739)) + (PORT datad (291:291:291) (319:319:319)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1630:1630:1630)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (738:738:738)) + (PORT datab (852:852:852) (733:733:733)) + (PORT datad (296:296:296) (324:324:324)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1630:1630:1630)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[4\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1093:1093:1093) (902:902:902)) + (PORT datab (852:852:852) (732:732:732)) + (PORT datad (297:297:297) (325:325:325)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1630:1630:1630)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (890:890:890)) + (PORT datab (346:346:346) (404:404:404)) + (PORT datac (303:303:303) (370:370:370)) + (PORT datad (304:304:304) (363:363:363)) + (IOPATH dataa combout (394:394:394) (400:400:400)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1168:1168:1168) (956:956:956)) + (PORT datab (856:856:856) (736:736:736)) + (PORT datad (293:293:293) (321:321:321)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1630:1630:1630)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (296:296:296) (317:317:317)) + (PORT datab (347:347:347) (405:405:405)) + (PORT datac (443:443:443) (380:380:380)) + (PORT datad (314:314:314) (376:376:376)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (926:926:926) (775:775:775)) + (PORT datab (852:852:852) (732:732:732)) + (PORT datad (296:296:296) (324:324:324)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1630:1630:1630)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT datab (347:347:347) (405:405:405)) + (PORT datac (305:305:305) (371:371:371)) + (PORT datad (306:306:306) (365:365:365)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[5\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (872:872:872) (735:735:735)) + (PORT datab (856:856:856) (737:737:737)) + (PORT datad (293:293:293) (321:321:321)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1630:1630:1630)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~14) + (DELAY + (ABSOLUTE + (PORT datab (553:553:553) (535:535:535)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[7\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (755:755:755)) + (PORT datab (270:270:270) (277:277:277)) + (PORT datad (1181:1181:1181) (989:989:989)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~18) + (DELAY + (ABSOLUTE + (PORT datad (311:311:311) (372:372:372)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[9\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (756:756:756)) + (PORT datab (271:271:271) (279:279:279)) + (PORT datad (1181:1181:1181) (990:990:990)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[6\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (284:284:284)) + (PORT datab (1241:1241:1241) (1030:1030:1030)) + (PORT datad (817:817:817) (712:712:712)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (399:399:399)) + (PORT datab (338:338:338) (393:393:393)) + (PORT datac (842:842:842) (777:777:777)) + (PORT datad (865:865:865) (793:793:793)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (295:295:295)) + (PORT datab (353:353:353) (414:414:414)) + (PORT datac (930:930:930) (847:847:847)) + (PORT datad (250:250:250) (271:271:271)) + (IOPATH dataa combout (349:349:349) (377:377:377)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan6\~1) + (DELAY + (ABSOLUTE + (PORT datab (347:347:347) (405:405:405)) + (PORT datad (313:313:313) (375:375:375)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~1) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (858:858:858)) + (PORT datab (349:349:349) (408:408:408)) + (PORT datac (511:511:511) (502:502:502)) + (PORT datad (501:501:501) (496:496:496)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~2) + (DELAY + (ABSOLUTE + (PORT dataa (277:277:277) (292:292:292)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (691:691:691) (555:555:555)) + (PORT datad (254:254:254) (275:275:275)) + (IOPATH dataa combout (394:394:394) (400:400:400)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan2\~1) + (DELAY + (ABSOLUTE + (PORT datab (902:902:902) (782:782:782)) + (PORT datac (821:821:821) (736:736:736)) + (PORT datad (303:303:303) (362:362:362)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb_valid\~0) + (DELAY + (ABSOLUTE + (PORT dataa (728:728:728) (604:604:604)) + (PORT datab (950:950:950) (840:840:840)) + (PORT datac (751:751:751) (625:625:625)) + (PORT datad (241:241:241) (255:255:255)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datab combout (423:423:423) (386:386:386)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (556:556:556)) + (PORT datab (810:810:810) (721:721:721)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (557:557:557)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~5) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (532:532:532)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~7) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (540:540:540)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~9) + (DELAY + (ABSOLUTE + (PORT dataa (831:831:831) (743:743:743)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~10) + (DELAY + (ABSOLUTE + (PORT datab (603:603:603) (555:555:555)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (747:747:747)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan14\~0) + (DELAY + (ABSOLUTE + (PORT datab (324:324:324) (343:343:343)) + (PORT datad (271:271:271) (289:289:289)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~14) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (578:578:578)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~16) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (557:557:557)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (705:705:705)) + (PORT datab (269:269:269) (276:276:276)) + (PORT datac (257:257:257) (276:276:276)) + (PORT datad (260:260:260) (272:272:272)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~0) + (DELAY + (ABSOLUTE + (PORT dataa (295:295:295) (317:317:317)) + (PORT datac (926:926:926) (842:842:842)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (755:755:755) (628:628:628)) + (PORT datab (951:951:951) (842:842:842)) + (PORT datac (750:750:750) (623:623:623)) + (PORT datad (244:244:244) (258:258:258)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~3) + (DELAY + (ABSOLUTE + (PORT dataa (728:728:728) (604:604:604)) + (PORT datab (951:951:951) (842:842:842)) + (PORT datac (710:710:710) (588:588:588)) + (PORT datad (242:242:242) (256:256:256)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~4) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (721:721:721)) + (PORT datab (902:902:902) (752:752:752)) + (PORT datac (226:226:226) (242:242:242)) + (PORT datad (227:227:227) (235:235:235)) + (IOPATH dataa combout (349:349:349) (377:377:377)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~4) + (DELAY + (ABSOLUTE + (PORT datab (1194:1194:1194) (1016:1016:1016)) + (PORT datad (824:824:824) (721:721:721)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~9) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (283:283:283)) + (PORT datab (867:867:867) (729:729:729)) + (PORT datac (897:897:897) (809:809:809)) + (PORT datad (262:262:262) (277:277:277)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (763:763:763)) + (PORT datab (943:943:943) (798:798:798)) + (PORT datac (898:898:898) (810:810:810)) + (PORT datad (1151:1151:1151) (977:977:977)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~6) + (DELAY + (ABSOLUTE + (PORT dataa (295:295:295) (317:317:317)) + (PORT datab (304:304:304) (317:317:317)) + (PORT datac (899:899:899) (811:811:811)) + (PORT datad (472:472:472) (420:420:420)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[4\]\~10) + (DELAY + (ABSOLUTE + (PORT datac (900:900:900) (813:813:813)) + (PORT datad (823:823:823) (719:719:719)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~11) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (727:727:727)) + (PORT datab (325:325:325) (345:345:345)) + (PORT datac (780:780:780) (666:666:666)) + (PORT datad (271:271:271) (289:289:289)) + (IOPATH dataa combout (394:394:394) (400:400:400)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~12) + (DELAY + (ABSOLUTE + (PORT dataa (296:296:296) (319:319:319)) + (PORT datab (291:291:291) (299:299:299)) + (PORT datac (232:232:232) (250:250:250)) + (PORT datad (778:778:778) (673:673:673)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~13) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (475:475:475)) + (PORT datab (276:276:276) (286:286:286)) + (PORT datac (271:271:271) (287:287:287)) + (PORT datad (235:235:235) (245:245:245)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1680:1680:1680) (1633:1633:1633)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (724:724:724)) + (PORT datab (318:318:318) (341:341:341)) + (PORT datac (822:822:822) (751:751:751)) + (PORT datad (846:846:846) (719:719:719)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[4\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (764:764:764)) + (PORT datab (951:951:951) (842:842:842)) + (PORT datac (1086:1086:1086) (919:919:919)) + (PORT datad (1154:1154:1154) (980:980:980)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~16) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (295:295:295)) + (PORT datab (307:307:307) (322:322:322)) + (PORT datac (234:234:234) (253:253:253)) + (PORT datad (488:488:488) (418:418:418)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1680:1680:1680) (1633:1633:1633)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (719:719:719)) + (PORT datab (900:900:900) (750:750:750)) + (PORT datac (274:274:274) (308:308:308)) + (PORT datad (883:883:883) (795:795:795)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~25) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (447:447:447)) + (PORT datab (501:501:501) (443:443:443)) + (PORT datac (248:248:248) (264:264:264)) + (PORT datad (791:791:791) (683:683:683)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (398:398:398)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1632:1632:1632)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[5\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (719:719:719)) + (PORT datab (900:900:900) (749:749:749)) + (PORT datac (275:275:275) (308:308:308)) + (PORT datad (277:277:277) (332:332:332)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~18) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (727:727:727)) + (PORT datab (323:323:323) (343:343:343)) + (PORT datac (774:774:774) (661:661:661)) + (PORT datad (271:271:271) (289:289:289)) + (IOPATH dataa combout (420:420:420) (444:444:444)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~14) + (DELAY + (ABSOLUTE + (PORT datab (300:300:300) (310:310:310)) + (PORT datac (781:781:781) (668:668:668)) + (PORT datad (285:285:285) (307:307:307)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~26) + (DELAY + (ABSOLUTE + (PORT dataa (818:818:818) (699:699:699)) + (PORT datab (266:266:266) (272:272:272)) + (PORT datac (255:255:255) (273:273:273)) + (PORT datad (252:252:252) (261:261:261)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~19) + (DELAY + (ABSOLUTE + (PORT datab (910:910:910) (765:765:765)) + (PORT datad (484:484:484) (412:412:412)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1680:1680:1680) (1633:1633:1633)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[7\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (721:721:721)) + (PORT datab (903:903:903) (753:753:753)) + (PORT datac (274:274:274) (307:307:307)) + (PORT datad (801:801:801) (739:739:739)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (512:512:512) (463:463:463)) + (PORT datab (959:959:959) (818:818:818)) + (PORT datad (1152:1152:1152) (978:978:978)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~20) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (749:749:749)) + (PORT datac (819:819:819) (709:709:709)) + (PORT datad (882:882:882) (754:754:754)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~21) + (DELAY + (ABSOLUTE + (PORT dataa (557:557:557) (463:463:463)) + (PORT datab (907:907:907) (762:762:762)) + (PORT datac (460:460:460) (399:399:399)) + (PORT datad (228:228:228) (235:235:235)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1680:1680:1680) (1633:1633:1633)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[10\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (724:724:724)) + (PORT datab (907:907:907) (758:758:758)) + (PORT datac (273:273:273) (306:306:306)) + (PORT datad (903:903:903) (814:814:814)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~22) + (DELAY + (ABSOLUTE + (PORT dataa (296:296:296) (319:319:319)) + (PORT datab (866:866:866) (728:728:728)) + (PORT datac (900:900:900) (813:813:813)) + (PORT datad (266:266:266) (280:280:280)) + (IOPATH dataa combout (349:349:349) (371:371:371)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~23) + (DELAY + (ABSOLUTE + (PORT dataa (302:302:302) (318:318:318)) + (PORT datab (273:273:273) (282:282:282)) + (PORT datac (448:448:448) (384:384:384)) + (PORT datad (270:270:270) (287:287:287)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1680:1680:1680) (1633:1633:1633)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[11\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (720:720:720)) + (PORT datab (889:889:889) (814:814:814)) + (PORT datac (274:274:274) (308:308:308)) + (PORT datad (840:840:840) (712:712:712)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~24) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (297:297:297)) + (PORT datab (311:311:311) (325:325:325)) + (PORT datac (448:448:448) (384:384:384)) + (PORT datad (261:261:261) (275:275:275)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1680:1680:1680) (1633:1633:1633)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[12\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (827:827:827) (723:723:723)) + (PORT datab (831:831:831) (724:724:724)) + (PORT datac (273:273:273) (307:307:307)) + (PORT datad (844:844:844) (717:717:717)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) +) diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_85c_slow.vo b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_85c_slow.vo new file mode 100644 index 0000000..cb1e982 --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_85c_slow.vo @@ -0,0 +1,2833 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 04:42:20" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module vga_colorbar ( + sys_clk, + sys_rst_n, + hsync, + vsync, + rgb); +input sys_clk; +input sys_rst_n; +output hsync; +output vsync; +output [15:0] rgb; + +// Design Ports Information +// hsync => Location: PIN_AA18, I/O Standard: 2.5 V, Current Strength: Default +// vsync => Location: PIN_AB17, I/O Standard: 2.5 V, Current Strength: Default +// rgb[0] => Location: PIN_AB18, I/O Standard: 2.5 V, Current Strength: Default +// rgb[1] => Location: PIN_AA19, I/O Standard: 2.5 V, Current Strength: Default +// rgb[2] => Location: PIN_AB19, I/O Standard: 2.5 V, Current Strength: Default +// rgb[3] => Location: PIN_Y21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[4] => Location: PIN_W19, I/O Standard: 2.5 V, Current Strength: Default +// rgb[5] => Location: PIN_W20, I/O Standard: 2.5 V, Current Strength: Default +// rgb[6] => Location: PIN_U21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[7] => Location: PIN_U22, I/O Standard: 2.5 V, Current Strength: Default +// rgb[8] => Location: PIN_N20, I/O Standard: 2.5 V, Current Strength: Default +// rgb[9] => Location: PIN_N21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[10] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[11] => Location: PIN_M22, I/O Standard: 2.5 V, Current Strength: Default +// rgb[12] => Location: PIN_L21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[13] => Location: PIN_L22, I/O Standard: 2.5 V, Current Strength: Default +// rgb[14] => Location: PIN_K21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[15] => Location: PIN_J21, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("vga_colorbar_8_1200mv_85c_v_slow.sdo"); +// synopsys translate_on + +wire \vga_ctrl_inst|Add0~4_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ; +wire \vga_ctrl_inst|Add1~0_combout ; +wire \vga_ctrl_inst|Add1~2_combout ; +wire \vga_ctrl_inst|Add1~4_combout ; +wire \vga_ctrl_inst|Add1~6_combout ; +wire \vga_ctrl_inst|Add1~8_combout ; +wire \vga_ctrl_inst|Add1~10_combout ; +wire \vga_ctrl_inst|Add1~12_combout ; +wire \vga_ctrl_inst|Add1~16_combout ; +wire \vga_ctrl_inst|Equal0~0_combout ; +wire \vga_ctrl_inst|cnt_v[8]~3_combout ; +wire \vga_pic_inst|pix_data[4]~5_combout ; +wire \vga_pic_inst|pix_data~8_combout ; +wire \vga_pic_inst|pix_data~15_combout ; +wire \vga_pic_inst|pix_data~17_combout ; +wire \sys_clk~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \vga_ctrl_inst|Add0~0_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \sys_rst_n~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ; +wire \rst_n~0_combout ; +wire \rst_n~0clkctrl_outclk ; +wire \vga_ctrl_inst|Add0~1 ; +wire \vga_ctrl_inst|Add0~3 ; +wire \vga_ctrl_inst|Add0~5 ; +wire \vga_ctrl_inst|Add0~6_combout ; +wire \vga_ctrl_inst|Add0~7 ; +wire \vga_ctrl_inst|Add0~8_combout ; +wire \vga_ctrl_inst|Add0~9 ; +wire \vga_ctrl_inst|Add0~11 ; +wire \vga_ctrl_inst|Add0~12_combout ; +wire \vga_ctrl_inst|Add0~13 ; +wire \vga_ctrl_inst|Add0~14_combout ; +wire \vga_ctrl_inst|Add0~15 ; +wire \vga_ctrl_inst|Add0~16_combout ; +wire \vga_ctrl_inst|Add0~17 ; +wire \vga_ctrl_inst|Add0~18_combout ; +wire \vga_ctrl_inst|cnt_h~1_combout ; +wire \vga_ctrl_inst|Add0~10_combout ; +wire \vga_ctrl_inst|cnt_h~0_combout ; +wire \vga_ctrl_inst|Equal0~2_combout ; +wire \vga_ctrl_inst|Add0~2_combout ; +wire \vga_ctrl_inst|Equal0~1_combout ; +wire \vga_ctrl_inst|Equal0~3_combout ; +wire \vga_ctrl_inst|cnt_h~2_combout ; +wire \vga_ctrl_inst|LessThan2~0_combout ; +wire \vga_ctrl_inst|LessThan0~0_combout ; +wire \vga_ctrl_inst|cnt_v[0]~9_combout ; +wire \vga_ctrl_inst|cnt_v[2]~8_combout ; +wire \vga_ctrl_inst|cnt_v[4]~6_combout ; +wire \vga_ctrl_inst|always1~1_combout ; +wire \vga_ctrl_inst|cnt_v[1]~0_combout ; +wire \vga_ctrl_inst|always1~2_combout ; +wire \vga_ctrl_inst|cnt_v[3]~7_combout ; +wire \vga_ctrl_inst|LessThan6~0_combout ; +wire \vga_ctrl_inst|cnt_v[5]~2_combout ; +wire \vga_ctrl_inst|Add1~1 ; +wire \vga_ctrl_inst|Add1~3 ; +wire \vga_ctrl_inst|Add1~5 ; +wire \vga_ctrl_inst|Add1~7 ; +wire \vga_ctrl_inst|Add1~9 ; +wire \vga_ctrl_inst|Add1~11 ; +wire \vga_ctrl_inst|Add1~13 ; +wire \vga_ctrl_inst|Add1~14_combout ; +wire \vga_ctrl_inst|cnt_v[7]~4_combout ; +wire \vga_ctrl_inst|Add1~15 ; +wire \vga_ctrl_inst|Add1~17 ; +wire \vga_ctrl_inst|Add1~18_combout ; +wire \vga_ctrl_inst|cnt_v[9]~1_combout ; +wire \vga_ctrl_inst|cnt_v[6]~5_combout ; +wire \vga_ctrl_inst|always1~0_combout ; +wire \vga_ctrl_inst|LessThan1~0_combout ; +wire \vga_ctrl_inst|LessThan6~1_combout ; +wire \vga_ctrl_inst|pix_data_req~1_combout ; +wire \vga_ctrl_inst|pix_data_req~2_combout ; +wire \vga_ctrl_inst|LessThan2~1_combout ; +wire \vga_ctrl_inst|rgb_valid~0_combout ; +wire \vga_ctrl_inst|Add2~1_cout ; +wire \vga_ctrl_inst|Add2~3_cout ; +wire \vga_ctrl_inst|Add2~5_cout ; +wire \vga_ctrl_inst|Add2~7_cout ; +wire \vga_ctrl_inst|Add2~9_cout ; +wire \vga_ctrl_inst|Add2~11 ; +wire \vga_ctrl_inst|Add2~12_combout ; +wire \vga_ctrl_inst|Add2~10_combout ; +wire \vga_pic_inst|LessThan14~0_combout ; +wire \vga_ctrl_inst|Add2~13 ; +wire \vga_ctrl_inst|Add2~15 ; +wire \vga_ctrl_inst|Add2~16_combout ; +wire \vga_ctrl_inst|Add2~14_combout ; +wire \vga_pic_inst|LessThan6~0_combout ; +wire \vga_ctrl_inst|pix_data_req~0_combout ; +wire \vga_ctrl_inst|LessThan4~0_combout ; +wire \vga_ctrl_inst|pix_data_req~3_combout ; +wire \vga_ctrl_inst|pix_data_req~4_combout ; +wire \vga_pic_inst|pix_data~4_combout ; +wire \vga_pic_inst|pix_data~9_combout ; +wire \vga_pic_inst|LessThan17~0_combout ; +wire \vga_pic_inst|pix_data~6_combout ; +wire \vga_pic_inst|pix_data[4]~10_combout ; +wire \vga_pic_inst|pix_data~11_combout ; +wire \vga_pic_inst|pix_data~12_combout ; +wire \vga_pic_inst|pix_data~13_combout ; +wire \vga_ctrl_inst|rgb[0]~0_combout ; +wire \vga_pic_inst|pix_data[4]~7_combout ; +wire \vga_pic_inst|pix_data~16_combout ; +wire \vga_ctrl_inst|rgb[1]~1_combout ; +wire \vga_pic_inst|pix_data~25_combout ; +wire \vga_ctrl_inst|rgb[5]~2_combout ; +wire \vga_pic_inst|pix_data~18_combout ; +wire \vga_pic_inst|pix_data~14_combout ; +wire \vga_pic_inst|pix_data~26_combout ; +wire \vga_pic_inst|pix_data~19_combout ; +wire \vga_ctrl_inst|rgb[7]~3_combout ; +wire \vga_pic_inst|LessThan2~2_combout ; +wire \vga_pic_inst|pix_data~20_combout ; +wire \vga_pic_inst|pix_data~21_combout ; +wire \vga_ctrl_inst|rgb[10]~4_combout ; +wire \vga_pic_inst|pix_data~22_combout ; +wire \vga_pic_inst|pix_data~23_combout ; +wire \vga_ctrl_inst|rgb[11]~5_combout ; +wire \vga_pic_inst|pix_data~24_combout ; +wire \vga_ctrl_inst|rgb[12]~6_combout ; +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk ; +wire [9:0] \vga_ctrl_inst|cnt_v ; +wire [9:0] \vga_ctrl_inst|cnt_h ; +wire [15:0] \vga_pic_inst|pix_data ; + +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ; + +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [3] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [4] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [4]; + +// Location: LCCOMB_X35_Y23_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~4 ( +// Equation(s): +// \vga_ctrl_inst|Add0~4_combout = (\vga_ctrl_inst|cnt_h [2] & (\vga_ctrl_inst|Add0~3 $ (GND))) # (!\vga_ctrl_inst|cnt_h [2] & (!\vga_ctrl_inst|Add0~3 & VCC)) +// \vga_ctrl_inst|Add0~5 = CARRY((\vga_ctrl_inst|cnt_h [2] & !\vga_ctrl_inst|Add0~3 )) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~3 ), + .combout(\vga_ctrl_inst|Add0~4_combout ), + .cout(\vga_ctrl_inst|Add0~5 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~4 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: PLL_2 +cycloneive_pll \clk_gen_inst|altpll_component|auto_generated|pll1 ( + .areset(!\sys_rst_n~input_o ), + .pfdena(vcc), + .fbin(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\sys_clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_high = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_low = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_divide_by = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_multiply_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .n = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pll_compensation_delay = 6891; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~0 ( +// Equation(s): +// \vga_ctrl_inst|Add1~0_combout = \vga_ctrl_inst|cnt_v [0] $ (VCC) +// \vga_ctrl_inst|Add1~1 = CARRY(\vga_ctrl_inst|cnt_v [0]) + + .dataa(\vga_ctrl_inst|cnt_v [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\vga_ctrl_inst|Add1~0_combout ), + .cout(\vga_ctrl_inst|Add1~1 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~0 .lut_mask = 16'h55AA; +defparam \vga_ctrl_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~2 ( +// Equation(s): +// \vga_ctrl_inst|Add1~2_combout = (\vga_ctrl_inst|cnt_v [1] & (!\vga_ctrl_inst|Add1~1 )) # (!\vga_ctrl_inst|cnt_v [1] & ((\vga_ctrl_inst|Add1~1 ) # (GND))) +// \vga_ctrl_inst|Add1~3 = CARRY((!\vga_ctrl_inst|Add1~1 ) # (!\vga_ctrl_inst|cnt_v [1])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [1]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~1 ), + .combout(\vga_ctrl_inst|Add1~2_combout ), + .cout(\vga_ctrl_inst|Add1~3 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~2 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~4 ( +// Equation(s): +// \vga_ctrl_inst|Add1~4_combout = (\vga_ctrl_inst|cnt_v [2] & (\vga_ctrl_inst|Add1~3 $ (GND))) # (!\vga_ctrl_inst|cnt_v [2] & (!\vga_ctrl_inst|Add1~3 & VCC)) +// \vga_ctrl_inst|Add1~5 = CARRY((\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|Add1~3 )) + + .dataa(\vga_ctrl_inst|cnt_v [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~3 ), + .combout(\vga_ctrl_inst|Add1~4_combout ), + .cout(\vga_ctrl_inst|Add1~5 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~4 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~6 ( +// Equation(s): +// \vga_ctrl_inst|Add1~6_combout = (\vga_ctrl_inst|cnt_v [3] & (!\vga_ctrl_inst|Add1~5 )) # (!\vga_ctrl_inst|cnt_v [3] & ((\vga_ctrl_inst|Add1~5 ) # (GND))) +// \vga_ctrl_inst|Add1~7 = CARRY((!\vga_ctrl_inst|Add1~5 ) # (!\vga_ctrl_inst|cnt_v [3])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~5 ), + .combout(\vga_ctrl_inst|Add1~6_combout ), + .cout(\vga_ctrl_inst|Add1~7 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~6 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~8 ( +// Equation(s): +// \vga_ctrl_inst|Add1~8_combout = (\vga_ctrl_inst|cnt_v [4] & (\vga_ctrl_inst|Add1~7 $ (GND))) # (!\vga_ctrl_inst|cnt_v [4] & (!\vga_ctrl_inst|Add1~7 & VCC)) +// \vga_ctrl_inst|Add1~9 = CARRY((\vga_ctrl_inst|cnt_v [4] & !\vga_ctrl_inst|Add1~7 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [4]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~7 ), + .combout(\vga_ctrl_inst|Add1~8_combout ), + .cout(\vga_ctrl_inst|Add1~9 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~8 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~10 ( +// Equation(s): +// \vga_ctrl_inst|Add1~10_combout = (\vga_ctrl_inst|cnt_v [5] & (!\vga_ctrl_inst|Add1~9 )) # (!\vga_ctrl_inst|cnt_v [5] & ((\vga_ctrl_inst|Add1~9 ) # (GND))) +// \vga_ctrl_inst|Add1~11 = CARRY((!\vga_ctrl_inst|Add1~9 ) # (!\vga_ctrl_inst|cnt_v [5])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [5]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~9 ), + .combout(\vga_ctrl_inst|Add1~10_combout ), + .cout(\vga_ctrl_inst|Add1~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~10 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~12 ( +// Equation(s): +// \vga_ctrl_inst|Add1~12_combout = (\vga_ctrl_inst|cnt_v [6] & (\vga_ctrl_inst|Add1~11 $ (GND))) # (!\vga_ctrl_inst|cnt_v [6] & (!\vga_ctrl_inst|Add1~11 & VCC)) +// \vga_ctrl_inst|Add1~13 = CARRY((\vga_ctrl_inst|cnt_v [6] & !\vga_ctrl_inst|Add1~11 )) + + .dataa(\vga_ctrl_inst|cnt_v [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~11 ), + .combout(\vga_ctrl_inst|Add1~12_combout ), + .cout(\vga_ctrl_inst|Add1~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~12 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N26 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~16 ( +// Equation(s): +// \vga_ctrl_inst|Add1~16_combout = (\vga_ctrl_inst|cnt_v [8] & (\vga_ctrl_inst|Add1~15 $ (GND))) # (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|Add1~15 & VCC)) +// \vga_ctrl_inst|Add1~17 = CARRY((\vga_ctrl_inst|cnt_v [8] & !\vga_ctrl_inst|Add1~15 )) + + .dataa(\vga_ctrl_inst|cnt_v [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~15 ), + .combout(\vga_ctrl_inst|Add1~16_combout ), + .cout(\vga_ctrl_inst|Add1~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~16 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y23_N13 +dffeas \vga_ctrl_inst|cnt_v[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[8]~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[8] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~0 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~0_combout = (\vga_ctrl_inst|cnt_h [8] & \vga_ctrl_inst|cnt_h [9]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~0 .lut_mask = 16'hCC00; +defparam \vga_ctrl_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N13 +dffeas \vga_ctrl_inst|cnt_h[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [2]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[2] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N12 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[8]~3 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[8]~3_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~16_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [8])))) + + .dataa(\vga_ctrl_inst|Add1~16_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [8]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[8]~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[8]~3 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[8]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data[4]~5 ( +// Equation(s): +// \vga_pic_inst|pix_data[4]~5_combout = (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~16_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|pix_data_req~4_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~16_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4]~5 .lut_mask = 16'h00CC; +defparam \vga_pic_inst|pix_data[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~8 ( +// Equation(s): +// \vga_pic_inst|pix_data~8_combout = (\vga_ctrl_inst|Add2~16_combout ) # (((\vga_ctrl_inst|Add2~14_combout ) # (!\vga_ctrl_inst|pix_data_req~4_combout )) # (!\vga_ctrl_inst|Add2~10_combout )) + + .dataa(\vga_ctrl_inst|Add2~16_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~8 .lut_mask = 16'hFBFF; +defparam \vga_pic_inst|pix_data~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N10 +cycloneive_lcell_comb \vga_pic_inst|pix_data~15 ( +// Equation(s): +// \vga_pic_inst|pix_data~15_combout = (\vga_pic_inst|pix_data[4]~5_combout & (\vga_pic_inst|pix_data~11_combout & ((!\vga_pic_inst|pix_data[4]~10_combout )))) # (!\vga_pic_inst|pix_data[4]~5_combout & (((\vga_pic_inst|pix_data~14_combout )))) + + .dataa(\vga_pic_inst|pix_data~11_combout ), + .datab(\vga_pic_inst|pix_data~14_combout ), + .datac(\vga_pic_inst|pix_data[4]~10_combout ), + .datad(\vga_pic_inst|pix_data[4]~5_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~15_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~15 .lut_mask = 16'h0ACC; +defparam \vga_pic_inst|pix_data~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~17 ( +// Equation(s): +// \vga_pic_inst|pix_data~17_combout = (\vga_ctrl_inst|Add2~12_combout & (!\vga_ctrl_inst|Add2~14_combout )) # (!\vga_ctrl_inst|Add2~12_combout & (\vga_ctrl_inst|Add2~14_combout & !\vga_ctrl_inst|Add2~10_combout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~17_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~17 .lut_mask = 16'h0C3C; +defparam \vga_pic_inst|pix_data~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOOBUF_X35_Y0_N30 +cycloneive_io_obuf \hsync~output ( + .i(!\vga_ctrl_inst|LessThan0~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(hsync), + .obar()); +// synopsys translate_off +defparam \hsync~output .bus_hold = "false"; +defparam \hsync~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X28_Y0_N2 +cycloneive_io_obuf \vsync~output ( + .i(!\vga_ctrl_inst|LessThan1~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(vsync), + .obar()); +// synopsys translate_off +defparam \vsync~output .bus_hold = "false"; +defparam \vsync~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X32_Y0_N2 +cycloneive_io_obuf \rgb[0]~output ( + .i(\vga_ctrl_inst|rgb[0]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[0]), + .obar()); +// synopsys translate_off +defparam \rgb[0]~output .bus_hold = "false"; +defparam \rgb[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X35_Y0_N23 +cycloneive_io_obuf \rgb[1]~output ( + .i(\vga_ctrl_inst|rgb[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[1]), + .obar()); +// synopsys translate_off +defparam \rgb[1]~output .bus_hold = "false"; +defparam \rgb[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X35_Y0_N16 +cycloneive_io_obuf \rgb[2]~output ( + .i(\vga_ctrl_inst|rgb[0]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[2]), + .obar()); +// synopsys translate_off +defparam \rgb[2]~output .bus_hold = "false"; +defparam \rgb[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y4_N9 +cycloneive_io_obuf \rgb[3]~output ( + .i(\vga_ctrl_inst|rgb[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[3]), + .obar()); +// synopsys translate_off +defparam \rgb[3]~output .bus_hold = "false"; +defparam \rgb[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y3_N9 +cycloneive_io_obuf \rgb[4]~output ( + .i(\vga_ctrl_inst|rgb[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[4]), + .obar()); +// synopsys translate_off +defparam \rgb[4]~output .bus_hold = "false"; +defparam \rgb[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y3_N16 +cycloneive_io_obuf \rgb[5]~output ( + .i(\vga_ctrl_inst|rgb[5]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[5]), + .obar()); +// synopsys translate_off +defparam \rgb[5]~output .bus_hold = "false"; +defparam \rgb[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y8_N2 +cycloneive_io_obuf \rgb[6]~output ( + .i(\vga_ctrl_inst|rgb[5]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[6]), + .obar()); +// synopsys translate_off +defparam \rgb[6]~output .bus_hold = "false"; +defparam \rgb[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y8_N9 +cycloneive_io_obuf \rgb[7]~output ( + .i(\vga_ctrl_inst|rgb[7]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[7]), + .obar()); +// synopsys translate_off +defparam \rgb[7]~output .bus_hold = "false"; +defparam \rgb[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y12_N16 +cycloneive_io_obuf \rgb[8]~output ( + .i(\vga_ctrl_inst|rgb[5]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[8]), + .obar()); +// synopsys translate_off +defparam \rgb[8]~output .bus_hold = "false"; +defparam \rgb[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y13_N9 +cycloneive_io_obuf \rgb[9]~output ( + .i(\vga_ctrl_inst|rgb[7]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[9]), + .obar()); +// synopsys translate_off +defparam \rgb[9]~output .bus_hold = "false"; +defparam \rgb[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y14_N23 +cycloneive_io_obuf \rgb[10]~output ( + .i(\vga_ctrl_inst|rgb[10]~4_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[10]), + .obar()); +// synopsys translate_off +defparam \rgb[10]~output .bus_hold = "false"; +defparam \rgb[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y13_N2 +cycloneive_io_obuf \rgb[11]~output ( + .i(\vga_ctrl_inst|rgb[11]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[11]), + .obar()); +// synopsys translate_off +defparam \rgb[11]~output .bus_hold = "false"; +defparam \rgb[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y18_N16 +cycloneive_io_obuf \rgb[12]~output ( + .i(\vga_ctrl_inst|rgb[12]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[12]), + .obar()); +// synopsys translate_off +defparam \rgb[12]~output .bus_hold = "false"; +defparam \rgb[12]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y18_N23 +cycloneive_io_obuf \rgb[13]~output ( + .i(\vga_ctrl_inst|rgb[11]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[13]), + .obar()); +// synopsys translate_off +defparam \rgb[13]~output .bus_hold = "false"; +defparam \rgb[13]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y19_N9 +cycloneive_io_obuf \rgb[14]~output ( + .i(\vga_ctrl_inst|rgb[12]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[14]), + .obar()); +// synopsys translate_off +defparam \rgb[14]~output .bus_hold = "false"; +defparam \rgb[14]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y20_N23 +cycloneive_io_obuf \rgb[15]~output ( + .i(\vga_ctrl_inst|rgb[12]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[15]), + .obar()); +// synopsys translate_off +defparam \rgb[15]~output .bus_hold = "false"; +defparam \rgb[15]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~0 ( +// Equation(s): +// \vga_ctrl_inst|Add0~0_combout = \vga_ctrl_inst|cnt_h [0] $ (VCC) +// \vga_ctrl_inst|Add0~1 = CARRY(\vga_ctrl_inst|cnt_h [0]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\vga_ctrl_inst|Add0~0_combout ), + .cout(\vga_ctrl_inst|Add0~1 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~0 .lut_mask = 16'h33CC; +defparam \vga_ctrl_inst|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y3_N0 +cycloneive_lcell_comb \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X35_Y3_N1 +dffeas \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .d(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y3_N10 +cycloneive_lcell_comb \rst_n~0 ( +// Equation(s): +// \rst_n~0_combout = ((!\sys_rst_n~input_o ) # (!\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q )) # (!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ) + + .dataa(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .datac(\sys_rst_n~input_o ), + .datad(gnd), + .cin(gnd), + .combout(\rst_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \rst_n~0 .lut_mask = 16'h7F7F; +defparam \rst_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G16 +cycloneive_clkctrl \rst_n~0clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~0_combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~0clkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~0clkctrl .clock_type = "global clock"; +defparam \rst_n~0clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X35_Y23_N9 +dffeas \vga_ctrl_inst|cnt_h[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[0] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~2 ( +// Equation(s): +// \vga_ctrl_inst|Add0~2_combout = (\vga_ctrl_inst|cnt_h [1] & (!\vga_ctrl_inst|Add0~1 )) # (!\vga_ctrl_inst|cnt_h [1] & ((\vga_ctrl_inst|Add0~1 ) # (GND))) +// \vga_ctrl_inst|Add0~3 = CARRY((!\vga_ctrl_inst|Add0~1 ) # (!\vga_ctrl_inst|cnt_h [1])) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~1 ), + .combout(\vga_ctrl_inst|Add0~2_combout ), + .cout(\vga_ctrl_inst|Add0~3 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~2 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~6 ( +// Equation(s): +// \vga_ctrl_inst|Add0~6_combout = (\vga_ctrl_inst|cnt_h [3] & (!\vga_ctrl_inst|Add0~5 )) # (!\vga_ctrl_inst|cnt_h [3] & ((\vga_ctrl_inst|Add0~5 ) # (GND))) +// \vga_ctrl_inst|Add0~7 = CARRY((!\vga_ctrl_inst|Add0~5 ) # (!\vga_ctrl_inst|cnt_h [3])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [3]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~5 ), + .combout(\vga_ctrl_inst|Add0~6_combout ), + .cout(\vga_ctrl_inst|Add0~7 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~6 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N15 +dffeas \vga_ctrl_inst|cnt_h[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [3]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[3] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~8 ( +// Equation(s): +// \vga_ctrl_inst|Add0~8_combout = (\vga_ctrl_inst|cnt_h [4] & (\vga_ctrl_inst|Add0~7 $ (GND))) # (!\vga_ctrl_inst|cnt_h [4] & (!\vga_ctrl_inst|Add0~7 & VCC)) +// \vga_ctrl_inst|Add0~9 = CARRY((\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|Add0~7 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [4]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~7 ), + .combout(\vga_ctrl_inst|Add0~8_combout ), + .cout(\vga_ctrl_inst|Add0~9 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~8 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N17 +dffeas \vga_ctrl_inst|cnt_h[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[4] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~10 ( +// Equation(s): +// \vga_ctrl_inst|Add0~10_combout = (\vga_ctrl_inst|cnt_h [5] & (!\vga_ctrl_inst|Add0~9 )) # (!\vga_ctrl_inst|cnt_h [5] & ((\vga_ctrl_inst|Add0~9 ) # (GND))) +// \vga_ctrl_inst|Add0~11 = CARRY((!\vga_ctrl_inst|Add0~9 ) # (!\vga_ctrl_inst|cnt_h [5])) + + .dataa(\vga_ctrl_inst|cnt_h [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~9 ), + .combout(\vga_ctrl_inst|Add0~10_combout ), + .cout(\vga_ctrl_inst|Add0~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~10 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~12 ( +// Equation(s): +// \vga_ctrl_inst|Add0~12_combout = (\vga_ctrl_inst|cnt_h [6] & (\vga_ctrl_inst|Add0~11 $ (GND))) # (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|Add0~11 & VCC)) +// \vga_ctrl_inst|Add0~13 = CARRY((\vga_ctrl_inst|cnt_h [6] & !\vga_ctrl_inst|Add0~11 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~11 ), + .combout(\vga_ctrl_inst|Add0~12_combout ), + .cout(\vga_ctrl_inst|Add0~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~12 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N21 +dffeas \vga_ctrl_inst|cnt_h[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [6]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[6] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~14 ( +// Equation(s): +// \vga_ctrl_inst|Add0~14_combout = (\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Add0~13 )) # (!\vga_ctrl_inst|cnt_h [7] & ((\vga_ctrl_inst|Add0~13 ) # (GND))) +// \vga_ctrl_inst|Add0~15 = CARRY((!\vga_ctrl_inst|Add0~13 ) # (!\vga_ctrl_inst|cnt_h [7])) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~13 ), + .combout(\vga_ctrl_inst|Add0~14_combout ), + .cout(\vga_ctrl_inst|Add0~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~14 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N23 +dffeas \vga_ctrl_inst|cnt_h[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [7]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[7] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N24 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~16 ( +// Equation(s): +// \vga_ctrl_inst|Add0~16_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|Add0~15 $ (GND))) # (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|Add0~15 & VCC)) +// \vga_ctrl_inst|Add0~17 = CARRY((\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|Add0~15 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~15 ), + .combout(\vga_ctrl_inst|Add0~16_combout ), + .cout(\vga_ctrl_inst|Add0~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~16 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N26 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~18 ( +// Equation(s): +// \vga_ctrl_inst|Add0~18_combout = \vga_ctrl_inst|Add0~17 $ (\vga_ctrl_inst|cnt_h [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(\vga_ctrl_inst|Add0~17 ), + .combout(\vga_ctrl_inst|Add0~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~18 .lut_mask = 16'h0FF0; +defparam \vga_ctrl_inst|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~1 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~1_combout = (!\vga_ctrl_inst|Equal0~3_combout & \vga_ctrl_inst|Add0~18_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|Add0~18_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~1 .lut_mask = 16'h3030; +defparam \vga_ctrl_inst|cnt_h~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N1 +dffeas \vga_ctrl_inst|cnt_h[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[9] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N24 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~0 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~0_combout = (\vga_ctrl_inst|Add0~10_combout & !\vga_ctrl_inst|Equal0~3_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add0~10_combout ), + .datac(\vga_ctrl_inst|Equal0~3_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~0 .lut_mask = 16'h0C0C; +defparam \vga_ctrl_inst|cnt_h~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y23_N25 +dffeas \vga_ctrl_inst|cnt_h[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [5]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[5] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N30 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~2 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~2_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|cnt_h [9] & (!\vga_ctrl_inst|cnt_h [5] & !\vga_ctrl_inst|cnt_h [6]))) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(\vga_ctrl_inst|cnt_h [9]), + .datac(\vga_ctrl_inst|cnt_h [5]), + .datad(\vga_ctrl_inst|cnt_h [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~2 .lut_mask = 16'h0008; +defparam \vga_ctrl_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N11 +dffeas \vga_ctrl_inst|cnt_h[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [1]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[1] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N28 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~1 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~1_combout = (\vga_ctrl_inst|cnt_h [2] & (\vga_ctrl_inst|cnt_h [3] & (\vga_ctrl_inst|cnt_h [0] & \vga_ctrl_inst|cnt_h [1]))) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(\vga_ctrl_inst|cnt_h [3]), + .datac(\vga_ctrl_inst|cnt_h [0]), + .datad(\vga_ctrl_inst|cnt_h [1]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~1 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~3 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~3_combout = (\vga_ctrl_inst|cnt_h [4] & (\vga_ctrl_inst|Equal0~2_combout & (\vga_ctrl_inst|Equal0~1_combout & !\vga_ctrl_inst|cnt_h [7]))) + + .dataa(\vga_ctrl_inst|cnt_h [4]), + .datab(\vga_ctrl_inst|Equal0~2_combout ), + .datac(\vga_ctrl_inst|Equal0~1_combout ), + .datad(\vga_ctrl_inst|cnt_h [7]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~3 .lut_mask = 16'h0080; +defparam \vga_ctrl_inst|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~2 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~2_combout = (\vga_ctrl_inst|Add0~16_combout & !\vga_ctrl_inst|Equal0~3_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add0~16_combout ), + .datac(\vga_ctrl_inst|Equal0~3_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~2 .lut_mask = 16'h0C0C; +defparam \vga_ctrl_inst|cnt_h~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N3 +dffeas \vga_ctrl_inst|cnt_h[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[8] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N4 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan2~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan2~0_combout = (!\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|cnt_h [9]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan2~0 .lut_mask = 16'h0033; +defparam \vga_ctrl_inst|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan0~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan0~0_combout = (\vga_ctrl_inst|cnt_h [7]) # (((\vga_ctrl_inst|cnt_h [6] & \vga_ctrl_inst|cnt_h [5])) # (!\vga_ctrl_inst|LessThan2~0_combout )) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(\vga_ctrl_inst|LessThan2~0_combout ), + .datad(\vga_ctrl_inst|cnt_h [5]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan0~0 .lut_mask = 16'hEFAF; +defparam \vga_ctrl_inst|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N28 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[0]~9 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[0]~9_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~0_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [0])))) + + .dataa(\vga_ctrl_inst|Add1~0_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [0]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[0]~9 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N29 +dffeas \vga_ctrl_inst|cnt_v[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[0]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[0] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N4 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[2]~8 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[2]~8_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~4_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [2])))) + + .dataa(\vga_ctrl_inst|Add1~4_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[2]~8 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N5 +dffeas \vga_ctrl_inst|cnt_v[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[2]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [2]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[2] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[4]~6 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[4]~6_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~8_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [4])))) + + .dataa(\vga_ctrl_inst|Add1~8_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [4]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[4]~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[4]~6 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[4]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N1 +dffeas \vga_ctrl_inst|cnt_v[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[4]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[4] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|always1~1 ( +// Equation(s): +// \vga_ctrl_inst|always1~1_combout = (\vga_ctrl_inst|cnt_v [9] & (\vga_ctrl_inst|cnt_v [3] & (\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|cnt_v [4]))) + + .dataa(\vga_ctrl_inst|cnt_v [9]), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|cnt_v [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~1 .lut_mask = 16'h0080; +defparam \vga_ctrl_inst|always1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[1]~0 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[1]~0_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~2_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [1])))) + + .dataa(\vga_ctrl_inst|Add1~2_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [1]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[1]~0 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N17 +dffeas \vga_ctrl_inst|cnt_v[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[1]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [1]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[1] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|always1~2 ( +// Equation(s): +// \vga_ctrl_inst|always1~2_combout = (\vga_ctrl_inst|always1~0_combout & (!\vga_ctrl_inst|cnt_v [0] & (\vga_ctrl_inst|always1~1_combout & !\vga_ctrl_inst|cnt_v [1]))) + + .dataa(\vga_ctrl_inst|always1~0_combout ), + .datab(\vga_ctrl_inst|cnt_v [0]), + .datac(\vga_ctrl_inst|always1~1_combout ), + .datad(\vga_ctrl_inst|cnt_v [1]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~2 .lut_mask = 16'h0020; +defparam \vga_ctrl_inst|always1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[3]~7 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[3]~7_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~6_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [3])))) + + .dataa(\vga_ctrl_inst|Add1~6_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [3]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[3]~7 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N3 +dffeas \vga_ctrl_inst|cnt_v[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[3]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [3]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[3] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan6~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan6~0_combout = (!\vga_ctrl_inst|cnt_v [3] & (!\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|cnt_v [4])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|cnt_v [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan6~0 .lut_mask = 16'h0003; +defparam \vga_ctrl_inst|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[5]~2 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[5]~2_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~10_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [5])))) + + .dataa(\vga_ctrl_inst|Add1~10_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [5]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[5]~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[5]~2 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[5]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N19 +dffeas \vga_ctrl_inst|cnt_v[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[5]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [5]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[5] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N24 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~14 ( +// Equation(s): +// \vga_ctrl_inst|Add1~14_combout = (\vga_ctrl_inst|cnt_v [7] & (!\vga_ctrl_inst|Add1~13 )) # (!\vga_ctrl_inst|cnt_v [7] & ((\vga_ctrl_inst|Add1~13 ) # (GND))) +// \vga_ctrl_inst|Add1~15 = CARRY((!\vga_ctrl_inst|Add1~13 ) # (!\vga_ctrl_inst|cnt_v [7])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [7]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~13 ), + .combout(\vga_ctrl_inst|Add1~14_combout ), + .cout(\vga_ctrl_inst|Add1~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~14 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[7]~4 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[7]~4_combout = (\vga_ctrl_inst|Equal0~3_combout & (!\vga_ctrl_inst|always1~2_combout & (\vga_ctrl_inst|Add1~14_combout ))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [7])))) + + .dataa(\vga_ctrl_inst|always1~2_combout ), + .datab(\vga_ctrl_inst|Add1~14_combout ), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[7]~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[7]~4 .lut_mask = 16'h44F0; +defparam \vga_ctrl_inst|cnt_v[7]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y24_N3 +dffeas \vga_ctrl_inst|cnt_v[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[7]~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [7]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[7] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N28 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~18 ( +// Equation(s): +// \vga_ctrl_inst|Add1~18_combout = \vga_ctrl_inst|Add1~17 $ (\vga_ctrl_inst|cnt_v [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_v [9]), + .cin(\vga_ctrl_inst|Add1~17 ), + .combout(\vga_ctrl_inst|Add1~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~18 .lut_mask = 16'h0FF0; +defparam \vga_ctrl_inst|Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[9]~1 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[9]~1_combout = (\vga_ctrl_inst|Equal0~3_combout & (!\vga_ctrl_inst|always1~2_combout & (\vga_ctrl_inst|Add1~18_combout ))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [9])))) + + .dataa(\vga_ctrl_inst|always1~2_combout ), + .datab(\vga_ctrl_inst|Add1~18_combout ), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[9]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[9]~1 .lut_mask = 16'h44F0; +defparam \vga_ctrl_inst|cnt_v[9]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y24_N1 +dffeas \vga_ctrl_inst|cnt_v[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[9]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[9] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N4 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[6]~5 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[6]~5_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~12_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [6])))) + + .dataa(\vga_ctrl_inst|Add1~12_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [6]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[6]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[6]~5 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[6]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y24_N5 +dffeas \vga_ctrl_inst|cnt_v[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[6]~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [6]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[6] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|always1~0 ( +// Equation(s): +// \vga_ctrl_inst|always1~0_combout = (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|cnt_v [5] & (!\vga_ctrl_inst|cnt_v [7] & !\vga_ctrl_inst|cnt_v [6]))) + + .dataa(\vga_ctrl_inst|cnt_v [8]), + .datab(\vga_ctrl_inst|cnt_v [5]), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|cnt_v [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~0 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan1~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan1~0_combout = ((\vga_ctrl_inst|cnt_v [1]) # ((\vga_ctrl_inst|cnt_v [9]) # (!\vga_ctrl_inst|always1~0_combout ))) # (!\vga_ctrl_inst|LessThan6~0_combout ) + + .dataa(\vga_ctrl_inst|LessThan6~0_combout ), + .datab(\vga_ctrl_inst|cnt_v [1]), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(\vga_ctrl_inst|always1~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan1~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan1~0 .lut_mask = 16'hFDFF; +defparam \vga_ctrl_inst|LessThan1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan6~1 ( +// Equation(s): +// \vga_ctrl_inst|LessThan6~1_combout = (!\vga_ctrl_inst|cnt_v [1]) # (!\vga_ctrl_inst|cnt_v [0]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [0]), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_v [1]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan6~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan6~1 .lut_mask = 16'h33FF; +defparam \vga_ctrl_inst|LessThan6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N30 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~1 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~1_combout = (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|cnt_v [9] & (!\vga_ctrl_inst|cnt_v [7] & !\vga_ctrl_inst|cnt_v [6]))) + + .dataa(\vga_ctrl_inst|cnt_v [8]), + .datab(\vga_ctrl_inst|cnt_v [9]), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|cnt_v [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~1 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|pix_data_req~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N24 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~2 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~2_combout = (\vga_ctrl_inst|LessThan6~0_combout & ((\vga_ctrl_inst|LessThan6~1_combout & (\vga_ctrl_inst|pix_data_req~1_combout )) # (!\vga_ctrl_inst|LessThan6~1_combout & ((\vga_ctrl_inst|always1~0_combout ))))) # +// (!\vga_ctrl_inst|LessThan6~0_combout & (((\vga_ctrl_inst|always1~0_combout )))) + + .dataa(\vga_ctrl_inst|LessThan6~0_combout ), + .datab(\vga_ctrl_inst|LessThan6~1_combout ), + .datac(\vga_ctrl_inst|pix_data_req~1_combout ), + .datad(\vga_ctrl_inst|always1~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~2 .lut_mask = 16'hF780; +defparam \vga_ctrl_inst|pix_data_req~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N28 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan2~1 ( +// Equation(s): +// \vga_ctrl_inst|LessThan2~1_combout = (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|cnt_h [5])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(\vga_ctrl_inst|cnt_h [4]), + .datad(\vga_ctrl_inst|cnt_h [5]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan2~1 .lut_mask = 16'h0003; +defparam \vga_ctrl_inst|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|rgb_valid~0 ( +// Equation(s): +// \vga_ctrl_inst|rgb_valid~0_combout = (\vga_ctrl_inst|Equal0~0_combout & (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|LessThan2~0_combout & \vga_ctrl_inst|LessThan2~1_combout ))) # (!\vga_ctrl_inst|Equal0~0_combout & (((\vga_ctrl_inst|cnt_h [7] & +// !\vga_ctrl_inst|LessThan2~1_combout )) # (!\vga_ctrl_inst|LessThan2~0_combout ))) + + .dataa(\vga_ctrl_inst|Equal0~0_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|LessThan2~0_combout ), + .datad(\vga_ctrl_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb_valid~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb_valid~0 .lut_mask = 16'h0745; +defparam \vga_ctrl_inst|rgb_valid~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~1 ( +// Equation(s): +// \vga_ctrl_inst|Add2~1_cout = CARRY((\vga_ctrl_inst|cnt_h [1] & \vga_ctrl_inst|cnt_h [0])) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(\vga_ctrl_inst|cnt_h [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\vga_ctrl_inst|Add2~1_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~1 .lut_mask = 16'h0088; +defparam \vga_ctrl_inst|Add2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~3 ( +// Equation(s): +// \vga_ctrl_inst|Add2~3_cout = CARRY((!\vga_ctrl_inst|Add2~1_cout ) # (!\vga_ctrl_inst|cnt_h [2])) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~1_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~3_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~3 .lut_mask = 16'h005F; +defparam \vga_ctrl_inst|Add2~3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~5 ( +// Equation(s): +// \vga_ctrl_inst|Add2~5_cout = CARRY((\vga_ctrl_inst|cnt_h [3] & !\vga_ctrl_inst|Add2~3_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~3_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~5_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~5 .lut_mask = 16'h000A; +defparam \vga_ctrl_inst|Add2~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~7 ( +// Equation(s): +// \vga_ctrl_inst|Add2~7_cout = CARRY((!\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|Add2~5_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~5_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~7_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~7 .lut_mask = 16'h0005; +defparam \vga_ctrl_inst|Add2~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~9 ( +// Equation(s): +// \vga_ctrl_inst|Add2~9_cout = CARRY((\vga_ctrl_inst|cnt_h [5]) # (!\vga_ctrl_inst|Add2~7_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~7_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~9_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~9 .lut_mask = 16'h00AF; +defparam \vga_ctrl_inst|Add2~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~10 ( +// Equation(s): +// \vga_ctrl_inst|Add2~10_combout = (\vga_ctrl_inst|cnt_h [6] & (\vga_ctrl_inst|Add2~9_cout & VCC)) # (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|Add2~9_cout )) +// \vga_ctrl_inst|Add2~11 = CARRY((!\vga_ctrl_inst|cnt_h [6] & !\vga_ctrl_inst|Add2~9_cout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~9_cout ), + .combout(\vga_ctrl_inst|Add2~10_combout ), + .cout(\vga_ctrl_inst|Add2~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~10 .lut_mask = 16'hC303; +defparam \vga_ctrl_inst|Add2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~12 ( +// Equation(s): +// \vga_ctrl_inst|Add2~12_combout = (\vga_ctrl_inst|cnt_h [7] & (\vga_ctrl_inst|Add2~11 $ (GND))) # (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Add2~11 & VCC)) +// \vga_ctrl_inst|Add2~13 = CARRY((\vga_ctrl_inst|cnt_h [7] & !\vga_ctrl_inst|Add2~11 )) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~11 ), + .combout(\vga_ctrl_inst|Add2~12_combout ), + .cout(\vga_ctrl_inst|Add2~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~12 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N24 +cycloneive_lcell_comb \vga_pic_inst|LessThan14~0 ( +// Equation(s): +// \vga_pic_inst|LessThan14~0_combout = (\vga_ctrl_inst|Add2~12_combout & \vga_ctrl_inst|Add2~10_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan14~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan14~0 .lut_mask = 16'hCC00; +defparam \vga_pic_inst|LessThan14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~14 ( +// Equation(s): +// \vga_ctrl_inst|Add2~14_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|Add2~13 & VCC)) # (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|Add2~13 )) +// \vga_ctrl_inst|Add2~15 = CARRY((!\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|Add2~13 )) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~13 ), + .combout(\vga_ctrl_inst|Add2~14_combout ), + .cout(\vga_ctrl_inst|Add2~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~14 .lut_mask = 16'hA505; +defparam \vga_ctrl_inst|Add2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~16 ( +// Equation(s): +// \vga_ctrl_inst|Add2~16_combout = \vga_ctrl_inst|cnt_h [9] $ (\vga_ctrl_inst|Add2~15 ) + + .dataa(\vga_ctrl_inst|cnt_h [9]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\vga_ctrl_inst|Add2~15 ), + .combout(\vga_ctrl_inst|Add2~16_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~16 .lut_mask = 16'h5A5A; +defparam \vga_ctrl_inst|Add2~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N2 +cycloneive_lcell_comb \vga_pic_inst|LessThan6~0 ( +// Equation(s): +// \vga_pic_inst|LessThan6~0_combout = ((\vga_pic_inst|LessThan14~0_combout ) # ((\vga_ctrl_inst|Add2~16_combout ) # (\vga_ctrl_inst|Add2~14_combout ))) # (!\vga_ctrl_inst|pix_data_req~4_combout ) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_pic_inst|LessThan14~0_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan6~0 .lut_mask = 16'hFFFD; +defparam \vga_pic_inst|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N26 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~0 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~0_combout = (!\vga_ctrl_inst|always1~0_combout & \vga_ctrl_inst|cnt_v [9]) + + .dataa(\vga_ctrl_inst|always1~0_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~0 .lut_mask = 16'h5050; +defparam \vga_ctrl_inst|pix_data_req~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N4 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan4~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan4~0_combout = (\vga_ctrl_inst|LessThan2~0_combout & (((!\vga_ctrl_inst|Equal0~1_combout & \vga_ctrl_inst|LessThan2~1_combout )) # (!\vga_ctrl_inst|cnt_h [7]))) + + .dataa(\vga_ctrl_inst|Equal0~1_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|LessThan2~0_combout ), + .datad(\vga_ctrl_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan4~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan4~0 .lut_mask = 16'h7030; +defparam \vga_ctrl_inst|LessThan4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~3 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~3_combout = ((!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Equal0~1_combout & \vga_ctrl_inst|LessThan2~1_combout ))) # (!\vga_ctrl_inst|Equal0~0_combout ) + + .dataa(\vga_ctrl_inst|Equal0~0_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|Equal0~1_combout ), + .datad(\vga_ctrl_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~3 .lut_mask = 16'h5755; +defparam \vga_ctrl_inst|pix_data_req~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~4 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~4_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (!\vga_ctrl_inst|LessThan4~0_combout & \vga_ctrl_inst|pix_data_req~3_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|LessThan4~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~4 .lut_mask = 16'h0100; +defparam \vga_ctrl_inst|pix_data_req~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N2 +cycloneive_lcell_comb \vga_pic_inst|pix_data~4 ( +// Equation(s): +// \vga_pic_inst|pix_data~4_combout = (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~12_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|pix_data_req~4_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~4 .lut_mask = 16'h00CC; +defparam \vga_pic_inst|pix_data~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~9 ( +// Equation(s): +// \vga_pic_inst|pix_data~9_combout = (\vga_pic_inst|pix_data~8_combout & ((\vga_pic_inst|LessThan6~0_combout ) # ((!\vga_ctrl_inst|Add2~14_combout & \vga_pic_inst|pix_data~4_combout )))) # (!\vga_pic_inst|pix_data~8_combout & +// (((!\vga_ctrl_inst|Add2~14_combout & \vga_pic_inst|pix_data~4_combout )))) + + .dataa(\vga_pic_inst|pix_data~8_combout ), + .datab(\vga_pic_inst|LessThan6~0_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_pic_inst|pix_data~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~9_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~9 .lut_mask = 16'h8F88; +defparam \vga_pic_inst|pix_data~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N8 +cycloneive_lcell_comb \vga_pic_inst|LessThan17~0 ( +// Equation(s): +// \vga_pic_inst|LessThan17~0_combout = (\vga_ctrl_inst|Add2~12_combout ) # ((\vga_ctrl_inst|Add2~10_combout ) # ((\vga_ctrl_inst|Add2~14_combout ) # (!\vga_ctrl_inst|pix_data_req~4_combout ))) + + .dataa(\vga_ctrl_inst|Add2~12_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan17~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan17~0 .lut_mask = 16'hFEFF; +defparam \vga_pic_inst|LessThan17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N14 +cycloneive_lcell_comb \vga_pic_inst|pix_data~6 ( +// Equation(s): +// \vga_pic_inst|pix_data~6_combout = ((\vga_pic_inst|LessThan17~0_combout & ((\vga_ctrl_inst|Add2~14_combout ) # (!\vga_pic_inst|pix_data~4_combout )))) # (!\vga_pic_inst|pix_data[4]~5_combout ) + + .dataa(\vga_pic_inst|pix_data[4]~5_combout ), + .datab(\vga_pic_inst|pix_data~4_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_pic_inst|LessThan17~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~6 .lut_mask = 16'hF755; +defparam \vga_pic_inst|pix_data~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N22 +cycloneive_lcell_comb \vga_pic_inst|pix_data[4]~10 ( +// Equation(s): +// \vga_pic_inst|pix_data[4]~10_combout = (!\vga_ctrl_inst|Add2~12_combout ) # (!\vga_ctrl_inst|Add2~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[4]~10_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4]~10 .lut_mask = 16'h0FFF; +defparam \vga_pic_inst|pix_data[4]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~11 ( +// Equation(s): +// \vga_pic_inst|pix_data~11_combout = (\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|Add2~12_combout & (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~10_combout ))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~11_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~11 .lut_mask = 16'h0080; +defparam \vga_pic_inst|pix_data~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N24 +cycloneive_lcell_comb \vga_pic_inst|pix_data~12 ( +// Equation(s): +// \vga_pic_inst|pix_data~12_combout = (\vga_pic_inst|pix_data[4]~5_combout & (((\vga_pic_inst|pix_data[4]~10_combout ) # (!\vga_pic_inst|pix_data~11_combout )))) # (!\vga_pic_inst|pix_data[4]~5_combout & (\vga_pic_inst|LessThan17~0_combout )) + + .dataa(\vga_pic_inst|pix_data[4]~5_combout ), + .datab(\vga_pic_inst|LessThan17~0_combout ), + .datac(\vga_pic_inst|pix_data[4]~10_combout ), + .datad(\vga_pic_inst|pix_data~11_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~12_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~12 .lut_mask = 16'hE4EE; +defparam \vga_pic_inst|pix_data~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N16 +cycloneive_lcell_comb \vga_pic_inst|pix_data~13 ( +// Equation(s): +// \vga_pic_inst|pix_data~13_combout = ((\vga_pic_inst|pix_data[4]~7_combout & (\vga_pic_inst|pix_data~9_combout & \vga_pic_inst|pix_data~6_combout ))) # (!\vga_pic_inst|pix_data~12_combout ) + + .dataa(\vga_pic_inst|pix_data[4]~7_combout ), + .datab(\vga_pic_inst|pix_data~9_combout ), + .datac(\vga_pic_inst|pix_data~6_combout ), + .datad(\vga_pic_inst|pix_data~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~13_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~13 .lut_mask = 16'h80FF; +defparam \vga_pic_inst|pix_data~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N17 +dffeas \vga_pic_inst|pix_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[0] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N0 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[0]~0 ( +// Equation(s): +// \vga_ctrl_inst|rgb[0]~0_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (\vga_ctrl_inst|rgb_valid~0_combout & (\vga_pic_inst|pix_data [0] & !\vga_ctrl_inst|pix_data_req~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|rgb_valid~0_combout ), + .datac(\vga_pic_inst|pix_data [0]), + .datad(\vga_ctrl_inst|pix_data_req~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[0]~0 .lut_mask = 16'h0040; +defparam \vga_ctrl_inst|rgb[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data[4]~7 ( +// Equation(s): +// \vga_pic_inst|pix_data[4]~7_combout = (!\vga_ctrl_inst|Add2~16_combout & (\vga_ctrl_inst|pix_data_req~4_combout & ((!\vga_ctrl_inst|Add2~14_combout ) # (!\vga_ctrl_inst|Add2~12_combout )))) + + .dataa(\vga_ctrl_inst|Add2~12_combout ), + .datab(\vga_ctrl_inst|Add2~14_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[4]~7_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4]~7 .lut_mask = 16'h0700; +defparam \vga_pic_inst|pix_data[4]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N18 +cycloneive_lcell_comb \vga_pic_inst|pix_data~16 ( +// Equation(s): +// \vga_pic_inst|pix_data~16_combout = (\vga_pic_inst|pix_data~15_combout ) # ((\vga_pic_inst|pix_data[4]~7_combout & (\vga_pic_inst|pix_data~9_combout & \vga_pic_inst|pix_data~6_combout ))) + + .dataa(\vga_pic_inst|pix_data~15_combout ), + .datab(\vga_pic_inst|pix_data[4]~7_combout ), + .datac(\vga_pic_inst|pix_data~9_combout ), + .datad(\vga_pic_inst|pix_data~6_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~16_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~16 .lut_mask = 16'hEAAA; +defparam \vga_pic_inst|pix_data~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N19 +dffeas \vga_pic_inst|pix_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N26 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[1]~1 ( +// Equation(s): +// \vga_ctrl_inst|rgb[1]~1_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [4]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[1]~1 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data~25 ( +// Equation(s): +// \vga_pic_inst|pix_data~25_combout = (\vga_ctrl_inst|Add2~16_combout & (((!\vga_pic_inst|LessThan17~0_combout )))) # (!\vga_ctrl_inst|Add2~16_combout & ((\vga_ctrl_inst|pix_data_req~4_combout & (\vga_pic_inst|pix_data~17_combout )) # +// (!\vga_ctrl_inst|pix_data_req~4_combout & ((!\vga_pic_inst|LessThan17~0_combout ))))) + + .dataa(\vga_pic_inst|pix_data~17_combout ), + .datab(\vga_ctrl_inst|Add2~16_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_pic_inst|LessThan17~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~25_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~25 .lut_mask = 16'h20EF; +defparam \vga_pic_inst|pix_data~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y23_N13 +dffeas \vga_pic_inst|pix_data[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[8] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N30 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[5]~2 ( +// Equation(s): +// \vga_ctrl_inst|rgb[5]~2_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [8]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [8]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[5]~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[5]~2 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[5]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N28 +cycloneive_lcell_comb \vga_pic_inst|pix_data~18 ( +// Equation(s): +// \vga_pic_inst|pix_data~18_combout = (\vga_ctrl_inst|pix_data_req~4_combout & ((\vga_ctrl_inst|Add2~14_combout & (!\vga_ctrl_inst|Add2~12_combout & !\vga_ctrl_inst|Add2~10_combout )) # (!\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|Add2~12_combout +// )))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~18 .lut_mask = 16'h4060; +defparam \vga_pic_inst|pix_data~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data~14 ( +// Equation(s): +// \vga_pic_inst|pix_data~14_combout = (!\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~12_combout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add2~14_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~14_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~14 .lut_mask = 16'h0030; +defparam \vga_pic_inst|pix_data~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N30 +cycloneive_lcell_comb \vga_pic_inst|pix_data~26 ( +// Equation(s): +// \vga_pic_inst|pix_data~26_combout = (\vga_ctrl_inst|pix_data_req~4_combout & ((\vga_ctrl_inst|Add2~16_combout & ((\vga_pic_inst|pix_data~14_combout ))) # (!\vga_ctrl_inst|Add2~16_combout & (\vga_pic_inst|pix_data~18_combout )))) # +// (!\vga_ctrl_inst|pix_data_req~4_combout & (((\vga_pic_inst|pix_data~14_combout )))) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_pic_inst|pix_data~18_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_pic_inst|pix_data~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~26_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~26 .lut_mask = 16'hFD08; +defparam \vga_pic_inst|pix_data~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data~19 ( +// Equation(s): +// \vga_pic_inst|pix_data~19_combout = (\vga_pic_inst|pix_data~26_combout & \vga_pic_inst|pix_data~6_combout ) + + .dataa(gnd), + .datab(\vga_pic_inst|pix_data~26_combout ), + .datac(gnd), + .datad(\vga_pic_inst|pix_data~6_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~19_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~19 .lut_mask = 16'hCC00; +defparam \vga_pic_inst|pix_data~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y24_N1 +dffeas \vga_pic_inst|pix_data[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[9] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[7]~3 ( +// Equation(s): +// \vga_ctrl_inst|rgb[7]~3_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [9]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[7]~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[7]~3 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[7]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N6 +cycloneive_lcell_comb \vga_pic_inst|LessThan2~2 ( +// Equation(s): +// \vga_pic_inst|LessThan2~2_combout = (\vga_pic_inst|LessThan17~0_combout ) # ((\vga_ctrl_inst|Add2~16_combout ) # (!\vga_ctrl_inst|pix_data_req~4_combout )) + + .dataa(\vga_pic_inst|LessThan17~0_combout ), + .datab(\vga_ctrl_inst|Add2~16_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan2~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan2~2 .lut_mask = 16'hEEFF; +defparam \vga_pic_inst|LessThan2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data~20 ( +// Equation(s): +// \vga_pic_inst|pix_data~20_combout = (!\vga_ctrl_inst|Add2~16_combout & (!\vga_ctrl_inst|Add2~14_combout & \vga_ctrl_inst|pix_data_req~4_combout )) + + .dataa(\vga_ctrl_inst|Add2~16_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~20_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~20 .lut_mask = 16'h0500; +defparam \vga_pic_inst|pix_data~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~21 ( +// Equation(s): +// \vga_pic_inst|pix_data~21_combout = (\vga_pic_inst|LessThan2~2_combout & ((\vga_pic_inst|pix_data~26_combout ) # ((\vga_pic_inst|pix_data~4_combout & \vga_pic_inst|pix_data~20_combout )))) + + .dataa(\vga_pic_inst|pix_data~4_combout ), + .datab(\vga_pic_inst|pix_data~26_combout ), + .datac(\vga_pic_inst|LessThan2~2_combout ), + .datad(\vga_pic_inst|pix_data~20_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~21_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~21 .lut_mask = 16'hE0C0; +defparam \vga_pic_inst|pix_data~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y24_N27 +dffeas \vga_pic_inst|pix_data[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [10]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[10] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N2 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[10]~4 ( +// Equation(s): +// \vga_ctrl_inst|rgb[10]~4_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [10]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [10]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[10]~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[10]~4 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[10]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N20 +cycloneive_lcell_comb \vga_pic_inst|pix_data~22 ( +// Equation(s): +// \vga_pic_inst|pix_data~22_combout = ((\vga_pic_inst|pix_data[4]~5_combout & (!\vga_ctrl_inst|Add2~14_combout & \vga_pic_inst|pix_data~4_combout ))) # (!\vga_pic_inst|LessThan6~0_combout ) + + .dataa(\vga_pic_inst|pix_data[4]~5_combout ), + .datab(\vga_pic_inst|LessThan6~0_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_pic_inst|pix_data~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~22_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~22 .lut_mask = 16'h3B33; +defparam \vga_pic_inst|pix_data~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N28 +cycloneive_lcell_comb \vga_pic_inst|pix_data~23 ( +// Equation(s): +// \vga_pic_inst|pix_data~23_combout = ((\vga_pic_inst|pix_data[4]~7_combout & ((\vga_pic_inst|pix_data~22_combout ) # (!\vga_pic_inst|LessThan2~2_combout )))) # (!\vga_pic_inst|pix_data~12_combout ) + + .dataa(\vga_pic_inst|LessThan2~2_combout ), + .datab(\vga_pic_inst|pix_data~12_combout ), + .datac(\vga_pic_inst|pix_data~22_combout ), + .datad(\vga_pic_inst|pix_data[4]~7_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~23_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~23 .lut_mask = 16'hF733; +defparam \vga_pic_inst|pix_data~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N29 +dffeas \vga_pic_inst|pix_data[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [13]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[11]~5 ( +// Equation(s): +// \vga_ctrl_inst|rgb[11]~5_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (\vga_pic_inst|pix_data [13] & (\vga_ctrl_inst|rgb_valid~0_combout & !\vga_ctrl_inst|pix_data_req~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_pic_inst|pix_data [13]), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[11]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[11]~5 .lut_mask = 16'h0040; +defparam \vga_ctrl_inst|rgb[11]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N30 +cycloneive_lcell_comb \vga_pic_inst|pix_data~24 ( +// Equation(s): +// \vga_pic_inst|pix_data~24_combout = (\vga_pic_inst|pix_data~15_combout ) # ((\vga_pic_inst|pix_data[4]~7_combout & ((\vga_pic_inst|pix_data~22_combout ) # (!\vga_pic_inst|LessThan2~2_combout )))) + + .dataa(\vga_pic_inst|pix_data~15_combout ), + .datab(\vga_pic_inst|pix_data[4]~7_combout ), + .datac(\vga_pic_inst|pix_data~22_combout ), + .datad(\vga_pic_inst|LessThan2~2_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~24_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~24 .lut_mask = 16'hEAEE; +defparam \vga_pic_inst|pix_data~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N31 +dffeas \vga_pic_inst|pix_data[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [15]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[15] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[12]~6 ( +// Equation(s): +// \vga_ctrl_inst|rgb[12]~6_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (\vga_pic_inst|pix_data [15] & (\vga_ctrl_inst|rgb_valid~0_combout & !\vga_ctrl_inst|pix_data_req~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_pic_inst|pix_data [15]), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[12]~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[12]~6 .lut_mask = 16'h0040; +defparam \vga_ctrl_inst|rgb[12]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +endmodule diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_85c_v_slow.sdo b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_85c_v_slow.sdo new file mode 100644 index 0000000..3c460d1 --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_85c_v_slow.sdo @@ -0,0 +1,2108 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE15F23C8, +// with speed grade 8, core voltage 1.2V, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "vga_colorbar") + (DATE "06/02/2023 04:42:20") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (460:460:460)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (4503:4503:4503) (4503:4503:4503)) + (PORT inclk[0] (2340:2340:2340) (2340:2340:2340)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (960:960:960) (961:961:961)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (971:971:971) (950:950:950)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (973:973:973) (953:953:953)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT datab (1006:1006:1006) (978:978:978)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~8) + (DELAY + (ABSOLUTE + (PORT datab (569:569:569) (599:599:599)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~10) + (DELAY + (ABSOLUTE + (PORT datab (960:960:960) (939:939:939)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (603:603:603)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (962:962:962)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT datab (397:397:397) (486:486:486)) + (PORT datad (343:343:343) (426:426:426)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[8\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (788:788:788)) + (PORT datab (858:858:858) (836:836:836)) + (PORT datad (316:316:316) (356:356:356)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[4\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (1230:1230:1230) (1146:1146:1146)) + (PORT datad (924:924:924) (874:874:874)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1160:1160:1160) (1082:1082:1082)) + (PORT datab (967:967:967) (899:899:899)) + (PORT datac (937:937:937) (910:910:910)) + (PORT datad (1184:1184:1184) (1098:1098:1098)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~15) + (DELAY + (ABSOLUTE + (PORT dataa (841:841:841) (803:803:803)) + (PORT datab (509:509:509) (494:494:494)) + (PORT datac (245:245:245) (275:275:275)) + (PORT datad (262:262:262) (300:300:300)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~17) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (383:383:383)) + (PORT datac (842:842:842) (776:776:776)) + (PORT datad (291:291:291) (318:318:318)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (806:806:806) (852:852:852)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2339:2339:2339) (2308:2308:2308)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE hsync\~output) + (DELAY + (ABSOLUTE + (PORT i (2108:2108:2108) (2266:2266:2266)) + (IOPATH i o (3174:3174:3174) (3271:3271:3271)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE vsync\~output) + (DELAY + (ABSOLUTE + (PORT i (1864:1864:1864) (2034:2034:2034)) + (IOPATH i o (3184:3184:3184) (3281:3281:3281)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2928:2928:2928) (2696:2696:2696)) + (IOPATH i o (3271:3271:3271) (3174:3174:3174)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2872:2872:2872) (2631:2631:2631)) + (IOPATH i o (3281:3281:3281) (3184:3184:3184)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3183:3183:3183) (2900:2900:2900)) + (IOPATH i o (3281:3281:3281) (3184:3184:3184)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3530:3530:3530) (3206:3206:3206)) + (IOPATH i o (3429:3429:3429) (3366:3366:3366)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3524:3524:3524) (3201:3201:3201)) + (IOPATH i o (3409:3409:3409) (3346:3346:3346)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1540:1540:1540) (1460:1460:1460)) + (IOPATH i o (3409:3409:3409) (3346:3346:3346)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1581:1581:1581) (1475:1475:1475)) + (IOPATH i o (3409:3409:3409) (3346:3346:3346)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2139:2139:2139) (1969:1969:1969)) + (IOPATH i o (3419:3419:3419) (3356:3356:3356)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1953:1953:1953) (1815:1815:1815)) + (IOPATH i o (3379:3379:3379) (3316:3316:3316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1947:1947:1947) (1781:1781:1781)) + (IOPATH i o (3399:3399:3399) (3336:3336:3336)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1885:1885:1885) (1698:1698:1698)) + (IOPATH i o (3389:3389:3389) (3326:3326:3326)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1851:1851:1851) (1680:1680:1680)) + (IOPATH i o (3389:3389:3389) (3326:3326:3326)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1486:1486:1486) (1329:1329:1329)) + (IOPATH i o (3399:3399:3399) (3336:3336:3336)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[13\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1506:1506:1506) (1334:1334:1334)) + (IOPATH i o (3389:3389:3389) (3326:3326:3326)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[14\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1091:1091:1091) (970:970:970)) + (IOPATH i o (3399:3399:3399) (3336:3336:3336)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[15\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1123:1123:1123) (999:999:999)) + (IOPATH i o (3389:3389:3389) (3326:3326:3326)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT datab (366:366:366) (447:447:447)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (2921:2921:2921) (2960:2960:2960)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (4667:4667:4667) (4459:4459:4459)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rst_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2254:2254:2254) (2277:2277:2277)) + (PORT datab (332:332:332) (408:408:408)) + (PORT datac (3743:3743:3743) (3918:3918:3918)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~0clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2220:2220:2220) (2115:2115:2115)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (456:456:456)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (450:450:450)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (917:917:917) (889:889:889)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datab (369:369:369) (448:448:448)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (402:402:402) (492:492:492)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datad (350:350:350) (435:435:435)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~1) + (DELAY + (ABSOLUTE + (PORT datab (848:848:848) (777:777:777)) + (PORT datac (240:240:240) (266:266:266)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~0) + (DELAY + (ABSOLUTE + (PORT datab (789:789:789) (706:706:706)) + (PORT datac (265:265:265) (291:291:291)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1878:1878:1878) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (668:668:668)) + (PORT datab (390:390:390) (477:477:477)) + (PORT datac (853:853:853) (839:839:839)) + (PORT datad (328:328:328) (405:405:405)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (461:461:461)) + (PORT datab (368:368:368) (451:451:451)) + (PORT datac (327:327:327) (412:412:412)) + (PORT datad (329:329:329) (405:405:405)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (876:876:876)) + (PORT datab (741:741:741) (680:680:680)) + (PORT datac (724:724:724) (663:663:663)) + (PORT datad (917:917:917) (899:899:899)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~2) + (DELAY + (ABSOLUTE + (PORT datab (279:279:279) (305:305:305)) + (PORT datac (806:806:806) (740:740:740)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan2\~0) + (DELAY + (ABSOLUTE + (PORT datab (396:396:396) (485:485:485)) + (PORT datad (342:342:342) (425:425:425)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (841:841:841)) + (PORT datab (933:933:933) (885:885:885)) + (PORT datac (767:767:767) (704:704:704)) + (PORT datad (328:328:328) (401:401:401)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (802:802:802)) + (PORT datab (862:862:862) (841:841:841)) + (PORT datad (313:313:313) (352:352:352)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (832:832:832)) + (PORT datab (857:857:857) (834:834:834)) + (PORT datad (317:317:317) (358:358:358)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[4\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1110:1110:1110) (1019:1019:1019)) + (PORT datab (856:856:856) (834:834:834)) + (PORT datad (318:318:318) (359:359:359)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1021:1021:1021) (997:997:997)) + (PORT datab (366:366:366) (449:449:449)) + (PORT datac (326:326:326) (408:408:408)) + (PORT datad (327:327:327) (401:401:401)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1194:1194:1194) (1079:1079:1079)) + (PORT datab (860:860:860) (838:838:838)) + (PORT datad (315:315:315) (355:355:355)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (307:307:307) (351:351:351)) + (PORT datab (367:367:367) (450:450:450)) + (PORT datac (450:450:450) (427:427:427)) + (PORT datad (337:337:337) (417:417:417)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (877:877:877)) + (PORT datab (856:856:856) (834:834:834)) + (PORT datad (318:318:318) (358:358:358)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (450:450:450)) + (PORT datac (327:327:327) (409:409:409)) + (PORT datad (329:329:329) (402:402:402)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[5\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (829:829:829)) + (PORT datab (860:860:860) (839:839:839)) + (PORT datad (315:315:315) (354:354:354)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~14) + (DELAY + (ABSOLUTE + (PORT datab (569:569:569) (597:597:597)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[7\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (846:846:846)) + (PORT datab (279:279:279) (305:305:305)) + (PORT datad (1206:1206:1206) (1115:1115:1115)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1878:1878:1878) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~18) + (DELAY + (ABSOLUTE + (PORT datad (333:333:333) (411:411:411)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[9\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (846:846:846)) + (PORT datab (280:280:280) (306:306:306)) + (PORT datad (1207:1207:1207) (1116:1116:1116)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1878:1878:1878) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[6\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (314:314:314)) + (PORT datab (1265:1265:1265) (1163:1163:1163)) + (PORT datad (838:838:838) (794:794:794)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1878:1878:1878) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (443:443:443)) + (PORT datab (359:359:359) (435:435:435)) + (PORT datac (872:872:872) (866:866:866)) + (PORT datad (893:893:893) (890:890:890)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (326:326:326)) + (PORT datab (377:377:377) (459:459:459)) + (PORT datac (959:959:959) (948:948:948)) + (PORT datad (261:261:261) (296:296:296)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan6\~1) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (449:449:449)) + (PORT datad (336:336:336) (416:416:416)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~1) + (DELAY + (ABSOLUTE + (PORT dataa (957:957:957) (961:961:961)) + (PORT datab (371:371:371) (451:451:451)) + (PORT datac (528:528:528) (560:560:560)) + (PORT datad (517:517:517) (552:552:552)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~2) + (DELAY + (ABSOLUTE + (PORT dataa (285:285:285) (323:323:323)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (698:698:698) (629:629:629)) + (PORT datad (265:265:265) (300:300:300)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan2\~1) + (DELAY + (ABSOLUTE + (PORT datab (930:930:930) (883:883:883)) + (PORT datac (848:848:848) (826:826:826)) + (PORT datad (326:326:326) (400:400:400)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb_valid\~0) + (DELAY + (ABSOLUTE + (PORT dataa (735:735:735) (684:684:684)) + (PORT datab (974:974:974) (944:944:944)) + (PORT datac (765:765:765) (703:703:703)) + (PORT datad (254:254:254) (280:280:280)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (455:455:455) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (628:628:628)) + (PORT datab (837:837:837) (806:806:806)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (628:628:628)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~5) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (597:597:597)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~7) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (607:607:607)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~9) + (DELAY + (ABSOLUTE + (PORT dataa (853:853:853) (839:839:839)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~10) + (DELAY + (ABSOLUTE + (PORT datab (620:620:620) (627:627:627)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (855:855:855) (837:837:837)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan14\~0) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (383:383:383)) + (PORT datad (291:291:291) (318:318:318)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~14) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (650:650:650)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~16) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (628:628:628)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (801:801:801)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (273:273:273) (303:303:303)) + (PORT datad (274:274:274) (299:299:299)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~0) + (DELAY + (ABSOLUTE + (PORT dataa (306:306:306) (351:351:351)) + (PORT datac (955:955:955) (943:943:943)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (767:767:767) (710:710:710)) + (PORT datab (976:976:976) (946:946:946)) + (PORT datac (764:764:764) (701:701:701)) + (PORT datad (257:257:257) (283:283:283)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~3) + (DELAY + (ABSOLUTE + (PORT dataa (736:736:736) (684:684:684)) + (PORT datab (976:976:976) (946:946:946)) + (PORT datac (723:723:723) (662:662:662)) + (PORT datad (256:256:256) (281:281:281)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~4) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (812:812:812)) + (PORT datab (918:918:918) (854:854:854)) + (PORT datac (237:237:237) (264:264:264)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~4) + (DELAY + (ABSOLUTE + (PORT datab (1232:1232:1232) (1148:1148:1148)) + (PORT datad (847:847:847) (804:804:804)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~9) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (313:313:313)) + (PORT datab (888:888:888) (823:823:823)) + (PORT datac (934:934:934) (907:907:907)) + (PORT datad (279:279:279) (305:305:305)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (855:855:855)) + (PORT datab (966:966:966) (898:898:898)) + (PORT datac (934:934:934) (907:907:907)) + (PORT datad (1188:1188:1188) (1104:1104:1104)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~6) + (DELAY + (ABSOLUTE + (PORT dataa (304:304:304) (351:351:351)) + (PORT datab (320:320:320) (350:350:350)) + (PORT datac (935:935:935) (908:908:908)) + (PORT datad (487:487:487) (468:468:468)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[4\]\~10) + (DELAY + (ABSOLUTE + (PORT datac (936:936:936) (910:910:910)) + (PORT datad (846:846:846) (803:803:803)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~11) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (824:824:824)) + (PORT datab (338:338:338) (384:384:384)) + (PORT datac (795:795:795) (753:753:753)) + (PORT datad (291:291:291) (318:318:318)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~12) + (DELAY + (ABSOLUTE + (PORT dataa (305:305:305) (353:353:353)) + (PORT datab (304:304:304) (329:329:329)) + (PORT datac (243:243:243) (274:274:274)) + (PORT datad (802:802:802) (754:754:754)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~13) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (537:537:537)) + (PORT datab (285:285:285) (315:315:315)) + (PORT datac (288:288:288) (315:315:315)) + (PORT datad (245:245:245) (270:270:270)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (815:815:815)) + (PORT datab (327:327:327) (381:381:381)) + (PORT datac (852:852:852) (839:839:839)) + (PORT datad (863:863:863) (814:814:814)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[4\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (856:856:856)) + (PORT datab (988:988:988) (944:944:944)) + (PORT datac (1120:1120:1120) (1040:1040:1040)) + (PORT datad (1190:1190:1190) (1106:1106:1106)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~16) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (326:326:326)) + (PORT datab (322:322:322) (356:356:356)) + (PORT datac (245:245:245) (278:278:278)) + (PORT datad (501:501:501) (465:465:465)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (810:810:810)) + (PORT datab (917:917:917) (852:852:852)) + (PORT datac (284:284:284) (343:343:343)) + (PORT datad (912:912:912) (892:892:892)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~25) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (510:510:510)) + (PORT datab (511:511:511) (499:499:499)) + (PORT datac (263:263:263) (289:289:289)) + (PORT datad (817:817:817) (766:766:766)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (455:455:455) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1878:1878:1878) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[5\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (810:810:810)) + (PORT datab (916:916:916) (852:852:852)) + (PORT datac (284:284:284) (343:343:343)) + (PORT datad (295:295:295) (365:365:365)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~18) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (824:824:824)) + (PORT datab (336:336:336) (382:382:382)) + (PORT datac (790:790:790) (746:746:746)) + (PORT datad (291:291:291) (318:318:318)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~14) + (DELAY + (ABSOLUTE + (PORT datab (314:314:314) (342:342:342)) + (PORT datac (796:796:796) (754:754:754)) + (PORT datad (299:299:299) (343:343:343)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~26) + (DELAY + (ABSOLUTE + (PORT dataa (833:833:833) (794:794:794)) + (PORT datab (275:275:275) (299:299:299)) + (PORT datac (270:270:270) (300:300:300)) + (PORT datad (267:267:267) (285:285:285)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~19) + (DELAY + (ABSOLUTE + (PORT datab (930:930:930) (864:864:864)) + (PORT datad (500:500:500) (460:460:460)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[7\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (836:836:836) (812:812:812)) + (PORT datab (919:919:919) (856:856:856)) + (PORT datac (284:284:284) (343:343:343)) + (PORT datad (829:829:829) (827:827:827)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (527:527:527) (519:519:519)) + (PORT datab (984:984:984) (924:924:924)) + (PORT datad (1189:1189:1189) (1104:1104:1104)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~20) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (843:843:843)) + (PORT datac (849:849:849) (795:795:795)) + (PORT datad (908:908:908) (849:849:849)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~21) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (524:524:524)) + (PORT datab (928:928:928) (861:861:861)) + (PORT datac (475:475:475) (447:447:447)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[10\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (815:815:815)) + (PORT datab (924:924:924) (861:861:861)) + (PORT datac (283:283:283) (342:342:342)) + (PORT datad (931:931:931) (915:915:915)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~22) + (DELAY + (ABSOLUTE + (PORT dataa (305:305:305) (353:353:353)) + (PORT datab (886:886:886) (822:822:822)) + (PORT datac (936:936:936) (910:910:910)) + (PORT datad (282:282:282) (309:309:309)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~23) + (DELAY + (ABSOLUTE + (PORT dataa (317:317:317) (352:352:352)) + (PORT datab (283:283:283) (311:311:311)) + (PORT datac (455:455:455) (430:430:430)) + (PORT datad (285:285:285) (317:317:317)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[11\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (811:811:811)) + (PORT datab (918:918:918) (911:911:911)) + (PORT datac (284:284:284) (343:343:343)) + (PORT datad (857:857:857) (807:807:807)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~24) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (328:328:328)) + (PORT datab (325:325:325) (360:360:360)) + (PORT datac (455:455:455) (430:430:430)) + (PORT datad (276:276:276) (301:301:301)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[12\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (814:814:814)) + (PORT datab (844:844:844) (810:810:810)) + (PORT datac (283:283:283) (342:342:342)) + (PORT datad (862:862:862) (812:812:812)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) +) diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_min_1200mv_0c_fast.vo b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_min_1200mv_0c_fast.vo new file mode 100644 index 0000000..3bcdef2 --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_min_1200mv_0c_fast.vo @@ -0,0 +1,2833 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 04:42:20" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module vga_colorbar ( + sys_clk, + sys_rst_n, + hsync, + vsync, + rgb); +input sys_clk; +input sys_rst_n; +output hsync; +output vsync; +output [15:0] rgb; + +// Design Ports Information +// hsync => Location: PIN_AA18, I/O Standard: 2.5 V, Current Strength: Default +// vsync => Location: PIN_AB17, I/O Standard: 2.5 V, Current Strength: Default +// rgb[0] => Location: PIN_AB18, I/O Standard: 2.5 V, Current Strength: Default +// rgb[1] => Location: PIN_AA19, I/O Standard: 2.5 V, Current Strength: Default +// rgb[2] => Location: PIN_AB19, I/O Standard: 2.5 V, Current Strength: Default +// rgb[3] => Location: PIN_Y21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[4] => Location: PIN_W19, I/O Standard: 2.5 V, Current Strength: Default +// rgb[5] => Location: PIN_W20, I/O Standard: 2.5 V, Current Strength: Default +// rgb[6] => Location: PIN_U21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[7] => Location: PIN_U22, I/O Standard: 2.5 V, Current Strength: Default +// rgb[8] => Location: PIN_N20, I/O Standard: 2.5 V, Current Strength: Default +// rgb[9] => Location: PIN_N21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[10] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[11] => Location: PIN_M22, I/O Standard: 2.5 V, Current Strength: Default +// rgb[12] => Location: PIN_L21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[13] => Location: PIN_L22, I/O Standard: 2.5 V, Current Strength: Default +// rgb[14] => Location: PIN_K21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[15] => Location: PIN_J21, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("vga_colorbar_min_1200mv_0c_v_fast.sdo"); +// synopsys translate_on + +wire \vga_ctrl_inst|Add0~4_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ; +wire \vga_ctrl_inst|Add1~0_combout ; +wire \vga_ctrl_inst|Add1~2_combout ; +wire \vga_ctrl_inst|Add1~4_combout ; +wire \vga_ctrl_inst|Add1~6_combout ; +wire \vga_ctrl_inst|Add1~8_combout ; +wire \vga_ctrl_inst|Add1~10_combout ; +wire \vga_ctrl_inst|Add1~12_combout ; +wire \vga_ctrl_inst|Add1~16_combout ; +wire \vga_ctrl_inst|Equal0~0_combout ; +wire \vga_ctrl_inst|cnt_v[8]~3_combout ; +wire \vga_pic_inst|pix_data[4]~5_combout ; +wire \vga_pic_inst|pix_data~8_combout ; +wire \vga_pic_inst|pix_data~15_combout ; +wire \vga_pic_inst|pix_data~17_combout ; +wire \sys_clk~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \vga_ctrl_inst|Add0~0_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \sys_rst_n~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ; +wire \rst_n~0_combout ; +wire \rst_n~0clkctrl_outclk ; +wire \vga_ctrl_inst|Add0~1 ; +wire \vga_ctrl_inst|Add0~3 ; +wire \vga_ctrl_inst|Add0~5 ; +wire \vga_ctrl_inst|Add0~6_combout ; +wire \vga_ctrl_inst|Add0~7 ; +wire \vga_ctrl_inst|Add0~8_combout ; +wire \vga_ctrl_inst|Add0~9 ; +wire \vga_ctrl_inst|Add0~11 ; +wire \vga_ctrl_inst|Add0~12_combout ; +wire \vga_ctrl_inst|Add0~13 ; +wire \vga_ctrl_inst|Add0~14_combout ; +wire \vga_ctrl_inst|Add0~15 ; +wire \vga_ctrl_inst|Add0~16_combout ; +wire \vga_ctrl_inst|Add0~17 ; +wire \vga_ctrl_inst|Add0~18_combout ; +wire \vga_ctrl_inst|cnt_h~1_combout ; +wire \vga_ctrl_inst|Add0~10_combout ; +wire \vga_ctrl_inst|cnt_h~0_combout ; +wire \vga_ctrl_inst|Equal0~2_combout ; +wire \vga_ctrl_inst|Add0~2_combout ; +wire \vga_ctrl_inst|Equal0~1_combout ; +wire \vga_ctrl_inst|Equal0~3_combout ; +wire \vga_ctrl_inst|cnt_h~2_combout ; +wire \vga_ctrl_inst|LessThan2~0_combout ; +wire \vga_ctrl_inst|LessThan0~0_combout ; +wire \vga_ctrl_inst|cnt_v[0]~9_combout ; +wire \vga_ctrl_inst|cnt_v[2]~8_combout ; +wire \vga_ctrl_inst|cnt_v[4]~6_combout ; +wire \vga_ctrl_inst|always1~1_combout ; +wire \vga_ctrl_inst|cnt_v[1]~0_combout ; +wire \vga_ctrl_inst|always1~2_combout ; +wire \vga_ctrl_inst|cnt_v[3]~7_combout ; +wire \vga_ctrl_inst|LessThan6~0_combout ; +wire \vga_ctrl_inst|cnt_v[5]~2_combout ; +wire \vga_ctrl_inst|Add1~1 ; +wire \vga_ctrl_inst|Add1~3 ; +wire \vga_ctrl_inst|Add1~5 ; +wire \vga_ctrl_inst|Add1~7 ; +wire \vga_ctrl_inst|Add1~9 ; +wire \vga_ctrl_inst|Add1~11 ; +wire \vga_ctrl_inst|Add1~13 ; +wire \vga_ctrl_inst|Add1~14_combout ; +wire \vga_ctrl_inst|cnt_v[7]~4_combout ; +wire \vga_ctrl_inst|Add1~15 ; +wire \vga_ctrl_inst|Add1~17 ; +wire \vga_ctrl_inst|Add1~18_combout ; +wire \vga_ctrl_inst|cnt_v[9]~1_combout ; +wire \vga_ctrl_inst|cnt_v[6]~5_combout ; +wire \vga_ctrl_inst|always1~0_combout ; +wire \vga_ctrl_inst|LessThan1~0_combout ; +wire \vga_ctrl_inst|LessThan6~1_combout ; +wire \vga_ctrl_inst|pix_data_req~1_combout ; +wire \vga_ctrl_inst|pix_data_req~2_combout ; +wire \vga_ctrl_inst|LessThan2~1_combout ; +wire \vga_ctrl_inst|rgb_valid~0_combout ; +wire \vga_ctrl_inst|Add2~1_cout ; +wire \vga_ctrl_inst|Add2~3_cout ; +wire \vga_ctrl_inst|Add2~5_cout ; +wire \vga_ctrl_inst|Add2~7_cout ; +wire \vga_ctrl_inst|Add2~9_cout ; +wire \vga_ctrl_inst|Add2~11 ; +wire \vga_ctrl_inst|Add2~12_combout ; +wire \vga_ctrl_inst|Add2~10_combout ; +wire \vga_pic_inst|LessThan14~0_combout ; +wire \vga_ctrl_inst|Add2~13 ; +wire \vga_ctrl_inst|Add2~15 ; +wire \vga_ctrl_inst|Add2~16_combout ; +wire \vga_ctrl_inst|Add2~14_combout ; +wire \vga_pic_inst|LessThan6~0_combout ; +wire \vga_ctrl_inst|pix_data_req~0_combout ; +wire \vga_ctrl_inst|LessThan4~0_combout ; +wire \vga_ctrl_inst|pix_data_req~3_combout ; +wire \vga_ctrl_inst|pix_data_req~4_combout ; +wire \vga_pic_inst|pix_data~4_combout ; +wire \vga_pic_inst|pix_data~9_combout ; +wire \vga_pic_inst|LessThan17~0_combout ; +wire \vga_pic_inst|pix_data~6_combout ; +wire \vga_pic_inst|pix_data[4]~10_combout ; +wire \vga_pic_inst|pix_data~11_combout ; +wire \vga_pic_inst|pix_data~12_combout ; +wire \vga_pic_inst|pix_data~13_combout ; +wire \vga_ctrl_inst|rgb[0]~0_combout ; +wire \vga_pic_inst|pix_data[4]~7_combout ; +wire \vga_pic_inst|pix_data~16_combout ; +wire \vga_ctrl_inst|rgb[1]~1_combout ; +wire \vga_pic_inst|pix_data~25_combout ; +wire \vga_ctrl_inst|rgb[5]~2_combout ; +wire \vga_pic_inst|pix_data~18_combout ; +wire \vga_pic_inst|pix_data~14_combout ; +wire \vga_pic_inst|pix_data~26_combout ; +wire \vga_pic_inst|pix_data~19_combout ; +wire \vga_ctrl_inst|rgb[7]~3_combout ; +wire \vga_pic_inst|LessThan2~2_combout ; +wire \vga_pic_inst|pix_data~20_combout ; +wire \vga_pic_inst|pix_data~21_combout ; +wire \vga_ctrl_inst|rgb[10]~4_combout ; +wire \vga_pic_inst|pix_data~22_combout ; +wire \vga_pic_inst|pix_data~23_combout ; +wire \vga_ctrl_inst|rgb[11]~5_combout ; +wire \vga_pic_inst|pix_data~24_combout ; +wire \vga_ctrl_inst|rgb[12]~6_combout ; +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk ; +wire [9:0] \vga_ctrl_inst|cnt_v ; +wire [9:0] \vga_ctrl_inst|cnt_h ; +wire [15:0] \vga_pic_inst|pix_data ; + +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ; + +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [3] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [4] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [4]; + +// Location: LCCOMB_X35_Y23_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~4 ( +// Equation(s): +// \vga_ctrl_inst|Add0~4_combout = (\vga_ctrl_inst|cnt_h [2] & (\vga_ctrl_inst|Add0~3 $ (GND))) # (!\vga_ctrl_inst|cnt_h [2] & (!\vga_ctrl_inst|Add0~3 & VCC)) +// \vga_ctrl_inst|Add0~5 = CARRY((\vga_ctrl_inst|cnt_h [2] & !\vga_ctrl_inst|Add0~3 )) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~3 ), + .combout(\vga_ctrl_inst|Add0~4_combout ), + .cout(\vga_ctrl_inst|Add0~5 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~4 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: PLL_2 +cycloneive_pll \clk_gen_inst|altpll_component|auto_generated|pll1 ( + .areset(!\sys_rst_n~input_o ), + .pfdena(vcc), + .fbin(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\sys_clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_high = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_low = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_divide_by = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_multiply_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .n = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pll_compensation_delay = 3334; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~0 ( +// Equation(s): +// \vga_ctrl_inst|Add1~0_combout = \vga_ctrl_inst|cnt_v [0] $ (VCC) +// \vga_ctrl_inst|Add1~1 = CARRY(\vga_ctrl_inst|cnt_v [0]) + + .dataa(\vga_ctrl_inst|cnt_v [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\vga_ctrl_inst|Add1~0_combout ), + .cout(\vga_ctrl_inst|Add1~1 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~0 .lut_mask = 16'h55AA; +defparam \vga_ctrl_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~2 ( +// Equation(s): +// \vga_ctrl_inst|Add1~2_combout = (\vga_ctrl_inst|cnt_v [1] & (!\vga_ctrl_inst|Add1~1 )) # (!\vga_ctrl_inst|cnt_v [1] & ((\vga_ctrl_inst|Add1~1 ) # (GND))) +// \vga_ctrl_inst|Add1~3 = CARRY((!\vga_ctrl_inst|Add1~1 ) # (!\vga_ctrl_inst|cnt_v [1])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [1]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~1 ), + .combout(\vga_ctrl_inst|Add1~2_combout ), + .cout(\vga_ctrl_inst|Add1~3 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~2 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~4 ( +// Equation(s): +// \vga_ctrl_inst|Add1~4_combout = (\vga_ctrl_inst|cnt_v [2] & (\vga_ctrl_inst|Add1~3 $ (GND))) # (!\vga_ctrl_inst|cnt_v [2] & (!\vga_ctrl_inst|Add1~3 & VCC)) +// \vga_ctrl_inst|Add1~5 = CARRY((\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|Add1~3 )) + + .dataa(\vga_ctrl_inst|cnt_v [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~3 ), + .combout(\vga_ctrl_inst|Add1~4_combout ), + .cout(\vga_ctrl_inst|Add1~5 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~4 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~6 ( +// Equation(s): +// \vga_ctrl_inst|Add1~6_combout = (\vga_ctrl_inst|cnt_v [3] & (!\vga_ctrl_inst|Add1~5 )) # (!\vga_ctrl_inst|cnt_v [3] & ((\vga_ctrl_inst|Add1~5 ) # (GND))) +// \vga_ctrl_inst|Add1~7 = CARRY((!\vga_ctrl_inst|Add1~5 ) # (!\vga_ctrl_inst|cnt_v [3])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~5 ), + .combout(\vga_ctrl_inst|Add1~6_combout ), + .cout(\vga_ctrl_inst|Add1~7 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~6 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~8 ( +// Equation(s): +// \vga_ctrl_inst|Add1~8_combout = (\vga_ctrl_inst|cnt_v [4] & (\vga_ctrl_inst|Add1~7 $ (GND))) # (!\vga_ctrl_inst|cnt_v [4] & (!\vga_ctrl_inst|Add1~7 & VCC)) +// \vga_ctrl_inst|Add1~9 = CARRY((\vga_ctrl_inst|cnt_v [4] & !\vga_ctrl_inst|Add1~7 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [4]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~7 ), + .combout(\vga_ctrl_inst|Add1~8_combout ), + .cout(\vga_ctrl_inst|Add1~9 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~8 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~10 ( +// Equation(s): +// \vga_ctrl_inst|Add1~10_combout = (\vga_ctrl_inst|cnt_v [5] & (!\vga_ctrl_inst|Add1~9 )) # (!\vga_ctrl_inst|cnt_v [5] & ((\vga_ctrl_inst|Add1~9 ) # (GND))) +// \vga_ctrl_inst|Add1~11 = CARRY((!\vga_ctrl_inst|Add1~9 ) # (!\vga_ctrl_inst|cnt_v [5])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [5]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~9 ), + .combout(\vga_ctrl_inst|Add1~10_combout ), + .cout(\vga_ctrl_inst|Add1~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~10 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~12 ( +// Equation(s): +// \vga_ctrl_inst|Add1~12_combout = (\vga_ctrl_inst|cnt_v [6] & (\vga_ctrl_inst|Add1~11 $ (GND))) # (!\vga_ctrl_inst|cnt_v [6] & (!\vga_ctrl_inst|Add1~11 & VCC)) +// \vga_ctrl_inst|Add1~13 = CARRY((\vga_ctrl_inst|cnt_v [6] & !\vga_ctrl_inst|Add1~11 )) + + .dataa(\vga_ctrl_inst|cnt_v [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~11 ), + .combout(\vga_ctrl_inst|Add1~12_combout ), + .cout(\vga_ctrl_inst|Add1~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~12 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N26 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~16 ( +// Equation(s): +// \vga_ctrl_inst|Add1~16_combout = (\vga_ctrl_inst|cnt_v [8] & (\vga_ctrl_inst|Add1~15 $ (GND))) # (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|Add1~15 & VCC)) +// \vga_ctrl_inst|Add1~17 = CARRY((\vga_ctrl_inst|cnt_v [8] & !\vga_ctrl_inst|Add1~15 )) + + .dataa(\vga_ctrl_inst|cnt_v [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~15 ), + .combout(\vga_ctrl_inst|Add1~16_combout ), + .cout(\vga_ctrl_inst|Add1~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~16 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y23_N13 +dffeas \vga_ctrl_inst|cnt_v[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[8]~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[8] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~0 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~0_combout = (\vga_ctrl_inst|cnt_h [8] & \vga_ctrl_inst|cnt_h [9]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~0 .lut_mask = 16'hCC00; +defparam \vga_ctrl_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N13 +dffeas \vga_ctrl_inst|cnt_h[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [2]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[2] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N12 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[8]~3 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[8]~3_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~16_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [8])))) + + .dataa(\vga_ctrl_inst|Add1~16_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [8]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[8]~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[8]~3 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[8]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data[4]~5 ( +// Equation(s): +// \vga_pic_inst|pix_data[4]~5_combout = (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~16_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|pix_data_req~4_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~16_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4]~5 .lut_mask = 16'h00CC; +defparam \vga_pic_inst|pix_data[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~8 ( +// Equation(s): +// \vga_pic_inst|pix_data~8_combout = (\vga_ctrl_inst|Add2~16_combout ) # (((\vga_ctrl_inst|Add2~14_combout ) # (!\vga_ctrl_inst|pix_data_req~4_combout )) # (!\vga_ctrl_inst|Add2~10_combout )) + + .dataa(\vga_ctrl_inst|Add2~16_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~8 .lut_mask = 16'hFBFF; +defparam \vga_pic_inst|pix_data~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N10 +cycloneive_lcell_comb \vga_pic_inst|pix_data~15 ( +// Equation(s): +// \vga_pic_inst|pix_data~15_combout = (\vga_pic_inst|pix_data[4]~5_combout & (\vga_pic_inst|pix_data~11_combout & ((!\vga_pic_inst|pix_data[4]~10_combout )))) # (!\vga_pic_inst|pix_data[4]~5_combout & (((\vga_pic_inst|pix_data~14_combout )))) + + .dataa(\vga_pic_inst|pix_data~11_combout ), + .datab(\vga_pic_inst|pix_data~14_combout ), + .datac(\vga_pic_inst|pix_data[4]~10_combout ), + .datad(\vga_pic_inst|pix_data[4]~5_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~15_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~15 .lut_mask = 16'h0ACC; +defparam \vga_pic_inst|pix_data~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~17 ( +// Equation(s): +// \vga_pic_inst|pix_data~17_combout = (\vga_ctrl_inst|Add2~12_combout & (!\vga_ctrl_inst|Add2~14_combout )) # (!\vga_ctrl_inst|Add2~12_combout & (\vga_ctrl_inst|Add2~14_combout & !\vga_ctrl_inst|Add2~10_combout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~17_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~17 .lut_mask = 16'h0C3C; +defparam \vga_pic_inst|pix_data~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOOBUF_X35_Y0_N30 +cycloneive_io_obuf \hsync~output ( + .i(!\vga_ctrl_inst|LessThan0~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(hsync), + .obar()); +// synopsys translate_off +defparam \hsync~output .bus_hold = "false"; +defparam \hsync~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X28_Y0_N2 +cycloneive_io_obuf \vsync~output ( + .i(!\vga_ctrl_inst|LessThan1~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(vsync), + .obar()); +// synopsys translate_off +defparam \vsync~output .bus_hold = "false"; +defparam \vsync~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X32_Y0_N2 +cycloneive_io_obuf \rgb[0]~output ( + .i(\vga_ctrl_inst|rgb[0]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[0]), + .obar()); +// synopsys translate_off +defparam \rgb[0]~output .bus_hold = "false"; +defparam \rgb[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X35_Y0_N23 +cycloneive_io_obuf \rgb[1]~output ( + .i(\vga_ctrl_inst|rgb[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[1]), + .obar()); +// synopsys translate_off +defparam \rgb[1]~output .bus_hold = "false"; +defparam \rgb[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X35_Y0_N16 +cycloneive_io_obuf \rgb[2]~output ( + .i(\vga_ctrl_inst|rgb[0]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[2]), + .obar()); +// synopsys translate_off +defparam \rgb[2]~output .bus_hold = "false"; +defparam \rgb[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y4_N9 +cycloneive_io_obuf \rgb[3]~output ( + .i(\vga_ctrl_inst|rgb[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[3]), + .obar()); +// synopsys translate_off +defparam \rgb[3]~output .bus_hold = "false"; +defparam \rgb[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y3_N9 +cycloneive_io_obuf \rgb[4]~output ( + .i(\vga_ctrl_inst|rgb[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[4]), + .obar()); +// synopsys translate_off +defparam \rgb[4]~output .bus_hold = "false"; +defparam \rgb[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y3_N16 +cycloneive_io_obuf \rgb[5]~output ( + .i(\vga_ctrl_inst|rgb[5]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[5]), + .obar()); +// synopsys translate_off +defparam \rgb[5]~output .bus_hold = "false"; +defparam \rgb[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y8_N2 +cycloneive_io_obuf \rgb[6]~output ( + .i(\vga_ctrl_inst|rgb[5]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[6]), + .obar()); +// synopsys translate_off +defparam \rgb[6]~output .bus_hold = "false"; +defparam \rgb[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y8_N9 +cycloneive_io_obuf \rgb[7]~output ( + .i(\vga_ctrl_inst|rgb[7]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[7]), + .obar()); +// synopsys translate_off +defparam \rgb[7]~output .bus_hold = "false"; +defparam \rgb[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y12_N16 +cycloneive_io_obuf \rgb[8]~output ( + .i(\vga_ctrl_inst|rgb[5]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[8]), + .obar()); +// synopsys translate_off +defparam \rgb[8]~output .bus_hold = "false"; +defparam \rgb[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y13_N9 +cycloneive_io_obuf \rgb[9]~output ( + .i(\vga_ctrl_inst|rgb[7]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[9]), + .obar()); +// synopsys translate_off +defparam \rgb[9]~output .bus_hold = "false"; +defparam \rgb[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y14_N23 +cycloneive_io_obuf \rgb[10]~output ( + .i(\vga_ctrl_inst|rgb[10]~4_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[10]), + .obar()); +// synopsys translate_off +defparam \rgb[10]~output .bus_hold = "false"; +defparam \rgb[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y13_N2 +cycloneive_io_obuf \rgb[11]~output ( + .i(\vga_ctrl_inst|rgb[11]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[11]), + .obar()); +// synopsys translate_off +defparam \rgb[11]~output .bus_hold = "false"; +defparam \rgb[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y18_N16 +cycloneive_io_obuf \rgb[12]~output ( + .i(\vga_ctrl_inst|rgb[12]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[12]), + .obar()); +// synopsys translate_off +defparam \rgb[12]~output .bus_hold = "false"; +defparam \rgb[12]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y18_N23 +cycloneive_io_obuf \rgb[13]~output ( + .i(\vga_ctrl_inst|rgb[11]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[13]), + .obar()); +// synopsys translate_off +defparam \rgb[13]~output .bus_hold = "false"; +defparam \rgb[13]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y19_N9 +cycloneive_io_obuf \rgb[14]~output ( + .i(\vga_ctrl_inst|rgb[12]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[14]), + .obar()); +// synopsys translate_off +defparam \rgb[14]~output .bus_hold = "false"; +defparam \rgb[14]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y20_N23 +cycloneive_io_obuf \rgb[15]~output ( + .i(\vga_ctrl_inst|rgb[12]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[15]), + .obar()); +// synopsys translate_off +defparam \rgb[15]~output .bus_hold = "false"; +defparam \rgb[15]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~0 ( +// Equation(s): +// \vga_ctrl_inst|Add0~0_combout = \vga_ctrl_inst|cnt_h [0] $ (VCC) +// \vga_ctrl_inst|Add0~1 = CARRY(\vga_ctrl_inst|cnt_h [0]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\vga_ctrl_inst|Add0~0_combout ), + .cout(\vga_ctrl_inst|Add0~1 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~0 .lut_mask = 16'h33CC; +defparam \vga_ctrl_inst|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y3_N0 +cycloneive_lcell_comb \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X35_Y3_N1 +dffeas \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .d(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y3_N10 +cycloneive_lcell_comb \rst_n~0 ( +// Equation(s): +// \rst_n~0_combout = ((!\sys_rst_n~input_o ) # (!\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q )) # (!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ) + + .dataa(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .datac(\sys_rst_n~input_o ), + .datad(gnd), + .cin(gnd), + .combout(\rst_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \rst_n~0 .lut_mask = 16'h7F7F; +defparam \rst_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G16 +cycloneive_clkctrl \rst_n~0clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~0_combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~0clkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~0clkctrl .clock_type = "global clock"; +defparam \rst_n~0clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X35_Y23_N9 +dffeas \vga_ctrl_inst|cnt_h[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[0] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~2 ( +// Equation(s): +// \vga_ctrl_inst|Add0~2_combout = (\vga_ctrl_inst|cnt_h [1] & (!\vga_ctrl_inst|Add0~1 )) # (!\vga_ctrl_inst|cnt_h [1] & ((\vga_ctrl_inst|Add0~1 ) # (GND))) +// \vga_ctrl_inst|Add0~3 = CARRY((!\vga_ctrl_inst|Add0~1 ) # (!\vga_ctrl_inst|cnt_h [1])) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~1 ), + .combout(\vga_ctrl_inst|Add0~2_combout ), + .cout(\vga_ctrl_inst|Add0~3 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~2 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~6 ( +// Equation(s): +// \vga_ctrl_inst|Add0~6_combout = (\vga_ctrl_inst|cnt_h [3] & (!\vga_ctrl_inst|Add0~5 )) # (!\vga_ctrl_inst|cnt_h [3] & ((\vga_ctrl_inst|Add0~5 ) # (GND))) +// \vga_ctrl_inst|Add0~7 = CARRY((!\vga_ctrl_inst|Add0~5 ) # (!\vga_ctrl_inst|cnt_h [3])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [3]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~5 ), + .combout(\vga_ctrl_inst|Add0~6_combout ), + .cout(\vga_ctrl_inst|Add0~7 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~6 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N15 +dffeas \vga_ctrl_inst|cnt_h[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [3]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[3] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~8 ( +// Equation(s): +// \vga_ctrl_inst|Add0~8_combout = (\vga_ctrl_inst|cnt_h [4] & (\vga_ctrl_inst|Add0~7 $ (GND))) # (!\vga_ctrl_inst|cnt_h [4] & (!\vga_ctrl_inst|Add0~7 & VCC)) +// \vga_ctrl_inst|Add0~9 = CARRY((\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|Add0~7 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [4]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~7 ), + .combout(\vga_ctrl_inst|Add0~8_combout ), + .cout(\vga_ctrl_inst|Add0~9 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~8 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N17 +dffeas \vga_ctrl_inst|cnt_h[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[4] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~10 ( +// Equation(s): +// \vga_ctrl_inst|Add0~10_combout = (\vga_ctrl_inst|cnt_h [5] & (!\vga_ctrl_inst|Add0~9 )) # (!\vga_ctrl_inst|cnt_h [5] & ((\vga_ctrl_inst|Add0~9 ) # (GND))) +// \vga_ctrl_inst|Add0~11 = CARRY((!\vga_ctrl_inst|Add0~9 ) # (!\vga_ctrl_inst|cnt_h [5])) + + .dataa(\vga_ctrl_inst|cnt_h [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~9 ), + .combout(\vga_ctrl_inst|Add0~10_combout ), + .cout(\vga_ctrl_inst|Add0~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~10 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~12 ( +// Equation(s): +// \vga_ctrl_inst|Add0~12_combout = (\vga_ctrl_inst|cnt_h [6] & (\vga_ctrl_inst|Add0~11 $ (GND))) # (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|Add0~11 & VCC)) +// \vga_ctrl_inst|Add0~13 = CARRY((\vga_ctrl_inst|cnt_h [6] & !\vga_ctrl_inst|Add0~11 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~11 ), + .combout(\vga_ctrl_inst|Add0~12_combout ), + .cout(\vga_ctrl_inst|Add0~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~12 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N21 +dffeas \vga_ctrl_inst|cnt_h[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [6]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[6] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~14 ( +// Equation(s): +// \vga_ctrl_inst|Add0~14_combout = (\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Add0~13 )) # (!\vga_ctrl_inst|cnt_h [7] & ((\vga_ctrl_inst|Add0~13 ) # (GND))) +// \vga_ctrl_inst|Add0~15 = CARRY((!\vga_ctrl_inst|Add0~13 ) # (!\vga_ctrl_inst|cnt_h [7])) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~13 ), + .combout(\vga_ctrl_inst|Add0~14_combout ), + .cout(\vga_ctrl_inst|Add0~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~14 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N23 +dffeas \vga_ctrl_inst|cnt_h[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [7]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[7] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N24 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~16 ( +// Equation(s): +// \vga_ctrl_inst|Add0~16_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|Add0~15 $ (GND))) # (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|Add0~15 & VCC)) +// \vga_ctrl_inst|Add0~17 = CARRY((\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|Add0~15 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~15 ), + .combout(\vga_ctrl_inst|Add0~16_combout ), + .cout(\vga_ctrl_inst|Add0~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~16 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N26 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~18 ( +// Equation(s): +// \vga_ctrl_inst|Add0~18_combout = \vga_ctrl_inst|Add0~17 $ (\vga_ctrl_inst|cnt_h [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(\vga_ctrl_inst|Add0~17 ), + .combout(\vga_ctrl_inst|Add0~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~18 .lut_mask = 16'h0FF0; +defparam \vga_ctrl_inst|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~1 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~1_combout = (!\vga_ctrl_inst|Equal0~3_combout & \vga_ctrl_inst|Add0~18_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|Add0~18_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~1 .lut_mask = 16'h3030; +defparam \vga_ctrl_inst|cnt_h~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N1 +dffeas \vga_ctrl_inst|cnt_h[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[9] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N24 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~0 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~0_combout = (\vga_ctrl_inst|Add0~10_combout & !\vga_ctrl_inst|Equal0~3_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add0~10_combout ), + .datac(\vga_ctrl_inst|Equal0~3_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~0 .lut_mask = 16'h0C0C; +defparam \vga_ctrl_inst|cnt_h~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y23_N25 +dffeas \vga_ctrl_inst|cnt_h[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [5]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[5] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N30 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~2 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~2_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|cnt_h [9] & (!\vga_ctrl_inst|cnt_h [5] & !\vga_ctrl_inst|cnt_h [6]))) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(\vga_ctrl_inst|cnt_h [9]), + .datac(\vga_ctrl_inst|cnt_h [5]), + .datad(\vga_ctrl_inst|cnt_h [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~2 .lut_mask = 16'h0008; +defparam \vga_ctrl_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N11 +dffeas \vga_ctrl_inst|cnt_h[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [1]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[1] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N28 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~1 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~1_combout = (\vga_ctrl_inst|cnt_h [2] & (\vga_ctrl_inst|cnt_h [3] & (\vga_ctrl_inst|cnt_h [0] & \vga_ctrl_inst|cnt_h [1]))) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(\vga_ctrl_inst|cnt_h [3]), + .datac(\vga_ctrl_inst|cnt_h [0]), + .datad(\vga_ctrl_inst|cnt_h [1]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~1 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~3 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~3_combout = (\vga_ctrl_inst|cnt_h [4] & (\vga_ctrl_inst|Equal0~2_combout & (\vga_ctrl_inst|Equal0~1_combout & !\vga_ctrl_inst|cnt_h [7]))) + + .dataa(\vga_ctrl_inst|cnt_h [4]), + .datab(\vga_ctrl_inst|Equal0~2_combout ), + .datac(\vga_ctrl_inst|Equal0~1_combout ), + .datad(\vga_ctrl_inst|cnt_h [7]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~3 .lut_mask = 16'h0080; +defparam \vga_ctrl_inst|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~2 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~2_combout = (\vga_ctrl_inst|Add0~16_combout & !\vga_ctrl_inst|Equal0~3_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add0~16_combout ), + .datac(\vga_ctrl_inst|Equal0~3_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~2 .lut_mask = 16'h0C0C; +defparam \vga_ctrl_inst|cnt_h~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N3 +dffeas \vga_ctrl_inst|cnt_h[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[8] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N4 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan2~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan2~0_combout = (!\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|cnt_h [9]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan2~0 .lut_mask = 16'h0033; +defparam \vga_ctrl_inst|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan0~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan0~0_combout = (\vga_ctrl_inst|cnt_h [7]) # (((\vga_ctrl_inst|cnt_h [6] & \vga_ctrl_inst|cnt_h [5])) # (!\vga_ctrl_inst|LessThan2~0_combout )) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(\vga_ctrl_inst|LessThan2~0_combout ), + .datad(\vga_ctrl_inst|cnt_h [5]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan0~0 .lut_mask = 16'hEFAF; +defparam \vga_ctrl_inst|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N28 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[0]~9 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[0]~9_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~0_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [0])))) + + .dataa(\vga_ctrl_inst|Add1~0_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [0]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[0]~9 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N29 +dffeas \vga_ctrl_inst|cnt_v[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[0]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[0] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N4 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[2]~8 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[2]~8_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~4_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [2])))) + + .dataa(\vga_ctrl_inst|Add1~4_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[2]~8 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N5 +dffeas \vga_ctrl_inst|cnt_v[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[2]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [2]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[2] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[4]~6 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[4]~6_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~8_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [4])))) + + .dataa(\vga_ctrl_inst|Add1~8_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [4]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[4]~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[4]~6 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[4]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N1 +dffeas \vga_ctrl_inst|cnt_v[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[4]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[4] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|always1~1 ( +// Equation(s): +// \vga_ctrl_inst|always1~1_combout = (\vga_ctrl_inst|cnt_v [9] & (\vga_ctrl_inst|cnt_v [3] & (\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|cnt_v [4]))) + + .dataa(\vga_ctrl_inst|cnt_v [9]), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|cnt_v [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~1 .lut_mask = 16'h0080; +defparam \vga_ctrl_inst|always1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[1]~0 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[1]~0_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~2_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [1])))) + + .dataa(\vga_ctrl_inst|Add1~2_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [1]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[1]~0 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N17 +dffeas \vga_ctrl_inst|cnt_v[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[1]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [1]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[1] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|always1~2 ( +// Equation(s): +// \vga_ctrl_inst|always1~2_combout = (\vga_ctrl_inst|always1~0_combout & (!\vga_ctrl_inst|cnt_v [0] & (\vga_ctrl_inst|always1~1_combout & !\vga_ctrl_inst|cnt_v [1]))) + + .dataa(\vga_ctrl_inst|always1~0_combout ), + .datab(\vga_ctrl_inst|cnt_v [0]), + .datac(\vga_ctrl_inst|always1~1_combout ), + .datad(\vga_ctrl_inst|cnt_v [1]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~2 .lut_mask = 16'h0020; +defparam \vga_ctrl_inst|always1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[3]~7 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[3]~7_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~6_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [3])))) + + .dataa(\vga_ctrl_inst|Add1~6_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [3]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[3]~7 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N3 +dffeas \vga_ctrl_inst|cnt_v[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[3]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [3]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[3] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan6~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan6~0_combout = (!\vga_ctrl_inst|cnt_v [3] & (!\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|cnt_v [4])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|cnt_v [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan6~0 .lut_mask = 16'h0003; +defparam \vga_ctrl_inst|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[5]~2 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[5]~2_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~10_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [5])))) + + .dataa(\vga_ctrl_inst|Add1~10_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [5]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[5]~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[5]~2 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[5]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N19 +dffeas \vga_ctrl_inst|cnt_v[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[5]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [5]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[5] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N24 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~14 ( +// Equation(s): +// \vga_ctrl_inst|Add1~14_combout = (\vga_ctrl_inst|cnt_v [7] & (!\vga_ctrl_inst|Add1~13 )) # (!\vga_ctrl_inst|cnt_v [7] & ((\vga_ctrl_inst|Add1~13 ) # (GND))) +// \vga_ctrl_inst|Add1~15 = CARRY((!\vga_ctrl_inst|Add1~13 ) # (!\vga_ctrl_inst|cnt_v [7])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [7]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~13 ), + .combout(\vga_ctrl_inst|Add1~14_combout ), + .cout(\vga_ctrl_inst|Add1~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~14 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[7]~4 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[7]~4_combout = (\vga_ctrl_inst|Equal0~3_combout & (!\vga_ctrl_inst|always1~2_combout & (\vga_ctrl_inst|Add1~14_combout ))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [7])))) + + .dataa(\vga_ctrl_inst|always1~2_combout ), + .datab(\vga_ctrl_inst|Add1~14_combout ), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[7]~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[7]~4 .lut_mask = 16'h44F0; +defparam \vga_ctrl_inst|cnt_v[7]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y24_N3 +dffeas \vga_ctrl_inst|cnt_v[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[7]~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [7]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[7] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N28 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~18 ( +// Equation(s): +// \vga_ctrl_inst|Add1~18_combout = \vga_ctrl_inst|Add1~17 $ (\vga_ctrl_inst|cnt_v [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_v [9]), + .cin(\vga_ctrl_inst|Add1~17 ), + .combout(\vga_ctrl_inst|Add1~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~18 .lut_mask = 16'h0FF0; +defparam \vga_ctrl_inst|Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[9]~1 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[9]~1_combout = (\vga_ctrl_inst|Equal0~3_combout & (!\vga_ctrl_inst|always1~2_combout & (\vga_ctrl_inst|Add1~18_combout ))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [9])))) + + .dataa(\vga_ctrl_inst|always1~2_combout ), + .datab(\vga_ctrl_inst|Add1~18_combout ), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[9]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[9]~1 .lut_mask = 16'h44F0; +defparam \vga_ctrl_inst|cnt_v[9]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y24_N1 +dffeas \vga_ctrl_inst|cnt_v[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[9]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[9] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N4 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[6]~5 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[6]~5_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~12_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [6])))) + + .dataa(\vga_ctrl_inst|Add1~12_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [6]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[6]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[6]~5 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[6]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y24_N5 +dffeas \vga_ctrl_inst|cnt_v[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[6]~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [6]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[6] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|always1~0 ( +// Equation(s): +// \vga_ctrl_inst|always1~0_combout = (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|cnt_v [5] & (!\vga_ctrl_inst|cnt_v [7] & !\vga_ctrl_inst|cnt_v [6]))) + + .dataa(\vga_ctrl_inst|cnt_v [8]), + .datab(\vga_ctrl_inst|cnt_v [5]), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|cnt_v [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~0 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan1~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan1~0_combout = ((\vga_ctrl_inst|cnt_v [1]) # ((\vga_ctrl_inst|cnt_v [9]) # (!\vga_ctrl_inst|always1~0_combout ))) # (!\vga_ctrl_inst|LessThan6~0_combout ) + + .dataa(\vga_ctrl_inst|LessThan6~0_combout ), + .datab(\vga_ctrl_inst|cnt_v [1]), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(\vga_ctrl_inst|always1~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan1~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan1~0 .lut_mask = 16'hFDFF; +defparam \vga_ctrl_inst|LessThan1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan6~1 ( +// Equation(s): +// \vga_ctrl_inst|LessThan6~1_combout = (!\vga_ctrl_inst|cnt_v [1]) # (!\vga_ctrl_inst|cnt_v [0]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [0]), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_v [1]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan6~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan6~1 .lut_mask = 16'h33FF; +defparam \vga_ctrl_inst|LessThan6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N30 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~1 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~1_combout = (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|cnt_v [9] & (!\vga_ctrl_inst|cnt_v [7] & !\vga_ctrl_inst|cnt_v [6]))) + + .dataa(\vga_ctrl_inst|cnt_v [8]), + .datab(\vga_ctrl_inst|cnt_v [9]), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|cnt_v [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~1 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|pix_data_req~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N24 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~2 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~2_combout = (\vga_ctrl_inst|LessThan6~0_combout & ((\vga_ctrl_inst|LessThan6~1_combout & (\vga_ctrl_inst|pix_data_req~1_combout )) # (!\vga_ctrl_inst|LessThan6~1_combout & ((\vga_ctrl_inst|always1~0_combout ))))) # +// (!\vga_ctrl_inst|LessThan6~0_combout & (((\vga_ctrl_inst|always1~0_combout )))) + + .dataa(\vga_ctrl_inst|LessThan6~0_combout ), + .datab(\vga_ctrl_inst|LessThan6~1_combout ), + .datac(\vga_ctrl_inst|pix_data_req~1_combout ), + .datad(\vga_ctrl_inst|always1~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~2 .lut_mask = 16'hF780; +defparam \vga_ctrl_inst|pix_data_req~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N28 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan2~1 ( +// Equation(s): +// \vga_ctrl_inst|LessThan2~1_combout = (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|cnt_h [5])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(\vga_ctrl_inst|cnt_h [4]), + .datad(\vga_ctrl_inst|cnt_h [5]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan2~1 .lut_mask = 16'h0003; +defparam \vga_ctrl_inst|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|rgb_valid~0 ( +// Equation(s): +// \vga_ctrl_inst|rgb_valid~0_combout = (\vga_ctrl_inst|Equal0~0_combout & (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|LessThan2~0_combout & \vga_ctrl_inst|LessThan2~1_combout ))) # (!\vga_ctrl_inst|Equal0~0_combout & (((\vga_ctrl_inst|cnt_h [7] & +// !\vga_ctrl_inst|LessThan2~1_combout )) # (!\vga_ctrl_inst|LessThan2~0_combout ))) + + .dataa(\vga_ctrl_inst|Equal0~0_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|LessThan2~0_combout ), + .datad(\vga_ctrl_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb_valid~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb_valid~0 .lut_mask = 16'h0745; +defparam \vga_ctrl_inst|rgb_valid~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~1 ( +// Equation(s): +// \vga_ctrl_inst|Add2~1_cout = CARRY((\vga_ctrl_inst|cnt_h [1] & \vga_ctrl_inst|cnt_h [0])) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(\vga_ctrl_inst|cnt_h [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\vga_ctrl_inst|Add2~1_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~1 .lut_mask = 16'h0088; +defparam \vga_ctrl_inst|Add2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~3 ( +// Equation(s): +// \vga_ctrl_inst|Add2~3_cout = CARRY((!\vga_ctrl_inst|Add2~1_cout ) # (!\vga_ctrl_inst|cnt_h [2])) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~1_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~3_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~3 .lut_mask = 16'h005F; +defparam \vga_ctrl_inst|Add2~3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~5 ( +// Equation(s): +// \vga_ctrl_inst|Add2~5_cout = CARRY((\vga_ctrl_inst|cnt_h [3] & !\vga_ctrl_inst|Add2~3_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~3_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~5_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~5 .lut_mask = 16'h000A; +defparam \vga_ctrl_inst|Add2~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~7 ( +// Equation(s): +// \vga_ctrl_inst|Add2~7_cout = CARRY((!\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|Add2~5_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~5_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~7_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~7 .lut_mask = 16'h0005; +defparam \vga_ctrl_inst|Add2~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~9 ( +// Equation(s): +// \vga_ctrl_inst|Add2~9_cout = CARRY((\vga_ctrl_inst|cnt_h [5]) # (!\vga_ctrl_inst|Add2~7_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~7_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~9_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~9 .lut_mask = 16'h00AF; +defparam \vga_ctrl_inst|Add2~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~10 ( +// Equation(s): +// \vga_ctrl_inst|Add2~10_combout = (\vga_ctrl_inst|cnt_h [6] & (\vga_ctrl_inst|Add2~9_cout & VCC)) # (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|Add2~9_cout )) +// \vga_ctrl_inst|Add2~11 = CARRY((!\vga_ctrl_inst|cnt_h [6] & !\vga_ctrl_inst|Add2~9_cout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~9_cout ), + .combout(\vga_ctrl_inst|Add2~10_combout ), + .cout(\vga_ctrl_inst|Add2~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~10 .lut_mask = 16'hC303; +defparam \vga_ctrl_inst|Add2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~12 ( +// Equation(s): +// \vga_ctrl_inst|Add2~12_combout = (\vga_ctrl_inst|cnt_h [7] & (\vga_ctrl_inst|Add2~11 $ (GND))) # (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Add2~11 & VCC)) +// \vga_ctrl_inst|Add2~13 = CARRY((\vga_ctrl_inst|cnt_h [7] & !\vga_ctrl_inst|Add2~11 )) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~11 ), + .combout(\vga_ctrl_inst|Add2~12_combout ), + .cout(\vga_ctrl_inst|Add2~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~12 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N24 +cycloneive_lcell_comb \vga_pic_inst|LessThan14~0 ( +// Equation(s): +// \vga_pic_inst|LessThan14~0_combout = (\vga_ctrl_inst|Add2~12_combout & \vga_ctrl_inst|Add2~10_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan14~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan14~0 .lut_mask = 16'hCC00; +defparam \vga_pic_inst|LessThan14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~14 ( +// Equation(s): +// \vga_ctrl_inst|Add2~14_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|Add2~13 & VCC)) # (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|Add2~13 )) +// \vga_ctrl_inst|Add2~15 = CARRY((!\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|Add2~13 )) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~13 ), + .combout(\vga_ctrl_inst|Add2~14_combout ), + .cout(\vga_ctrl_inst|Add2~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~14 .lut_mask = 16'hA505; +defparam \vga_ctrl_inst|Add2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~16 ( +// Equation(s): +// \vga_ctrl_inst|Add2~16_combout = \vga_ctrl_inst|cnt_h [9] $ (\vga_ctrl_inst|Add2~15 ) + + .dataa(\vga_ctrl_inst|cnt_h [9]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\vga_ctrl_inst|Add2~15 ), + .combout(\vga_ctrl_inst|Add2~16_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~16 .lut_mask = 16'h5A5A; +defparam \vga_ctrl_inst|Add2~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N2 +cycloneive_lcell_comb \vga_pic_inst|LessThan6~0 ( +// Equation(s): +// \vga_pic_inst|LessThan6~0_combout = ((\vga_pic_inst|LessThan14~0_combout ) # ((\vga_ctrl_inst|Add2~16_combout ) # (\vga_ctrl_inst|Add2~14_combout ))) # (!\vga_ctrl_inst|pix_data_req~4_combout ) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_pic_inst|LessThan14~0_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan6~0 .lut_mask = 16'hFFFD; +defparam \vga_pic_inst|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N26 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~0 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~0_combout = (!\vga_ctrl_inst|always1~0_combout & \vga_ctrl_inst|cnt_v [9]) + + .dataa(\vga_ctrl_inst|always1~0_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~0 .lut_mask = 16'h5050; +defparam \vga_ctrl_inst|pix_data_req~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N4 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan4~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan4~0_combout = (\vga_ctrl_inst|LessThan2~0_combout & (((!\vga_ctrl_inst|Equal0~1_combout & \vga_ctrl_inst|LessThan2~1_combout )) # (!\vga_ctrl_inst|cnt_h [7]))) + + .dataa(\vga_ctrl_inst|Equal0~1_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|LessThan2~0_combout ), + .datad(\vga_ctrl_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan4~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan4~0 .lut_mask = 16'h7030; +defparam \vga_ctrl_inst|LessThan4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~3 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~3_combout = ((!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Equal0~1_combout & \vga_ctrl_inst|LessThan2~1_combout ))) # (!\vga_ctrl_inst|Equal0~0_combout ) + + .dataa(\vga_ctrl_inst|Equal0~0_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|Equal0~1_combout ), + .datad(\vga_ctrl_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~3 .lut_mask = 16'h5755; +defparam \vga_ctrl_inst|pix_data_req~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~4 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~4_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (!\vga_ctrl_inst|LessThan4~0_combout & \vga_ctrl_inst|pix_data_req~3_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|LessThan4~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~4 .lut_mask = 16'h0100; +defparam \vga_ctrl_inst|pix_data_req~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N2 +cycloneive_lcell_comb \vga_pic_inst|pix_data~4 ( +// Equation(s): +// \vga_pic_inst|pix_data~4_combout = (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~12_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|pix_data_req~4_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~4 .lut_mask = 16'h00CC; +defparam \vga_pic_inst|pix_data~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~9 ( +// Equation(s): +// \vga_pic_inst|pix_data~9_combout = (\vga_pic_inst|pix_data~8_combout & ((\vga_pic_inst|LessThan6~0_combout ) # ((!\vga_ctrl_inst|Add2~14_combout & \vga_pic_inst|pix_data~4_combout )))) # (!\vga_pic_inst|pix_data~8_combout & +// (((!\vga_ctrl_inst|Add2~14_combout & \vga_pic_inst|pix_data~4_combout )))) + + .dataa(\vga_pic_inst|pix_data~8_combout ), + .datab(\vga_pic_inst|LessThan6~0_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_pic_inst|pix_data~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~9_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~9 .lut_mask = 16'h8F88; +defparam \vga_pic_inst|pix_data~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N8 +cycloneive_lcell_comb \vga_pic_inst|LessThan17~0 ( +// Equation(s): +// \vga_pic_inst|LessThan17~0_combout = (\vga_ctrl_inst|Add2~12_combout ) # ((\vga_ctrl_inst|Add2~10_combout ) # ((\vga_ctrl_inst|Add2~14_combout ) # (!\vga_ctrl_inst|pix_data_req~4_combout ))) + + .dataa(\vga_ctrl_inst|Add2~12_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan17~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan17~0 .lut_mask = 16'hFEFF; +defparam \vga_pic_inst|LessThan17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N14 +cycloneive_lcell_comb \vga_pic_inst|pix_data~6 ( +// Equation(s): +// \vga_pic_inst|pix_data~6_combout = ((\vga_pic_inst|LessThan17~0_combout & ((\vga_ctrl_inst|Add2~14_combout ) # (!\vga_pic_inst|pix_data~4_combout )))) # (!\vga_pic_inst|pix_data[4]~5_combout ) + + .dataa(\vga_pic_inst|pix_data[4]~5_combout ), + .datab(\vga_pic_inst|pix_data~4_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_pic_inst|LessThan17~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~6 .lut_mask = 16'hF755; +defparam \vga_pic_inst|pix_data~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N22 +cycloneive_lcell_comb \vga_pic_inst|pix_data[4]~10 ( +// Equation(s): +// \vga_pic_inst|pix_data[4]~10_combout = (!\vga_ctrl_inst|Add2~12_combout ) # (!\vga_ctrl_inst|Add2~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[4]~10_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4]~10 .lut_mask = 16'h0FFF; +defparam \vga_pic_inst|pix_data[4]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~11 ( +// Equation(s): +// \vga_pic_inst|pix_data~11_combout = (\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|Add2~12_combout & (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~10_combout ))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~11_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~11 .lut_mask = 16'h0080; +defparam \vga_pic_inst|pix_data~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N24 +cycloneive_lcell_comb \vga_pic_inst|pix_data~12 ( +// Equation(s): +// \vga_pic_inst|pix_data~12_combout = (\vga_pic_inst|pix_data[4]~5_combout & (((\vga_pic_inst|pix_data[4]~10_combout ) # (!\vga_pic_inst|pix_data~11_combout )))) # (!\vga_pic_inst|pix_data[4]~5_combout & (\vga_pic_inst|LessThan17~0_combout )) + + .dataa(\vga_pic_inst|pix_data[4]~5_combout ), + .datab(\vga_pic_inst|LessThan17~0_combout ), + .datac(\vga_pic_inst|pix_data[4]~10_combout ), + .datad(\vga_pic_inst|pix_data~11_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~12_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~12 .lut_mask = 16'hE4EE; +defparam \vga_pic_inst|pix_data~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N16 +cycloneive_lcell_comb \vga_pic_inst|pix_data~13 ( +// Equation(s): +// \vga_pic_inst|pix_data~13_combout = ((\vga_pic_inst|pix_data[4]~7_combout & (\vga_pic_inst|pix_data~9_combout & \vga_pic_inst|pix_data~6_combout ))) # (!\vga_pic_inst|pix_data~12_combout ) + + .dataa(\vga_pic_inst|pix_data[4]~7_combout ), + .datab(\vga_pic_inst|pix_data~9_combout ), + .datac(\vga_pic_inst|pix_data~6_combout ), + .datad(\vga_pic_inst|pix_data~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~13_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~13 .lut_mask = 16'h80FF; +defparam \vga_pic_inst|pix_data~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N17 +dffeas \vga_pic_inst|pix_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[0] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N0 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[0]~0 ( +// Equation(s): +// \vga_ctrl_inst|rgb[0]~0_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (\vga_ctrl_inst|rgb_valid~0_combout & (\vga_pic_inst|pix_data [0] & !\vga_ctrl_inst|pix_data_req~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|rgb_valid~0_combout ), + .datac(\vga_pic_inst|pix_data [0]), + .datad(\vga_ctrl_inst|pix_data_req~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[0]~0 .lut_mask = 16'h0040; +defparam \vga_ctrl_inst|rgb[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data[4]~7 ( +// Equation(s): +// \vga_pic_inst|pix_data[4]~7_combout = (!\vga_ctrl_inst|Add2~16_combout & (\vga_ctrl_inst|pix_data_req~4_combout & ((!\vga_ctrl_inst|Add2~14_combout ) # (!\vga_ctrl_inst|Add2~12_combout )))) + + .dataa(\vga_ctrl_inst|Add2~12_combout ), + .datab(\vga_ctrl_inst|Add2~14_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[4]~7_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4]~7 .lut_mask = 16'h0700; +defparam \vga_pic_inst|pix_data[4]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N18 +cycloneive_lcell_comb \vga_pic_inst|pix_data~16 ( +// Equation(s): +// \vga_pic_inst|pix_data~16_combout = (\vga_pic_inst|pix_data~15_combout ) # ((\vga_pic_inst|pix_data[4]~7_combout & (\vga_pic_inst|pix_data~9_combout & \vga_pic_inst|pix_data~6_combout ))) + + .dataa(\vga_pic_inst|pix_data~15_combout ), + .datab(\vga_pic_inst|pix_data[4]~7_combout ), + .datac(\vga_pic_inst|pix_data~9_combout ), + .datad(\vga_pic_inst|pix_data~6_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~16_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~16 .lut_mask = 16'hEAAA; +defparam \vga_pic_inst|pix_data~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N19 +dffeas \vga_pic_inst|pix_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N26 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[1]~1 ( +// Equation(s): +// \vga_ctrl_inst|rgb[1]~1_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [4]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[1]~1 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data~25 ( +// Equation(s): +// \vga_pic_inst|pix_data~25_combout = (\vga_ctrl_inst|Add2~16_combout & (((!\vga_pic_inst|LessThan17~0_combout )))) # (!\vga_ctrl_inst|Add2~16_combout & ((\vga_ctrl_inst|pix_data_req~4_combout & (\vga_pic_inst|pix_data~17_combout )) # +// (!\vga_ctrl_inst|pix_data_req~4_combout & ((!\vga_pic_inst|LessThan17~0_combout ))))) + + .dataa(\vga_pic_inst|pix_data~17_combout ), + .datab(\vga_ctrl_inst|Add2~16_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_pic_inst|LessThan17~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~25_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~25 .lut_mask = 16'h20EF; +defparam \vga_pic_inst|pix_data~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y23_N13 +dffeas \vga_pic_inst|pix_data[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[8] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N30 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[5]~2 ( +// Equation(s): +// \vga_ctrl_inst|rgb[5]~2_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [8]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [8]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[5]~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[5]~2 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[5]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N28 +cycloneive_lcell_comb \vga_pic_inst|pix_data~18 ( +// Equation(s): +// \vga_pic_inst|pix_data~18_combout = (\vga_ctrl_inst|pix_data_req~4_combout & ((\vga_ctrl_inst|Add2~14_combout & (!\vga_ctrl_inst|Add2~12_combout & !\vga_ctrl_inst|Add2~10_combout )) # (!\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|Add2~12_combout +// )))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~18 .lut_mask = 16'h4060; +defparam \vga_pic_inst|pix_data~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data~14 ( +// Equation(s): +// \vga_pic_inst|pix_data~14_combout = (!\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~12_combout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add2~14_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~14_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~14 .lut_mask = 16'h0030; +defparam \vga_pic_inst|pix_data~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N30 +cycloneive_lcell_comb \vga_pic_inst|pix_data~26 ( +// Equation(s): +// \vga_pic_inst|pix_data~26_combout = (\vga_ctrl_inst|pix_data_req~4_combout & ((\vga_ctrl_inst|Add2~16_combout & ((\vga_pic_inst|pix_data~14_combout ))) # (!\vga_ctrl_inst|Add2~16_combout & (\vga_pic_inst|pix_data~18_combout )))) # +// (!\vga_ctrl_inst|pix_data_req~4_combout & (((\vga_pic_inst|pix_data~14_combout )))) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_pic_inst|pix_data~18_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_pic_inst|pix_data~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~26_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~26 .lut_mask = 16'hFD08; +defparam \vga_pic_inst|pix_data~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data~19 ( +// Equation(s): +// \vga_pic_inst|pix_data~19_combout = (\vga_pic_inst|pix_data~26_combout & \vga_pic_inst|pix_data~6_combout ) + + .dataa(gnd), + .datab(\vga_pic_inst|pix_data~26_combout ), + .datac(gnd), + .datad(\vga_pic_inst|pix_data~6_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~19_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~19 .lut_mask = 16'hCC00; +defparam \vga_pic_inst|pix_data~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y24_N1 +dffeas \vga_pic_inst|pix_data[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[9] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[7]~3 ( +// Equation(s): +// \vga_ctrl_inst|rgb[7]~3_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [9]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[7]~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[7]~3 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[7]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N6 +cycloneive_lcell_comb \vga_pic_inst|LessThan2~2 ( +// Equation(s): +// \vga_pic_inst|LessThan2~2_combout = (\vga_pic_inst|LessThan17~0_combout ) # ((\vga_ctrl_inst|Add2~16_combout ) # (!\vga_ctrl_inst|pix_data_req~4_combout )) + + .dataa(\vga_pic_inst|LessThan17~0_combout ), + .datab(\vga_ctrl_inst|Add2~16_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan2~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan2~2 .lut_mask = 16'hEEFF; +defparam \vga_pic_inst|LessThan2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data~20 ( +// Equation(s): +// \vga_pic_inst|pix_data~20_combout = (!\vga_ctrl_inst|Add2~16_combout & (!\vga_ctrl_inst|Add2~14_combout & \vga_ctrl_inst|pix_data_req~4_combout )) + + .dataa(\vga_ctrl_inst|Add2~16_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~20_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~20 .lut_mask = 16'h0500; +defparam \vga_pic_inst|pix_data~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~21 ( +// Equation(s): +// \vga_pic_inst|pix_data~21_combout = (\vga_pic_inst|LessThan2~2_combout & ((\vga_pic_inst|pix_data~26_combout ) # ((\vga_pic_inst|pix_data~4_combout & \vga_pic_inst|pix_data~20_combout )))) + + .dataa(\vga_pic_inst|pix_data~4_combout ), + .datab(\vga_pic_inst|pix_data~26_combout ), + .datac(\vga_pic_inst|LessThan2~2_combout ), + .datad(\vga_pic_inst|pix_data~20_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~21_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~21 .lut_mask = 16'hE0C0; +defparam \vga_pic_inst|pix_data~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y24_N27 +dffeas \vga_pic_inst|pix_data[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [10]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[10] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N2 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[10]~4 ( +// Equation(s): +// \vga_ctrl_inst|rgb[10]~4_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [10]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [10]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[10]~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[10]~4 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[10]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N20 +cycloneive_lcell_comb \vga_pic_inst|pix_data~22 ( +// Equation(s): +// \vga_pic_inst|pix_data~22_combout = ((\vga_pic_inst|pix_data[4]~5_combout & (!\vga_ctrl_inst|Add2~14_combout & \vga_pic_inst|pix_data~4_combout ))) # (!\vga_pic_inst|LessThan6~0_combout ) + + .dataa(\vga_pic_inst|pix_data[4]~5_combout ), + .datab(\vga_pic_inst|LessThan6~0_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_pic_inst|pix_data~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~22_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~22 .lut_mask = 16'h3B33; +defparam \vga_pic_inst|pix_data~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N28 +cycloneive_lcell_comb \vga_pic_inst|pix_data~23 ( +// Equation(s): +// \vga_pic_inst|pix_data~23_combout = ((\vga_pic_inst|pix_data[4]~7_combout & ((\vga_pic_inst|pix_data~22_combout ) # (!\vga_pic_inst|LessThan2~2_combout )))) # (!\vga_pic_inst|pix_data~12_combout ) + + .dataa(\vga_pic_inst|LessThan2~2_combout ), + .datab(\vga_pic_inst|pix_data~12_combout ), + .datac(\vga_pic_inst|pix_data~22_combout ), + .datad(\vga_pic_inst|pix_data[4]~7_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~23_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~23 .lut_mask = 16'hF733; +defparam \vga_pic_inst|pix_data~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N29 +dffeas \vga_pic_inst|pix_data[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [13]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[11]~5 ( +// Equation(s): +// \vga_ctrl_inst|rgb[11]~5_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (\vga_pic_inst|pix_data [13] & (\vga_ctrl_inst|rgb_valid~0_combout & !\vga_ctrl_inst|pix_data_req~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_pic_inst|pix_data [13]), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[11]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[11]~5 .lut_mask = 16'h0040; +defparam \vga_ctrl_inst|rgb[11]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N30 +cycloneive_lcell_comb \vga_pic_inst|pix_data~24 ( +// Equation(s): +// \vga_pic_inst|pix_data~24_combout = (\vga_pic_inst|pix_data~15_combout ) # ((\vga_pic_inst|pix_data[4]~7_combout & ((\vga_pic_inst|pix_data~22_combout ) # (!\vga_pic_inst|LessThan2~2_combout )))) + + .dataa(\vga_pic_inst|pix_data~15_combout ), + .datab(\vga_pic_inst|pix_data[4]~7_combout ), + .datac(\vga_pic_inst|pix_data~22_combout ), + .datad(\vga_pic_inst|LessThan2~2_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~24_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~24 .lut_mask = 16'hEAEE; +defparam \vga_pic_inst|pix_data~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N31 +dffeas \vga_pic_inst|pix_data[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [15]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[15] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[12]~6 ( +// Equation(s): +// \vga_ctrl_inst|rgb[12]~6_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (\vga_pic_inst|pix_data [15] & (\vga_ctrl_inst|rgb_valid~0_combout & !\vga_ctrl_inst|pix_data_req~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_pic_inst|pix_data [15]), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[12]~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[12]~6 .lut_mask = 16'h0040; +defparam \vga_ctrl_inst|rgb[12]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +endmodule diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_min_1200mv_0c_v_fast.sdo b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_min_1200mv_0c_v_fast.sdo new file mode 100644 index 0000000..3c10c0b --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_min_1200mv_0c_v_fast.sdo @@ -0,0 +1,2108 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Fast Corner delays for the design using part EP4CE15F23C8, +// with speed grade M, core voltage 1.2V, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "vga_colorbar") + (DATE "06/02/2023 04:42:20") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (147:147:147) (199:199:199)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (2024:2024:2024) (2024:2024:2024)) + (PORT inclk[0] (1104:1104:1104) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (451:451:451)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (371:371:371) (445:445:445)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (445:445:445)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT datab (381:381:381) (460:460:460)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~8) + (DELAY + (ABSOLUTE + (PORT datab (214:214:214) (270:270:270)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~10) + (DELAY + (ABSOLUTE + (PORT datab (366:366:366) (442:442:442)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (275:275:275)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (454:454:454)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT datab (162:162:162) (213:213:213)) + (PORT datad (139:139:139) (183:183:183)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[8\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (377:377:377)) + (PORT datab (336:336:336) (392:392:392)) + (PORT datad (128:128:128) (157:157:157)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[4\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (474:474:474) (551:551:551)) + (PORT datad (354:354:354) (415:415:415)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~8) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (512:512:512)) + (PORT datab (363:363:363) (428:428:428)) + (PORT datac (376:376:376) (445:445:445)) + (PORT datad (456:456:456) (524:524:524)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~15) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (383:383:383)) + (PORT datab (188:188:188) (225:225:225)) + (PORT datac (95:95:95) (119:119:119)) + (PORT datad (105:105:105) (128:128:128)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~17) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (170:170:170)) + (PORT datac (305:305:305) (361:361:361)) + (PORT datad (115:115:115) (138:138:138)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (358:358:358) (738:738:738)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1120:1120:1120) (1119:1119:1119)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE hsync\~output) + (DELAY + (ABSOLUTE + (PORT i (1064:1064:1064) (938:938:938)) + (IOPATH i o (1647:1647:1647) (1667:1667:1667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE vsync\~output) + (DELAY + (ABSOLUTE + (PORT i (913:913:913) (809:809:809)) + (IOPATH i o (1657:1657:1657) (1677:1677:1677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1225:1225:1225) (1372:1372:1372)) + (IOPATH i o (1667:1667:1667) (1647:1647:1647)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1200:1200:1200) (1338:1338:1338)) + (IOPATH i o (1677:1677:1677) (1657:1657:1657)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1318:1318:1318) (1471:1471:1471)) + (IOPATH i o (1677:1677:1677) (1657:1657:1657)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1443:1443:1443) (1614:1614:1614)) + (IOPATH i o (1812:1812:1812) (1785:1785:1785)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1444:1444:1444) (1617:1617:1617)) + (IOPATH i o (1792:1792:1792) (1765:1765:1765)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (636:636:636) (726:726:726)) + (IOPATH i o (1792:1792:1792) (1765:1765:1765)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (644:644:644) (734:734:734)) + (IOPATH i o (1792:1792:1792) (1765:1765:1765)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (865:865:865) (976:976:976)) + (IOPATH i o (1802:1802:1802) (1775:1775:1775)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (802:802:802) (910:910:910)) + (IOPATH i o (1762:1762:1762) (1735:1735:1735)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (792:792:792) (896:896:896)) + (IOPATH i o (1782:1782:1782) (1755:1755:1755)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (755:755:755) (852:852:852)) + (IOPATH i o (1772:1772:1772) (1745:1745:1745)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (748:748:748) (836:836:836)) + (IOPATH i o (1772:1772:1772) (1745:1745:1745)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (592:592:592) (654:654:654)) + (IOPATH i o (1782:1782:1782) (1755:1755:1755)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[13\]\~output) + (DELAY + (ABSOLUTE + (PORT i (586:586:586) (650:650:650)) + (IOPATH i o (1772:1772:1772) (1745:1745:1745)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[14\]\~output) + (DELAY + (ABSOLUTE + (PORT i (428:428:428) (469:469:469)) + (IOPATH i o (1782:1782:1782) (1755:1755:1755)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[15\]\~output) + (DELAY + (ABSOLUTE + (PORT i (438:438:438) (484:484:484)) + (IOPATH i o (1772:1772:1772) (1745:1745:1745)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT datab (146:146:146) (196:196:196)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (698:698:698)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (1411:1411:1411) (1239:1239:1239)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2263:2263:2263) (2046:2046:2046)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rst_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1116:1116:1116) (942:942:942)) + (PORT datab (130:130:130) (178:178:178)) + (PORT datac (1749:1749:1749) (1960:1960:1960)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~0clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (910:910:910) (1027:1027:1027)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (146:146:146) (198:198:198)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (146:146:146) (196:196:196)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (411:411:411)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datab (146:146:146) (195:195:195)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (167:167:167) (219:219:219)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datad (146:146:146) (190:190:190)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~1) + (DELAY + (ABSOLUTE + (PORT datab (312:312:312) (362:362:362)) + (PORT datac (93:93:93) (115:115:115)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~0) + (DELAY + (ABSOLUTE + (PORT datab (287:287:287) (330:330:330)) + (PORT datac (104:104:104) (125:125:125)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (247:247:247) (303:303:303)) + (PORT datab (160:160:160) (214:214:214)) + (PORT datac (322:322:322) (386:386:386)) + (PORT datad (134:134:134) (173:173:173)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (149:149:149) (202:202:202)) + (PORT datab (147:147:147) (197:197:197)) + (PORT datac (134:134:134) (177:177:177)) + (PORT datad (135:135:135) (175:175:175)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (404:404:404)) + (PORT datab (276:276:276) (321:321:321)) + (PORT datac (273:273:273) (312:312:312)) + (PORT datad (349:349:349) (419:419:419)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~2) + (DELAY + (ABSOLUTE + (PORT datab (106:106:106) (135:135:135)) + (PORT datac (298:298:298) (341:341:341)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan2\~0) + (DELAY + (ABSOLUTE + (PORT datab (161:161:161) (213:213:213)) + (PORT datad (139:139:139) (182:182:182)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (388:388:388)) + (PORT datab (342:342:342) (409:409:409)) + (PORT datac (286:286:286) (333:333:333)) + (PORT datad (133:133:133) (171:171:171)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (324:324:324) (381:381:381)) + (PORT datab (340:340:340) (397:397:397)) + (PORT datad (126:126:126) (150:150:150)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (397:397:397)) + (PORT datab (334:334:334) (390:390:390)) + (PORT datad (130:130:130) (158:158:158)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[4\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (424:424:424) (489:489:489)) + (PORT datab (333:333:333) (390:390:390)) + (PORT datad (131:131:131) (159:159:159)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (472:472:472)) + (PORT datab (146:146:146) (197:197:197)) + (PORT datac (132:132:132) (176:176:176)) + (PORT datad (133:133:133) (172:172:172)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (442:442:442) (510:510:510)) + (PORT datab (337:337:337) (394:394:394)) + (PORT datad (127:127:127) (152:152:152)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (158:158:158)) + (PORT datab (147:147:147) (198:198:198)) + (PORT datac (162:162:162) (191:191:191)) + (PORT datad (137:137:137) (178:178:178)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (414:414:414)) + (PORT datab (334:334:334) (390:390:390)) + (PORT datad (131:131:131) (159:159:159)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT datab (148:148:148) (198:198:198)) + (PORT datac (134:134:134) (177:177:177)) + (PORT datad (135:135:135) (174:174:174)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[5\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (392:392:392)) + (PORT datab (338:338:338) (394:394:394)) + (PORT datad (127:127:127) (151:151:151)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~14) + (DELAY + (ABSOLUTE + (PORT datab (214:214:214) (274:274:274)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[7\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (405:405:405)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datad (466:466:466) (539:539:539)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~18) + (DELAY + (ABSOLUTE + (PORT datad (138:138:138) (179:179:179)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[9\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (405:405:405)) + (PORT datab (106:106:106) (136:136:136)) + (PORT datad (467:467:467) (539:539:539)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[6\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (484:484:484) (562:562:562)) + (PORT datad (331:331:331) (379:379:379)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (192:192:192)) + (PORT datab (142:142:142) (190:190:190)) + (PORT datac (340:340:340) (408:408:408)) + (PORT datad (344:344:344) (418:418:418)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (143:143:143)) + (PORT datab (150:150:150) (201:201:201)) + (PORT datac (368:368:368) (448:448:448)) + (PORT datad (103:103:103) (127:127:127)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan6\~1) + (DELAY + (ABSOLUTE + (PORT datab (147:147:147) (198:198:198)) + (PORT datad (136:136:136) (177:177:177)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~1) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (454:454:454)) + (PORT datab (150:150:150) (201:201:201)) + (PORT datac (200:200:200) (253:253:253)) + (PORT datad (197:197:197) (250:250:250)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~2) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (140:140:140)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (253:253:253) (288:288:288)) + (PORT datad (107:107:107) (132:132:132)) + (IOPATH dataa combout (181:181:181) (175:175:175)) + (IOPATH datab combout (182:182:182) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan2\~1) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (408:408:408)) + (PORT datac (315:315:315) (377:377:377)) + (PORT datad (132:132:132) (170:170:170)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb_valid\~0) + (DELAY + (ABSOLUTE + (PORT dataa (274:274:274) (319:319:319)) + (PORT datab (366:366:366) (441:441:441)) + (PORT datac (285:285:285) (331:331:331)) + (PORT datad (99:99:99) (122:122:122)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (280:280:280)) + (PORT datab (312:312:312) (370:370:370)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (280:280:280)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~5) + (DELAY + (ABSOLUTE + (PORT dataa (212:212:212) (266:266:266)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~7) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (272:272:272)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~9) + (DELAY + (ABSOLUTE + (PORT dataa (320:320:320) (387:387:387)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~10) + (DELAY + (ABSOLUTE + (PORT datab (227:227:227) (282:282:282)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (385:385:385)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan14\~0) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (169:169:169)) + (PORT datad (115:115:115) (137:137:137)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~14) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (291:291:291)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~16) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (281:281:281)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (375:375:375)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (108:108:108) (132:132:132)) + (PORT datad (110:110:110) (130:130:130)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~0) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (158:158:158)) + (PORT datac (365:365:365) (444:444:444)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (336:336:336)) + (PORT datab (368:368:368) (444:444:444)) + (PORT datac (283:283:283) (329:329:329)) + (PORT datad (101:101:101) (124:124:124)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~3) + (DELAY + (ABSOLUTE + (PORT dataa (274:274:274) (319:319:319)) + (PORT datab (367:367:367) (443:443:443)) + (PORT datac (272:272:272) (311:311:311)) + (PORT datad (100:100:100) (123:123:123)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~4) + (DELAY + (ABSOLUTE + (PORT dataa (324:324:324) (385:385:385)) + (PORT datab (344:344:344) (409:409:409)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~4) + (DELAY + (ABSOLUTE + (PORT datab (476:476:476) (553:553:553)) + (PORT datad (334:334:334) (384:384:384)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~9) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (336:336:336) (394:394:394)) + (PORT datac (372:372:372) (441:441:441)) + (PORT datad (110:110:110) (131:131:131)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (409:409:409)) + (PORT datab (363:363:363) (427:427:427)) + (PORT datac (372:372:372) (442:442:442)) + (PORT datad (460:460:460) (529:529:529)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~6) + (DELAY + (ABSOLUTE + (PORT dataa (118:118:118) (156:156:156)) + (PORT datab (125:125:125) (157:157:157)) + (PORT datac (373:373:373) (443:443:443)) + (PORT datad (182:182:182) (213:213:213)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[4\]\~10) + (DELAY + (ABSOLUTE + (PORT datac (375:375:375) (445:445:445)) + (PORT datad (334:334:334) (383:383:383)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~11) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (384:384:384)) + (PORT datab (136:136:136) (171:171:171)) + (PORT datac (304:304:304) (352:352:352)) + (PORT datad (115:115:115) (138:138:138)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~12) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (157:157:157)) + (PORT datab (117:117:117) (145:145:145)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (312:312:312) (361:361:361)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~13) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (242:242:242)) + (PORT datab (109:109:109) (140:140:140)) + (PORT datac (114:114:114) (135:135:135)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (388:388:388)) + (PORT datab (134:134:134) (172:172:172)) + (PORT datac (329:329:329) (393:393:393)) + (PORT datad (330:330:330) (390:390:390)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[4\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (410:410:410)) + (PORT datab (390:390:390) (461:461:461)) + (PORT datac (433:433:433) (493:493:493)) + (PORT datad (462:462:462) (531:531:531)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~16) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (144:144:144)) + (PORT datab (127:127:127) (161:161:161)) + (PORT datac (95:95:95) (119:119:119)) + (PORT datad (185:185:185) (207:207:207)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (383:383:383)) + (PORT datab (342:342:342) (408:408:408)) + (PORT datac (117:117:117) (152:152:152)) + (PORT datad (347:347:347) (420:420:420)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~25) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (230:230:230)) + (PORT datab (189:189:189) (227:227:227)) + (PORT datac (103:103:103) (124:124:124)) + (PORT datad (319:319:319) (364:364:364)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[5\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (383:383:383)) + (PORT datab (341:341:341) (407:407:407)) + (PORT datac (118:118:118) (153:153:153)) + (PORT datad (119:119:119) (155:155:155)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~18) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (383:383:383)) + (PORT datab (135:135:135) (170:170:170)) + (PORT datac (299:299:299) (345:345:345)) + (PORT datad (115:115:115) (138:138:138)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~14) + (DELAY + (ABSOLUTE + (PORT datab (123:123:123) (153:153:153)) + (PORT datac (305:305:305) (353:353:353)) + (PORT datad (123:123:123) (147:147:147)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~26) + (DELAY + (ABSOLUTE + (PORT dataa (314:314:314) (368:368:368)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (106:106:106) (129:129:129)) + (PORT datad (106:106:106) (124:124:124)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~19) + (DELAY + (ABSOLUTE + (PORT datab (349:349:349) (413:413:413)) + (PORT datad (185:185:185) (206:206:206)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[7\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (385:385:385)) + (PORT datab (345:345:345) (411:411:411)) + (PORT datac (115:115:115) (151:151:151)) + (PORT datad (322:322:322) (388:388:388)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (194:194:194) (237:237:237)) + (PORT datab (373:373:373) (440:440:440)) + (PORT datad (461:461:461) (530:530:530)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~20) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (401:401:401)) + (PORT datac (330:330:330) (377:377:377)) + (PORT datad (345:345:345) (401:401:401)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~21) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (238:238:238)) + (PORT datab (347:347:347) (410:410:410)) + (PORT datac (175:175:175) (202:202:202)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[10\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (388:388:388)) + (PORT datab (350:350:350) (416:416:416)) + (PORT datac (116:116:116) (151:151:151)) + (PORT datad (354:354:354) (430:430:430)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~22) + (DELAY + (ABSOLUTE + (PORT dataa (119:119:119) (157:157:157)) + (PORT datab (335:335:335) (393:393:393)) + (PORT datac (375:375:375) (445:445:445)) + (PORT datad (113:113:113) (135:135:135)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~23) + (DELAY + (ABSOLUTE + (PORT dataa (123:123:123) (157:157:157)) + (PORT datab (106:106:106) (136:136:136)) + (PORT datac (165:165:165) (194:194:194)) + (PORT datad (116:116:116) (140:140:140)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[11\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (324:324:324) (385:385:385)) + (PORT datab (351:351:351) (431:431:431)) + (PORT datac (116:116:116) (152:152:152)) + (PORT datad (324:324:324) (383:383:383)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~24) + (DELAY + (ABSOLUTE + (PORT dataa (111:111:111) (145:145:145)) + (PORT datab (130:130:130) (163:163:163)) + (PORT datac (165:165:165) (194:194:194)) + (PORT datad (111:111:111) (132:132:132)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[12\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (388:388:388)) + (PORT datab (311:311:311) (371:371:371)) + (PORT datac (116:116:116) (150:150:150)) + (PORT datad (329:329:329) (388:388:388)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) +) diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_modelsim.xrf b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_modelsim.xrf new file mode 100644 index 0000000..b3b9b6c --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_modelsim.xrf @@ -0,0 +1,166 @@ +vendor_name = ModelSim +source_file = 1, E:/simiao/lc/A415/09_vga/vga/sim/tb_vga_ctrl.v +source_file = 1, E:/simiao/lc/A415/09_vga/vga/sim/tb_vga_colorbar.v +source_file = 1, E:/simiao/lc/A415/09_vga/vga/rtl/vga_pic.v +source_file = 1, E:/simiao/lc/A415/09_vga/vga/rtl/vga_ctrl.v +source_file = 1, E:/simiao/lc/A415/09_vga/vga/rtl/vga_colorbar.v +source_file = 1, E:/simiao/lc/A415/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen.qip +source_file = 1, E:/simiao/lc/A415/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen.v +source_file = 1, E:/simiao/lc/A415/09_vga/vga/quartus_prj/db/vga_colorbar.cbx.xml +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/altpll.tdf +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/aglobal130.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/stratix_pll.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/stratixii_pll.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/cycloneii_pll.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/cbx.lst +source_file = 1, E:/simiao/lc/A415/09_vga/vga/quartus_prj/db/clk_gen_altpll.v +design_name = vga_colorbar +instance = comp, \vga_ctrl_inst|Add0~4 , vga_ctrl_inst|Add0~4, vga_colorbar, 1 +instance = comp, \clk_gen_inst|altpll_component|auto_generated|pll1 , clk_gen_inst|altpll_component|auto_generated|pll1, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~0 , vga_ctrl_inst|Add1~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~2 , vga_ctrl_inst|Add1~2, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~4 , vga_ctrl_inst|Add1~4, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~6 , vga_ctrl_inst|Add1~6, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~8 , vga_ctrl_inst|Add1~8, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~10 , vga_ctrl_inst|Add1~10, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~12 , vga_ctrl_inst|Add1~12, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~16 , vga_ctrl_inst|Add1~16, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[8] , vga_ctrl_inst|cnt_v[8], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Equal0~0 , vga_ctrl_inst|Equal0~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[2] , vga_ctrl_inst|cnt_h[2], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[8]~3 , vga_ctrl_inst|cnt_v[8]~3, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[4]~5 , vga_pic_inst|pix_data[4]~5, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~8 , vga_pic_inst|pix_data~8, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~15 , vga_pic_inst|pix_data~15, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~17 , vga_pic_inst|pix_data~17, vga_colorbar, 1 +instance = comp, \sys_clk~input , sys_clk~input, vga_colorbar, 1 +instance = comp, \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl , clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl, vga_colorbar, 1 +instance = comp, \hsync~output , hsync~output, vga_colorbar, 1 +instance = comp, \vsync~output , vsync~output, vga_colorbar, 1 +instance = comp, \rgb[0]~output , rgb[0]~output, vga_colorbar, 1 +instance = comp, \rgb[1]~output , rgb[1]~output, vga_colorbar, 1 +instance = comp, \rgb[2]~output , rgb[2]~output, vga_colorbar, 1 +instance = comp, \rgb[3]~output , rgb[3]~output, vga_colorbar, 1 +instance = comp, \rgb[4]~output , rgb[4]~output, vga_colorbar, 1 +instance = comp, \rgb[5]~output , rgb[5]~output, vga_colorbar, 1 +instance = comp, \rgb[6]~output , rgb[6]~output, vga_colorbar, 1 +instance = comp, \rgb[7]~output , rgb[7]~output, vga_colorbar, 1 +instance = comp, \rgb[8]~output , rgb[8]~output, vga_colorbar, 1 +instance = comp, \rgb[9]~output , rgb[9]~output, vga_colorbar, 1 +instance = comp, \rgb[10]~output , rgb[10]~output, vga_colorbar, 1 +instance = comp, \rgb[11]~output , rgb[11]~output, vga_colorbar, 1 +instance = comp, \rgb[12]~output , rgb[12]~output, vga_colorbar, 1 +instance = comp, \rgb[13]~output , rgb[13]~output, vga_colorbar, 1 +instance = comp, \rgb[14]~output , rgb[14]~output, vga_colorbar, 1 +instance = comp, \rgb[15]~output , rgb[15]~output, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~0 , vga_ctrl_inst|Add0~0, vga_colorbar, 1 +instance = comp, \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder , clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder, vga_colorbar, 1 +instance = comp, \sys_rst_n~input , sys_rst_n~input, vga_colorbar, 1 +instance = comp, \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync , clk_gen_inst|altpll_component|auto_generated|pll_lock_sync, vga_colorbar, 1 +instance = comp, \rst_n~0 , rst_n~0, vga_colorbar, 1 +instance = comp, \rst_n~0clkctrl , rst_n~0clkctrl, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[0] , vga_ctrl_inst|cnt_h[0], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~2 , vga_ctrl_inst|Add0~2, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~6 , vga_ctrl_inst|Add0~6, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[3] , vga_ctrl_inst|cnt_h[3], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~8 , vga_ctrl_inst|Add0~8, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[4] , vga_ctrl_inst|cnt_h[4], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~10 , vga_ctrl_inst|Add0~10, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~12 , vga_ctrl_inst|Add0~12, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[6] , vga_ctrl_inst|cnt_h[6], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~14 , vga_ctrl_inst|Add0~14, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[7] , vga_ctrl_inst|cnt_h[7], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~16 , vga_ctrl_inst|Add0~16, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~18 , vga_ctrl_inst|Add0~18, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h~1 , vga_ctrl_inst|cnt_h~1, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[9] , vga_ctrl_inst|cnt_h[9], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h~0 , vga_ctrl_inst|cnt_h~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[5] , vga_ctrl_inst|cnt_h[5], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Equal0~2 , vga_ctrl_inst|Equal0~2, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[1] , vga_ctrl_inst|cnt_h[1], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Equal0~1 , vga_ctrl_inst|Equal0~1, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Equal0~3 , vga_ctrl_inst|Equal0~3, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h~2 , vga_ctrl_inst|cnt_h~2, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[8] , vga_ctrl_inst|cnt_h[8], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|LessThan2~0 , vga_ctrl_inst|LessThan2~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|LessThan0~0 , vga_ctrl_inst|LessThan0~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[0]~9 , vga_ctrl_inst|cnt_v[0]~9, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[0] , vga_ctrl_inst|cnt_v[0], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[2]~8 , vga_ctrl_inst|cnt_v[2]~8, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[2] , vga_ctrl_inst|cnt_v[2], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[4]~6 , vga_ctrl_inst|cnt_v[4]~6, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[4] , vga_ctrl_inst|cnt_v[4], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|always1~1 , vga_ctrl_inst|always1~1, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[1]~0 , vga_ctrl_inst|cnt_v[1]~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[1] , vga_ctrl_inst|cnt_v[1], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|always1~2 , vga_ctrl_inst|always1~2, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[3]~7 , vga_ctrl_inst|cnt_v[3]~7, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[3] , vga_ctrl_inst|cnt_v[3], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|LessThan6~0 , vga_ctrl_inst|LessThan6~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[5]~2 , vga_ctrl_inst|cnt_v[5]~2, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[5] , vga_ctrl_inst|cnt_v[5], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~14 , vga_ctrl_inst|Add1~14, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[7]~4 , vga_ctrl_inst|cnt_v[7]~4, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[7] , vga_ctrl_inst|cnt_v[7], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~18 , vga_ctrl_inst|Add1~18, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[9]~1 , vga_ctrl_inst|cnt_v[9]~1, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[9] , vga_ctrl_inst|cnt_v[9], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[6]~5 , vga_ctrl_inst|cnt_v[6]~5, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[6] , vga_ctrl_inst|cnt_v[6], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|always1~0 , vga_ctrl_inst|always1~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|LessThan1~0 , vga_ctrl_inst|LessThan1~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|LessThan6~1 , vga_ctrl_inst|LessThan6~1, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|pix_data_req~1 , vga_ctrl_inst|pix_data_req~1, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|pix_data_req~2 , vga_ctrl_inst|pix_data_req~2, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|LessThan2~1 , vga_ctrl_inst|LessThan2~1, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|rgb_valid~0 , vga_ctrl_inst|rgb_valid~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~1 , vga_ctrl_inst|Add2~1, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~3 , vga_ctrl_inst|Add2~3, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~5 , vga_ctrl_inst|Add2~5, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~7 , vga_ctrl_inst|Add2~7, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~9 , vga_ctrl_inst|Add2~9, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~10 , vga_ctrl_inst|Add2~10, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~12 , vga_ctrl_inst|Add2~12, vga_colorbar, 1 +instance = comp, \vga_pic_inst|LessThan14~0 , vga_pic_inst|LessThan14~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~14 , vga_ctrl_inst|Add2~14, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~16 , vga_ctrl_inst|Add2~16, vga_colorbar, 1 +instance = comp, \vga_pic_inst|LessThan6~0 , vga_pic_inst|LessThan6~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|pix_data_req~0 , vga_ctrl_inst|pix_data_req~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|LessThan4~0 , vga_ctrl_inst|LessThan4~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|pix_data_req~3 , vga_ctrl_inst|pix_data_req~3, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|pix_data_req~4 , vga_ctrl_inst|pix_data_req~4, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~4 , vga_pic_inst|pix_data~4, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~9 , vga_pic_inst|pix_data~9, vga_colorbar, 1 +instance = comp, \vga_pic_inst|LessThan17~0 , vga_pic_inst|LessThan17~0, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~6 , vga_pic_inst|pix_data~6, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[4]~10 , vga_pic_inst|pix_data[4]~10, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~11 , vga_pic_inst|pix_data~11, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~12 , vga_pic_inst|pix_data~12, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~13 , vga_pic_inst|pix_data~13, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[0] , vga_pic_inst|pix_data[0], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|rgb[0]~0 , vga_ctrl_inst|rgb[0]~0, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[4]~7 , vga_pic_inst|pix_data[4]~7, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~16 , vga_pic_inst|pix_data~16, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[4] , vga_pic_inst|pix_data[4], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|rgb[1]~1 , vga_ctrl_inst|rgb[1]~1, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~25 , vga_pic_inst|pix_data~25, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[8] , vga_pic_inst|pix_data[8], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|rgb[5]~2 , vga_ctrl_inst|rgb[5]~2, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~18 , vga_pic_inst|pix_data~18, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~14 , vga_pic_inst|pix_data~14, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~26 , vga_pic_inst|pix_data~26, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~19 , vga_pic_inst|pix_data~19, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[9] , vga_pic_inst|pix_data[9], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|rgb[7]~3 , vga_ctrl_inst|rgb[7]~3, vga_colorbar, 1 +instance = comp, \vga_pic_inst|LessThan2~2 , vga_pic_inst|LessThan2~2, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~20 , vga_pic_inst|pix_data~20, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~21 , vga_pic_inst|pix_data~21, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[10] , vga_pic_inst|pix_data[10], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|rgb[10]~4 , vga_ctrl_inst|rgb[10]~4, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~22 , vga_pic_inst|pix_data~22, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~23 , vga_pic_inst|pix_data~23, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[13] , vga_pic_inst|pix_data[13], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|rgb[11]~5 , vga_ctrl_inst|rgb[11]~5, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~24 , vga_pic_inst|pix_data~24, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[15] , vga_pic_inst|pix_data[15], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|rgb[12]~6 , vga_ctrl_inst|rgb[12]~6, vga_colorbar, 1 diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_v.sdo b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_v.sdo new file mode 100644 index 0000000..3c460d1 --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_v.sdo @@ -0,0 +1,2108 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE15F23C8, +// with speed grade 8, core voltage 1.2V, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "vga_colorbar") + (DATE "06/02/2023 04:42:20") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (460:460:460)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (4503:4503:4503) (4503:4503:4503)) + (PORT inclk[0] (2340:2340:2340) (2340:2340:2340)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (960:960:960) (961:961:961)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (971:971:971) (950:950:950)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (973:973:973) (953:953:953)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT datab (1006:1006:1006) (978:978:978)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~8) + (DELAY + (ABSOLUTE + (PORT datab (569:569:569) (599:599:599)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~10) + (DELAY + (ABSOLUTE + (PORT datab (960:960:960) (939:939:939)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (603:603:603)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (962:962:962)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT datab (397:397:397) (486:486:486)) + (PORT datad (343:343:343) (426:426:426)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[8\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (788:788:788)) + (PORT datab (858:858:858) (836:836:836)) + (PORT datad (316:316:316) (356:356:356)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[4\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (1230:1230:1230) (1146:1146:1146)) + (PORT datad (924:924:924) (874:874:874)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1160:1160:1160) (1082:1082:1082)) + (PORT datab (967:967:967) (899:899:899)) + (PORT datac (937:937:937) (910:910:910)) + (PORT datad (1184:1184:1184) (1098:1098:1098)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~15) + (DELAY + (ABSOLUTE + (PORT dataa (841:841:841) (803:803:803)) + (PORT datab (509:509:509) (494:494:494)) + (PORT datac (245:245:245) (275:275:275)) + (PORT datad (262:262:262) (300:300:300)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~17) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (383:383:383)) + (PORT datac (842:842:842) (776:776:776)) + (PORT datad (291:291:291) (318:318:318)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (806:806:806) (852:852:852)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2339:2339:2339) (2308:2308:2308)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE hsync\~output) + (DELAY + (ABSOLUTE + (PORT i (2108:2108:2108) (2266:2266:2266)) + (IOPATH i o (3174:3174:3174) (3271:3271:3271)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE vsync\~output) + (DELAY + (ABSOLUTE + (PORT i (1864:1864:1864) (2034:2034:2034)) + (IOPATH i o (3184:3184:3184) (3281:3281:3281)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2928:2928:2928) (2696:2696:2696)) + (IOPATH i o (3271:3271:3271) (3174:3174:3174)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2872:2872:2872) (2631:2631:2631)) + (IOPATH i o (3281:3281:3281) (3184:3184:3184)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3183:3183:3183) (2900:2900:2900)) + (IOPATH i o (3281:3281:3281) (3184:3184:3184)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3530:3530:3530) (3206:3206:3206)) + (IOPATH i o (3429:3429:3429) (3366:3366:3366)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3524:3524:3524) (3201:3201:3201)) + (IOPATH i o (3409:3409:3409) (3346:3346:3346)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1540:1540:1540) (1460:1460:1460)) + (IOPATH i o (3409:3409:3409) (3346:3346:3346)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1581:1581:1581) (1475:1475:1475)) + (IOPATH i o (3409:3409:3409) (3346:3346:3346)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2139:2139:2139) (1969:1969:1969)) + (IOPATH i o (3419:3419:3419) (3356:3356:3356)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1953:1953:1953) (1815:1815:1815)) + (IOPATH i o (3379:3379:3379) (3316:3316:3316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1947:1947:1947) (1781:1781:1781)) + (IOPATH i o (3399:3399:3399) (3336:3336:3336)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1885:1885:1885) (1698:1698:1698)) + (IOPATH i o (3389:3389:3389) (3326:3326:3326)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1851:1851:1851) (1680:1680:1680)) + (IOPATH i o (3389:3389:3389) (3326:3326:3326)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1486:1486:1486) (1329:1329:1329)) + (IOPATH i o (3399:3399:3399) (3336:3336:3336)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[13\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1506:1506:1506) (1334:1334:1334)) + (IOPATH i o (3389:3389:3389) (3326:3326:3326)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[14\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1091:1091:1091) (970:970:970)) + (IOPATH i o (3399:3399:3399) (3336:3336:3336)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[15\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1123:1123:1123) (999:999:999)) + (IOPATH i o (3389:3389:3389) (3326:3326:3326)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT datab (366:366:366) (447:447:447)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (2921:2921:2921) (2960:2960:2960)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (4667:4667:4667) (4459:4459:4459)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rst_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2254:2254:2254) (2277:2277:2277)) + (PORT datab (332:332:332) (408:408:408)) + (PORT datac (3743:3743:3743) (3918:3918:3918)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~0clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2220:2220:2220) (2115:2115:2115)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (456:456:456)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (450:450:450)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (917:917:917) (889:889:889)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datab (369:369:369) (448:448:448)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (402:402:402) (492:492:492)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datad (350:350:350) (435:435:435)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~1) + (DELAY + (ABSOLUTE + (PORT datab (848:848:848) (777:777:777)) + (PORT datac (240:240:240) (266:266:266)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~0) + (DELAY + (ABSOLUTE + (PORT datab (789:789:789) (706:706:706)) + (PORT datac (265:265:265) (291:291:291)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1878:1878:1878) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (668:668:668)) + (PORT datab (390:390:390) (477:477:477)) + (PORT datac (853:853:853) (839:839:839)) + (PORT datad (328:328:328) (405:405:405)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (461:461:461)) + (PORT datab (368:368:368) (451:451:451)) + (PORT datac (327:327:327) (412:412:412)) + (PORT datad (329:329:329) (405:405:405)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (876:876:876)) + (PORT datab (741:741:741) (680:680:680)) + (PORT datac (724:724:724) (663:663:663)) + (PORT datad (917:917:917) (899:899:899)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~2) + (DELAY + (ABSOLUTE + (PORT datab (279:279:279) (305:305:305)) + (PORT datac (806:806:806) (740:740:740)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan2\~0) + (DELAY + (ABSOLUTE + (PORT datab (396:396:396) (485:485:485)) + (PORT datad (342:342:342) (425:425:425)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (841:841:841)) + (PORT datab (933:933:933) (885:885:885)) + (PORT datac (767:767:767) (704:704:704)) + (PORT datad (328:328:328) (401:401:401)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (802:802:802)) + (PORT datab (862:862:862) (841:841:841)) + (PORT datad (313:313:313) (352:352:352)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (832:832:832)) + (PORT datab (857:857:857) (834:834:834)) + (PORT datad (317:317:317) (358:358:358)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[4\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1110:1110:1110) (1019:1019:1019)) + (PORT datab (856:856:856) (834:834:834)) + (PORT datad (318:318:318) (359:359:359)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1021:1021:1021) (997:997:997)) + (PORT datab (366:366:366) (449:449:449)) + (PORT datac (326:326:326) (408:408:408)) + (PORT datad (327:327:327) (401:401:401)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1194:1194:1194) (1079:1079:1079)) + (PORT datab (860:860:860) (838:838:838)) + (PORT datad (315:315:315) (355:355:355)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (307:307:307) (351:351:351)) + (PORT datab (367:367:367) (450:450:450)) + (PORT datac (450:450:450) (427:427:427)) + (PORT datad (337:337:337) (417:417:417)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (877:877:877)) + (PORT datab (856:856:856) (834:834:834)) + (PORT datad (318:318:318) (358:358:358)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (450:450:450)) + (PORT datac (327:327:327) (409:409:409)) + (PORT datad (329:329:329) (402:402:402)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[5\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (829:829:829)) + (PORT datab (860:860:860) (839:839:839)) + (PORT datad (315:315:315) (354:354:354)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~14) + (DELAY + (ABSOLUTE + (PORT datab (569:569:569) (597:597:597)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[7\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (846:846:846)) + (PORT datab (279:279:279) (305:305:305)) + (PORT datad (1206:1206:1206) (1115:1115:1115)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1878:1878:1878) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~18) + (DELAY + (ABSOLUTE + (PORT datad (333:333:333) (411:411:411)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[9\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (846:846:846)) + (PORT datab (280:280:280) (306:306:306)) + (PORT datad (1207:1207:1207) (1116:1116:1116)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1878:1878:1878) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[6\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (314:314:314)) + (PORT datab (1265:1265:1265) (1163:1163:1163)) + (PORT datad (838:838:838) (794:794:794)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1878:1878:1878) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (443:443:443)) + (PORT datab (359:359:359) (435:435:435)) + (PORT datac (872:872:872) (866:866:866)) + (PORT datad (893:893:893) (890:890:890)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (326:326:326)) + (PORT datab (377:377:377) (459:459:459)) + (PORT datac (959:959:959) (948:948:948)) + (PORT datad (261:261:261) (296:296:296)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan6\~1) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (449:449:449)) + (PORT datad (336:336:336) (416:416:416)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~1) + (DELAY + (ABSOLUTE + (PORT dataa (957:957:957) (961:961:961)) + (PORT datab (371:371:371) (451:451:451)) + (PORT datac (528:528:528) (560:560:560)) + (PORT datad (517:517:517) (552:552:552)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~2) + (DELAY + (ABSOLUTE + (PORT dataa (285:285:285) (323:323:323)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (698:698:698) (629:629:629)) + (PORT datad (265:265:265) (300:300:300)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan2\~1) + (DELAY + (ABSOLUTE + (PORT datab (930:930:930) (883:883:883)) + (PORT datac (848:848:848) (826:826:826)) + (PORT datad (326:326:326) (400:400:400)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb_valid\~0) + (DELAY + (ABSOLUTE + (PORT dataa (735:735:735) (684:684:684)) + (PORT datab (974:974:974) (944:944:944)) + (PORT datac (765:765:765) (703:703:703)) + (PORT datad (254:254:254) (280:280:280)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (455:455:455) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (628:628:628)) + (PORT datab (837:837:837) (806:806:806)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (628:628:628)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~5) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (597:597:597)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~7) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (607:607:607)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~9) + (DELAY + (ABSOLUTE + (PORT dataa (853:853:853) (839:839:839)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~10) + (DELAY + (ABSOLUTE + (PORT datab (620:620:620) (627:627:627)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (855:855:855) (837:837:837)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan14\~0) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (383:383:383)) + (PORT datad (291:291:291) (318:318:318)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~14) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (650:650:650)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~16) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (628:628:628)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (801:801:801)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (273:273:273) (303:303:303)) + (PORT datad (274:274:274) (299:299:299)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~0) + (DELAY + (ABSOLUTE + (PORT dataa (306:306:306) (351:351:351)) + (PORT datac (955:955:955) (943:943:943)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (767:767:767) (710:710:710)) + (PORT datab (976:976:976) (946:946:946)) + (PORT datac (764:764:764) (701:701:701)) + (PORT datad (257:257:257) (283:283:283)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~3) + (DELAY + (ABSOLUTE + (PORT dataa (736:736:736) (684:684:684)) + (PORT datab (976:976:976) (946:946:946)) + (PORT datac (723:723:723) (662:662:662)) + (PORT datad (256:256:256) (281:281:281)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~4) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (812:812:812)) + (PORT datab (918:918:918) (854:854:854)) + (PORT datac (237:237:237) (264:264:264)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~4) + (DELAY + (ABSOLUTE + (PORT datab (1232:1232:1232) (1148:1148:1148)) + (PORT datad (847:847:847) (804:804:804)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~9) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (313:313:313)) + (PORT datab (888:888:888) (823:823:823)) + (PORT datac (934:934:934) (907:907:907)) + (PORT datad (279:279:279) (305:305:305)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (855:855:855)) + (PORT datab (966:966:966) (898:898:898)) + (PORT datac (934:934:934) (907:907:907)) + (PORT datad (1188:1188:1188) (1104:1104:1104)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~6) + (DELAY + (ABSOLUTE + (PORT dataa (304:304:304) (351:351:351)) + (PORT datab (320:320:320) (350:350:350)) + (PORT datac (935:935:935) (908:908:908)) + (PORT datad (487:487:487) (468:468:468)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[4\]\~10) + (DELAY + (ABSOLUTE + (PORT datac (936:936:936) (910:910:910)) + (PORT datad (846:846:846) (803:803:803)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~11) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (824:824:824)) + (PORT datab (338:338:338) (384:384:384)) + (PORT datac (795:795:795) (753:753:753)) + (PORT datad (291:291:291) (318:318:318)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~12) + (DELAY + (ABSOLUTE + (PORT dataa (305:305:305) (353:353:353)) + (PORT datab (304:304:304) (329:329:329)) + (PORT datac (243:243:243) (274:274:274)) + (PORT datad (802:802:802) (754:754:754)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~13) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (537:537:537)) + (PORT datab (285:285:285) (315:315:315)) + (PORT datac (288:288:288) (315:315:315)) + (PORT datad (245:245:245) (270:270:270)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (815:815:815)) + (PORT datab (327:327:327) (381:381:381)) + (PORT datac (852:852:852) (839:839:839)) + (PORT datad (863:863:863) (814:814:814)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[4\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (856:856:856)) + (PORT datab (988:988:988) (944:944:944)) + (PORT datac (1120:1120:1120) (1040:1040:1040)) + (PORT datad (1190:1190:1190) (1106:1106:1106)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~16) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (326:326:326)) + (PORT datab (322:322:322) (356:356:356)) + (PORT datac (245:245:245) (278:278:278)) + (PORT datad (501:501:501) (465:465:465)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (810:810:810)) + (PORT datab (917:917:917) (852:852:852)) + (PORT datac (284:284:284) (343:343:343)) + (PORT datad (912:912:912) (892:892:892)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~25) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (510:510:510)) + (PORT datab (511:511:511) (499:499:499)) + (PORT datac (263:263:263) (289:289:289)) + (PORT datad (817:817:817) (766:766:766)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (455:455:455) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1878:1878:1878) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[5\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (810:810:810)) + (PORT datab (916:916:916) (852:852:852)) + (PORT datac (284:284:284) (343:343:343)) + (PORT datad (295:295:295) (365:365:365)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~18) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (824:824:824)) + (PORT datab (336:336:336) (382:382:382)) + (PORT datac (790:790:790) (746:746:746)) + (PORT datad (291:291:291) (318:318:318)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~14) + (DELAY + (ABSOLUTE + (PORT datab (314:314:314) (342:342:342)) + (PORT datac (796:796:796) (754:754:754)) + (PORT datad (299:299:299) (343:343:343)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~26) + (DELAY + (ABSOLUTE + (PORT dataa (833:833:833) (794:794:794)) + (PORT datab (275:275:275) (299:299:299)) + (PORT datac (270:270:270) (300:300:300)) + (PORT datad (267:267:267) (285:285:285)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~19) + (DELAY + (ABSOLUTE + (PORT datab (930:930:930) (864:864:864)) + (PORT datad (500:500:500) (460:460:460)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[7\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (836:836:836) (812:812:812)) + (PORT datab (919:919:919) (856:856:856)) + (PORT datac (284:284:284) (343:343:343)) + (PORT datad (829:829:829) (827:827:827)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (527:527:527) (519:519:519)) + (PORT datab (984:984:984) (924:924:924)) + (PORT datad (1189:1189:1189) (1104:1104:1104)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~20) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (843:843:843)) + (PORT datac (849:849:849) (795:795:795)) + (PORT datad (908:908:908) (849:849:849)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~21) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (524:524:524)) + (PORT datab (928:928:928) (861:861:861)) + (PORT datac (475:475:475) (447:447:447)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[10\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (815:815:815)) + (PORT datab (924:924:924) (861:861:861)) + (PORT datac (283:283:283) (342:342:342)) + (PORT datad (931:931:931) (915:915:915)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~22) + (DELAY + (ABSOLUTE + (PORT dataa (305:305:305) (353:353:353)) + (PORT datab (886:886:886) (822:822:822)) + (PORT datac (936:936:936) (910:910:910)) + (PORT datad (282:282:282) (309:309:309)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~23) + (DELAY + (ABSOLUTE + (PORT dataa (317:317:317) (352:352:352)) + (PORT datab (283:283:283) (311:311:311)) + (PORT datac (455:455:455) (430:430:430)) + (PORT datad (285:285:285) (317:317:317)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[11\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (811:811:811)) + (PORT datab (918:918:918) (911:911:911)) + (PORT datac (284:284:284) (343:343:343)) + (PORT datad (857:857:857) (807:807:807)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~24) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (328:328:328)) + (PORT datab (325:325:325) (360:360:360)) + (PORT datac (455:455:455) (430:430:430)) + (PORT datad (276:276:276) (301:301:301)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[12\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (814:814:814)) + (PORT datab (844:844:844) (810:810:810)) + (PORT datac (283:283:283) (342:342:342)) + (PORT datad (862:862:862) (812:812:812)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) +) diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/vga_colorbar.qpf b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/vga_colorbar.qpf new file mode 100644 index 0000000..3e567ad --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/vga_colorbar.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +# Date created = 13:49:09 February 27, 2020 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "13:49:09 February 27, 2020" + +# Revisions + +PROJECT_REVISION = "vga_colorbar" diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/vga_colorbar.qsf b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/vga_colorbar.qsf new file mode 100644 index 0000000..d74cf77 --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/vga_colorbar.qsf @@ -0,0 +1,99 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +# Date created = 13:49:09 February 27, 2020 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# vga_colorbar_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE15F23C8 +set_global_assignment -name TOP_LEVEL_ENTITY vga_colorbar +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:49:09 FEBRUARY 27, 2020" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation +set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb_vga_ctrl -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_NAME tb_vga_colorbar -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb_vga_colorbar +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 us" -section_id tb_vga_colorbar +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_vga_colorbar -section_id tb_vga_colorbar +set_global_assignment -name EDA_TEST_BENCH_NAME tb_vga_ctrl -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb_vga_ctrl +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 us" -section_id tb_vga_ctrl +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_vga_ctrl -section_id tb_vga_ctrl +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + +set_location_assignment PIN_T22 -to sys_clk +set_location_assignment PIN_U20 -to sys_rst_n +set_location_assignment PIN_AB17 -to vsync +set_location_assignment PIN_AA18 -to hsync +set_location_assignment PIN_J21 -to rgb[15] +set_location_assignment PIN_K21 -to rgb[14] +set_location_assignment PIN_L22 -to rgb[13] +set_location_assignment PIN_L21 -to rgb[12] +set_location_assignment PIN_M22 -to rgb[11] +set_location_assignment PIN_M21 -to rgb[10] +set_location_assignment PIN_N21 -to rgb[9] +set_location_assignment PIN_N20 -to rgb[8] +set_location_assignment PIN_U22 -to rgb[7] +set_location_assignment PIN_U21 -to rgb[6] +set_location_assignment PIN_W20 -to rgb[5] +set_location_assignment PIN_W19 -to rgb[4] +set_location_assignment PIN_Y21 -to rgb[3] +set_location_assignment PIN_AB19 -to rgb[2] +set_location_assignment PIN_AA19 -to rgb[1] +set_location_assignment PIN_AB18 -to rgb[0] + + +set_global_assignment -name VERILOG_FILE ../sim/tb_vga_ctrl.v +set_global_assignment -name VERILOG_FILE ../sim/tb_vga_colorbar.v +set_global_assignment -name VERILOG_FILE ../rtl/vga_pic.v +set_global_assignment -name VERILOG_FILE ../rtl/vga_ctrl.v +set_global_assignment -name VERILOG_FILE ../rtl/vga_colorbar.v +set_global_assignment -name QIP_FILE ip_core/clk_gen/clk_gen.qip +set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/tb_vga_colorbar.v -section_id tb_vga_colorbar +set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/tb_vga_ctrl.v -section_id tb_vga_ctrl +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/vga_colorbar.qws b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/vga_colorbar.qws new file mode 100644 index 0000000..27fd4ea Binary files /dev/null and b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/vga_colorbar.qws differ diff --git a/smh-ac415-fpga/examples/09_vga/vga/rtl/vga_colorbar.v b/smh-ac415-fpga/examples/09_vga/vga/rtl/vga_colorbar.v new file mode 100644 index 0000000..6b5f4dc --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/rtl/vga_colorbar.v @@ -0,0 +1,84 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/03/12 +// Module Name : vga_colorbar +// Project Name : vga_colorbar +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : vga_colorbar顶层模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module vga_colorbar +( + input wire sys_clk , //输入工作时钟,频率50MHz + input wire sys_rst_n , //输入复位信号,低电平有效 + + output wire hsync , //输出行同步信号 + output wire vsync , //输出场同步信号 + output wire [15:0] rgb //输出像素信息 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//wire define +wire vga_clk ; //VGA工作时钟,频率25MHz +wire locked ; //PLL locked信号 +wire rst_n ; //VGA模块复位信号 +wire [9:0] pix_x ; //VGA有效显示区域X轴坐标 +wire [9:0] pix_y ; //VGA有效显示区域Y轴坐标 +wire [15:0] pix_data; //VGA像素点色彩信息 + +//rst_n:VGA模块复位信号 +assign rst_n = (sys_rst_n & locked); + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// + +//------------- clk_gen_inst ------------- +clk_gen clk_gen_inst +( + .areset (~sys_rst_n ), //输入复位信号,高电平有效,1bit + .inclk0 (sys_clk ), //输入50MHz晶振时钟,1bit + + .c0 (vga_clk ), //输出VGA工作时钟,频率25Mhz,1bit + .locked (locked ) //输出pll locked信号,1bit +); + +//------------- vga_ctrl_inst ------------- +vga_ctrl vga_ctrl_inst +( + .vga_clk (vga_clk ), //输入工作时钟,频率25MHz,1bit + .sys_rst_n (rst_n ), //输入复位信号,低电平有效,1bit + .pix_data (pix_data ), //输入像素点色彩信息,16bit + + .pix_x (pix_x ), //输出VGA有效显示区域像素点X轴坐标,10bit + .pix_y (pix_y ), //输出VGA有效显示区域像素点Y轴坐标,10bit + .hsync (hsync ), //输出行同步信号,1bit + .vsync (vsync ), //输出场同步信号,1bit + .rgb (rgb ) //输出像素点色彩信息,16bit +); + +//------------- vga_pic_inst ------------- +vga_pic vga_pic_inst +( + .vga_clk (vga_clk ), //输入工作时钟,频率25MHz,1bit + .sys_rst_n (rst_n ), //输入复位信号,低电平有效,1bit + .pix_x (pix_x ), //输入VGA有效显示区域像素点X轴坐标,10bit + .pix_y (pix_y ), //输入VGA有效显示区域像素点Y轴坐标,10bit + + .pix_data (pix_data ) //输出像素点色彩信息,16bit + +); + +endmodule diff --git a/smh-ac415-fpga/examples/09_vga/vga/rtl/vga_ctrl.v b/smh-ac415-fpga/examples/09_vga/vga/rtl/vga_ctrl.v new file mode 100644 index 0000000..c00ab5c --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/rtl/vga_ctrl.v @@ -0,0 +1,113 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/03/12 +// Module Name : vga_ctrl +// Project Name : vga_colorbar +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : VGA控制模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module vga_ctrl +( + input wire vga_clk , //输入工作时钟,频率25MHz + input wire sys_rst_n , //输入复位信号,低电平有效 + input wire [15:0] pix_data , //输入像素点色彩信息 + + output wire [9:0] pix_x , //输出VGA有效显示区域像素点X轴坐标 + output wire [9:0] pix_y , //输出VGA有效显示区域像素点Y轴坐标 + output wire hsync , //输出行同步信号 + output wire vsync , //输出场同步信号 + output wire [15:0] rgb //输出像素点色彩信息 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//parameter define +parameter H_SYNC = 10'd96 , //行同步 + H_BACK = 10'd40 , //行时序后沿 + H_LEFT = 10'd8 , //行时序左边框 + H_VALID = 10'd640 , //行有效数据 + H_RIGHT = 10'd8 , //行时序右边框 + H_FRONT = 10'd8 , //行时序前沿 + H_TOTAL = 10'd800 ; //行扫描周期 +parameter V_SYNC = 10'd2 , //场同步 + V_BACK = 10'd25 , //场时序后沿 + V_TOP = 10'd8 , //场时序上边框 + V_VALID = 10'd480 , //场有效数据 + V_BOTTOM = 10'd8 , //场时序下边框 + V_FRONT = 10'd2 , //场时序前沿 + V_TOTAL = 10'd525 ; //场扫描周期 + +//wire define +wire rgb_valid ; //VGA有效显示区域 +wire pix_data_req ; //像素点色彩信息请求信号 + +//reg define +reg [9:0] cnt_h ; //行同步信号计数器 +reg [9:0] cnt_v ; //场同步信号计数器 + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// + +//cnt_h:行同步信号计数器 +always@(posedge vga_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_h <= 10'd0 ; + else if(cnt_h == H_TOTAL - 1'd1) + cnt_h <= 10'd0 ; + else + cnt_h <= cnt_h + 1'd1 ; + +//hsync:行同步信号 +assign hsync = (cnt_h <= H_SYNC - 1'd1) ? 1'b1 : 1'b0 ; + +//cnt_v:场同步信号计数器 +always@(posedge vga_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_v <= 10'd0 ; + else if((cnt_v == V_TOTAL - 1'd1) && (cnt_h == H_TOTAL-1'd1)) + cnt_v <= 10'd0 ; + else if(cnt_h == H_TOTAL - 1'd1) + cnt_v <= cnt_v + 1'd1 ; + else + cnt_v <= cnt_v ; + +//vsync:场同步信号 +assign vsync = (cnt_v <= V_SYNC - 1'd1) ? 1'b1 : 1'b0 ; + +//rgb_valid:VGA有效显示区域 +assign rgb_valid = (((cnt_h >= H_SYNC + H_BACK + H_LEFT) + && (cnt_h < H_SYNC + H_BACK + H_LEFT + H_VALID)) + &&((cnt_v >= V_SYNC + V_BACK + V_TOP) + && (cnt_v < V_SYNC + V_BACK + V_TOP + V_VALID))) + ? 1'b1 : 1'b0; + +//pix_data_req:像素点色彩信息请求信号,超前rgb_valid信号一个时钟周期 +assign pix_data_req = (((cnt_h >= H_SYNC + H_BACK + H_LEFT - 1'b1) + && (cnt_h < H_SYNC + H_BACK + H_LEFT + H_VALID - 1'b1)) + &&((cnt_v >= V_SYNC + V_BACK + V_TOP) + && (cnt_v < V_SYNC + V_BACK + V_TOP + V_VALID))) + ? 1'b1 : 1'b0; + +//pix_x,pix_y:VGA有效显示区域像素点坐标 +assign pix_x = (pix_data_req == 1'b1) + ? (cnt_h - (H_SYNC + H_BACK + H_LEFT - 1'b1)) : 10'h3ff; +assign pix_y = (pix_data_req == 1'b1) + ? (cnt_v - (V_SYNC + V_BACK + V_TOP)) : 10'h3ff; + +//rgb:输出像素点色彩信息 +assign rgb = (rgb_valid == 1'b1) ? pix_data : 16'b0 ; + +endmodule diff --git a/smh-ac415-fpga/examples/09_vga/vga/rtl/vga_pic.v b/smh-ac415-fpga/examples/09_vga/vga/rtl/vga_pic.v new file mode 100644 index 0000000..b0c178c --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/rtl/vga_pic.v @@ -0,0 +1,79 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/03/12 +// Module Name : vga_pic +// Project Name : vga_colorbar +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : 图像数据生成模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module vga_pic +( + input wire vga_clk , //输入工作时钟,频率25MHz + input wire sys_rst_n , //输入复位信号,低电平有效 + input wire [9:0] pix_x , //输入VGA有效显示区域像素点X轴坐标 + input wire [9:0] pix_y , //输入VGA有效显示区域像素点Y轴坐标 + + output reg [15:0] pix_data //输出像素点色彩信息 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//parameter define +parameter H_VALID = 10'd640 , //行有效数据 + V_VALID = 10'd480 ; //场有效数据 + +parameter RED = 16'hF800, //红色 + ORANGE = 16'hFC00, //橙色 + YELLOW = 16'hFFE0, //黄色 + GREEN = 16'h07E0, //绿色 + CYAN = 16'h07FF, //青色 + BLUE = 16'h001F, //蓝色 + PURPPLE = 16'hF81F, //紫色 + BLACK = 16'h0000, //黑色 + WHITE = 16'hFFFF, //白色 + GRAY = 16'hD69A; //灰色 + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// + +//pix_data:输出像素点色彩信息,根据当前像素点坐标指定当前像素点颜色数据 +always@(posedge vga_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + pix_data <= 16'd0; + else if((pix_x >= 0) && (pix_x < (H_VALID/10)*1)) + pix_data <= RED; + else if((pix_x >= (H_VALID/10)*1) && (pix_x < (H_VALID/10)*2)) + pix_data <= ORANGE; + else if((pix_x >= (H_VALID/10)*2) && (pix_x < (H_VALID/10)*3)) + pix_data <= YELLOW; + else if((pix_x >= (H_VALID/10)*3) && (pix_x < (H_VALID/10)*4)) + pix_data <= GREEN; + else if((pix_x >= (H_VALID/10)*4) && (pix_x < (H_VALID/10)*5)) + pix_data <= CYAN; + else if((pix_x >= (H_VALID/10)*5) && (pix_x < (H_VALID/10)*6)) + pix_data <= BLUE; + else if((pix_x >= (H_VALID/10)*6) && (pix_x < (H_VALID/10)*7)) + pix_data <= PURPPLE; + else if((pix_x >= (H_VALID/10)*7) && (pix_x < (H_VALID/10)*8)) + pix_data <= BLACK; + else if((pix_x >= (H_VALID/10)*8) && (pix_x < (H_VALID/10)*9)) + pix_data <= WHITE; + else if((pix_x >= (H_VALID/10)*9) && (pix_x < H_VALID)) + pix_data <= GRAY; + else + pix_data <= BLACK; + +endmodule diff --git a/smh-ac415-fpga/examples/09_vga/vga/sim/tb_vga_colorbar.v b/smh-ac415-fpga/examples/09_vga/vga/sim/tb_vga_colorbar.v new file mode 100644 index 0000000..6d6bb9f --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/sim/tb_vga_colorbar.v @@ -0,0 +1,65 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/03/12 +// Module Name : tb_vga_colorbar +// Project Name : vga_colorbar +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : vga_colorbar仿真文件 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module tb_vga_colorbar(); +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//wire define +wire hsync ; +wire [15:0] rgb ; +wire vsync ; + +//reg define +reg sys_clk ; +reg sys_rst_n ; + +//********************************************************************// +//**************************** Clk And Rst ***************************// +//********************************************************************// + +//sys_clk,sys_rst_n初始赋值 +initial + begin + sys_clk = 1'b1; + sys_rst_n <= 1'b0; + #200 + sys_rst_n <= 1'b1; + end + +//sys_clk：产生时钟 +always #10 sys_clk = ~sys_clk ; + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// + +//------------- vga_colorbar_inst ------------- +vga_colorbar vga_colorbar_inst +( + .sys_clk (sys_clk ), //输入晶振时钟,频率50MHz,1bit + .sys_rst_n (sys_rst_n ), //输入复位信号,低电平有效,1bit + + .hsync (hsync ), //输出行同步信号,1bit + .vsync (vsync ), //输出场同步信号,1bit + .rgb (rgb ) //输出RGB图像信息,16bit +); + +endmodule + diff --git a/smh-ac415-fpga/examples/09_vga/vga/sim/tb_vga_ctrl.v b/smh-ac415-fpga/examples/09_vga/vga/sim/tb_vga_ctrl.v new file mode 100644 index 0000000..fe027dd --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/sim/tb_vga_ctrl.v @@ -0,0 +1,88 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/03/12 +// Module Name : tb_vga_ctrl +// Project Name : vga_colorbar +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : vga_ctrl仿真文件 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module tb_vga_ctrl(); +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//wire define +//wire locked ; +//wire rst_n ; +//wire vga_clk ; + +//reg define +reg sys_clk ; +reg sys_rst_n ; +reg [15:0] pix_data ; + +//********************************************************************// +//**************************** Clk And Rst ***************************// +//********************************************************************// + +//sys_clk,sys_rst_n初始赋值 +initial + begin + sys_clk = 1'b1; + sys_rst_n <= 1'b0; + #200 + sys_rst_n <= 1'b1; + end + +//sys_clk：产生时钟 +always #20 sys_clk = ~sys_clk; + +//rst_n:VGA模块复位信号 +//assign rst_n = (sys_rst_n & locked); + +//pix_data:输入像素点色彩信息 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + pix_data <= 16'h0; + else + pix_data <= 16'hffff; + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// + +//------------- clk_gen_inst ------------- +/* clk_gen clk_gen_inst +( + .areset (~sys_rst_n ), //输入复位信号,高电平有效,1bit + .inclk0 (sys_clk ), //输入50MHz晶振时钟,1bit + .c0 (vga_clk ), //输出VGA工作时钟,频率25Mhz,1bit + .locked (locked ) //输出pll locked信号,1bit +); */ + +//------------- vga_ctrl_inst ------------- +vga_ctrl vga_ctrl_inst +( + .vga_clk (sys_clk ), //输入工作时钟,频率25MHz,1bit + .sys_rst_n (sys_rst_n ), //输入复位信号,低电平有效,1bit + .pix_data (pix_data ), //输入像素点色彩信息,16bit + + .pix_x (pix_x ), //输出VGA有效显示区域像素点X轴坐标,10bit + .pix_y (pix_y ), //输出VGA有效显示区域像素点Y轴坐标,10bit + .hsync (hsync ), //输出行同步信号,1bit + .vsync (vsync ), //输出场同步信号,1bit + .rgb (rgb ) //输出像素点色彩信息,16bit +); + +endmodule + diff --git "a/smh-ac415-fpga/examples/09_vga/\345\256\236\351\252\214\347\216\260\350\261\241.txt" "b/smh-ac415-fpga/examples/09_vga/\345\256\236\351\252\214\347\216\260\350\261\241.txt" new file mode 100644 index 0000000..0d9b9c8 --- /dev/null +++ "b/smh-ac415-fpga/examples/09_vga/\345\256\236\351\252\214\347\216\260\350\261\241.txt" @@ -0,0 +1,5 @@ +现象：用vga线连接显示器，可以显示色条colorbar。此例程参考野火fpga例程修改而来。具体可参考野火教程。 + +测试：可以测试vga接口是否正常。 + + -- cgit v1.2.3