From bc24ae901b74c5b673837d7f83423c1f7aa45c29 Mon Sep 17 00:00:00 2001 From: James McKenzie Date: Fri, 18 Apr 2025 12:37:26 +0100 Subject: fish --- .../examples/02_water_rgb/water_rgb/water_rgb.qpf | 30 +++++++++ .../examples/02_water_rgb/water_rgb/water_rgb.qsf | 69 +++++++++++++++++++++ .../examples/02_water_rgb/water_rgb/water_rgb.qws | Bin 0 -> 1359 bytes .../examples/02_water_rgb/water_rgb/water_rgb.v | 45 ++++++++++++++ .../02_water_rgb/water_rgb/water_rgb.v.bak | 45 ++++++++++++++ ...56\236\351\252\214\347\216\260\350\261\241.txt" | 2 + 6 files changed, 191 insertions(+) create mode 100644 smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.qpf create mode 100644 smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.qsf create mode 100644 smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.qws create mode 100644 smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.v create mode 100644 smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.v.bak create mode 100644 "smh-ac415-fpga/examples/02_water_rgb/\345\256\236\351\252\214\347\216\260\350\261\241.txt" (limited to 'smh-ac415-fpga/examples/02_water_rgb') diff --git a/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.qpf b/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.qpf new file mode 100644 index 0000000..75f7176 --- /dev/null +++ b/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +# Date created = 02:23:16 June 02, 2023 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "02:23:16 June 02, 2023" + +# Revisions + +PROJECT_REVISION = "water_rgb" diff --git a/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.qsf b/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.qsf new file mode 100644 index 0000000..1895fba --- /dev/null +++ b/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.qsf @@ -0,0 +1,69 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +# Date created = 02:23:16 June 02, 2023 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# water_rgb_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE15F23C8 +set_global_assignment -name TOP_LEVEL_ENTITY water_rgb +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "02:23:16 JUNE 02, 2023" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name VERILOG_FILE water_rgb.v +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_location_assignment PIN_V22 -to led_out[11] +set_location_assignment PIN_V21 -to led_out[10] +set_location_assignment PIN_W22 -to led_out[9] +set_location_assignment PIN_W21 -to led_out[8] +set_location_assignment PIN_Y22 -to led_out[7] +set_location_assignment PIN_AA21 -to led_out[6] +set_location_assignment PIN_AB20 -to led_out[5] +set_location_assignment PIN_AA20 -to led_out[4] +set_location_assignment PIN_AA17 -to led_out[3] +set_location_assignment PIN_Y17 -to led_out[2] +set_location_assignment PIN_W17 -to led_out[1] +set_location_assignment PIN_AB16 -to led_out[0] +set_location_assignment PIN_T22 -to sys_clk +set_location_assignment PIN_U20 -to sys_rst_n +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.qws b/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.qws new file mode 100644 index 0000000..f52d856 Binary files /dev/null and b/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.qws differ diff --git a/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.v b/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.v new file mode 100644 index 0000000..3e5789b --- /dev/null +++ b/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.v @@ -0,0 +1,45 @@ +`timescale 1ns/1ns + +module water_rgb +#( + parameter CNT_MAX = 25'd24_999_999 +) +( + input wire sys_clk , + input wire sys_rst_n , + + output wire [11:0] led_out + +); + +reg [24:0] cnt ; +reg cnt_flag ; +reg [11:0] led_out_reg ; + +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt <= 25'b0; + else if(cnt == CNT_MAX) + cnt <= 25'b0; + else + cnt <= cnt + 1'b1; + +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_flag <= 1'b0; + else if(cnt == CNT_MAX - 1) + cnt_flag <= 1'b1; + else + cnt_flag <= 1'b0; + +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + led_out_reg <= 12'b000000000001; + else if(led_out_reg == 12'b1000000000000 && cnt_flag == 1'b1) + led_out_reg <= 12'b000000000001; + else if(cnt_flag == 1'b1) + led_out_reg <= led_out_reg << 1'b1; + +assign led_out = ~led_out_reg; + +endmodule diff --git a/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.v.bak b/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.v.bak new file mode 100644 index 0000000..26b5726 --- /dev/null +++ b/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.v.bak @@ -0,0 +1,45 @@ +`timescale 1ns/1ns + +module water_led +#( + parameter CNT_MAX = 25'd24_999_999 +) +( + input wire sys_clk , + input wire sys_rst_n , + + output wire [11:0] led_out + +); + +reg [24:0] cnt ; +reg cnt_flag ; +reg [11:0] led_out_reg ; + +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt <= 25'b0; + else if(cnt == CNT_MAX) + cnt <= 25'b0; + else + cnt <= cnt + 1'b1; + +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_flag <= 1'b0; + else if(cnt == CNT_MAX - 1) + cnt_flag <= 1'b1; + else + cnt_flag <= 1'b0; + +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + led_out_reg <= 12'b000000000001; + else if(led_out_reg == 12'b1000000000000 && cnt_flag == 1'b1) + led_out_reg <= 12'b000000000001; + else if(cnt_flag == 1'b1) + led_out_reg <= led_out_reg << 1'b1; + +assign led_out = ~led_out_reg; + +endmodule diff --git "a/smh-ac415-fpga/examples/02_water_rgb/\345\256\236\351\252\214\347\216\260\350\261\241.txt" "b/smh-ac415-fpga/examples/02_water_rgb/\345\256\236\351\252\214\347\216\260\350\261\241.txt" new file mode 100644 index 0000000..1bddefc --- /dev/null +++ "b/smh-ac415-fpga/examples/02_water_rgb/\345\256\236\351\252\214\347\216\260\350\261\241.txt" @@ -0,0 +1,2 @@ +现象：4颗三色RGB灯依次闪烁。 +测试：可以测试4颗三色RGB灯是否正常。 \ No newline at end of file -- cgit v1.2.3