From c181f4737fc7cf9f87382c61d4c2f200226477fc Mon Sep 17 00:00:00 2001 From: root Date: Sun, 5 Oct 2025 17:30:34 +0100 Subject: remote alternate encoders --- fpga/hp_lcd_driver/tmds_encoder_a.vhdl | 117 ------------------------ fpga/hp_lcd_driver/tmds_encoder_b.vhdl | 143 ----------------------------- fpga/hp_lcd_driver/tmds_encoder_c.vhdl | 162 --------------------------------- 3 files changed, 422 deletions(-) delete mode 100644 fpga/hp_lcd_driver/tmds_encoder_a.vhdl delete mode 100644 fpga/hp_lcd_driver/tmds_encoder_b.vhdl delete mode 100644 fpga/hp_lcd_driver/tmds_encoder_c.vhdl (limited to 'fpga') diff --git a/fpga/hp_lcd_driver/tmds_encoder_a.vhdl b/fpga/hp_lcd_driver/tmds_encoder_a.vhdl deleted file mode 100644 index 40f8dd4..0000000 --- a/fpga/hp_lcd_driver/tmds_encoder_a.vhdl +++ /dev/null @@ -1,117 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity tmds_encoder is - port ( - clk : in std_logic; - sys_rst_n : in std_logic; - blank : in std_logic; - ctrl : in std_logic_vector(1 downto 0); - din : in std_logic_vector(7 downto 0); - dout : out std_logic_vector(9 downto 0) - ); -end tmds_encoder; - -architecture beh of tmds_encoder is - signal n_ones_din : integer range 0 to 8; - - signal xored, xnored : std_logic_vector(8 downto 0); - signal q_m : std_logic_vector(8 downto 0); - - -- a positive value represents the excess number of 1's that have been transmitted - -- a negative value represents the excess number of 0's that have been transmitted - signal disparity : signed(3 downto 0) := to_signed(0, 4); - -- difference between 1's and 0's (/2 since the last bit is never used) - signal diff : signed(3 downto 0) := to_signed(0, 4); - -begin - - -- ones counter for input data - process(din) is - variable c : integer range 0 to 8; - begin - c := 0; - for i in 0 to 7 loop - if din(i) = '1' then - c := c + 1; - end if; - end loop; - n_ones_din <= c; - end process; - - -- create xor encodings - xored(0) <= din(0); - encode_xor : for i in 1 to 7 generate - begin - xored(i) <= din(i) xor xored(i - 1); - end generate; - xored(8) <= '1'; - - -- create xnor encodings - xnored(0) <= din(0); - encode_xnor : for i in 1 to 7 generate - begin - xnored(i) <= din(i) xnor xnored(i - 1); - end generate; - xnored(8) <= '0'; - - -- use xnored or xored data based on the ones - q_m <= xnored when n_ones_din > 4 or (n_ones_din = 4 and din(0) = '0') else xored; - - -- ones counter for internal data - process(q_m) is - variable c : integer range 0 to 8; - begin - c := 0; - for i in 0 to 7 loop - if q_m(i) = '1' then - c := c + 1; - end if; - end loop; - diff <= to_signed(c-4, 4); - end process; - - process(clk) is - begin - if rising_edge(clk) then - if blank = '1' then - case ctrl is - when "00" => dout <= "1101010100"; - when "01" => dout <= "0010101011"; - when "10" => dout <= "0101010100"; - when others => dout <= "1010101011"; - end case; - disparity <= (others => '0'); - else - if disparity = 0 or diff = 0 then - -- xnored data - if q_m(8) = '0' then - dout <= "10" & not q_m(7 downto 0); - disparity <= disparity - diff; - -- xored data - else - dout <= "01" & q_m(7 downto 0); - disparity <= disparity + diff; - end if; - elsif (diff(diff'left) = '0' and disparity(disparity'left) = '0') or - (diff(diff'left) = '1' and disparity(disparity'left) = '1') then - dout <= '1' & q_m(8) & not q_m(7 downto 0); - if q_m(8) = '1' then - disparity <= disparity + 1 - diff; - else - disparity <= disparity - diff; - end if; - else - dout <= '0' & q_m; - if q_m(8) = '1' then - disparity <= disparity + diff; - else - disparity <= disparity - 1 + diff; - end if; - end if; - end if; - end if; - end process; -end beh; - diff --git a/fpga/hp_lcd_driver/tmds_encoder_b.vhdl b/fpga/hp_lcd_driver/tmds_encoder_b.vhdl deleted file mode 100644 index a6e8b54..0000000 --- a/fpga/hp_lcd_driver/tmds_encoder_b.vhdl +++ /dev/null @@ -1,143 +0,0 @@ --------------------------------------------------------------------------------- --- --- FileName: tmds_encoder.vhd --- Dependencies: none --- Design Software: Quartus II 64-bit Version 13.1.0 Build 162 SJ Full Version --- --- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY --- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT --- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A --- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY --- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL --- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF --- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS --- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), --- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. --- --- Version History --- Version 1.0 8/7/2014 Scott Larson --- Initial Public Release --- Version 2.0 2/24/2014 Scott Larson --- Corrected bug in the control signals --- --------------------------------------------------------------------------------- - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -ENTITY tmds_encoder IS - PORT( - clk : in std_logic; - sys_rst_n : in std_logic; - blank : in std_logic; - ctrl : in std_logic_vector(1 downto 0); - din : in std_logic_vector(7 downto 0); - dout : out std_logic_vector(9 downto 0) - ); -END tmds_encoder; - -ARCHITECTURE logic OF tmds_encoder IS - SIGNAL q_m : STD_LOGIC_VECTOR(8 DOWNTO 0); --internal data - SIGNAL ones_din : INTEGER RANGE 0 TO 8; --number of ones in the input data - SIGNAL ones_q_m : INTEGER RANGE 0 TO 8; --number of ones in the internal data - SIGNAL diff_q_m : INTEGER RANGE -8 TO 8; --number of ones minus the number of zeros in the internal data - SIGNAL disparity : INTEGER RANGE -16 TO 15; --disparity -BEGIN - - --count the ones in the input data byte - PROCESS(din) - VARIABLE ones: INTEGER RANGE 0 TO 8; - BEGIN - ones := 0; - FOR i IN 0 TO 7 LOOP - IF(din(i) = '1') THEN - ones := ones + 1; - END IF; - END LOOP; - ones_din <= ones; - END PROCESS; - - --process interval data to minimize transitions - PROCESS(din, q_m, ones_din) - BEGIN - IF(ones_din > 4 OR (ones_din = 4 AND din(0) = '0')) THEN - q_m(0) <= din(0); - q_m(1) <= q_m(0) XNOR din(1); - q_m(2) <= q_m(1) XNOR din(2); - q_m(3) <= q_m(2) XNOR din(3); - q_m(4) <= q_m(3) XNOR din(4); - q_m(5) <= q_m(4) XNOR din(5); - q_m(6) <= q_m(5) XNOR din(6); - q_m(7) <= q_m(6) XNOR din(7); - q_m(8) <= '0'; - ELSE - q_m(0) <= din(0); - q_m(1) <= q_m(0) XOR din(1); - q_m(2) <= q_m(1) XOR din(2); - q_m(3) <= q_m(2) XOR din(3); - q_m(4) <= q_m(3) XOR din(4); - q_m(5) <= q_m(4) XOR din(5); - q_m(6) <= q_m(5) XOR din(6); - q_m(7) <= q_m(6) XOR din(7); - q_m(8) <= '1'; - END IF; - END PROCESS; - - --count the ones in the internal data - PROCESS(q_m) - VARIABLE ones: INTEGER RANGE 0 TO 8; - BEGIN - ones := 0; - FOR i IN 0 TO 7 LOOP - IF(q_m(i) = '1') THEN - ones := ones + 1; - END IF; - END LOOP; - ones_q_m <= ones; - diff_q_m <= ones + ones - 8; --determine the difference between the number of ones and zeros - END PROCESS; - - --determine output and new disparity - PROCESS(clk) - BEGIN - IF(clk'EVENT AND clk = '1') THEN - IF(blank = '0') THEN - IF(disparity = 0 OR ones_q_m = 4) THEN - IF(q_m(8) = '0') THEN - dout <= NOT q_m(8) & q_m(8) & NOT q_m(7 DOWNTO 0); - disparity <= disparity - diff_q_m; - ELSE - dout <= NOT q_m(8)& q_m(8 DOWNTO 0); - disparity <= disparity + diff_q_m; - END IF; - ELSE - IF((disparity > 0 AND ones_q_m > 4) OR (disparity < 0 AND ones_q_m < 4)) THEN - dout <= '1' & q_m(8) & NOT q_m(7 DOWNTO 0); - IF(q_m(8) = '0') THEN - disparity <= disparity - diff_q_m; - ELSE - disparity <= disparity - diff_q_m + 2; - END IF; - ELSE - dout <= '0' & q_m(8 DOWNTO 0); - IF(q_m(8) = '0') THEN - disparity <= disparity + diff_q_m - 2; - ELSE - disparity <= disparity + diff_q_m; - END IF; - END IF; - END IF; - ELSE - CASE ctrl IS - WHEN "00" => dout <= "1101010100"; - WHEN "01" => dout <= "0010101011"; - WHEN "10" => dout <= "0101010100"; - WHEN "11" => dout <= "1010101011"; - WHEN OTHERS => NULL; - END CASE; - disparity <= 0; - END IF; - END IF; - END PROCESS; - -END logic; diff --git a/fpga/hp_lcd_driver/tmds_encoder_c.vhdl b/fpga/hp_lcd_driver/tmds_encoder_c.vhdl deleted file mode 100644 index 03415aa..0000000 --- a/fpga/hp_lcd_driver/tmds_encoder_c.vhdl +++ /dev/null @@ -1,162 +0,0 @@ --------------------------------------------------------------------------------- --- --- FileName: tmds_encoder.vhd --- Dependencies: none --- Design Software: Quartus II 64-bit Version 13.1.0 Build 162 SJ Full Version --- --- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY --- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT --- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A --- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY --- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL --- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF --- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS --- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), --- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. --- --- Version History --- Version 1.0 8/7/2014 Scott Larson --- Initial Public Release --- Version 2.0 2/24/2014 Scott Larson --- Corrected bug in the control signals --- --------------------------------------------------------------------------------- - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -ENTITY tmds_encoder IS - PORT( - clk : in std_logic; - sys_rst_n : in std_logic; - blank : in std_logic; - ctrl : in std_logic_vector(1 downto 0); - din : in std_logic_vector(7 downto 0); - dout : out std_logic_vector(9 downto 0) - ); -END tmds_encoder; - -ARCHITECTURE logic OF tmds_encoder IS - SIGNAL dind : std_logic_vector(7 downto 0); - SIGNAL q_m : STD_LOGIC_VECTOR(8 DOWNTO 0); --internal data - SIGNAL q_md : STD_LOGIC_VECTOR(8 DOWNTO 0); --internal data - SIGNAL ones_din : INTEGER RANGE 0 TO 8; --number of ones in the input data - SIGNAL ones_dind : INTEGER RANGE 0 TO 8; --number of ones in the input data - SIGNAL ones_q_md : INTEGER RANGE 0 TO 8; --number of ones in the internal data - SIGNAL diff_q_md : INTEGER RANGE -8 TO 8; --number of ones minus the number of zeros in the internal data - SIGNAL disparity : INTEGER RANGE -16 TO 15; --disparity -BEGIN - - --count the ones in the input data byte - PROCESS(din) - VARIABLE ones: INTEGER RANGE 0 TO 8; - BEGIN - ones := 0; - FOR i IN 0 TO 7 LOOP - IF(din(i) = '1') THEN - ones := ones + 1; - END IF; - END LOOP; - ones_din <= ones; - END PROCESS; - - process(clk) begin - if rising_edge(clk) then - dind<=din; - ones_dind<=ones_din; - end if; - end process; - - - --process interval data to minimize transitions - PROCESS(dind, q_m, ones_dind) - BEGIN - IF(ones_dind > 4 OR (ones_dind = 4 AND dind(0) = '0')) THEN - q_m(0) <= dind(0); - q_m(1) <= q_m(0) XNOR dind(1); - q_m(2) <= q_m(1) XNOR dind(2); - q_m(3) <= q_m(2) XNOR dind(3); - q_m(4) <= q_m(3) XNOR dind(4); - q_m(5) <= q_m(4) XNOR dind(5); - q_m(6) <= q_m(5) XNOR dind(6); - q_m(7) <= q_m(6) XNOR dind(7); - q_m(8) <= '0'; - ELSE - q_m(0) <= dind(0); - q_m(1) <= q_m(0) XOR dind(1); - q_m(2) <= q_m(1) XOR dind(2); - q_m(3) <= q_m(2) XOR dind(3); - q_m(4) <= q_m(3) XOR dind(4); - q_m(5) <= q_m(4) XOR dind(5); - q_m(6) <= q_m(5) XOR dind(6); - q_m(7) <= q_m(6) XOR dind(7); - q_m(8) <= '1'; - END IF; - END PROCESS; - - process(clk) begin - if rising_edge(clk) then - q_md<=q_m; - end if; - end process; - - - - --count the ones in the internal data - PROCESS(q_md) - VARIABLE ones: INTEGER RANGE 0 TO 8; - BEGIN - ones := 0; - FOR i IN 0 TO 7 LOOP - IF(q_md(i) = '1') THEN - ones := ones + 1; - END IF; - END LOOP; - ones_q_md <= ones; - diff_q_md <= ones + ones - 8; --determine the difference between the number of ones and zeros - END PROCESS; - - --determine output and new disparity - PROCESS(clk) - BEGIN - IF(clk'EVENT AND clk = '1') THEN - IF(blank = '0') THEN - IF(disparity = 0 OR ones_q_md = 4) THEN - IF(q_md(8) = '0') THEN - dout <= NOT q_md(8) & q_md(8) & NOT q_md(7 DOWNTO 0); - disparity <= disparity - diff_q_md; - ELSE - dout <= NOT q_md(8)& q_md(8 DOWNTO 0); - disparity <= disparity + diff_q_md; - END IF; - ELSE - IF((disparity > 0 AND ones_q_md > 4) OR (disparity < 0 AND ones_q_md < 4)) THEN - dout <= '1' & q_md(8) & NOT q_md(7 DOWNTO 0); - IF(q_md(8) = '0') THEN - disparity <= disparity - diff_q_md; - ELSE - disparity <= disparity - diff_q_md + 2; - END IF; - ELSE - dout <= '0' & q_md(8 DOWNTO 0); - IF(q_md(8) = '0') THEN - disparity <= disparity + diff_q_md - 2; - ELSE - disparity <= disparity + diff_q_md; - END IF; - END IF; - END IF; - ELSE - CASE ctrl IS - WHEN "00" => dout <= "1101010100"; - WHEN "01" => dout <= "0010101011"; - WHEN "10" => dout <= "0101010100"; - WHEN "11" => dout <= "1010101011"; - WHEN OTHERS => NULL; - END CASE; - disparity <= 0; - END IF; - END IF; - END PROCESS; - -END logic; -- cgit v1.2.3