From 2cccfc49706cd0b5d3b7ac5333a8bcce041b206d Mon Sep 17 00:00:00 2001 From: James McKenzie Date: Fri, 5 Sep 2025 00:41:14 +0100 Subject: tidy --- fpga/hp_lcd_driver/common.vhdl | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'fpga/hp_lcd_driver/common.vhdl') diff --git a/fpga/hp_lcd_driver/common.vhdl b/fpga/hp_lcd_driver/common.vhdl index df58203..7275184 100644 --- a/fpga/hp_lcd_driver/common.vhdl +++ b/fpga/hp_lcd_driver/common.vhdl @@ -84,8 +84,8 @@ architecture Behavioral of common is signal c : natural; signal t : std_logic; - - signal wr_index: std_logic; + + signal wr_index : std_logic; begin @@ -250,19 +250,19 @@ begin - r <=x"ff" when rd_data(0) = '1' else - x"00"; + r <= x"ff" when rd_data(0) = '1' else + x"00"; -- r<=x"ff" when rd_data(0)='1' and rd_data(3)='1' else -- x"80" when rd_data(0)='1' else -- x"00"; - g <=x"ff" when rd_data(1) = '1' and rd_data(3) = '1' else - x"80" when rd_data(1) = '1' else - x"00"; - b <=x"ff" when rd_data(2) = '1' and rd_data(3) = '1' else - x"80" when rd_data(2) = '1' else - x"00"; + g <= x"ff" when rd_data(1) = '1' and rd_data(3) = '1' else + x"80" when rd_data(1) = '1' else + x"00"; + b <= x"ff" when rd_data(2) = '1' and rd_data(3) = '1' else + x"80" when rd_data(2) = '1' else + x"00"; -- cgit v1.2.3