diff options
Diffstat (limited to 'fpga')
| -rw-r--r-- | fpga/ebaz4205/linux-6.16.4-pq/master/jmm-fb | 301 | ||||
| -rw-r--r-- | fpga/ebaz4205/src/ebaz4205-zynq7.dts | 6 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/common.vhdl | 24 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/ebaz4205.xdc | 3 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl | 2 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/zynq7_ip/axi_bram_ctrl_0.tcl | 25 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_1.tcl | 33 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl | 5 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/zynq7_wrapper.vhdl | 239 |
9 files changed, 522 insertions, 116 deletions
diff --git a/fpga/ebaz4205/linux-6.16.4-pq/master/jmm-fb b/fpga/ebaz4205/linux-6.16.4-pq/master/jmm-fb new file mode 100644 index 0000000..f12063f --- /dev/null +++ b/fpga/ebaz4205/linux-6.16.4-pq/master/jmm-fb @@ -0,0 +1,301 @@ +diff --git a/.config b/.config +index 470123376..e06bfbd12 100644 +--- a/.config ++++ b/.config +@@ -1793,6 +1793,7 @@ CONFIG_PCI_ENDPOINT_TEST=m + # CONFIG_NSM is not set + # CONFIG_MCHP_LAN966X_PCI is not set + CONFIG_MISC_JMM_VCAP=y ++CONFIG_MISC_JMM_FB=y + # CONFIG_C2PORT is not set + + # +diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig +index 626152d80..b56499f42 100644 +--- a/drivers/misc/Kconfig ++++ b/drivers/misc/Kconfig +@@ -647,6 +647,9 @@ config MCHP_LAN966X_PCI + config MISC_JMM_VCAP + tristate "JMM_VCAP Driver" + ++config MISC_JMM_FB ++ tristate "JMM_FB Driver" ++ + source "drivers/misc/c2port/Kconfig" + source "drivers/misc/eeprom/Kconfig" + source "drivers/misc/cb710/Kconfig" +diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile +index cef74a483..7f3eadf0e 100644 +--- a/drivers/misc/Makefile ++++ b/drivers/misc/Makefile +@@ -67,6 +67,7 @@ obj-$(CONFIG_VCPU_STALL_DETECTOR) += vcpu_stall_detector.o + obj-$(CONFIG_TMR_MANAGER) += xilinx_tmr_manager.o + obj-$(CONFIG_TMR_INJECT) += xilinx_tmr_inject.o + obj-$(CONFIG_MISC_JMM_VCAP) += jmm_vcap.o ++obj-$(CONFIG_MISC_JMM_FB) += jmm_fb.o + obj-$(CONFIG_TPS6594_ESM) += tps6594-esm.o + obj-$(CONFIG_TPS6594_PFSM) += tps6594-pfsm.o + obj-$(CONFIG_NSM) += nsm.o +diff --git a/drivers/misc/jmm_fb.c b/drivers/misc/jmm_fb.c +new file mode 100644 +index 000000000..2fe454b5f +--- /dev/null ++++ b/drivers/misc/jmm_fb.c +@@ -0,0 +1,257 @@ ++#include <linux/miscdevice.h> ++#include <linux/fs.h> ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/init.h> ++#include <linux/uaccess.h> ++#include <linux/io.h> ++#include <linux/platform_device.h> ++#include <linux/pm_runtime.h> ++#include <linux/of.h> ++#include <linux/gpio.h> ++ ++ ++ ++static struct jmm_vcap { ++ struct gpio_desc *gpio; ++ int gpio_state; ++ uint8_t *ocm_base; ++ size_t ocm_len; ++} jmm_vcap; ++ ++ ++/* ++** This function will be called when we open the Misc device file ++*/ ++static int jmm_vcap_open(struct inode *inode, struct file *file) ++{ ++ pr_info("jmm_vcap device open\n"); ++ return 0; ++} ++ ++/* ++** This function will be called when we close the Misc Device file ++*/ ++static int jmm_vcap_close(struct inode *inodep, struct file *filp) ++{ ++ pr_info("jmm_vcap device close\n"); ++ return 0; ++} ++ ++/* ++** This function will be called when we write the Misc Device file ++*/ ++static ssize_t jmm_vcap_write(struct file *file, const char __user *buf, ++ size_t len, loff_t *ppos) ++{ ++ pr_info("jmm_vcap device write\n"); ++ ++ /* We are not doing anything with this data now */ ++ ++ return -ENODEV; ++} ++ ++/* ++** This function will be called when we read the Misc Device file ++*/ ++static ssize_t jmm_vcap_read(struct file *filp, char __user *buf, ++ size_t count, loff_t *f_pos) ++{ ++ ++ if (*f_pos>=jmm_vcap.ocm_len) return 0; ++ ++ if ((*f_pos+count)>jmm_vcap.ocm_len) { ++ count=jmm_vcap.ocm_len-*f_pos; ++ } ++ ++ if (copy_to_user(buf, jmm_vcap.ocm_base+(*f_pos), count)) ++ return -EFAULT; ++ ++ (*f_pos) += count; ++ ++ return count; ++} ++ ++static loff_t jmm_vcap_llseek(struct file *filp, loff_t offset, int whence) ++{ ++loff_t new_offset; ++ ++ ++switch(whence) { ++case SEEK_SET: ++ new_offset=offset; ++ break; ++case SEEK_CUR: ++ new_offset=filp->f_pos + offset; ++ break; ++case SEEK_END: ++ new_offset=jmm_vcap.ocm_len + offset; ++ break; ++default: ++ return -EINVAL; ++} ++ ++ ++if (new_offset<0) ++ return -EINVAL; ++if (new_offset>jmm_vcap.ocm_len) ++ return -EINVAL; ++ ++filp->f_pos=new_offset; ++ ++return new_offset; ++} ++ ++ ++//File operation structure ++static const struct file_operations fops = { ++ .owner = THIS_MODULE, ++ .write = jmm_vcap_write, ++ .read = jmm_vcap_read, ++ .open = jmm_vcap_open, ++ .release = jmm_vcap_close, ++ .llseek = jmm_vcap_llseek, ++}; ++ ++//Misc device structure ++struct miscdevice jmm_vcap_device = { ++ .minor = MISC_DYNAMIC_MINOR, ++ .name = "jmm_vcap", ++ .fops = &fops, ++}; ++ ++ ++static const struct of_device_id jmm_vcap_of_match[] = { ++ { .compatible = "jmm,video-capture-device" }, ++ { /* end of table */ } ++}; ++MODULE_DEVICE_TABLE(of, jmm_vcap_of_match); ++ ++ ++static int jmm_vcap_probe(struct platform_device *pdev) ++{ ++ struct resource *res; ++ const struct of_device_id *match; ++ uint8_t *ptr; ++ ++ ++ match = of_match_node(jmm_vcap_of_match, pdev->dev.of_node); ++ pr_info("jmm_vcap match %px\n",match); ++ printk(KERN_ERR "jmm_vcap" "jmm_vcap match %px\n",match); ++ if (!match) { ++ dev_err(&pdev->dev, "of_match_node() failed\n"); ++ printk(KERN_ERR "jmm_vcap" "of_match_node() failed\n"); ++ return -EINVAL; ++ } ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ dev_err(&pdev->dev, "can't get parent mmio range\n"); ++ printk(KERN_ERR "jmm_vcap" "can't get parent mmio range\n"); ++ return -EINVAL; ++ } ++ ++ jmm_vcap.gpio = devm_gpiod_get(&(pdev->dev), NULL, GPIOD_OUT_LOW); ++ if (IS_ERR(jmm_vcap.gpio)) { ++ dev_err(&pdev->dev, "can't get enable gpio\n"); ++ printk(KERN_ERR "jmm_vcap" "can't get enable gpio\n"); ++ return -EINVAL; ++ } ++ ++ jmm_vcap.ocm_len=res->end - res->start; ++ jmm_vcap.ocm_len++; ++ pr_info("jmm_vcap resource indicates length of 0x%x\n",jmm_vcap.ocm_len); ++ printk(KERN_ERR "jmm_vcap" "jmm_vcap resource indicates length of 0x%x\n",jmm_vcap.ocm_len); ++ ++ ptr = devm_ioremap_resource(&pdev->dev, res); ++ pr_info("jmm_vcap devm_ioremap_resource() gives %px\n",ptr); ++ printk(KERN_ERR "jmm_vcap" "jmm_vcap devm_ioremap_resource() gives %px\n",ptr); ++ ++ if (IS_ERR(ptr)) ++ return PTR_ERR(ptr); ++ ++ jmm_vcap.ocm_base=ptr; ++ ++ gpiod_set_value(jmm_vcap.gpio,1); ++ ++ return 0; ++} ++ ++/** ++ * zynq_gpio_remove - Driver removal function ++ * @pdev: platform device instance ++ * ++ * Return: 0 always ++ */ ++static void jmm_vcap_remove(struct platform_device *pdev) ++{ ++ //struct zynq_gpio *gpio = platform_get_drvdata(pdev); ++ ++ jmm_vcap.ocm_base=NULL; ++} ++ ++static struct platform_driver jmm_vcap_driver = { ++ .driver = { ++ .name = "jmm-vcap", ++ .of_match_table = jmm_vcap_of_match, ++ }, ++ .probe = jmm_vcap_probe, ++ .remove = jmm_vcap_remove, ++}; ++ ++ ++static int __init jmm_vcap_init(void) ++{ ++ int error; ++ ++ //jmm_vcap_driver->driver.owner = THIS_MODULE; ++ //jmm_vcap_driver->driver.bus=&platform_bus_type; ++ ++ error=platform_driver_register(&jmm_vcap_driver); ++ if (error) { ++ pr_err("platform_driver_register failed!!!\n"); ++ printk(KERN_ERR "jmm_vcap" "platform_driver_register failed!!!\n"); ++ return error; ++ } ++ ++ error = misc_register(&jmm_vcap_device); ++ if (error) { ++ platform_driver_unregister(&jmm_vcap_driver); ++ pr_err("misc_register failed!!!\n"); ++ printk(KERN_ERR "jmm_vcap" "misc_register failed!!!\n"); ++ return error; ++ } ++ ++ pr_info("misc_register init done!!!\n"); ++ printk(KERN_ERR "jmm_vcap" "misc_register init done!!!\n"); ++ ++#if 0 ++ jmm_vcap = ioremap(0xfffc0000,0x40000); ++ pr_info("jmm_vcap mapped at %px\n",jmm_vcap); ++#endif ++ ++ return 0; ++} ++ ++static void __exit jmm_vcap_exit(void) ++{ ++ misc_deregister(&jmm_vcap_device); ++ platform_driver_unregister(&jmm_vcap_driver); ++ ++ pr_info("misc_register exit done!!!\n"); ++ ++#if 0 ++ if (jmm_vcap.ocm_base) iounmap(jmm_vcap.ocm_base); ++#endif ++} ++ ++module_init(jmm_vcap_init) ++module_exit(jmm_vcap_exit) ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("meh"); ++MODULE_DESCRIPTION("jmm_vcap driver"); ++MODULE_VERSION("1.00"); ++ ++ ++ diff --git a/fpga/ebaz4205/src/ebaz4205-zynq7.dts b/fpga/ebaz4205/src/ebaz4205-zynq7.dts index 1bfc5d5..eb5e3ac 100644 --- a/fpga/ebaz4205/src/ebaz4205-zynq7.dts +++ b/fpga/ebaz4205/src/ebaz4205-zynq7.dts @@ -30,12 +30,12 @@ &amba { plfb: sram@40000000 { compatible = "jmm,frame-buffer-device"; - reg = <0x40000000 0x10000>; + reg = <0x40000000 0x40000>; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x80000000 0x10000>; + ranges = <0 0x40000000 0x40000>; plfb@0 { - reg = <0x0 0x10000>; + reg = <0x0 0x40000>; }; }; }; diff --git a/fpga/hp_lcd_driver/common.vhdl b/fpga/hp_lcd_driver/common.vhdl index 08895d8..39d1f28 100644 --- a/fpga/hp_lcd_driver/common.vhdl +++ b/fpga/hp_lcd_driver/common.vhdl @@ -264,21 +264,15 @@ begin --- r <= r_s when video_in_data(1) = '0' else --- x"00" when video_in_data(0)='0' else --- x"ff"; --- g <= g_s when video_in_data(1) = '0' else --- x"00" when video_in_data(0)='0' else --- x"ff"; --- b <= b_s when video_in_data(1) = '0' else --- x"00" when video_in_data(0)='0' else --- x"ff"; - -r<=r_s; -g<=g_s; -b<=b_s; - - + r <= r_s when video_in_data(1) = '0' else + x"00" when video_in_data(0)='0' else + x"ff"; + g <= g_s when video_in_data(1) = '0' else + x"00" when video_in_data(0)='0' else + x"ff"; + b <= b_s when video_in_data(1) = '0' else + x"00" when video_in_data(0)='0' else + x"ff"; output0 : entity work.output_stage diff --git a/fpga/hp_lcd_driver/ebaz4205.xdc b/fpga/hp_lcd_driver/ebaz4205.xdc index 30b073a..39ea882 100644 --- a/fpga/hp_lcd_driver/ebaz4205.xdc +++ b/fpga/hp_lcd_driver/ebaz4205.xdc @@ -117,6 +117,9 @@ set_property IOSTANDARD LVCMOS33 [get_ports {hsync_in}] #set_property PULLTYPE PULLUP [get_ports {sys_rst_n}] # +set_property PACKAGE_PIN M20 [get_ports {scope_ch1}]; #data2-19 +set_property IOSTANDARD LVCMOS33 [get_ports {scope_ch1}] + create_clock -period 20.000 -name pcie_clkin [get_ports clk_50m] ##set_false_path -from [get_ports pci_exp_rst_n] # diff --git a/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl b/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl index babcc70..7887f6a 100644 --- a/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl +++ b/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl @@ -20,7 +20,7 @@ if {[llength $files] != 0} { #read_verilog [ glob ../source/*.v ] #read_vhdl -vhdl2008 -library work [ glob ../source/*.vhdl ] -read_vhdl -vhdl2008 -library work { ../zynq7_wrapper.vhdl ../fifo_to_axi.vhdl ../clkgen_artix7.vhdl ../debounce.vhdl ../delay.vhdl ../edge_det.vhdl ../common.vhdl ../input_formatter.vhdl ../input_stage.vhdl ../output_analog.vhdl ../output_formatter.vhdl ../output_stage.vhdl ../synchronizer.vhdl ../tmds_encoder.vhdl ../tmds_encode.vhdl ../tmds_output_artix7.vhdl ../tmds_phy_artix7.vhdl ../vram_artix7.vhdl ../vnc_serializer.vhdl ../overlay_vram_artix7.vhdl } +read_vhdl -vhdl2008 -library work { ../zynq7_wrapper.vhdl ../fifo_to_axi.vhdl ../clkgen_artix7.vhdl ../debounce.vhdl ../delay.vhdl ../edge_det.vhdl ../common.vhdl ../input_formatter.vhdl ../input_stage.vhdl ../output_analog.vhdl ../output_formatter.vhdl ../output_stage.vhdl ../synchronizer.vhdl ../tmds_encoder.vhdl ../tmds_encode.vhdl ../tmds_output_artix7.vhdl ../tmds_phy_artix7.vhdl ../vram_artix7.vhdl ../vnc_serializer.vhdl } set generics {} append generics { } "video_width=$video_width" diff --git a/fpga/hp_lcd_driver/zynq7_ip/axi_bram_ctrl_0.tcl b/fpga/hp_lcd_driver/zynq7_ip/axi_bram_ctrl_0.tcl new file mode 100644 index 0000000..1933b91 --- /dev/null +++ b/fpga/hp_lcd_driver/zynq7_ip/axi_bram_ctrl_0.tcl @@ -0,0 +1,25 @@ + +set source_dir [file dirname [file dirname [file normalize [info script]]]] + +source $source_dir/zynq7_config.tcl + +create_ip -name axi_bram_ctrl -vendor xilinx.com -library ip -version 4.1 -module_name axi_bram_ctrl_0 -dir $ip_dir + + +set_property -dict [list \ + CONFIG.BMG_INSTANCE {EXTERNAL} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FAULT_INJECT {0} \ + CONFIG.ID_WIDTH {12} \ + CONFIG.MEM_DEPTH {262144} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.RD_CMD_OPTIMIZATION {0} \ + CONFIG.READ_LATENCY {2} \ + CONFIG.SINGLE_PORT_BRAM {1} \ + CONFIG.SUPPORTS_NARROW_BURST {0} \ + CONFIG.USE_ECC {0} \ + ] [get_ips axi_bram_ctrl_0] + +generate_target all [get_ips] + +synth_ip [get_ips] diff --git a/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_1.tcl b/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_1.tcl new file mode 100644 index 0000000..e178395 --- /dev/null +++ b/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_1.tcl @@ -0,0 +1,33 @@ + + +set source_dir [file dirname [file dirname [file normalize [info script]]]] + +source $source_dir/zynq7_config.tcl + +create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name blk_mem_gen_1 -dir $ip_dir + + + +set_property -dict [list \ + CONFIG.Memory_Type {True_Dual_Port_RAM} \ + CONFIG.Use_Byte_Write_Enable {true} \ + CONFIG.Byte_Size {8} \ + CONFIG.Write_Width_A {32} \ + CONFIG.Write_Depth_A {16384} \ + CONFIG.Read_Width_A {32} \ + CONFIG.Operating_Mode_A {WRITE_FIRST} \ + CONFIG.Write_Width_B {32} \ + CONFIG.Read_Width_B {32} \ + CONFIG.Operating_Mode_B {READ_FIRST} \ + CONFIG.Enable_B {Always_Enabled} \ + CONFIG.Register_PortA_Output_of_Memory_Primitives {true} \ + CONFIG.Register_PortB_Output_of_Memory_Primitives {true} \ + CONFIG.Port_B_Clock {100} \ + CONFIG.Port_B_Write_Rate {50} \ + CONFIG.Port_B_Enable_Rate {100} \ + ] [get_ips blk_mem_gen_1] + +generate_target all [get_ips] + +synth_ip [get_ips] + diff --git a/fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl b/fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl index 4bd2319..92cf5d4 100644 --- a/fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl +++ b/fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl @@ -11,6 +11,11 @@ set_property -dict [list \ CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {250} \ CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {100} \ CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \ + CONFIG.PCW_M_AXI_GP0_FREQMHZ {100} \ + CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \ + CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0} \ + CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12} \ CONFIG.PCW_USE_S_AXI_HP0 {1} \ CONFIG.PCW_USE_HIGH_OCM {1} \ CONFIG.PCW_EN_CLK0_PORT {1} \ diff --git a/fpga/hp_lcd_driver/zynq7_wrapper.vhdl b/fpga/hp_lcd_driver/zynq7_wrapper.vhdl index 00d56a8..ca90bea 100644 --- a/fpga/hp_lcd_driver/zynq7_wrapper.vhdl +++ b/fpga/hp_lcd_driver/zynq7_wrapper.vhdl @@ -89,7 +89,9 @@ entity zynq7_wrapper is hdmi_g_n : out std_logic; hdmi_b_p : out std_logic; hdmi_b_n : out std_logic; - hdmi_vcc : out std_logic + hdmi_vcc : out std_logic; + + scope_ch1: out std_logic ); end entity zynq7_wrapper; @@ -105,43 +107,48 @@ architecture arch of zynq7_wrapper is signal emio_o : std_logic_vector(63 downto 0); signal emio_t : std_logic_vector(63 downto 0); - - signal gp0_aclk : std_logic; signal gp0_nrst : std_logic; - signal gp0_awaddr : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal gp0_awlen : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal gp0_awsize : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal gp0_awburst : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal gp0_awlock : STD_LOGIC_VECTOR ( 1 downto 0); - signal gp0_awcache : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal gp0_awprot : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal gp0_awvalid : STD_LOGIC; - signal gp0_awready : STD_LOGIC; - signal gp0_wdata : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal gp0_wstrb : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal gp0_wlast : STD_LOGIC; - signal gp0_wvalid : STD_LOGIC; - signal gp0_wready : STD_LOGIC; - signal gp0_bresp : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal gp0_bvalid : STD_LOGIC; - signal gp0_bready : STD_LOGIC; - signal gp0_araddr : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal gp0_arlen : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal gp0_arsize : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal gp0_arburst : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal gp0_arlock : STD_LOGIC_VECTOR( 1 downto 0); - signal gp0_arcache : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal gp0_arprot : STD_LOGIC_VECTOR ( 2 downto 0 ); - signal gp0_arvalid : STD_LOGIC; - signal gp0_arready : STD_LOGIC; - signal gp0_rdata : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal gp0_rresp : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal gp0_rlast : STD_LOGIC; - signal gp0_rvalid : STD_LOGIC; - signal gp0_rready : STD_LOGIC; - + signal gp0_arvalid : std_logic; + signal gp0_awvalid : std_logic; + signal gp0_bready : std_logic; + signal gp0_rready : std_logic; + signal gp0_wlast : std_logic; + signal gp0_wvalid : std_logic; + signal gp0_arid : std_logic_vector ( 11 downto 0 ); + signal gp0_awid : std_logic_vector ( 11 downto 0 ); + signal gp0_wid : std_logic_vector ( 11 downto 0 ); + signal gp0_arburst : std_logic_vector ( 1 downto 0 ); + signal gp0_arlock : std_logic_vector ( 1 downto 0 ); + signal gp0_arsize : std_logic_vector ( 2 downto 0 ); + signal gp0_awburst : std_logic_vector ( 1 downto 0 ); + signal gp0_awlock : std_logic_vector ( 1 downto 0 ); + signal gp0_awsize : std_logic_vector ( 2 downto 0 ); + signal gp0_arprot : std_logic_vector ( 2 downto 0 ); + signal gp0_awprot : std_logic_vector ( 2 downto 0 ); + signal gp0_araddr : std_logic_vector ( 31 downto 0 ); + signal gp0_awaddr : std_logic_vector ( 31 downto 0 ); + signal gp0_wdata : std_logic_vector ( 31 downto 0 ); + signal gp0_arcache : std_logic_vector ( 3 downto 0 ); + signal gp0_arlen : std_logic_vector ( 3 downto 0 ); + signal gp0_arqos : std_logic_vector ( 3 downto 0 ); + signal gp0_awcache : std_logic_vector ( 3 downto 0 ); + signal gp0_awlen : std_logic_vector ( 3 downto 0 ); + signal gp0_awqos : std_logic_vector ( 3 downto 0 ); + signal gp0_wstrb : std_logic_vector ( 3 downto 0 ); + signal gp0_arready : std_logic; + signal gp0_awready : std_logic; + signal gp0_bvalid : std_logic; + signal gp0_rlast : std_logic; + signal gp0_rvalid : std_logic; + signal gp0_wready : std_logic; + signal gp0_bid : std_logic_vector ( 11 downto 0 ); + signal gp0_rid : std_logic_vector ( 11 downto 0 ); + signal gp0_bresp : std_logic_vector ( 1 downto 0 ); + signal gp0_rresp : std_logic_vector ( 1 downto 0 ); + signal gp0_rdata : std_logic_vector ( 31 downto 0 ); + signal hp0_aclk : std_logic; signal hp0_nrst : std_logic; signal hp0_arvalid : std_logic; @@ -184,22 +191,26 @@ architecture arch of zynq7_wrapper is signal clk_50m_ps : std_logic; - signal overlay_r_addr : std_logic_vector(addr_width-1 downto 0); - signal overlay_r_clk : std_logic; - signal overlay_r_data : std_logic_vector(1 downto 0); + signal overlay_addr : std_logic_vector(addr_width-1 downto 0); + signal overlay_clk : std_logic; + signal overlay_data : std_logic_vector(1 downto 0); + signal overlay_demux :integer; - signal overlay_w_clk : std_logic; - signal overlay_w_en : std_logic; - signal overlay_w_data : std_logic_vector(1 downto 0); - signal overlay_w_addr : std_logic_vector(addr_width-1 downto 0); - signal mem_ctl_addr : std_logic_vector (19 downto 0); - signal mem_ctl_data : std_logic_vector (31 downto 0); - signal mem_ctl_we_a : std_logic_vector (3 downto 0); + signal fb_ps_clk : STD_LOGIC; + signal fb_ps_en : STD_LOGIC; + signal fb_ps_we : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal fb_ps_addr : STD_LOGIC_VECTOR ( 19 downto 0 ); + signal fb_ps_wrdata : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal fb_ps_rddata : STD_LOGIC_VECTOR ( 31 downto 0 ); + + signal fb_pl_addr : STD_LOGIC_VECTOR ( 13 downto 0 ); + signal fb_pl_rddata : STD_LOGIC_VECTOR ( 31 downto 0 ); - begin + scope_ch1 <= gp0_awvalid; --clk_50m_ps; + common_i : entity work.common @@ -237,9 +248,9 @@ begin video_out_valid => vnc_valid, video_out_data => vnc_data, video_out_index => vnc_index, - video_in_clk => overlay_r_clk, - video_in_addr => overlay_r_addr, - video_in_data => overlay_r_data + video_in_clk => overlay_clk, + video_in_addr => overlay_addr, + video_in_data => overlay_data ); processing_system7_0_i : entity work.processing_system7_0 @@ -293,39 +304,46 @@ begin GPIO_O => emio_o, GPIO_T => emio_t, - M_AXI_GP0_ACLK => gp0_aclk, - M_AXI_GP0_AWADDR => gp0_awaddr , - M_AXI_GP0_AWLEN => gp0_awlen , - M_AXI_GP0_AWSIZE => gp0_awsize , - M_AXI_GP0_AWBURST => gp0_awburst , - M_AXI_GP0_AWLOCK => gp0_awlock , - M_AXI_GP0_AWCACHE => gp0_awcache , - M_AXI_GP0_AWPROT => gp0_awprot , + M_AXI_GP0_ARVALID => gp0_arvalid , M_AXI_GP0_AWVALID => gp0_awvalid , - M_AXI_GP0_AWREADY => gp0_awready , - M_AXI_GP0_WDATA => gp0_wdata , - M_AXI_GP0_WSTRB => gp0_wstrb , + M_AXI_GP0_BREADY => gp0_bready , + M_AXI_GP0_RREADY => gp0_rready , M_AXI_GP0_WLAST => gp0_wlast , M_AXI_GP0_WVALID => gp0_wvalid , - M_AXI_GP0_WREADY => gp0_wready , - M_AXI_GP0_BRESP => gp0_bresp , - M_AXI_GP0_BVALID => gp0_bvalid , - M_AXI_GP0_BREADY => gp0_bready , - M_AXI_GP0_ARADDR => gp0_araddr , - M_AXI_GP0_ARLEN => gp0_arlen , - M_AXI_GP0_ARSIZE => gp0_arsize , + M_AXI_GP0_ARID => gp0_arid , + M_AXI_GP0_AWID => gp0_awid , + M_AXI_GP0_WID => gp0_wid , M_AXI_GP0_ARBURST => gp0_arburst , M_AXI_GP0_ARLOCK => gp0_arlock , - M_AXI_GP0_ARCACHE => gp0_arcache , + M_AXI_GP0_ARSIZE => gp0_arsize , + M_AXI_GP0_AWBURST => gp0_awburst , + M_AXI_GP0_AWLOCK => gp0_awlock , + M_AXI_GP0_AWSIZE => gp0_awsize , M_AXI_GP0_ARPROT => gp0_arprot , - M_AXI_GP0_ARVALID => gp0_arvalid , + M_AXI_GP0_AWPROT => gp0_awprot , + M_AXI_GP0_ARADDR => gp0_araddr , + M_AXI_GP0_AWADDR => gp0_awaddr , + M_AXI_GP0_WDATA => gp0_wdata , + M_AXI_GP0_ARCACHE => gp0_arcache , + M_AXI_GP0_ARLEN => gp0_arlen , + M_AXI_GP0_ARQOS => gp0_arqos , + M_AXI_GP0_AWCACHE => gp0_awcache , + M_AXI_GP0_AWLEN => gp0_awlen , + M_AXI_GP0_AWQOS => gp0_awqos , + M_AXI_GP0_WSTRB => gp0_wstrb , + M_AXI_GP0_ACLK => gp0_aclk , M_AXI_GP0_ARREADY => gp0_arready , - M_AXI_GP0_RDATA => gp0_rdata , - M_AXI_GP0_RRESP => gp0_rresp , + M_AXI_GP0_AWREADY => gp0_awready , + M_AXI_GP0_BVALID => gp0_bvalid , M_AXI_GP0_RLAST => gp0_rlast , M_AXI_GP0_RVALID => gp0_rvalid , - M_AXI_GP0_RREADY => gp0_rready , + M_AXI_GP0_WREADY => gp0_wready , + M_AXI_GP0_BID => gp0_bid , + M_AXI_GP0_RID => gp0_rid , + M_AXI_GP0_BRESP => gp0_bresp , + M_AXI_GP0_RRESP => gp0_rresp , + M_AXI_GP0_RDATA => gp0_rdata , S_AXI_HP0_ACLK => hp0_aclk, S_AXI_HP0_ARADDR => hp0_araddr, @@ -440,26 +458,54 @@ begin fifo_rd_en => fifo_rd_en ); + fb_ram0: entity work.blk_mem_gen_1 + port map ( + clka => fb_ps_clk, + ena => fb_ps_en, + wea => fb_ps_we, + addra => fb_ps_addr (15 downto 2), + dina => fb_ps_wrdata, + douta => fb_ps_rddata, + clkb => overlay_clk, + web => "0000", + addrb => fb_pl_addr, + dinb => x"00000000", + doutb => fb_pl_rddata + ); + + + + fb_pl_addr <= overlay_addr(17 downto 4); + + overlay_demux <= to_integer(unsigned(overlay_addr(3 downto 0)))*2; + overlay_data(0) <= fb_pl_rddata(overlay_demux); + overlay_data(1) <= fb_pl_rddata(overlay_demux +1); + + -- fb_ps_rddata <=x"9abcdef0"; - overlay_vram0 : entity work.overlay_vram - generic map ( - addr_width => addr_width - ) - port map ( - wr_clk => overlay_w_clk, - wr_en => overlay_w_en, - wr_addr => overlay_w_addr, - wr_data => overlay_w_data, - rd_clk => overlay_r_clk, - rd_addr => overlay_r_addr, - rd_data => overlay_r_data - ); + +-- ps_fb_rddata<=x"12345678"; +-- pl_fb_rddata<=x"9abcdef0"; + + +-- signal fb_ps_clk : STD_LOGIC; +-- signal fb_ps_en : STD_LOGIC; +-- signal fb_ps_we : STD_LOGIC_VECTOR ( 3 downto 0 ); +-- signal fb_ps_addr : STD_LOGIC_VECTOR ( 19 downto 0 ); +-- signal fb_ps_wrdata : STD_LOGIC_VECTOR ( 31 downto 0 ); +-- signal fb_ps_rddata : STD_LOGIC_VECTOR ( 31 downto 0 ) +-- + +-- +-- +-- overlay_data <= "00"; axi_bram_ctrl_0_i : entity work.axi_bram_ctrl_0 port map ( s_axi_aclk => gp0_aclk, s_axi_aresetn => gp0_nrst, + s_axi_awid => gp0_awid , s_axi_awaddr => gp0_awaddr(19 downto 0) , s_axi_awlen => gp0_awlen , s_axi_awsize => gp0_awsize , @@ -474,10 +520,12 @@ begin s_axi_wlast => gp0_wlast , s_axi_wvalid => gp0_wvalid , s_axi_wready => gp0_wready , + s_axi_bid => gp0_bid , s_axi_bresp => gp0_bresp , s_axi_bvalid => gp0_bvalid , s_axi_bready => gp0_bready , - s_axi_araddr => gp0_araddr (19 downto 0) , + s_axi_arid => gp0_arid , + s_axi_araddr => gp0_araddr(19 downto 0) , s_axi_arlen => gp0_arlen , s_axi_arsize => gp0_arsize , s_axi_arburst => gp0_arburst , @@ -486,25 +534,22 @@ begin s_axi_arprot => gp0_arprot , s_axi_arvalid => gp0_arvalid , s_axi_arready => gp0_arready , + s_axi_rid => gp0_rid , s_axi_rdata => gp0_rdata , s_axi_rresp => gp0_rresp , s_axi_rlast => gp0_rlast , s_axi_rvalid => gp0_rvalid , s_axi_rready => gp0_rready , - bram_rst_a => open, - bram_clk_a => overlay_w_clk, - bram_en_a =>open, - bram_we_a => mem_ctl_we_a, - bram_addr_a => mem_ctl_addr, - bram_wrdata_a => mem_ctl_data, - bram_rddata_a => x"12345678" - ); + bram_clk_a => fb_ps_clk , + bram_en_a => fb_ps_en , + bram_we_a => fb_ps_we , + bram_addr_a => fb_ps_addr , + bram_wrdata_a => fb_ps_wrdata , + bram_rddata_a => fb_ps_rddata - overlay_w_addr <= mem_ctl_addr(addr_width -1 downto 0); - overlay_w_data <= mem_ctl_data(1 downto 0); - overlay_w_en <=mem_ctl_we_a(0); + ); hp0_araddr <= (others => '0'); hp0_arvalid <= '0'; |