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-rw-r--r--fpga/hp_lcd_driver/kbd_uarts.vhdl412
-rw-r--r--fpga/hp_lcd_driver/zynq7_wrapper.vhdl16
2 files changed, 214 insertions, 214 deletions
diff --git a/fpga/hp_lcd_driver/kbd_uarts.vhdl b/fpga/hp_lcd_driver/kbd_uarts.vhdl
index 01bdbce..a0188f0 100644
--- a/fpga/hp_lcd_driver/kbd_uarts.vhdl
+++ b/fpga/hp_lcd_driver/kbd_uarts.vhdl
@@ -5,47 +5,47 @@ use work.all;
entity kbd_uarts is
port (
- s_axi_aclk : in std_logic;
- s_axi_aresetn : in std_logic;
-
- s_axi_arvalid : in STD_LOGIC;
- s_axi_awvalid : in STD_LOGIC;
- s_axi_bready : in STD_LOGIC;
- s_axi_rready : in STD_LOGIC;
- s_axi_wlast : in STD_LOGIC;
- s_axi_wvalid : in STD_LOGIC;
- s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
- s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
- s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s_axi_arready : out STD_LOGIC;
- s_axi_awready : out STD_LOGIC;
- s_axi_bvalid : out STD_LOGIC;
- s_axi_rlast : out STD_LOGIC;
- s_axi_rvalid : out STD_LOGIC;
- s_axi_wready : out STD_LOGIC;
- s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
- s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
- s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
-
+ s_axi_aclk : in std_logic;
+ s_axi_aresetn : in std_logic;
+
+ s_axi_arvalid : in std_logic;
+ s_axi_awvalid : in std_logic;
+ s_axi_bready : in std_logic;
+ s_axi_rready : in std_logic;
+ s_axi_wlast : in std_logic;
+ s_axi_wvalid : in std_logic;
+ s_axi_arid : in std_logic_vector (11 downto 0);
+ s_axi_awid : in std_logic_vector (11 downto 0);
+ s_axi_arburst : in std_logic_vector (1 downto 0);
+ s_axi_arlock : in std_logic_vector (1 downto 0);
+ s_axi_arsize : in std_logic_vector (2 downto 0);
+ s_axi_awburst : in std_logic_vector (1 downto 0);
+ s_axi_awlock : in std_logic_vector (1 downto 0);
+ s_axi_awsize : in std_logic_vector (2 downto 0);
+ s_axi_arprot : in std_logic_vector (2 downto 0);
+ s_axi_awprot : in std_logic_vector (2 downto 0);
+ s_axi_araddr : in std_logic_vector (31 downto 0);
+ s_axi_awaddr : in std_logic_vector (31 downto 0);
+ s_axi_wdata : in std_logic_vector (31 downto 0);
+ s_axi_arcache : in std_logic_vector (3 downto 0);
+ s_axi_arlen : in std_logic_vector (3 downto 0);
+ s_axi_arqos : in std_logic_vector (3 downto 0);
+ s_axi_awcache : in std_logic_vector (3 downto 0);
+ s_axi_awlen : in std_logic_vector (3 downto 0);
+ s_axi_awqos : in std_logic_vector (3 downto 0);
+ s_axi_wstrb : in std_logic_vector (3 downto 0);
+ s_axi_arready : out std_logic;
+ s_axi_awready : out std_logic;
+ s_axi_bvalid : out std_logic;
+ s_axi_rlast : out std_logic;
+ s_axi_rvalid : out std_logic;
+ s_axi_wready : out std_logic;
+ s_axi_bid : out std_logic_vector (11 downto 0);
+ s_axi_rid : out std_logic_vector (11 downto 0);
+ s_axi_bresp : out std_logic_vector (1 downto 0);
+ s_axi_rresp : out std_logic_vector (1 downto 0);
+ s_axi_rdata : out std_logic_vector (31 downto 0);
+
u0_tx : out std_logic;
u0_rx : in std_logic;
u0_int : out std_logic;
@@ -58,163 +58,163 @@ end kbd_uarts;
architecture Behavioural of kbd_uarts is
- signal m_axi_awaddr : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal m_axi_awprot : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal m_axi_awvalid : STD_LOGIC;
- signal m_axi_awready : STD_LOGIC;
- signal m_axi_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal m_axi_wstrb : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal m_axi_wvalid : STD_LOGIC;
- signal m_axi_wready : STD_LOGIC;
- signal m_axi_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal m_axi_bvalid : STD_LOGIC;
- signal m_axi_bready : STD_LOGIC;
- signal m_axi_araddr : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal m_axi_arprot : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal m_axi_arvalid : STD_LOGIC;
- signal m_axi_arready : STD_LOGIC;
- signal m_axi_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal m_axi_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal m_axi_rvalid : STD_LOGIC;
- signal m_axi_rready : STD_LOGIC;
-
-
- signal uc_axi_awaddr : STD_LOGIC_VECTOR ( 63 downto 0 );
- signal uc_axi_awprot : STD_LOGIC_VECTOR ( 5 downto 0 );
- signal uc_axi_awvalid : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal uc_axi_awready : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal uc_axi_wdata : STD_LOGIC_VECTOR ( 63 downto 0 );
- signal uc_axi_wstrb : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal uc_axi_wvalid : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal uc_axi_wready : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal uc_axi_bresp : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal uc_axi_bvalid : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal uc_axi_bready : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal uc_axi_araddr : STD_LOGIC_VECTOR ( 63 downto 0 );
- signal uc_axi_arprot : STD_LOGIC_VECTOR ( 5 downto 0 );
- signal uc_axi_arvalid : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal uc_axi_arready : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal uc_axi_rdata : STD_LOGIC_VECTOR ( 63 downto 0 );
- signal uc_axi_rresp : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal uc_axi_rvalid : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal uc_axi_rready : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal m_axi_awaddr : std_logic_vector (31 downto 0);
+ signal m_axi_awprot : std_logic_vector (2 downto 0);
+ signal m_axi_awvalid : std_logic;
+ signal m_axi_awready : std_logic;
+ signal m_axi_wdata : std_logic_vector (31 downto 0);
+ signal m_axi_wstrb : std_logic_vector (3 downto 0);
+ signal m_axi_wvalid : std_logic;
+ signal m_axi_wready : std_logic;
+ signal m_axi_bresp : std_logic_vector (1 downto 0);
+ signal m_axi_bvalid : std_logic;
+ signal m_axi_bready : std_logic;
+ signal m_axi_araddr : std_logic_vector (31 downto 0);
+ signal m_axi_arprot : std_logic_vector (2 downto 0);
+ signal m_axi_arvalid : std_logic;
+ signal m_axi_arready : std_logic;
+ signal m_axi_rdata : std_logic_vector (31 downto 0);
+ signal m_axi_rresp : std_logic_vector (1 downto 0);
+ signal m_axi_rvalid : std_logic;
+ signal m_axi_rready : std_logic;
+
+
+ signal uc_axi_awaddr : std_logic_vector (63 downto 0);
+ signal uc_axi_awprot : std_logic_vector (5 downto 0);
+ signal uc_axi_awvalid : std_logic_vector (1 downto 0);
+ signal uc_axi_awready : std_logic_vector (1 downto 0);
+ signal uc_axi_wdata : std_logic_vector (63 downto 0);
+ signal uc_axi_wstrb : std_logic_vector (7 downto 0);
+ signal uc_axi_wvalid : std_logic_vector (1 downto 0);
+ signal uc_axi_wready : std_logic_vector (1 downto 0);
+ signal uc_axi_bresp : std_logic_vector (3 downto 0);
+ signal uc_axi_bvalid : std_logic_vector (1 downto 0);
+ signal uc_axi_bready : std_logic_vector (1 downto 0);
+ signal uc_axi_araddr : std_logic_vector (63 downto 0);
+ signal uc_axi_arprot : std_logic_vector (5 downto 0);
+ signal uc_axi_arvalid : std_logic_vector (1 downto 0);
+ signal uc_axi_arready : std_logic_vector (1 downto 0);
+ signal uc_axi_rdata : std_logic_vector (63 downto 0);
+ signal uc_axi_rresp : std_logic_vector (3 downto 0);
+ signal uc_axi_rvalid : std_logic_vector (1 downto 0);
+ signal uc_axi_rready : std_logic_vector (1 downto 0);
begin
-axi_protocol_converter_0_i: entity work.axi_protocol_converter_0
- Port map (
- aclk => s_axi_aclk,
- aresetn => s_axi_aresetn,
-
- s_axi_arvalid => s_axi_arvalid,
- s_axi_awvalid => s_axi_awvalid,
- s_axi_bready => s_axi_bready,
- s_axi_rready => s_axi_rready,
- s_axi_wlast => s_axi_wlast,
- s_axi_wvalid => s_axi_wvalid,
- s_axi_arid => s_axi_arid,
- s_axi_awid => s_axi_awid,
- s_axi_arburst => s_axi_arburst,
- s_axi_arlock => s_axi_arlock,
- s_axi_arsize => s_axi_arsize,
- s_axi_awburst => s_axi_awburst,
- s_axi_awlock => s_axi_awlock,
- s_axi_awsize => s_axi_awsize,
- s_axi_arprot => s_axi_arprot,
- s_axi_awprot => s_axi_awprot,
- s_axi_araddr => s_axi_araddr,
- s_axi_awaddr => s_axi_awaddr,
- s_axi_wdata => s_axi_wdata,
- s_axi_arcache => s_axi_arcache,
- s_axi_arlen => s_axi_arlen,
- s_axi_arqos => s_axi_arqos,
- s_axi_awcache => s_axi_awcache,
- s_axi_awlen => s_axi_awlen,
- s_axi_awqos => s_axi_awqos,
- s_axi_wstrb => s_axi_wstrb,
- s_axi_arready => s_axi_arready,
- s_axi_awready => s_axi_awready,
- s_axi_bvalid => s_axi_bvalid,
- s_axi_rlast => s_axi_rlast,
- s_axi_rvalid => s_axi_rvalid,
- s_axi_wready => s_axi_wready,
- s_axi_bid => s_axi_bid,
- s_axi_rid => s_axi_rid,
- s_axi_bresp => s_axi_bresp,
- s_axi_rresp => s_axi_rresp,
- s_axi_rdata => s_axi_rdata,
-
-
- m_axi_awaddr => m_axi_awaddr,
- m_axi_awprot => m_axi_awprot,
- m_axi_awvalid => m_axi_awvalid,
- m_axi_awready => m_axi_awready,
- m_axi_wdata => m_axi_wdata,
- m_axi_wstrb => m_axi_wstrb,
- m_axi_wvalid => m_axi_wvalid,
- m_axi_wready => m_axi_wready,
- m_axi_bresp => m_axi_bresp,
- m_axi_bvalid => m_axi_bvalid,
- m_axi_bready => m_axi_bready,
- m_axi_araddr => m_axi_araddr,
- m_axi_arprot => m_axi_arprot,
- m_axi_arvalid => m_axi_arvalid,
- m_axi_arready => m_axi_arready,
- m_axi_rdata => m_axi_rdata,
- m_axi_rresp => m_axi_rresp,
- m_axi_rvalid => m_axi_rvalid,
- m_axi_rready => m_axi_rready
- );
+ axi_protocol_converter_0_i : entity work.axi_protocol_converter_0
+ port map (
+ aclk => s_axi_aclk,
+ aresetn => s_axi_aresetn,
+
+ s_axi_arvalid => s_axi_arvalid,
+ s_axi_awvalid => s_axi_awvalid,
+ s_axi_bready => s_axi_bready,
+ s_axi_rready => s_axi_rready,
+ s_axi_wlast => s_axi_wlast,
+ s_axi_wvalid => s_axi_wvalid,
+ s_axi_arid => s_axi_arid,
+ s_axi_awid => s_axi_awid,
+ s_axi_arburst => s_axi_arburst,
+ s_axi_arlock => s_axi_arlock,
+ s_axi_arsize => s_axi_arsize,
+ s_axi_awburst => s_axi_awburst,
+ s_axi_awlock => s_axi_awlock,
+ s_axi_awsize => s_axi_awsize,
+ s_axi_arprot => s_axi_arprot,
+ s_axi_awprot => s_axi_awprot,
+ s_axi_araddr => s_axi_araddr,
+ s_axi_awaddr => s_axi_awaddr,
+ s_axi_wdata => s_axi_wdata,
+ s_axi_arcache => s_axi_arcache,
+ s_axi_arlen => s_axi_arlen,
+ s_axi_arqos => s_axi_arqos,
+ s_axi_awcache => s_axi_awcache,
+ s_axi_awlen => s_axi_awlen,
+ s_axi_awqos => s_axi_awqos,
+ s_axi_wstrb => s_axi_wstrb,
+ s_axi_arready => s_axi_arready,
+ s_axi_awready => s_axi_awready,
+ s_axi_bvalid => s_axi_bvalid,
+ s_axi_rlast => s_axi_rlast,
+ s_axi_rvalid => s_axi_rvalid,
+ s_axi_wready => s_axi_wready,
+ s_axi_bid => s_axi_bid,
+ s_axi_rid => s_axi_rid,
+ s_axi_bresp => s_axi_bresp,
+ s_axi_rresp => s_axi_rresp,
+ s_axi_rdata => s_axi_rdata,
+
+
+ m_axi_awaddr => m_axi_awaddr,
+ m_axi_awprot => m_axi_awprot,
+ m_axi_awvalid => m_axi_awvalid,
+ m_axi_awready => m_axi_awready,
+ m_axi_wdata => m_axi_wdata,
+ m_axi_wstrb => m_axi_wstrb,
+ m_axi_wvalid => m_axi_wvalid,
+ m_axi_wready => m_axi_wready,
+ m_axi_bresp => m_axi_bresp,
+ m_axi_bvalid => m_axi_bvalid,
+ m_axi_bready => m_axi_bready,
+ m_axi_araddr => m_axi_araddr,
+ m_axi_arprot => m_axi_arprot,
+ m_axi_arvalid => m_axi_arvalid,
+ m_axi_arready => m_axi_arready,
+ m_axi_rdata => m_axi_rdata,
+ m_axi_rresp => m_axi_rresp,
+ m_axi_rvalid => m_axi_rvalid,
+ m_axi_rready => m_axi_rready
+ );
axi_crossbar_0_i : entity work.axi_crossbar_0
port map (
- aclk => s_axi_aclk,
- aresetn => s_axi_aresetn,
-
- s_axi_awaddr => m_axi_awaddr ,
- s_axi_awprot => m_axi_awprot ,
- s_axi_awvalid => m_axi_awvalid ,
- s_axi_awready => m_axi_awready ,
- s_axi_wdata => m_axi_wdata ,
- s_axi_wstrb => m_axi_wstrb ,
- s_axi_wvalid => m_axi_wvalid ,
- s_axi_wready => m_axi_wready ,
- s_axi_bresp => m_axi_bresp ,
- s_axi_bvalid => m_axi_bvalid ,
- s_axi_bready => m_axi_bready ,
- s_axi_araddr => m_axi_araddr ,
- s_axi_arprot => m_axi_arprot ,
- s_axi_arvalid => m_axi_arvalid ,
- s_axi_arready => m_axi_arready ,
- s_axi_rdata => m_axi_rdata ,
- s_axi_rresp => m_axi_rresp ,
- s_axi_rvalid => m_axi_rvalid ,
- s_axi_rready => m_axi_rready ,
-
- m_axi_awaddr => uc_axi_awaddr ,
- m_axi_awprot => uc_axi_awprot ,
- m_axi_awvalid => uc_axi_awvalid ,
- m_axi_awready => uc_axi_awready ,
- m_axi_wdata => uc_axi_wdata ,
- m_axi_wstrb => uc_axi_wstrb ,
- m_axi_wvalid => uc_axi_wvalid ,
- m_axi_wready => uc_axi_wready ,
- m_axi_bresp => uc_axi_bresp ,
- m_axi_bvalid => uc_axi_bvalid ,
- m_axi_bready => uc_axi_bready ,
- m_axi_araddr => uc_axi_araddr ,
- m_axi_arprot => uc_axi_arprot ,
- m_axi_arvalid => uc_axi_arvalid ,
- m_axi_arready => uc_axi_arready ,
- m_axi_rdata => uc_axi_rdata ,
- m_axi_rresp => uc_axi_rresp ,
- m_axi_rvalid => uc_axi_rvalid ,
- m_axi_rready => uc_axi_rready
-);
+ aclk => s_axi_aclk,
+ aresetn => s_axi_aresetn,
+
+ s_axi_awaddr => m_axi_awaddr,
+ s_axi_awprot => m_axi_awprot,
+ s_axi_awvalid => m_axi_awvalid,
+ s_axi_awready => m_axi_awready,
+ s_axi_wdata => m_axi_wdata,
+ s_axi_wstrb => m_axi_wstrb,
+ s_axi_wvalid => m_axi_wvalid,
+ s_axi_wready => m_axi_wready,
+ s_axi_bresp => m_axi_bresp,
+ s_axi_bvalid => m_axi_bvalid,
+ s_axi_bready => m_axi_bready,
+ s_axi_araddr => m_axi_araddr,
+ s_axi_arprot => m_axi_arprot,
+ s_axi_arvalid => m_axi_arvalid,
+ s_axi_arready => m_axi_arready,
+ s_axi_rdata => m_axi_rdata,
+ s_axi_rresp => m_axi_rresp,
+ s_axi_rvalid => m_axi_rvalid,
+ s_axi_rready => m_axi_rready,
+
+ m_axi_awaddr => uc_axi_awaddr,
+ m_axi_awprot => uc_axi_awprot,
+ m_axi_awvalid => uc_axi_awvalid,
+ m_axi_awready => uc_axi_awready,
+ m_axi_wdata => uc_axi_wdata,
+ m_axi_wstrb => uc_axi_wstrb,
+ m_axi_wvalid => uc_axi_wvalid,
+ m_axi_wready => uc_axi_wready,
+ m_axi_bresp => uc_axi_bresp,
+ m_axi_bvalid => uc_axi_bvalid,
+ m_axi_bready => uc_axi_bready,
+ m_axi_araddr => uc_axi_araddr,
+ m_axi_arprot => uc_axi_arprot,
+ m_axi_arvalid => uc_axi_arvalid,
+ m_axi_arready => uc_axi_arready,
+ m_axi_rdata => uc_axi_rdata,
+ m_axi_rresp => uc_axi_rresp,
+ m_axi_rvalid => uc_axi_rvalid,
+ m_axi_rready => uc_axi_rready
+ );
@@ -242,15 +242,15 @@ axi_protocol_converter_0_i: entity work.axi_protocol_converter_0
s_axi_rvalid => uc_axi_rvalid(0),
s_axi_rready => uc_axi_rready(0),
- ip2intc_irpt => u0_int,
- freeze => '0',
- sin => u0_rx,
- sout => u0_tx,
- ctsn => '0',
- dcdn =>'0',
- dsrn => '0',
- rin => '1'
-
+ ip2intc_irpt => u0_int,
+ freeze => '0',
+ sin => u0_rx,
+ sout => u0_tx,
+ ctsn => '0',
+ dcdn => '0',
+ dsrn => '0',
+ rin => '1'
+
-- baudoutn : out STD_LOGIC;
-- ctsn : in STD_LOGIC;
-- dcdn : in STD_LOGIC;
@@ -288,15 +288,15 @@ axi_protocol_converter_0_i: entity work.axi_protocol_converter_0
s_axi_rvalid => uc_axi_rvalid(1),
s_axi_rready => uc_axi_rready(1),
- ip2intc_irpt => u1_int,
- freeze => '0',
- sin => u1_rx,
- sout => u1_tx,
- ctsn => '0',
- dcdn =>'0',
- dsrn => '0',
- rin => '1'
-
+ ip2intc_irpt => u1_int,
+ freeze => '0',
+ sin => u1_rx,
+ sout => u1_tx,
+ ctsn => '0',
+ dcdn => '0',
+ dsrn => '0',
+ rin => '1'
+
-- baudoutn : out STD_LOGIC;
-- ctsn : in STD_LOGIC;
-- dcdn : in STD_LOGIC;
diff --git a/fpga/hp_lcd_driver/zynq7_wrapper.vhdl b/fpga/hp_lcd_driver/zynq7_wrapper.vhdl
index 2319b08..7f7fdf0 100644
--- a/fpga/hp_lcd_driver/zynq7_wrapper.vhdl
+++ b/fpga/hp_lcd_driver/zynq7_wrapper.vhdl
@@ -213,7 +213,7 @@ architecture arch of zynq7_wrapper is
signal hp0_wvalid : std_logic;
signal hp0_wstrb : std_logic_vector(7 downto 0);
- signal pl_irqs : std_logic_vector(1 downto 0);
+ signal pl_irqs : std_logic_vector(1 downto 0);
signal run : std_logic;
@@ -462,7 +462,7 @@ begin
S_AXI_HP0_WSTRB => hp0_wstrb,
S_AXI_HP0_WVALID => hp0_wvalid,
- IRQ_F2P => pl_irqs
+ IRQ_F2P => pl_irqs
);
eth0_mdio_mdio_iobuf : IOBUF
@@ -600,12 +600,12 @@ begin
s_axi_rresp => gp1_rresp,
s_axi_rdata => gp1_rdata,
- u0_tx => u0_tx,
- u0_rx => u0_rx,
- u1_tx => u1_tx,
- u1_rx => u1_rx,
- u0_int => pl_irqs(0),
- u1_int => pl_irqs(1)
+ u0_tx => u0_tx,
+ u0_rx => u0_rx,
+ u1_tx => u1_tx,
+ u1_rx => u1_rx,
+ u0_int => pl_irqs(0),
+ u1_int => pl_irqs(1)
);
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-17 22:06:24 +0000