diff options
| -rw-r--r-- | fpga/hp_lcd_driver/fb_hw.vhdl | 180 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/kbd_uarts.vhdl | 65 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/vnc_hw.vhdl | 111 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/zynq7.mk | 9 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl | 4 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/zynq7_ip/axi_crossbar_0.tcl | 50 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/zynq7_ip/axi_uart16550_0.tcl | 11 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/zynq7_wrapper.vhdl | 174 |
8 files changed, 454 insertions, 150 deletions
diff --git a/fpga/hp_lcd_driver/fb_hw.vhdl b/fpga/hp_lcd_driver/fb_hw.vhdl new file mode 100644 index 0000000..9d12ae1 --- /dev/null +++ b/fpga/hp_lcd_driver/fb_hw.vhdl @@ -0,0 +1,180 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use work.all; + +entity fb_hw is + generic ( + addr_width : integer := 17 + ); + port ( + s_axi_aclk : in STD_LOGIC; + s_axi_aresetn : in STD_LOGIC; + s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR(1 downto 0); + s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wlast : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arlock : in STD_LOGIC_VECTOR( 1 downto 0); + s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rlast : out STD_LOGIC; + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC; + + overlay_clk : in std_logic; + overlay_addr : in std_logic_vector(addr_width-1 downto 0); + overlay_gate : out std_logic; + overlay_r : out std_logic_vector(7 downto 0); + overlay_g : out std_logic_vector(7 downto 0); + overlay_b : out std_logic_vector(7 downto 0) + + + +); +end fb_hw; +architecture Behavioural of fb_hw is + + + type t_palette is array (0 to 15) of std_logic_vector(7 downto 0); + constant r_lut : t_palette := ( + x"00", x"00", x"00", x"00", x"AA", x"AA", x"AA", x"AA", + x"55", x"55", x"55", x"55", x"FF", x"FF", x"FF", x"FF" + ); + constant g_lut : t_palette := ( + x"00", x"00", x"AA", x"AA", x"00", x"00", x"55", x"AA", + x"55", x"55", x"FF", x"FF", x"55", x"55", x"FF", x"FF" + ); + constant b_lut : t_palette := ( + x"00", x"AA", x"00", x"AA", x"00", x"AA", x"00", x"AA", + x"55", x"FF", x"55", x"FF", x"55", x"FF", x"55", x"FF" + ); + + + signal overlay_demux_p :integer; + signal overlay_demux :integer; + signal overlay_data : integer; + + + signal fb_ps_clk : STD_LOGIC; + signal fb_ps_en : STD_LOGIC; + signal fb_ps_we : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal fb_ps_addr : STD_LOGIC_VECTOR ( 19 downto 0 ); + signal fb_ps_wrdata : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal fb_ps_rddata : STD_LOGIC_VECTOR ( 31 downto 0 ); + + signal fb_pl_addr : STD_LOGIC_VECTOR ( 14 downto 0 ); + signal fb_pl_rddata : STD_LOGIC_VECTOR ( 31 downto 0 ); + +begin + + fb_ram0: entity work.blk_mem_gen_1 + port map ( + clka => fb_ps_clk, + ena => fb_ps_en, + wea => fb_ps_we, + addra => fb_ps_addr (15 downto 2), + dina => fb_ps_wrdata, + douta => fb_ps_rddata, + clkb => overlay_clk, + web => "0000", + addrb => fb_pl_addr, + dinb => x"00000000", + doutb => fb_pl_rddata + ); + + + + fb_pl_addr <= overlay_addr(17 downto 3); + + process (overlay_clk) begin + if rising_edge(overlay_clk) then + overlay_demux_p <= to_integer(unsigned(overlay_addr(2 downto 0)))*4; + overlay_demux <=overlay_demux_p; + end if; + end process; + + overlay_data <= to_integer(unsigned(fb_pl_rddata(overlay_demux+3 downto overlay_demux))); + + overlay_gate <= '0' when overlay_data = 0 else '1'; + overlay_r <= r_lut(overlay_data); + overlay_g <= g_lut(overlay_data); + overlay_b <= b_lut(overlay_data); + + + axi_bram_ctrl_0_i : entity work.axi_bram_ctrl_0 + port map ( + s_axi_aclk => s_axi_aclk, + s_axi_aresetn => s_axi_aresetn, + + s_axi_awid => s_axi_awid , + s_axi_awaddr => s_axi_awaddr(19 downto 0) , + s_axi_awlen => s_axi_awlen , + s_axi_awsize => s_axi_awsize , + s_axi_awburst => s_axi_awburst , + s_axi_awlock => s_axi_awlock(0) , + s_axi_awcache => s_axi_awcache , + s_axi_awprot => s_axi_awprot , + s_axi_awvalid => s_axi_awvalid , + s_axi_awready => s_axi_awready , + s_axi_wdata => s_axi_wdata , + s_axi_wstrb => s_axi_wstrb , + s_axi_wlast => s_axi_wlast , + s_axi_wvalid => s_axi_wvalid , + s_axi_wready => s_axi_wready , + s_axi_bid => s_axi_bid , + s_axi_bresp => s_axi_bresp , + s_axi_bvalid => s_axi_bvalid , + s_axi_bready => s_axi_bready , + s_axi_arid => s_axi_arid , + s_axi_araddr => s_axi_araddr(19 downto 0) , + s_axi_arlen => s_axi_arlen , + s_axi_arsize => s_axi_arsize , + s_axi_arburst => s_axi_arburst , + s_axi_arlock => s_axi_arlock(0) , + s_axi_arcache => s_axi_arcache , + s_axi_arprot => s_axi_arprot , + s_axi_arvalid => s_axi_arvalid , + s_axi_arready => s_axi_arready , + s_axi_rid => s_axi_rid , + s_axi_rdata => s_axi_rdata , + s_axi_rresp => s_axi_rresp , + s_axi_rlast => s_axi_rlast , + s_axi_rvalid => s_axi_rvalid , + s_axi_rready => s_axi_rready , + + bram_clk_a => fb_ps_clk , + bram_en_a => fb_ps_en , + bram_we_a => fb_ps_we , + bram_addr_a => fb_ps_addr , + bram_wrdata_a => fb_ps_wrdata , + bram_rddata_a => fb_ps_rddata + + ); + + +end Behavioural; diff --git a/fpga/hp_lcd_driver/kbd_uarts.vhdl b/fpga/hp_lcd_driver/kbd_uarts.vhdl new file mode 100644 index 0000000..64bc3a3 --- /dev/null +++ b/fpga/hp_lcd_driver/kbd_uarts.vhdl @@ -0,0 +1,65 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use work.all; + +entity kbd_uarts is + port ( + s_axi_aclk : in STD_LOGIC; + s_axi_aresetn : in STD_LOGIC; + s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_awlock : in STD_LOGIC_VECTOR(1 downto 0); + s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_awvalid : in STD_LOGIC; + s_axi_awready : out STD_LOGIC; + s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_wlast : in STD_LOGIC; + s_axi_wvalid : in STD_LOGIC; + s_axi_wready : out STD_LOGIC; + s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_bvalid : out STD_LOGIC; + s_axi_bready : in STD_LOGIC; + s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_arlock : in STD_LOGIC_VECTOR( 1 downto 0); + s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_arvalid : in STD_LOGIC; + s_axi_arready : out STD_LOGIC; + s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_rlast : out STD_LOGIC; + s_axi_rvalid : out STD_LOGIC; + s_axi_rready : in STD_LOGIC; + + u0_tx: out std_logic; + u0_rx: in std_logic; + u0_int: out std_logic; + + u1_tx: out std_logic; + u1_rx: in std_logic; + u1_int: out std_logic +); +end kbd_uarts; +architecture Behavioural of kbd_uarts is +begin + + u0_int <= '0'; + u0_tx <='1'; + u1_int <= '0'; + u1_tx <='1'; + + + +end Behavioural; diff --git a/fpga/hp_lcd_driver/vnc_hw.vhdl b/fpga/hp_lcd_driver/vnc_hw.vhdl new file mode 100644 index 0000000..a4ea94a --- /dev/null +++ b/fpga/hp_lcd_driver/vnc_hw.vhdl @@ -0,0 +1,111 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use work.all; + +entity vnc_hw is + generic ( + video_width : integer := 2 + ); + port ( + vnc_clk : in std_logic; + vnc_valid : in std_logic; + vnc_data : in std_logic_vector(video_width -1 downto 0); + vnc_index : in std_logic; + + sys_rst_n : in std_logic; + + run : in std_logic; + + clk_50m : in std_logic; + + axi_aclk : in std_logic; + axi_aresetn : in std_logic; + + axi_awaddr : out std_logic_vector (31 downto 0); + axi_awvalid : out std_logic; + axi_awready : in std_logic; + axi_wdata : out std_logic_vector (63 downto 0); + axi_wstrb : out std_logic_vector (7 downto 0); + axi_wvalid : out std_logic; + axi_wready : in std_logic; + axi_bvalid : in std_logic; + axi_bready : out std_logic +); +end vnc_hw; +architecture Behavioural of vnc_hw is + + signal fifo_rst_cnt : natural; + signal fifo_rst : std_logic; + signal fifo_wr_en : std_logic; + signal fifo_wdata : std_logic_vector(64 downto 0); + signal fifo_rd_en : std_logic; + signal fifo_rdata : std_logic_vector(64 downto 0); + signal fifo_empty : std_logic; + +begin + + vnc_serializer_i : entity work.vnc_serializer + generic map ( + video_width => video_width + ) + port map ( + clk => vnc_clk, + vnc_valid => vnc_valid, + vnc_data => vnc_data, + vnc_index => vnc_index, + + fifo_data => fifo_wdata, + fifo_wren => fifo_wr_en); + + + process (clk_50m) + begin + if rising_edge(clk_50m) then + if sys_rst_n = '0' then + fifo_rst_cnt <= 20; + fifo_rst <= '1'; + elsif fifo_rst_cnt /= 0 then + fifo_rst_cnt <= fifo_rst_cnt -1; + else + fifo_rst <= '0'; + end if; + end if; + end process; + + fifo_i : entity work.fifo_generator_0 + port map ( + rst => fifo_rst, + wr_clk => vnc_clk, + din => fifo_wdata, + wr_en => fifo_wr_en, + rd_clk => axi_aclk, + rd_en => fifo_rd_en, + dout => fifo_rdata, + empty => fifo_empty + ); + + + + fifo_to_axi_i : entity work.fifo_to_axi + port map( + aclk => axi_aclk, + aresetn => axi_aresetn, + axi_awaddr => axi_awaddr, + axi_awvalid => axi_awvalid, + axi_awready => axi_awready, + axi_wdata => axi_wdata, + axi_wstrb => axi_wstrb, + axi_wvalid => axi_wvalid, + axi_wready => axi_wready, + axi_bvalid => axi_bvalid, + axi_bready => axi_bready, + + run => run, + + fifo_empty => fifo_empty, + fifo_rdata => fifo_rdata, + fifo_rd_en => fifo_rd_en + ); + +end Behavioural; diff --git a/fpga/hp_lcd_driver/zynq7.mk b/fpga/hp_lcd_driver/zynq7.mk index 05f5727..31afd86 100644 --- a/fpga/hp_lcd_driver/zynq7.mk +++ b/fpga/hp_lcd_driver/zynq7.mk @@ -7,7 +7,9 @@ IP= \ zynq7_ip/blk_mem_gen_1.tcl \ zynq7_ip/axi_bram_ctrl_0.tcl \ zynq7_ip/processing_system7_0.tcl \ - zynq7_ip/fifo_generator_0.tcl + zynq7_ip/fifo_generator_0.tcl \ + zynq7_ip/axi_uart16550_0.tcl \ + zynq7_ip/axi_crossbar_0.tcl BIT=${BUILD}/out/hp_lcd_driver.bit @@ -37,7 +39,10 @@ SRCS= ${IP} \ vram_artix7.vhdl \ zynq7_wrapper.vhdl \ fifo_to_axi.vhdl \ - vnc_serializer.vhdl + vnc_hw.vhdl \ + vnc_serializer.vhdl \ + fb_hw.vhdl \ + kbd_uarts.vhdl diff --git a/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl b/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl index 7887f6a..a73d793 100644 --- a/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl +++ b/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl @@ -20,7 +20,7 @@ if {[llength $files] != 0} { #read_verilog [ glob ../source/*.v ] #read_vhdl -vhdl2008 -library work [ glob ../source/*.vhdl ] -read_vhdl -vhdl2008 -library work { ../zynq7_wrapper.vhdl ../fifo_to_axi.vhdl ../clkgen_artix7.vhdl ../debounce.vhdl ../delay.vhdl ../edge_det.vhdl ../common.vhdl ../input_formatter.vhdl ../input_stage.vhdl ../output_analog.vhdl ../output_formatter.vhdl ../output_stage.vhdl ../synchronizer.vhdl ../tmds_encoder.vhdl ../tmds_encode.vhdl ../tmds_output_artix7.vhdl ../tmds_phy_artix7.vhdl ../vram_artix7.vhdl ../vnc_serializer.vhdl } +read_vhdl -vhdl2008 -library work { ../zynq7_wrapper.vhdl ../fifo_to_axi.vhdl ../clkgen_artix7.vhdl ../debounce.vhdl ../delay.vhdl ../edge_det.vhdl ../common.vhdl ../input_formatter.vhdl ../input_stage.vhdl ../output_analog.vhdl ../output_formatter.vhdl ../output_stage.vhdl ../synchronizer.vhdl ../tmds_encoder.vhdl ../tmds_encode.vhdl ../tmds_output_artix7.vhdl ../tmds_phy_artix7.vhdl ../vram_artix7.vhdl ../vnc_hw.vhdl ../vnc_serializer.vhdl ../fb_hw.vhdl ../kbd_uarts.vhdl } set generics {} append generics { } "video_width=$video_width" @@ -38,6 +38,8 @@ read_ip $ip_dir/blk_mem_gen_1/blk_mem_gen_1.xci read_ip $ip_dir/axi_bram_ctrl_0/axi_bram_ctrl_0.xci read_ip $ip_dir/processing_system7_0/processing_system7_0.xci read_ip $ip_dir/fifo_generator_0/fifo_generator_0.xci +read_ip $ip_dir/axi_uart16550_0/axi_uart16550_0.xci +read_ip $ip_dir/axi_crossbar_0/axi_crossbar_0.xci read_xdc $normal_xdc diff --git a/fpga/hp_lcd_driver/zynq7_ip/axi_crossbar_0.tcl b/fpga/hp_lcd_driver/zynq7_ip/axi_crossbar_0.tcl new file mode 100644 index 0000000..d297c7a --- /dev/null +++ b/fpga/hp_lcd_driver/zynq7_ip/axi_crossbar_0.tcl @@ -0,0 +1,50 @@ +set source_dir [file dirname [file dirname [file normalize [info script]]]] + +source $source_dir/zynq7_config.tcl + + +create_ip -name axi_crossbar -vendor xilinx.com -library ip -version 2.1 -module_name axi_crossbar_0 -dir $ip_dir + +set_property -dict [list \ + CONFIG.NUM_SI {1} \ + CONFIG.NUM_MI {2} \ + CONFIG.ID_WIDTH {12} \ + CONFIG.S00_THREAD_ID_WIDTH {12} \ + CONFIG.S01_THREAD_ID_WIDTH {12} \ + CONFIG.S02_THREAD_ID_WIDTH {12} \ + CONFIG.S03_THREAD_ID_WIDTH {12} \ + CONFIG.S04_THREAD_ID_WIDTH {12} \ + CONFIG.S05_THREAD_ID_WIDTH {12} \ + CONFIG.S06_THREAD_ID_WIDTH {12} \ + CONFIG.S07_THREAD_ID_WIDTH {12} \ + CONFIG.S08_THREAD_ID_WIDTH {12} \ + CONFIG.S09_THREAD_ID_WIDTH {12} \ + CONFIG.S10_THREAD_ID_WIDTH {12} \ + CONFIG.S11_THREAD_ID_WIDTH {12} \ + CONFIG.S12_THREAD_ID_WIDTH {12} \ + CONFIG.S13_THREAD_ID_WIDTH {12} \ + CONFIG.S14_THREAD_ID_WIDTH {12} \ + CONFIG.S15_THREAD_ID_WIDTH {12} \ + CONFIG.S01_BASE_ID {0x00001000} \ + CONFIG.S02_BASE_ID {0x00002000} \ + CONFIG.S03_BASE_ID {0x00003000} \ + CONFIG.S04_BASE_ID {0x00004000} \ + CONFIG.S05_BASE_ID {0x00005000} \ + CONFIG.S06_BASE_ID {0x00006000} \ + CONFIG.S07_BASE_ID {0x00007000} \ + CONFIG.S08_BASE_ID {0x00008000} \ + CONFIG.S09_BASE_ID {0x00009000} \ + CONFIG.S10_BASE_ID {0x0000a000} \ + CONFIG.S11_BASE_ID {0x0000b000} \ + CONFIG.S12_BASE_ID {0x0000c000} \ + CONFIG.S13_BASE_ID {0x0000d000} \ + CONFIG.S14_BASE_ID {0x0000e000} \ + CONFIG.S15_BASE_ID {0x0000f000} \ + CONFIG.M00_A00_BASE_ADDR {0x0000000000000000} \ + CONFIG.M01_A00_BASE_ADDR {0x0000000000001000} \ + ] [get_ips axi_crossbar_0] + +generate_target all [get_ips] + +synth_ip [get_ips] + diff --git a/fpga/hp_lcd_driver/zynq7_ip/axi_uart16550_0.tcl b/fpga/hp_lcd_driver/zynq7_ip/axi_uart16550_0.tcl new file mode 100644 index 0000000..7005584 --- /dev/null +++ b/fpga/hp_lcd_driver/zynq7_ip/axi_uart16550_0.tcl @@ -0,0 +1,11 @@ +set source_dir [file dirname [file dirname [file normalize [info script]]]] + +source $source_dir/zynq7_config.tcl + + +create_ip -name axi_uart16550 -vendor xilinx.com -library ip -version 2.0 -module_name axi_uart16550_0 -dir $ip_dir + +generate_target all [get_ips] + +synth_ip [get_ips] + diff --git a/fpga/hp_lcd_driver/zynq7_wrapper.vhdl b/fpga/hp_lcd_driver/zynq7_wrapper.vhdl index 0e7367e..6e90760 100644 --- a/fpga/hp_lcd_driver/zynq7_wrapper.vhdl +++ b/fpga/hp_lcd_driver/zynq7_wrapper.vhdl @@ -100,21 +100,6 @@ end entity zynq7_wrapper; architecture arch of zynq7_wrapper is - type t_palette is array (0 to 15) of std_logic_vector(7 downto 0); - constant r_lut : t_palette := ( - x"00", x"00", x"00", x"00", x"AA", x"AA", x"AA", x"AA", - x"55", x"55", x"55", x"55", x"FF", x"FF", x"FF", x"FF" - ); - constant g_lut : t_palette := ( - x"00", x"00", x"AA", x"AA", x"00", x"00", x"55", x"AA", - x"55", x"55", x"FF", x"FF", x"55", x"55", x"FF", x"FF" - ); - constant b_lut : t_palette := ( - x"00", x"AA", x"00", x"AA", x"00", x"AA", x"00", x"AA", - x"55", x"FF", x"55", x"FF", x"55", x"FF", x"55", x"FF" - ); - - signal eth0_gmii_txd : std_logic_vector(7 downto 0); signal eth0_gmii_rxd : std_logic_vector(7 downto 0); @@ -183,14 +168,6 @@ architecture arch of zynq7_wrapper is signal hp0_wstrb : std_logic_vector(7 downto 0); - signal fifo_rst_cnt : natural; - signal fifo_rst : std_logic; - signal fifo_wr_en : std_logic; - signal fifo_wdata : std_logic_vector(64 downto 0); - signal fifo_rd_en : std_logic; - signal fifo_rdata : std_logic_vector(64 downto 0); - signal fifo_empty : std_logic; - signal run : std_logic; signal eth0_mdio_mdio_i : std_logic; @@ -206,27 +183,13 @@ architecture arch of zynq7_wrapper is signal clk_50m_ps : std_logic; - signal overlay_addr : std_logic_vector(addr_width-1 downto 0); signal overlay_clk : std_logic; - signal overlay_demux_p :integer; - signal overlay_demux :integer; - signal overlay_data : integer; + signal overlay_addr : std_logic_vector(addr_width-1 downto 0); signal overlay_gate : std_logic; signal overlay_r : std_logic_vector(7 downto 0); signal overlay_g : std_logic_vector(7 downto 0); signal overlay_b : std_logic_vector(7 downto 0); - - signal fb_ps_clk : STD_LOGIC; - signal fb_ps_en : STD_LOGIC; - signal fb_ps_we : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal fb_ps_addr : STD_LOGIC_VECTOR ( 19 downto 0 ); - signal fb_ps_wrdata : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal fb_ps_rddata : STD_LOGIC_VECTOR ( 31 downto 0 ); - - signal fb_pl_addr : STD_LOGIC_VECTOR ( 14 downto 0 ); - signal fb_pl_rddata : STD_LOGIC_VECTOR ( 31 downto 0 ); - begin @@ -420,52 +383,25 @@ begin ); - vnc_serializer_i : entity work.vnc_serializer + vnc_hw_i: entity work.vnc_hw generic map ( video_width => video_width ) port map ( - clk => vnc_clk, + vnc_clk => vnc_clk, vnc_valid => vnc_valid, vnc_data => vnc_data, vnc_index => vnc_index, - fifo_data => fifo_wdata, - fifo_wren => fifo_wr_en); - - - process (clk_50m_ps) - begin - if rising_edge(clk_50m_ps) then - if sys_rst_n = '0' then - fifo_rst_cnt <= 20; - fifo_rst <= '1'; - elsif fifo_rst_cnt /= 0 then - fifo_rst_cnt <= fifo_rst_cnt -1; - else - fifo_rst <= '0'; - end if; - end if; - end process; - - fifo_i : entity work.fifo_generator_0 - port map ( - rst => fifo_rst, - wr_clk => vnc_clk, - din => fifo_wdata, - wr_en => fifo_wr_en, - rd_clk => hp0_aclk, - rd_en => fifo_rd_en, - dout => fifo_rdata, - empty => fifo_empty - ); + sys_rst_n => sys_rst_n, + + run => run, + clk_50m => clk_50m_ps, + axi_aclk => hp0_aclk, + axi_aresetn => hp0_nrst, - fifo_to_axi_i : entity work.fifo_to_axi - port map( - aclk => hp0_aclk, - aresetn => hp0_nrst, axi_awaddr => hp0_awaddr, axi_awvalid => hp0_awvalid, axi_awready => hp0_awready, @@ -474,79 +410,24 @@ begin axi_wvalid => hp0_wvalid, axi_wready => hp0_wready, axi_bvalid => hp0_bvalid, - axi_bready => hp0_bready, - - run => run, - - fifo_empty => fifo_empty, - fifo_rdata => fifo_rdata, - fifo_rd_en => fifo_rd_en - ); - - fb_ram0: entity work.blk_mem_gen_1 - port map ( - clka => fb_ps_clk, - ena => fb_ps_en, - wea => fb_ps_we, - addra => fb_ps_addr (15 downto 2), - dina => fb_ps_wrdata, - douta => fb_ps_rddata, - clkb => overlay_clk, - web => "0000", - addrb => fb_pl_addr, - dinb => x"00000000", - doutb => fb_pl_rddata - ); + axi_bready => hp0_bready + ); - - fb_pl_addr <= overlay_addr(17 downto 3); - - process (overlay_clk) begin - if rising_edge(overlay_clk) then - overlay_demux_p <= to_integer(unsigned(overlay_addr(2 downto 0)))*4; - overlay_demux <=overlay_demux_p; - end if; - end process; - - overlay_data <= to_integer(unsigned(fb_pl_rddata(overlay_demux+3 downto overlay_demux))); - - overlay_gate <= '0' when overlay_data = 0 else '1'; - overlay_r <= r_lut(overlay_data); - overlay_g <= g_lut(overlay_data); - overlay_b <= b_lut(overlay_data); - - - -- fb_ps_rddata <=x"9abcdef0"; - - --- ps_fb_rddata<=x"12345678"; --- pl_fb_rddata<=x"9abcdef0"; - - --- signal fb_ps_clk : STD_LOGIC; --- signal fb_ps_en : STD_LOGIC; --- signal fb_ps_we : STD_LOGIC_VECTOR ( 3 downto 0 ); --- signal fb_ps_addr : STD_LOGIC_VECTOR ( 19 downto 0 ); --- signal fb_ps_wrdata : STD_LOGIC_VECTOR ( 31 downto 0 ); --- signal fb_ps_rddata : STD_LOGIC_VECTOR ( 31 downto 0 ) --- - --- --- --- overlay_data <= "00"; - - axi_bram_ctrl_0_i : entity work.axi_bram_ctrl_0 + fb_hw_i: entity work.fb_hw + generic map ( + addr_width => addr_width + ) port map ( s_axi_aclk => gp0_aclk, s_axi_aresetn => gp0_nrst, s_axi_awid => gp0_awid , - s_axi_awaddr => gp0_awaddr(19 downto 0) , + s_axi_awaddr => gp0_awaddr, s_axi_awlen => gp0_awlen , s_axi_awsize => gp0_awsize , s_axi_awburst => gp0_awburst , - s_axi_awlock => gp0_awlock(0) , + s_axi_awlock => gp0_awlock , s_axi_awcache => gp0_awcache , s_axi_awprot => gp0_awprot , s_axi_awvalid => gp0_awvalid , @@ -561,11 +442,11 @@ begin s_axi_bvalid => gp0_bvalid , s_axi_bready => gp0_bready , s_axi_arid => gp0_arid , - s_axi_araddr => gp0_araddr(19 downto 0) , - s_axi_arlen => gp0_arlen , + s_axi_araddr => gp0_araddr, + s_axi_arlen => gp0_arlen, s_axi_arsize => gp0_arsize , s_axi_arburst => gp0_arburst , - s_axi_arlock => gp0_arlock(0) , + s_axi_arlock => gp0_arlock , s_axi_arcache => gp0_arcache , s_axi_arprot => gp0_arprot , s_axi_arvalid => gp0_arvalid , @@ -576,16 +457,15 @@ begin s_axi_rlast => gp0_rlast , s_axi_rvalid => gp0_rvalid , s_axi_rready => gp0_rready , + overlay_clk => overlay_clk, + overlay_addr => overlay_addr, + overlay_gate => overlay_gate, + overlay_r => overlay_r, + overlay_g =>overlay_g, + overlay_b => overlay_b +); - bram_clk_a => fb_ps_clk , - bram_en_a => fb_ps_en , - bram_we_a => fb_ps_we , - bram_addr_a => fb_ps_addr , - bram_wrdata_a => fb_ps_wrdata , - bram_rddata_a => fb_ps_rddata - - ); hp0_araddr <= (others => '0'); hp0_arvalid <= '0'; |