diff options
| -rw-r--r-- | spartan6/hp_lcd_driver/Makefile | 31 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/hp_lcd_driver.ucf | 19 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/hp_lcd_driver.vhdl | 77 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/input_formatter.vhdl | 113 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/output_formatter.vhdl | 2 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/output_stage.vhdl | 6 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/pll_50_80.xco | 269 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/pll_50_p10_p2_p.xco | 269 | ||||
| -rw-r--r-- | spartan6/hp_lcd_driver/tmds_output.vhdl | 26 |
9 files changed, 137 insertions, 675 deletions
diff --git a/spartan6/hp_lcd_driver/Makefile b/spartan6/hp_lcd_driver/Makefile index 39963a2..e1beea7 100644 --- a/spartan6/hp_lcd_driver/Makefile +++ b/spartan6/hp_lcd_driver/Makefile @@ -1,14 +1,17 @@ include relpath.mk +XILNXD_LICENSE_FILE:=${PWD}/xilinx_ise_vivado_license.lic +export XILINXD_LICENSE_FILE PART=xc6slx9-2-tqg144 TOP=hp_lcd_driver BUILD=build -VSRCS=synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl serdes_n_to_1.vhdl tmds_encoder.vhdl tmds_phy.vhdl tmds_output.vhdl output_stage.vhdl hp_lcd_driver.vhdl +VSRCS=synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl serdes_n_to_1.vhdl tmds_encoder.vhdl tmds_phy.vhdl tmds_output.vhdl output_stage.vhdl clkgen.vhdl hp_lcd_driver.vhdl UCF=hp_lcd_driver.ucf UT=hp_lcd_driver.ut -IPSRCS= pll_50_80.xco pll_50_p10_p2_p.xco vram.xco +IPSRCS=vram.xco DESIGN_NAME=${TOP} -ISE_HOME=/software/apps/xilinx/ISE/14.7/ISE_DS/ISE +DS_HOME=/software/apps/xilinx/ISE/14.7/ISE_DS +ISE_HOME=${DS_HOME}/ISE ISE_BINDIR_32=${ISE_HOME}/bin/lin ISE_BINDIR_64=${ISE_HOME}/bin/lin64 INTSTYLE= @@ -36,6 +39,8 @@ TWR=${BASE}.twr TWX=${BASE}.twx BIT=${BASE}.bit SVF=${BASE}.svf +PA=${BUILD}/pa +PAT=${PA}/script.tcl XST_TMPDIR=xst/projnav.tmp XST_DIR=xst @@ -97,6 +102,26 @@ ${BUILD}/%.vhd:%.xco (cd ${BUILD} && touch empty.prj && ${ISE_BINDIR_32}/coregen -b $(call relpath,$<,${BUILD}) -p empty.prj) +planahead: ${NGC} ${TWX} + rm -rf ${PA} + mkdir -p ${PA} + echo 'create_project -name ${TOP} -dir "$(abspath ${PA})" -part ${PART}' >> ${PAT} + echo 'set srcset [get_property srcset [current_run -impl]]' >> ${PAT} + echo 'set_property design_mode GateLvl $$srcset' >> ${PAT} + echo 'set_property top ${TOP} [current_fileset]' >> ${PAT} + echo 'set_property edif_top_file "$(abspasth ${NGC})" [ get_property srcset [ current_run ] ]' >> ${PAT} + echo 'add_files -norecurse { {$(abspath ${BUILD})} }' >> ${PAT} + echo 'set_property target_constrs_file "$(abspath ${UCF})" [current_fileset -constrset]' >> ${PAT} + echo 'add_files [list {$(abspath ${UCF})}] -fileset [get_property constrset [current_run]]' >> ${PAT} + echo 'link_design' >> ${PAT} + echo 'read_xdl -file "$(abspath ${NCD})"' >> ${PAT} + echo 'if {[catch {read_twx -name results_1 -file "$(abspath ${TWX})"} eInfo]} {' >> ${PAT} + echo 'puts "WARNING: there was a problem importing \"$(abspath ${TWX})\": $$eInfo"' >> ${PAT} + echo '}' >> ${PAT} + (cd ${PA} && ${DS_HOME}/PlanAhead/bin/planAhead -log $(abspath ${PA}/pa.log) -journal $(abspath ${PA}/pa.jou) -source $(abspath ${PAT})) + + + tidy: git diff --exit-code -s ${VSRCS} for i in ${VSRCS}; do /bin/cp -f $$i $$i.orig && scripts/vhdl-pretty < $$i.orig > $$i; done diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.ucf b/spartan6/hp_lcd_driver/hp_lcd_driver.ucf index 4864b7c..c30e6e3 100644 --- a/spartan6/hp_lcd_driver/hp_lcd_driver.ucf +++ b/spartan6/hp_lcd_driver/hp_lcd_driver.ucf @@ -3,8 +3,8 @@ NET "clk_50m" IOSTANDARD = LVCMOS33; NET "sys_rst_n" IOSTANDARD = LVCMOS33; -NET "video(0)" IOSTANDARD = LVCMOS33; -NET "video(1)" IOSTANDARD = LVCMOS33; +NET "video[0]" IOSTANDARD = LVCMOS33; +NET "video[1]" IOSTANDARD = LVCMOS33; NET "hsync_in" IOSTANDARD = LVCMOS33; NET "vsync_in" IOSTANDARD = LVCMOS33; NET "r_out" IOSTANDARD = LVCMOS33; @@ -14,10 +14,21 @@ NET "hsync_out" IOSTANDARD = LVCMOS33; NET "vsync_out" IOSTANDARD = LVCMOS33; -INST "pll" LOC = "PLL_ADV_X0Y1"; -INST "ioclk_buf" LOC = "BUFPLL_X1Y0"; +INST "clkgen/pll" LOC = PLL_ADV_X0Y1; +INST "output0/tmds/ioclk_buf" LOC = BUFPLL_X1Y5; +NET "hdmi_c_p" LOC = P144; +NET "hdmi_c_n" LOC = P143; +NET "hdmi_r_p" LOC = P142; +NET "hdmi_r_n" LOC = P141; +NET "hdmi_g_p" LOC = P140; +NET "hdmi_g_n" LOC = P139; + + +NET "clk_50m" PERIOD = 20 ns; +NET "hdmi_b_p" LOC = P138; +NET "hdmi_b_n" LOC = P137; diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl b/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl index ba0c460..d37db58 100644 --- a/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl +++ b/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl @@ -71,78 +71,30 @@ architecture Behavioral of hp_lcd_driver is signal b : std_logic_vector(7 downto 0); + signal clk_locked : std_logic; + signal i_clk : std_logic; - signal o_clk_locked : std_logic; signal o_clk : std_logic; signal o_clk_x2 : std_logic; signal o_clk_x10 : std_logic; - signal serdesstrobe : std_logic; - - signal clkfbout : std_logic; - signal clk_200m : std_logic; - signal clk_80m : std_logic; - signal clk_40m : std_logic; - signal clk_20m : std_logic; - signal pll_locked : std_logic; - signal pll_locked_n : std_logic; - signal sys_rst : std_logic; begin - - - pll : PLL_BASE generic map ( - CLKIN_PERIOD => 20.0, - CLKFBOUT_MULT => 8, - CLKOUT0_DIVIDE => 2, - CLKOUT1_DIVIDE => 5, - CLKOUT2_DIVIDE => 10, - CLKOUT3_DIVIDE => 20, - COMPENSATION => "INTERNAL") - port map ( - CLKFBOUT => clkfbout, - CLKOUT0 => clk_200m, - CLKOUT1 => clk_80m, - CLKOUT2 => clk_40m, - CLKOUT3 => clk_20m, - LOCKED => pll_locked, - CLKFBIN => clkfbout, - CLKIN => clk_50m, - RST => pll_locked_n); - - pll_locked_n <= not pll_locked; - - - - - ioclk_buf : BUFPLL generic map (DIVIDE => 5) - port map ( - PLLIN => clk_200m, - GCLK => o_clk_x2, - LOCKED => pll_locked, - IOCLK => o_clk_x10, - SERDESSTROBE => serdesstrobe, - LOCK => o_clk_locked); - - o_clk_buf : BUFG port map ( - I =>clk_20m, - O =>o_clk); - - - o_clk_x2_buf : BUFG port map ( - I =>clk_40m, - O =>o_clk_x2); - - - i_clk_buf : BUFG port map ( - I =>clk_80m, - O =>i_clk); - - + clkgen: entity work.clkgen + port map ( + sys_rst_n => sys_rst_n, + clk_in => clk_50m, + i_clk => i_clk, + o_clk => o_clk, + o_clk_x2 => o_clk_x2, + o_clk_x10 => o_clk_x10, + locked => clk_locked + + ); input0 : entity work.input_stage generic map( @@ -207,11 +159,10 @@ begin v_stride => 384 ) port map( - clk_locked => o_clk_locked, + clk_locked => clk_locked, clk => o_clk, clk_x2 => o_clk_x2, clk_x10 => o_clk_x10, - serdesstrobe => serdesstrobe, sys_rst_n => sys_rst_n, vsync_in => vsync_in, r_in => r, diff --git a/spartan6/hp_lcd_driver/input_formatter.vhdl b/spartan6/hp_lcd_driver/input_formatter.vhdl index ef1cc0d..ecde480 100644 --- a/spartan6/hp_lcd_driver/input_formatter.vhdl +++ b/spartan6/hp_lcd_driver/input_formatter.vhdl @@ -33,11 +33,13 @@ architecture beh of input_formatter is signal addr : std_logic_vector(addr_width-1 downto 0); signal wren : std_logic; - signal hsync_pe : std_logic; signal hsync_ne : std_logic; - signal fp_counter : natural; - signal active_counter : natural; + signal v_fp_counter : natural; + signal v_active_counter : natural; + signal h_fp_counter : natural; + signal h_active_counter : natural; + signal h_div:natural; begin @@ -47,64 +49,63 @@ begin port map( clk => clk, sig => hsync, - pe => hsync_pe, + e => open, + pe => open, ne => hsync_ne); - addr <= (others => '0'); addr_out <= addr; - wren_out <= '0'; - - ----- horizontal state machine --- --- process (sys_rst_n,p_clk,d_hsync,d_vsync) begin --- if sys_rst_n = '0' then --- row_addr<=(others =>'0'); --- addr<=(others =>'0'); --- p_clk_div<=p_clk_multiple; --- active_counter <=0; --- fp_counter <=0; --- elsif rising_edge(p_clk) then --- if d_vsync='1' then --- row_addr<=(others => '0'); --- addr<=(others => '0'); --- fp_counter <= front_porch; --- active_counter <=hres; --- p_clk_div <=p_clk_multiple; --- elsif pe_gsync ='1' then --- row_addr <= std_logic_vector(unsigned(row_addr)+1); --- elsif ne_hsync='1' then --- fp_counter <= front_porch; --- active_counter <=hres; --- p_clk_div <=p_clk_multiple; --- addr<=row_addr; --- elsif fp_counter /= 0 then --- fp_counter <= fp_counter -1; --- elsif active_counter /= 0 then --- if p_clk_div = 0 then --- p_clk_div <=p_clk_multiple; --- active_counter <= active_counter -1; --- addr <= std_logic_vector(unsigned(addr)+vres); --- else --- p_clk_div <= p_clk_div - 1; --- end if; --- else --- p_clk_div <=p_clk_multiple; --- end if; --- end if; --- end process; --- --- --- wren <= '1' when p_clk_div=2 else '0'; --- --- addr_out <= addr; --- video_out <= (s_video, s_bright); --- wren_out <= wren; --- --- p_clk_out <= p_clk; --- + + + process (sys_rst_n,clk,hsync_ne,vsync) begin + if sys_rst_n = '0' then + row_addr<=(others =>'0'); + addr<=(others =>'0'); + h_div <=0; + h_active_counter <=0; + h_fp_counter <=0; + v_active_counter <=0; + v_fp_counter <=0; + elsif rising_edge(clk) then + if hsync_ne = '1' then + if vsync='1' then + row_addr<=(others =>'0'); + v_fp_counter <= v_front_porch; + v_active_counter <= v_active; + elsif v_fp_counter /= 0 then + v_fp_counter <= v_fp_counter -1; + elsif v_active_counter /= 0 then + v_active_counter <=v_active_counter -1; + + h_fp_counter <= h_front_porch * clk_multiple + phase; + h_active_counter <= h_active; + h_div <=0; + + addr<=row_addr; + row_addr<=std_logic_vector(unsigned(row_addr)+v_stride); + end if; + elsif h_fp_counter /= 0 then + h_fp_counter <= h_fp_counter -1; + elsif h_active_counter /= 0 then + + if h_div = 0 then + wren <='1'; + h_div <= clk_multiple -1; + elsif h_div =clk_multiple -1 then + wren <='0'; + h_active_counter <= h_active_counter -1; + addr<=std_logic_vector(unsigned(addr)+h_stride); + h_div <=clk_multiple -1; + else + h_div <=clk_multiple -1; + end if; + end if; + end if; + end process; + + addr_out <= addr; + wren_out <= wren; end beh; diff --git a/spartan6/hp_lcd_driver/output_formatter.vhdl b/spartan6/hp_lcd_driver/output_formatter.vhdl index 4f35e35..4969b8a 100644 --- a/spartan6/hp_lcd_driver/output_formatter.vhdl +++ b/spartan6/hp_lcd_driver/output_formatter.vhdl @@ -53,6 +53,8 @@ begin port map( clk => clk, sig => vsync_in, + e => open, + pe => open, ne => vsync_in_ne); process (clk, vsync_in_ne, sys_rst_n) diff --git a/spartan6/hp_lcd_driver/output_stage.vhdl b/spartan6/hp_lcd_driver/output_stage.vhdl index d4b3d9f..0b04de0 100644 --- a/spartan6/hp_lcd_driver/output_stage.vhdl +++ b/spartan6/hp_lcd_driver/output_stage.vhdl @@ -28,7 +28,6 @@ entity output_stage is clk : in std_logic; clk_x2 : in std_logic; clk_x10 : in std_logic; - serdesstrobe : in std_logic; sys_rst_n : in std_logic; vsync_in : in std_logic; @@ -117,7 +116,7 @@ begin addr_out <= addr; - output_analog : entity work.output_analog + analog : entity work.output_analog port map( sys_rst_n => sys_rst_n, @@ -139,14 +138,13 @@ begin - output_tmds : entity work.tmds_output + tmds : entity work.tmds_output port map ( sys_rst_n => sys_rst_n, pclk_locked => clk_locked, pclk => clk, pclk_x2 => clk_x2, pclk_x10 => clk_x10, - serdesstrobe => serdesstrobe, r_in => r_in, g_in => g_in, diff --git a/spartan6/hp_lcd_driver/pll_50_80.xco b/spartan6/hp_lcd_driver/pll_50_80.xco deleted file mode 100644 index b175ef8..0000000 --- a/spartan6/hp_lcd_driver/pll_50_80.xco +++ /dev/null @@ -1,269 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.7 -# Date: Sat Apr 26 17:50:20 2025 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:clk_wiz:3.6 -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc6slx9 -SET devicefamily = spartan6 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = tqg144 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -2 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6 -# END Select -# BEGIN Parameters -CSET calc_done=DONE -CSET clk_in_sel_port=CLK_IN_SEL -CSET clk_out1_port=clk_80_out -CSET clk_out1_use_fine_ps_gui=false -CSET clk_out2_port=CLK_OUT2 -CSET clk_out2_use_fine_ps_gui=false -CSET clk_out3_port=CLK_OUT3 -CSET clk_out3_use_fine_ps_gui=false -CSET clk_out4_port=CLK_OUT4 -CSET clk_out4_use_fine_ps_gui=false -CSET clk_out5_port=CLK_OUT5 -CSET clk_out5_use_fine_ps_gui=false -CSET clk_out6_port=CLK_OUT6 -CSET clk_out6_use_fine_ps_gui=false -CSET clk_out7_port=CLK_OUT7 -CSET clk_out7_use_fine_ps_gui=false -CSET clk_valid_port=CLK_VALID -CSET clkfb_in_n_port=CLKFB_IN_N -CSET clkfb_in_p_port=CLKFB_IN_P -CSET clkfb_in_port=CLKFB_IN -CSET clkfb_in_signaling=SINGLE -CSET clkfb_out_n_port=CLKFB_OUT_N -CSET clkfb_out_p_port=CLKFB_OUT_P -CSET clkfb_out_port=CLKFB_OUT -CSET clkfb_stopped_port=CLKFB_STOPPED -CSET clkin1_jitter_ps=200.0 -CSET clkin1_ui_jitter=0.010 -CSET clkin2_jitter_ps=100.0 -CSET clkin2_ui_jitter=0.010 -CSET clkout1_drives=BUFG -CSET clkout1_requested_duty_cycle=50.000 -CSET clkout1_requested_out_freq=80.000 -CSET clkout1_requested_phase=0.000 -CSET clkout2_drives=BUFG -CSET clkout2_requested_duty_cycle=50.000 -CSET clkout2_requested_out_freq=100.000 -CSET clkout2_requested_phase=0.000 -CSET clkout2_used=false -CSET clkout3_drives=BUFG -CSET clkout3_requested_duty_cycle=50.000 -CSET clkout3_requested_out_freq=100.000 -CSET clkout3_requested_phase=0.000 -CSET clkout3_used=false -CSET clkout4_drives=BUFG -CSET clkout4_requested_duty_cycle=50.000 -CSET clkout4_requested_out_freq=100.000 -CSET clkout4_requested_phase=0.000 -CSET clkout4_used=false -CSET clkout5_drives=BUFG -CSET clkout5_requested_duty_cycle=50.000 -CSET clkout5_requested_out_freq=100.000 -CSET clkout5_requested_phase=0.000 -CSET clkout5_used=false -CSET clkout6_drives=BUFG -CSET clkout6_requested_duty_cycle=50.000 -CSET clkout6_requested_out_freq=100.000 -CSET clkout6_requested_phase=0.000 -CSET clkout6_used=false -CSET clkout7_drives=BUFG -CSET clkout7_requested_duty_cycle=50.000 -CSET clkout7_requested_out_freq=100.000 -CSET clkout7_requested_phase=0.000 -CSET clkout7_used=false -CSET clock_mgr_type=AUTO -CSET component_name=pll_50_80 -CSET daddr_port=DADDR -CSET dclk_port=DCLK -CSET dcm_clk_feedback=1X -CSET dcm_clk_out1_port=CLKFX -CSET dcm_clk_out2_port=CLK0 -CSET dcm_clk_out3_port=CLK0 -CSET dcm_clk_out4_port=CLK0 -CSET dcm_clk_out5_port=CLK0 -CSET dcm_clk_out6_port=CLK0 -CSET dcm_clkdv_divide=2.0 -CSET dcm_clkfx_divide=5 -CSET dcm_clkfx_multiply=8 -CSET dcm_clkgen_clk_out1_port=CLKFX -CSET dcm_clkgen_clk_out2_port=CLKFX -CSET dcm_clkgen_clk_out3_port=CLKFX -CSET dcm_clkgen_clkfx_divide=1 -CSET dcm_clkgen_clkfx_md_max=0.000 -CSET dcm_clkgen_clkfx_multiply=4 -CSET dcm_clkgen_clkfxdv_divide=2 -CSET dcm_clkgen_clkin_period=10.000 -CSET dcm_clkgen_notes=None -CSET dcm_clkgen_spread_spectrum=NONE -CSET dcm_clkgen_startup_wait=false -CSET dcm_clkin_divide_by_2=false -CSET dcm_clkin_period=20.000 -CSET dcm_clkout_phase_shift=NONE -CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS -CSET dcm_notes=None -CSET dcm_phase_shift=0 -CSET dcm_pll_cascade=NONE -CSET dcm_startup_wait=false -CSET den_port=DEN -CSET din_port=DIN -CSET dout_port=DOUT -CSET drdy_port=DRDY -CSET dwe_port=DWE -CSET feedback_source=FDBK_AUTO -CSET in_freq_units=Units_MHz -CSET in_jitter_units=Units_UI -CSET input_clk_stopped_port=INPUT_CLK_STOPPED -CSET jitter_options=UI -CSET jitter_sel=No_Jitter -CSET locked_port=LOCKED -CSET mmcm_bandwidth=OPTIMIZED -CSET mmcm_clkfbout_mult_f=4.000 -CSET mmcm_clkfbout_phase=0.000 -CSET mmcm_clkfbout_use_fine_ps=false -CSET mmcm_clkin1_period=10.000 -CSET mmcm_clkin2_period=10.000 -CSET mmcm_clkout0_divide_f=4.000 -CSET mmcm_clkout0_duty_cycle=0.500 -CSET mmcm_clkout0_phase=0.000 -CSET mmcm_clkout0_use_fine_ps=false -CSET mmcm_clkout1_divide=1 -CSET mmcm_clkout1_duty_cycle=0.500 -CSET mmcm_clkout1_phase=0.000 -CSET mmcm_clkout1_use_fine_ps=false -CSET mmcm_clkout2_divide=1 -CSET mmcm_clkout2_duty_cycle=0.500 -CSET mmcm_clkout2_phase=0.000 -CSET mmcm_clkout2_use_fine_ps=false -CSET mmcm_clkout3_divide=1 -CSET mmcm_clkout3_duty_cycle=0.500 -CSET mmcm_clkout3_phase=0.000 -CSET mmcm_clkout3_use_fine_ps=false -CSET mmcm_clkout4_cascade=false -CSET mmcm_clkout4_divide=1 -CSET mmcm_clkout4_duty_cycle=0.500 -CSET mmcm_clkout4_phase=0.000 -CSET mmcm_clkout4_use_fine_ps=false -CSET mmcm_clkout5_divide=1 -CSET mmcm_clkout5_duty_cycle=0.500 -CSET mmcm_clkout5_phase=0.000 -CSET mmcm_clkout5_use_fine_ps=false -CSET mmcm_clkout6_divide=1 -CSET mmcm_clkout6_duty_cycle=0.500 -CSET mmcm_clkout6_phase=0.000 -CSET mmcm_clkout6_use_fine_ps=false -CSET mmcm_clock_hold=false -CSET mmcm_compensation=ZHOLD -CSET mmcm_divclk_divide=1 -CSET mmcm_notes=None -CSET mmcm_ref_jitter1=0.010 -CSET mmcm_ref_jitter2=0.010 -CSET mmcm_startup_wait=false -CSET num_out_clks=1 -CSET override_dcm=false -CSET override_dcm_clkgen=false -CSET override_mmcm=false -CSET override_pll=false -CSET platform=lin -CSET pll_bandwidth=OPTIMIZED -CSET pll_clk_feedback=CLKFBOUT -CSET pll_clkfbout_mult=4 -CSET pll_clkfbout_phase=0.000 -CSET pll_clkin_period=10.000 -CSET pll_clkout0_divide=1 -CSET pll_clkout0_duty_cycle=0.500 -CSET pll_clkout0_phase=0.000 -CSET pll_clkout1_divide=1 -CSET pll_clkout1_duty_cycle=0.500 -CSET pll_clkout1_phase=0.000 -CSET pll_clkout2_divide=1 -CSET pll_clkout2_duty_cycle=0.500 -CSET pll_clkout2_phase=0.000 -CSET pll_clkout3_divide=1 -CSET pll_clkout3_duty_cycle=0.500 -CSET pll_clkout3_phase=0.000 -CSET pll_clkout4_divide=1 -CSET pll_clkout4_duty_cycle=0.500 -CSET pll_clkout4_phase=0.000 -CSET pll_clkout5_divide=1 -CSET pll_clkout5_duty_cycle=0.500 -CSET pll_clkout5_phase=0.000 -CSET pll_compensation=SYSTEM_SYNCHRONOUS -CSET pll_divclk_divide=1 -CSET pll_notes=None -CSET pll_ref_jitter=0.010 -CSET power_down_port=POWER_DOWN -CSET prim_in_freq=50.000 -CSET prim_in_jitter=0.010 -CSET prim_source=No_buffer -CSET primary_port=clk_50_in -CSET primitive=MMCM -CSET primtype_sel=PLL_BASE -CSET psclk_port=PSCLK -CSET psdone_port=PSDONE -CSET psen_port=PSEN -CSET psincdec_port=PSINCDEC -CSET relative_inclk=REL_PRIMARY -CSET reset_port=RESET -CSET secondary_in_freq=100.000 -CSET secondary_in_jitter=0.010 -CSET secondary_port=CLK_IN2 -CSET secondary_source=Single_ended_clock_capable_pin -CSET ss_mod_freq=250 -CSET ss_mode=CENTER_HIGH -CSET status_port=STATUS -CSET summary_strings=empty -CSET use_clk_valid=false -CSET use_clkfb_stopped=false -CSET use_dyn_phase_shift=false -CSET use_dyn_reconfig=false -CSET use_freeze=false -CSET use_freq_synth=true -CSET use_inclk_stopped=false -CSET use_inclk_switchover=false -CSET use_locked=true -CSET use_max_i_jitter=false -CSET use_min_o_jitter=false -CSET use_min_power=false -CSET use_phase_alignment=true -CSET use_power_down=false -CSET use_reset=true -CSET use_spread_spectrum=false -CSET use_spread_spectrum_1=false -CSET use_status=false -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2012-05-10T12:44:55Z -# END Extra information -GENERATE -# CRC: fe735cf8 diff --git a/spartan6/hp_lcd_driver/pll_50_p10_p2_p.xco b/spartan6/hp_lcd_driver/pll_50_p10_p2_p.xco deleted file mode 100644 index 9d75f11..0000000 --- a/spartan6/hp_lcd_driver/pll_50_p10_p2_p.xco +++ /dev/null @@ -1,269 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.7 -# Date: Sat Apr 26 23:17:11 2025 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:clk_wiz:3.6 -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc6slx9 -SET devicefamily = spartan6 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = tqg144 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -2 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6 -# END Select -# BEGIN Parameters -CSET calc_done=DONE -CSET clk_in_sel_port=CLK_IN_SEL -CSET clk_out1_port=pclk_x10_out -CSET clk_out1_use_fine_ps_gui=false -CSET clk_out2_port=pclk_x2_out -CSET clk_out2_use_fine_ps_gui=false -CSET clk_out3_port=pclk_out -CSET clk_out3_use_fine_ps_gui=false -CSET clk_out4_port=CLK_OUT4 -CSET clk_out4_use_fine_ps_gui=false -CSET clk_out5_port=CLK_OUT5 -CSET clk_out5_use_fine_ps_gui=false -CSET clk_out6_port=CLK_OUT6 -CSET clk_out6_use_fine_ps_gui=false -CSET clk_out7_port=CLK_OUT7 -CSET clk_out7_use_fine_ps_gui=false -CSET clk_valid_port=CLK_VALID -CSET clkfb_in_n_port=CLKFB_IN_N -CSET clkfb_in_p_port=CLKFB_IN_P -CSET clkfb_in_port=CLKFB_IN -CSET clkfb_in_signaling=SINGLE -CSET clkfb_out_n_port=CLKFB_OUT_N -CSET clkfb_out_p_port=CLKFB_OUT_P -CSET clkfb_out_port=CLKFB_OUT -CSET clkfb_stopped_port=CLKFB_STOPPED -CSET clkin1_jitter_ps=200.0 -CSET clkin1_ui_jitter=0.010 -CSET clkin2_jitter_ps=100.0 -CSET clkin2_ui_jitter=0.010 -CSET clkout1_drives=BUFG -CSET clkout1_requested_duty_cycle=50.000 -CSET clkout1_requested_out_freq=91.667 -CSET clkout1_requested_phase=0.000 -CSET clkout2_drives=BUFG -CSET clkout2_requested_duty_cycle=50.000 -CSET clkout2_requested_out_freq=36.667 -CSET clkout2_requested_phase=0.000 -CSET clkout2_used=true -CSET clkout3_drives=BUFG -CSET clkout3_requested_duty_cycle=50.000 -CSET clkout3_requested_out_freq=18.333 -CSET clkout3_requested_phase=0.000 -CSET clkout3_used=true -CSET clkout4_drives=BUFG -CSET clkout4_requested_duty_cycle=50.000 -CSET clkout4_requested_out_freq=100.000 -CSET clkout4_requested_phase=0.000 -CSET clkout4_used=false -CSET clkout5_drives=BUFG -CSET clkout5_requested_duty_cycle=50.000 -CSET clkout5_requested_out_freq=100.000 -CSET clkout5_requested_phase=0.000 -CSET clkout5_used=false -CSET clkout6_drives=BUFG -CSET clkout6_requested_duty_cycle=50.000 -CSET clkout6_requested_out_freq=100.000 -CSET clkout6_requested_phase=0.000 -CSET clkout6_used=false -CSET clkout7_drives=BUFG -CSET clkout7_requested_duty_cycle=50.000 -CSET clkout7_requested_out_freq=100.000 -CSET clkout7_requested_phase=0.000 -CSET clkout7_used=false -CSET clock_mgr_type=AUTO -CSET component_name=pll_50_p10_p2_p -CSET daddr_port=DADDR -CSET dclk_port=DCLK -CSET dcm_clk_feedback=2X -CSET dcm_clk_out1_port=CLKFX -CSET dcm_clk_out2_port=CLKDV -CSET dcm_clk_out3_port=CLK2X -CSET dcm_clk_out4_port=CLK0 -CSET dcm_clk_out5_port=CLK0 -CSET dcm_clk_out6_port=CLK0 -CSET dcm_clkdv_divide=15.0 -CSET dcm_clkfx_divide=6 -CSET dcm_clkfx_multiply=11 -CSET dcm_clkgen_clk_out1_port=CLKFX -CSET dcm_clkgen_clk_out2_port=CLKFX -CSET dcm_clkgen_clk_out3_port=CLKFX -CSET dcm_clkgen_clkfx_divide=1 -CSET dcm_clkgen_clkfx_md_max=0.000 -CSET dcm_clkgen_clkfx_multiply=4 -CSET dcm_clkgen_clkfxdv_divide=2 -CSET dcm_clkgen_clkin_period=10.000 -CSET dcm_clkgen_notes=None -CSET dcm_clkgen_spread_spectrum=NONE -CSET dcm_clkgen_startup_wait=false -CSET dcm_clkin_divide_by_2=false -CSET dcm_clkin_period=20.000 -CSET dcm_clkout_phase_shift=NONE -CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS -CSET dcm_notes=None -CSET dcm_phase_shift=0 -CSET dcm_pll_cascade=NONE -CSET dcm_startup_wait=false -CSET den_port=DEN -CSET din_port=DIN -CSET dout_port=DOUT -CSET drdy_port=DRDY -CSET dwe_port=DWE -CSET feedback_source=FDBK_AUTO -CSET in_freq_units=Units_MHz -CSET in_jitter_units=Units_UI -CSET input_clk_stopped_port=INPUT_CLK_STOPPED -CSET jitter_options=UI -CSET jitter_sel=No_Jitter -CSET locked_port=LOCKED -CSET mmcm_bandwidth=OPTIMIZED -CSET mmcm_clkfbout_mult_f=4.000 -CSET mmcm_clkfbout_phase=0.000 -CSET mmcm_clkfbout_use_fine_ps=false -CSET mmcm_clkin1_period=10.000 -CSET mmcm_clkin2_period=10.000 -CSET mmcm_clkout0_divide_f=4.000 -CSET mmcm_clkout0_duty_cycle=0.500 -CSET mmcm_clkout0_phase=0.000 -CSET mmcm_clkout0_use_fine_ps=false -CSET mmcm_clkout1_divide=1 -CSET mmcm_clkout1_duty_cycle=0.500 -CSET mmcm_clkout1_phase=0.000 -CSET mmcm_clkout1_use_fine_ps=false -CSET mmcm_clkout2_divide=1 -CSET mmcm_clkout2_duty_cycle=0.500 -CSET mmcm_clkout2_phase=0.000 -CSET mmcm_clkout2_use_fine_ps=false -CSET mmcm_clkout3_divide=1 -CSET mmcm_clkout3_duty_cycle=0.500 -CSET mmcm_clkout3_phase=0.000 -CSET mmcm_clkout3_use_fine_ps=false -CSET mmcm_clkout4_cascade=false -CSET mmcm_clkout4_divide=1 -CSET mmcm_clkout4_duty_cycle=0.500 -CSET mmcm_clkout4_phase=0.000 -CSET mmcm_clkout4_use_fine_ps=false -CSET mmcm_clkout5_divide=1 -CSET mmcm_clkout5_duty_cycle=0.500 -CSET mmcm_clkout5_phase=0.000 -CSET mmcm_clkout5_use_fine_ps=false -CSET mmcm_clkout6_divide=1 -CSET mmcm_clkout6_duty_cycle=0.500 -CSET mmcm_clkout6_phase=0.000 -CSET mmcm_clkout6_use_fine_ps=false -CSET mmcm_clock_hold=false -CSET mmcm_compensation=ZHOLD -CSET mmcm_divclk_divide=1 -CSET mmcm_notes=None -CSET mmcm_ref_jitter1=0.010 -CSET mmcm_ref_jitter2=0.010 -CSET mmcm_startup_wait=false -CSET num_out_clks=3 -CSET override_dcm=false -CSET override_dcm_clkgen=false -CSET override_mmcm=false -CSET override_pll=false -CSET platform=lin -CSET pll_bandwidth=OPTIMIZED -CSET pll_clk_feedback=CLKFBOUT -CSET pll_clkfbout_mult=11 -CSET pll_clkfbout_phase=0.000 -CSET pll_clkin_period=20.000 -CSET pll_clkout0_divide=6 -CSET pll_clkout0_duty_cycle=0.500 -CSET pll_clkout0_phase=0.000 -CSET pll_clkout1_divide=15 -CSET pll_clkout1_duty_cycle=0.500 -CSET pll_clkout1_phase=0.000 -CSET pll_clkout2_divide=30 -CSET pll_clkout2_duty_cycle=0.500 -CSET pll_clkout2_phase=0.000 -CSET pll_clkout3_divide=1 -CSET pll_clkout3_duty_cycle=0.500 -CSET pll_clkout3_phase=0.000 -CSET pll_clkout4_divide=1 -CSET pll_clkout4_duty_cycle=0.500 -CSET pll_clkout4_phase=0.000 -CSET pll_clkout5_divide=1 -CSET pll_clkout5_duty_cycle=0.500 -CSET pll_clkout5_phase=0.000 -CSET pll_compensation=SYSTEM_SYNCHRONOUS -CSET pll_divclk_divide=1 -CSET pll_notes=None -CSET pll_ref_jitter=0.010 -CSET power_down_port=POWER_DOWN -CSET prim_in_freq=50.000 -CSET prim_in_jitter=0.010 -CSET prim_source=No_buffer -CSET primary_port=clk_50_in -CSET primitive=MMCM -CSET primtype_sel=PLL_BASE -CSET psclk_port=PSCLK -CSET psdone_port=PSDONE -CSET psen_port=PSEN -CSET psincdec_port=PSINCDEC -CSET relative_inclk=REL_PRIMARY -CSET reset_port=RESET -CSET secondary_in_freq=100.000 -CSET secondary_in_jitter=0.010 -CSET secondary_port=CLK_IN2 -CSET secondary_source=Single_ended_clock_capable_pin -CSET ss_mod_freq=250 -CSET ss_mode=CENTER_HIGH -CSET status_port=STATUS -CSET summary_strings=empty -CSET use_clk_valid=false -CSET use_clkfb_stopped=false -CSET use_dyn_phase_shift=false -CSET use_dyn_reconfig=false -CSET use_freeze=false -CSET use_freq_synth=true -CSET use_inclk_stopped=false -CSET use_inclk_switchover=false -CSET use_locked=true -CSET use_max_i_jitter=false -CSET use_min_o_jitter=false -CSET use_min_power=false -CSET use_phase_alignment=true -CSET use_power_down=false -CSET use_reset=true -CSET use_spread_spectrum=false -CSET use_spread_spectrum_1=false -CSET use_status=false -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2012-05-10T12:44:55Z -# END Extra information -GENERATE -# CRC: d987c511 diff --git a/spartan6/hp_lcd_driver/tmds_output.vhdl b/spartan6/hp_lcd_driver/tmds_output.vhdl index 8f413b8..ba095ef 100644 --- a/spartan6/hp_lcd_driver/tmds_output.vhdl +++ b/spartan6/hp_lcd_driver/tmds_output.vhdl @@ -13,7 +13,6 @@ entity tmds_output is pclk : in std_logic; pclk_x2 : in std_logic; pclk_x10 : in std_logic; - serdesstrobe : in std_logic; r_in : in std_logic_vector(7 downto 0); g_in : in std_logic_vector(7 downto 0); b_in : in std_logic_vector(7 downto 0); @@ -40,8 +39,11 @@ architecture beh of tmds_output is signal b_p10 : std_logic_vector(9 downto 0); signal phy_reset : std_logic; - signal bufpll_lock : std_logic; signal upper : std_logic; + signal pll_locked: std_logic; + signal ioclk: std_logic; + signal serdesstrobe : std_logic; + begin @@ -84,9 +86,9 @@ begin ); - phy_reset <= not sys_rst_n or not bufpll_lock; + phy_reset <= not sys_rst_n or not pll_locked; - process (pclk_x2) + process (pclk_x2,phy_reset) begin if phy_reset = '1' then upper <= '1'; @@ -96,12 +98,22 @@ begin end process; + ioclk_buf : BUFPLL generic map (DIVIDE => 5) + port map ( + PLLIN => pclk_x10, + GCLK => pclk_x2, + LOCKED => pclk_locked, + IOCLK => ioclk, + SERDESSTROBE => serdesstrobe, + LOCK => pll_locked); + + phy_c : entity work.tmds_phy port map ( reset => phy_reset, pclk_x2 => pclk_x2, serdesstrobe => serdesstrobe, - ioclk => pclk_x10, + ioclk => ioclk, upper => upper, din => "1111100000", tmds_out_p => tmds_c_out_p, @@ -113,7 +125,7 @@ begin reset => phy_reset, pclk_x2 => pclk_x2, serdesstrobe => serdesstrobe, - ioclk => pclk_x10, + ioclk => ioclk, upper => upper, din => r_p10, tmds_out_p => tmds_r_out_p, @@ -126,7 +138,7 @@ begin reset => phy_reset, pclk_x2 => pclk_x2, serdesstrobe => serdesstrobe, - ioclk => pclk_x10, + ioclk => ioclk, upper => upper, din => g_p10, tmds_out_p => tmds_g_out_p, |