diff options
| -rw-r--r-- | fpga/hp_lcd_driver_a7/source/hp_lcd_driver.tcl | 85 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver_a7/source/hp_lcd_driver.vhdl | 4 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver_a7/source/input_formatter.vhdl | 48 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver_a7/source/input_stage.vhdl | 6 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver_a7/source/rando_a7.tcl | 7 |
5 files changed, 44 insertions, 106 deletions
diff --git a/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.tcl b/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.tcl index b244449..b98c722 100644 --- a/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.tcl +++ b/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.tcl @@ -16,20 +16,16 @@ if {[llength $files] != 0} { #Reference HDL and constraint source files -read_xdc $early_xdc +#read_xdc $early_xdc #read_verilog [ glob ../source/*.v ] -read_vhdl -vhdl2008 -library work [ glob ../source/*.vhdl ] +#read_vhdl -vhdl2008 -library work [ glob ../source/*.vhdl ] +read_vhdl -vhdl2008 -library work { clkgen_artix7.vhdl debounce.vhdl delay.vhdl edge_det.vhdl hp_lcd_driver.vhdl input_formatter.vhdl input_stage.vhdl output_analog.vhdl output_formatter.vhdl output_stage.vhdl synchronizer.vhdl tmds_encoder.vhdl tmds_encode.vhdl tmds_output_artix7.vhdl tmds_phy_artix7.vhdl vram_artix7.vhdl } set generics {} -append generics { } "video_width=6" +append generics { } "video_width=$video_width" append generics { } "BOARD=\"$board\"" -#append generics { } "LA_ADDR_WIDTH=$LA_ADDR_WIDTH" -#append generics { } "MEM_DATA_WIDTH=$MEM_DATA_WIDTH" -#append generics { } "MEM_ADDR_WIDTH=$MEM_ADDR_WIDTH" -#append generics { } "DDR3_D_WIDTH=$DDR3_D_WIDTH" -#append generics { } "DDR3_A_WIDTH=$DDR3_A_WIDTH" -#append generics { } "DDR3_B_WIDTH=$DDR3_B_WIDTH" +append generics { } "use_pclk=$use_pclk" set_property generic "$generics" [current_fileset] puts $generics @@ -37,19 +33,6 @@ puts $generics read_ip $ip_dir/blk_mem_gen_0/blk_mem_gen_0.xci read_ip $ip_dir/mmcm_0/mmcm_0.xci read_ip $ip_dir/mmcm_1/mmcm_1.xci -#read_ip $ip_dir/dma_block_0/dma_block_0.xci -#read_ip $ip_dir/fa_8x4k_ft_${sclk}_${aclk}/fa_8x4k_ft_${sclk}_${aclk}.xci -#read_ip $ip_dir/fa_8x4k_ft_${aclk}_${sclk}/fa_8x4k_ft_${aclk}_${sclk}.xci -#read_ip $ip_dir/fa_19x512_ft_${sclk}_${aclk}/fa_19x512_ft_${sclk}_${aclk}.xci -#read_ip $ip_dir/fa_32x8k_ft_${sclk}_${aclk}/fa_32x8k_ft_${sclk}_${aclk}.xci -#read_ip $ip_dir/fa_64x8k_ft_${sclk}_${aclk}/fa_64x8k_ft_${sclk}_${aclk}.xci -#read_ip $ip_dir/f_11x512_ft/f_11x512_ft.xci -#read_ip $ip_dir/axi_dwidth_converter_128_MDW_LAW_4/axi_dwidth_converter_128_MDW_LAW_4.xci -#read_ip $ip_dir/axi_protocol_converter_lite_full_64_LAW/axi_protocol_converter_lite_full_64_LAW.xci -#read_ip $ip_dir/axi_dwidth_converter_64_MDW_LAW_1/axi_dwidth_converter_64_MDW_LAW_1.xci -#read_ip $ip_dir/axi_crossbar_2_1_MDW_LAW/axi_crossbar_2_1_MDW_LAW.xci -#read_ip $ip_dir/axi_clock_converter_MDW_MAW_4/axi_clock_converter_MDW_MAW_4.xci -#read_ip $ip_dir/mig_7series_$board/mig_7series_$board.xci read_xdc $normal_xdc @@ -76,64 +59,6 @@ puts $f [get_pins -hierarchical] close $f set_param tcl.collectionResultDisplayLimit $crdl - -## erugh set_clock_groups can only take thee arguments there are reasonably 5 hierachies in play pci_e refclk, the axi clock, the clock used by the spi_slave and logic analyzer and the mig clock -## -#set_clock_groups -asynchronous \ -# -group [get_clocks -include_generated_clocks -of_objects [get_nets clk_100m]] \ -# -group "[get_clocks -include_generated_clocks -of_objects [get_nets clk_200m]] [get_clocks -include_generated_clocks -of_objects [get_nets clk_333m]]" \ -# -group [get_clocks -include_generated_clocks -of_objects [get_nets axi_aclk]] -# -#set_clock_groups -asynchronous \ -# -group [get_clocks -include_generated_clocks -of_objects [get_nets clk_100m]] \ -# -## -group [get_clocks -include_generated_clocks -of_objects [get_nets sys_clk_p]] -# -#set_clock_groups -asynchronous \ -# -group "[get_clocks -include_generated_clocks -of_objects [get_nets clk_200m]] [get_clocks -include_generated_clocks -of_objects [get_nets clk_333m]]" \ -# -## -group [get_clocks -include_generated_clocks -of_objects [get_nets sys_clk_p]] -# -#set_clock_groups -asynchronous \ -# -group [get_clocks -include_generated_clocks -of_objects [get_nets axi_aclk]] \ -# -## -group [get_clocks -include_generated_clocks -of_objects [get_nets sys_clk_p]] -# -# -##set_false_path -from [get_pins {srst_reg/C}] -to [get_pins {srst_sclk_sync/flipflops_reg[0]/D}] -# -#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_100m] -# -##puts [get_ports -of_objects [get_objects srst_sclk_sync ]] -##exit -# -##puts [get_clocks -include_generated_clocks -of_objects [get_nets axi_aclk]] -##puts [get_clocks -include_generated_clocks -of_objects [get_nets mmcm_0_i/inst/clk_out1]] -# -##set_false_path -from [get_pins {srst_reg/C}] -to [get_pins {srst_sclk_sync/flipflops_reg[0]/D}] -# -#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_100m] -# -##puts [get_ports -of_objects [get_objects srst_sclk_sync ]] -##exit -# -##puts [get_clocks -include_generated_clocks -of_objects [get_nets axi_aclk]] -##puts [get_clocks -include_generated_clocks -of_objects [get_nets mmcm_0_i/inst/clk_out1]] -# -## JMM because we've clocked the two async domains from the same input - vivado thinks there exist timing relationships -## tell it there aren't -# -##set_false_path -from [get_clocks clk_100m] -to [get_clocks -include_generated_clocks clk_out3_mmcm_0] -##set_false_path -from [get_clocks -include_generated_clocks clk_out3_mmcm_0] -to [get_clocks clk_100m] -## -##set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_nets axi_aclk]] -to [get_clocks -include_generated_clocks clk_out3_mmcm_0] -##set_false_path -from [get_clocks -include_generated_clocks clk_out3_mmcm_0] -to [get_clocks -include_generated_clocks -of_objects [get_nets axi_aclk]] -## -##set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_nets axi_aclk]] -to [get_clocks clk_100m] -##set_false_path -from [get_clocks clk_100m] -to [get_clocks -include_generated_clocks -of_objects [get_nets axi_aclk]] -# -# - #run optimization opt_design place_design diff --git a/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.vhdl b/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.vhdl index fb4f194..28c00f4 100644 --- a/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.vhdl +++ b/fpga/hp_lcd_driver_a7/source/hp_lcd_driver.vhdl @@ -15,6 +15,7 @@ entity hp_lcd_driver is addr_width : natural := 18; phase_slip : natural := 320; i_clk_multiple : natural := 4; + use_pclk : natural := 0; target : string := "artix7"); port (clk_50m : in std_logic; -- sys_rst_n : in std_logic; @@ -155,7 +156,8 @@ sys_rst_n <='1'; frame_start => 383, h_stride => 384, v_stride => 524287, - phase_slip => phase_slip + phase_slip => phase_slip, + use_pclk => use_pclk, ) port map ( sys_rst_n => sys_rst_n, diff --git a/fpga/hp_lcd_driver_a7/source/input_formatter.vhdl b/fpga/hp_lcd_driver_a7/source/input_formatter.vhdl index f50f6e5..1f27932 100644 --- a/fpga/hp_lcd_driver_a7/source/input_formatter.vhdl +++ b/fpga/hp_lcd_driver_a7/source/input_formatter.vhdl @@ -16,7 +16,9 @@ entity input_formatter is frame_start : natural := 0; h_stride : natural := 384; v_stride : natural := 1; - phase_slip : natural := 320); + phase_slip : natural := 320 + use_pclk : natural := 0 + ); port ( sys_rst_n : in std_logic; @@ -50,8 +52,8 @@ architecture beh of input_formatter is signal h_fp_counter : natural; signal h_active_counter : natural; --- signal h_div : natural; --- signal phase_accum : natural; + signal h_div : natural; + signal phase_accum : natural; begin @@ -84,12 +86,12 @@ begin if sys_rst_n = '0' then row_addr <= (others => '0'); addr <= (others => '0'); - --h_div <= 0; + h_div <= 0; h_active_counter <= 0; h_fp_counter <= 0; v_active_counter <= 0; v_fp_counter <= 0; - --phase_accum <= 0; + phase_accum <= phase_slip; elsif rising_edge(clk) then if hsync_pe = '1' then --if v_active_counter = 0 and v_fp_counter=0 then @@ -104,8 +106,8 @@ begin h_fp_counter <= h_front_porch * clk_multiple + phase; h_active_counter <= h_active; - --phase_accum <= phase_slip; - --h_div <= 0; + phase_accum <= phase_slip; + h_div <= 0; addr <= row_addr; row_addr <= std_logic_vector(unsigned(row_addr)+v_stride); @@ -114,24 +116,34 @@ begin h_fp_counter <= h_fp_counter -1; elsif h_active_counter /= 0 then --- if h_div = 0 then + + g_hclk: if use_pclk='0' generate + if h_div = 0 then + wren <= '1'; + if phase_accum = 0 then + phase_accum <= phase_slip; + h_div <= clk_multiple; + else + phase_accum <= phase_accum-1; + h_div <= clk_multiple-1; + end if; + else + h_div <= h_div -1; + wren <= '0'; + end if; + end generate; + g_hclk: if use_pclk='0' generate if pclk_pe = '1' then wren <= '1'; --- if phase_accum = 0 then --- phase_accum <= phase_slip; --- h_div <= clk_multiple; --- else --- phase_accum <= phase_accum-1; --- h_div <= clk_multiple-1; --- end if; else - if wren = '1' then wren <= '0'; + end if; + end generate; + + if wren = '1' then h_active_counter <= h_active_counter -1; addr <= std_logic_vector(unsigned(addr)+h_stride); end if; - --h_div <= h_div -1; - end if; end if; end if; end process; diff --git a/fpga/hp_lcd_driver_a7/source/input_stage.vhdl b/fpga/hp_lcd_driver_a7/source/input_stage.vhdl index 028c5d6..16ea9bb 100644 --- a/fpga/hp_lcd_driver_a7/source/input_stage.vhdl +++ b/fpga/hp_lcd_driver_a7/source/input_stage.vhdl @@ -16,7 +16,8 @@ entity input_stage is frame_start : natural := 0; h_stride : natural := 384; v_stride : natural := 1; - phase_slip : natural := 320); + phase_slip : natural := 320 + use_pclk : natural := 0); port ( clk : in std_logic; @@ -129,7 +130,8 @@ begin frame_start => frame_start, h_stride => h_stride, v_stride => v_stride, - phase_slip => phase_slip) + phase_slip => phase_slip, + use_pclk => use_pclk) port map ( sys_rst_n => sys_rst_n, clk => clk, diff --git a/fpga/hp_lcd_driver_a7/source/rando_a7.tcl b/fpga/hp_lcd_driver_a7/source/rando_a7.tcl index 6d652e1..a596e1e 100644 --- a/fpga/hp_lcd_driver_a7/source/rando_a7.tcl +++ b/fpga/hp_lcd_driver_a7/source/rando_a7.tcl @@ -1,8 +1,5 @@ # set part_num "xc7a35tfgg484-2" -set early_xdc "../source/rando_a7_early.xdc" set normal_xdc "../source/rando_a7.xdc" -#set MEM_DATA_WIDTH 0 -#set MEM_ADDR_WIDTH 0 -#set aclk 125 -#set sclk 200 +set use_pclk 1 +set video_width 6 |