| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Register 6522 reads so that data is available outside of "phase 2" cycles, ↵ | Mike Stirling | 2011-07-17 | 1 | -31/+34 |
| | | | | | otherwise CPU can't see it | ||||
| * | Work in progress: Added MOS6522 from www.fpgaarcade.com. Added simple_uart ↵ | Mike Stirling | 2011-07-17 | 6 | -18/+1613 |
| | | | | | component in "FRED" for test purposes and added alternative EHBASIC ROM for debugging | ||||
| * | Fixed SRAM routing logic | Mike Stirling | 2011-07-16 | 4 | -20/+43 |
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| * | Added top-level, PLL, MOS ROM and CRTC. CRTC seems to behave strangely ↵ | Mike Stirling | 2011-07-16 | 8 | -0/+1407 |
| | | | | | although the design is passing timing. | ||||
| * | Initial commit. Some modules imported from experimental 6502 platform. ↵ | Mike Stirling | 2011-07-12 | 10 | -0/+3575 |
| Project added for Quartus 9.1 | |||||
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index : bbc-b/fpga-bbc | |
| bbc-b fpga implementation from GH | James |
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