/* * This file is subject to the terms of the GFX License. If a copy of * the license was not distributed with this file, you can obtain one at: * * http://ugfx.org/license.html */ /** * @file boards/addons/gdisp/board_SSD1289_stm32f4discovery.h * @brief GDISP Graphic Driver subsystem board interface for the SSD1289 display. * * @note This file contains a mix of hardware specific and operating system specific * code. You will need to change it for your CPU and/or operating system. */ #ifndef _GDISP_LLD_BOARD_H #define _GDISP_LLD_BOARD_H // For a multiple display configuration we would put all this in a structure and then // set g->board to that structure. #define GDISP_REG ((volatile uint16_t *) 0x60000000)[0] /* RS = 0 */ #define GDISP_RAM ((volatile uint16_t *) 0x60020000)[0] /* RS = 1 */ #define GDISP_DMA_STREAM STM32_DMA2_STREAM6 #define FSMC_BANK 0 /* PWM configuration structure. We use timer 3 channel 3 */ static const PWMConfig pwmcfg = { 100000, /* 100 kHz PWM clock frequency. */ 100, /* PWM period is 100 cycles. */ 0, { {PWM_OUTPUT_DISABLED, 0}, {PWM_OUTPUT_DISABLED, 0}, {PWM_OUTPUT_ACTIVE_HIGH, 0}, {PWM_OUTPUT_DISABLED, 0} }, 0, 0 }; static inline void init_board(GDisplay *g) { // As we are not using multiple displays we set g->board to NULL as we don't use it. g->board = 0; switch(g->controllerdisplay) { case 0: // Set up for Display 0 /** * Performs the following functions: * 1. initialise the io port used by the display * 2. initialise the reset pin (initial state not-in-reset) * 3. initialise the chip select pin (initial state not-active) * 4. initialise the backlight pin (initial state back-light off) */ #if defined(STM32F1XX) || defined(STM32F3XX) /* FSMC setup for F1/F3 */ rccEnableAHB(RCC_AHBENR_FSMCEN, 0); #if defined(GDISP_USE_DMA) #error "GDISP: SSD1289 - DMA not implemented for F1/F3 Devices" #endif #elif defined(STM32F4XX) || defined(STM32F2XX) /* STM32F2-F4 FSMC init */ rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0); #if defined(GDISP_USE_DMA) if (dmaStreamAllocate(GDISP_DMA_STREAM, 0, 0, 0)) gfxExit(); dmaStreamSetMemory0(GDISP_DMA_STREAM, &GDISP_RAM); dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M); #else #warning "GDISP: SSD1289 - DMA is supported for F2/F4 Devices. Define GDISP_USE_DMA in your gfxconf.h to turn this on for better performance." #endif #else #error "GDISP: SSD1289 - FSMC not implemented for this device" #endif /* set pins to FSMC mode */ IOBus busD = {GPIOD, (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | (1 << 14) | (1 << 15), 0}; IOBus busE = {GPIOE, (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) | (1 << 15), 0}; palSetBusMode(&busD, PAL_MODE_ALTERNATE(12)); palSetBusMode(&busE, PAL_MODE_ALTERNATE(12)); /* FSMC timing */ FSMC_Bank1->BTCR[FSMC_BANK+1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0 ; /* Bank1 NOR/SRAM control register configuration * This is actually not needed as already set by default after reset */ FSMC_Bank1->BTCR[FSMC_BANK] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN; /* Display backlight control */ /* TIM3 is an alternate function 2 (AF2) */ pwmStart(&PWMD3, &pwmcfg); palSetPadMode(GPIOB, 0, PAL_MODE_ALTERNATE(2)); pwmEnableChannel(&PWMD3, 2, 100); break; } } static inline void post_init_board(GDisplay *g) { (void) g; } static inline void setpin_reset(GDisplay *g, bool_t state) { (void) g; (void) state; } static inline void set_backlight(GDisplay *g, uint8_t percent) { (void) g; pwmEnableChannel(&PWMD3, 2, percent); } static inline void acquire_bus(GDisplay *g) { (void) g; } static inline void release_bus(GDisplay *g) { (void) g; } static inline void write_index(GDisplay *g, uint16_t index) { (void) g; GDISP_REG = index; } static inline void write_data(GDisplay *g, uint16_t data) { (void) g; GDISP_RAM = data; } static inline void setreadmode(GDisplay *g) { (void) g; FSMC_Bank1->BTCR[FSMC_BANK+1] = FSMC_BTR1_ADDSET_3 | FSMC_BTR1_DATAST_3 | FSMC_BTR1_BUSTURN_0; /* FSMC timing */ } static inline void setwritemode(GDisplay *g) { (void) g; FSMC_Bank1->BTCR[FSMC_BANK+1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0; /* FSMC timing */ } static inline uint16_t read_data(GDisplay *g) { (void) g; return GDISP_RAM; } #if defined(GDISP_USE_DMA) || defined(__DOXYGEN__) static inline void dma_with_noinc(GDisplay *g, color_t *buffer, int area) { (void) g; dmaStreamSetPeripheral(GDISP_DMA_STREAM, buffer); dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M); for (; area > 0; area -= 65535) { dmaStreamSetTransactionSize(GDISP_DMA_STREAM, area > 65535 ? 65535 : area); dmaStreamEnable(GDISP_DMA_STREAM); dmaWaitCompletion(GDISP_DMA_STREAM); } } static inline void dma_with_inc(GDisplay *g, color_t *buffer, int area) { (void) g; dmaStreamSetPeripheral(GDISP_DMA_STREAM, buffer); dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PINC | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M); for (; area > 0; area -= 65535) { dmaStreamSetTransactionSize(GDISP_DMA_STREAM, area > 65535 ? 65535 : area); dmaStreamEnable(GDISP_DMA_STREAM); dmaWaitCompletion(GDISP_DMA_STREAM); } } #endif #endif /* _GDISP_LLD_BOARD_H */ 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573