\chapter{Technology Mapping}
\label{chapter:techmap}
Previous chapters outlined how HDL code is transformed into an RTL netlist. The
RTL netlist is still based on abstract coarse-grain cell types like arbitrary
width adders and even multipliers. This chapter covers how an RTL netlist is
transformed into a functionally equivialent netlist utililizing the cell types
available in the target architecture.
Technology mapping is often performed in two phases. In the first phase RTL cells
are mapped to an internal library of single-bit cells (see Sec.~\ref{sec:celllib_gates}).
In the second phase this netlist of internal gate types is transformed to a netlist
of gates from the target technology library.
When the target architecture provides coarse-grain cells (such as block ram
or ALUs), these must be mapped to directly form the RTL netlist, as information
on the coarse-grain structure of the design is lost when it is mapped to
bit-width gate types.
\section{Cell Substitution}
The simplest form of technology mapping is cell substitution, as performed by
the {\tt techmap} pass. This pass, when provided with a Verilog file that
implements the RTL cell types using simpler cells, simply replaces the RTL
cells with the provided implementation.
When no map file is provided, {\tt techmap} uses a built-in map file that
maps the Yosys RTL cell types to the internal gate library used by Yosys.
The curious reader may find this map file as {\tt techlibs/common/techmap.v} in
the Yosys source tree.
Additional features have been added to {\tt techmap} to allow for conditional
mapping of cells (see {\tt help techmap} or Sec.~\ref{cmd:techmap}). This can
for example be useful if the target architecture supports hardware multipliers for
certain bit-widths but not for others.
A usual synthesis flow would first use the {\tt techmap} pass to directly map
some RTL cells to coarse-grain cells provided by the target architecture (if
any) and then use techmap with the built-in default file to map the remaining
RTL cells to gate logic.
\section{Subcircuit Substitution}
Sometimes the target architecture provides cells that are more powerful than
the RTL cells used by Yosys. For example a cell in the target architecture that can
calculate the absolute-difference of two numbers does not match any single
RTL cell type but only combinations of cells.
For these cases Yosys provides the {\tt extract} pass that can match a given set
of modules against a design and identify the portions of the design that are
identical (i.e.~isomorphic subcircuits) to any of the given modules. These
matched subcircuits are then replaced by instances of the given modules.
The {\tt extract} pass also finds basic variations of the given modules,
such as swapped inputs on commutative cell types.
In addition to this the {\tt extract} pass also has limited support for
frequent subcircuit mining, i.e.~the process of finding recurring subcircuits
in the design. This has a few applications, including the design of new
coarse-grain architectures \cite{intersynthFdlBookChapter}.
The hard algorithmic work done by the {\tt extract} pass (solving the
isomorphic subcircuit problem and frequent subcircuit mining) is performed
using the SubCircuit library that can also be used stand-alone without Yosys
(see Sec.~\ref{sec:SubCircuit}).
\section{Gate-Level Technology Mapping}
\label{sec:techmap_extern}
On the gate-level the target architecture is usually described by a ``Liberty
file''. The Liberty file format is an industry standard format that can be
used to describe the behaviour and other properties of standard library cells
\citeweblink{LibertyFormat}.
Mapping a design utilizing the Yosys internal gate library (e.g.~as a result
of mapping it to this representation using the {\tt techmap} pass) is
performed in two phases.
First the register cells must be mapped to the registers that are available
on the target architectures. The target architecture might not provide all
variations of d-type flip-flops with positive and negative clock edge,
high-active and low-active asynchronous set and/or reset, etc. Therefore the
process of mapping the registers might add additional inverters to the design
and thus it is important to map the register cells first.
Mapping of the register cells may be performed by using the {\tt dfflibmap}
pass. This pass expects a Liberty file as argument (using the {\tt -liberty}
option) and only uses the register cells from the Liberty file.
Secondly the combinational logic must be mapped to the target architecture.
This is done using the external program ABC \citeweblink{ABC} via the
{\tt abc} pass by using the {\tt -liberty} option to the pass. Note that
in this case only the combinatorial cells are used from the cell library.
Occasionally Liberty files contain trade secrets (such as sensitive timing
information) that cannot be shared freely. This complicates processes such as
reporting bugs in the tools involved. When the information in the Liberty file
used by Yosys and ABC are not part of the sensitive information, the additional
tool {\tt yosys-filterlib} (see Sec.~\ref{sec:filterlib}) can be used to strip
the sensitive information from the Liberty file.
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/*
LUFA Library
Copyright (C) Dean Camera, 2010.
dean [at] fourwalledcubicle [dot] com
www.fourwalledcubicle.com
*/
/*
Copyright 2010 Dean Camera (dean [at] fourwalledcubicle [dot] com)
Permission to use, copy, modify, distribute, and sell this
software and its documentation for any purpose is hereby granted
without fee, provided that the above copyright notice appear in
all copies and that both that the copyright notice and this
permission notice and warranty disclaimer appear in supporting
documentation, and that the name of the author not be used in
advertising or publicity pertaining to distribution of the
software without specific, written prior permission.
The author disclaim all warranties with regard to this
software, including all implied warranties of merchantability
and fitness. In no event shall the author be liable for any
special, indirect or consequential damages or any damages
whatsoever resulting from loss of use, data or profits, whether
in an action of contract, negligence or other tortious action,
arising out of or in connection with the use or performance of
this software.
*/
/** \file
*
* Main source file for the AudioOutput demo. This file contains the main tasks of the demo and
* is responsible for the initial application hardware configuration.
*/
#include "AudioOutput.h"
/** Flag to indicate if the streaming audio alternative interface has been selected by the host. */
bool StreamingAudioInterfaceSelected = false;
/** Main program entry point. This routine contains the overall program flow, including initial
* setup of all components and the main program loop.
*/
int main(void)
{
SetupHardware();
LEDs_SetAllLEDs(LEDMASK_USB_NOTREADY);
for (;;)
{
USB_Audio_Task();
USB_USBTask();
}
}
/** Configures the board hardware and chip peripherals for the demo's functionality. */
void SetupHardware(void)
{
/* Disable watchdog if enabled by bootloader/fuses */
MCUSR &= ~(1 << WDRF);
wdt_disable();
/* Disable clock division */
clock_prescale_set(clock_div_1);
/* Hardware Initialization */
LEDs_Init();
USB_Init();
}
/** Event handler for the USB_Connect event. This indicates that the device is enumerating via the status LEDs, and
* configures the sample update and PWM timers.
*/
void EVENT_USB_Device_Connect(void)
{
/* Indicate USB enumerating */
LEDs_SetAllLEDs(LEDMASK_USB_ENUMERATING);
/* Sample reload timer initialization */
OCR0A = (F_CPU / 8 / AUDIO_SAMPLE_FREQUENCY) - 1;
TCCR0A = (1 << WGM01); // CTC mode
TCCR0B = (1 << CS01); // Fcpu/8 speed
#if defined(AUDIO_OUT_MONO)
/* Set speaker as output */
DDRC |= (1 << 6);
#elif defined(AUDIO_OUT_STEREO)
/* Set speakers as outputs */
DDRC |= ((1 << 6) | (1 << 5));
#elif defined(AUDIO_OUT_PORTC)
/* Set PORTC as outputs */
DDRC |= 0xFF;
#endif
#if (defined(AUDIO_OUT_MONO) || defined(AUDIO_OUT_STEREO))
/* PWM speaker timer initialization */
TCCR3A = ((1 << WGM30) | (1 << COM3A1) | (1 << COM3A0)
| (1 << COM3B1) | (1 << COM3B0)); // Set on match, clear on TOP
TCCR3B = ((1 << WGM32) | (1 << CS30)); // Fast 8-Bit PWM, Fcpu speed
#endif
}
/** Event handler for the USB_Disconnect event. This indicates that the device is no longer connected to a host via
* the status LEDs, disables the sample update and PWM output timers and stops the USB and Audio management tasks.
*/
void EVENT_USB_Device_Disconnect(void)
{
/* Stop the timers */
TCCR0B = 0;
#if (defined(AUDIO_OUT_MONO) || defined(AUDIO_OUT_STEREO))
TCCR3B = 0;
#endif
#if defined(AUDIO_OUT_MONO)
/* Set speaker as input to reduce current draw */
DDRC &= ~(1 << 6);
#elif defined(AUDIO_OUT_STEREO)
/* Set speakers as inputs to reduce current draw */
DDRC &= ~((1 << 6) | (1 << 5));
#elif defined(AUDIO_OUT_PORTC)
/* Set PORTC low */
PORTC = 0x00;
#endif
/* Indicate streaming audio interface not selected */
StreamingAudioInterfaceSelected = false;
/* Indicate USB not ready */
LEDs_SetAllLEDs(LEDMASK_USB_NOTREADY);
}
/** Event handler for the USB_ConfigurationChanged event. This is fired when the host set the current configuration
* of the USB device after enumeration - the device endpoints are configured.
*/
void EVENT_USB_Device_ConfigurationChanged(void)
{
/* Indicate USB connected and ready */
LEDs_SetAllLEDs(LEDMASK_USB_READY);
/* Setup audio stream endpoint */
if (!(Endpoint_ConfigureEndpoint(AUDIO_STREAM_EPNUM, EP_TYPE_ISOCHRONOUS,
ENDPOINT_DIR_OUT, AUDIO_STREAM_EPSIZE,
ENDPOINT_BANK_DOUBLE)))
{
LEDs_SetAllLEDs(LEDMASK_USB_ERROR);
}
}
/** Event handler for the USB_UnhandledControlRequest event. This is used to catch standard and class specific
* control requests that are not handled internally by the USB library (including the Audio class-specific
* requests) so that they can be handled appropriately for the application.
*/
void EVENT_USB_Device_UnhandledControlRequest(void)
{
/* Process General and Audio specific control requests */
switch (USB_ControlRequest.bRequest)
{
case REQ_SetInterface:
/* Set Interface is not handled by the library, as its function is application-specific */
if (USB_ControlRequest.bmRequestType == (REQDIR_HOSTTODEVICE | REQTYPE_STANDARD | REQREC_INTERFACE))
{
Endpoint_ClearSETUP();
/* Check if the host is enabling the audio interface (setting AlternateSetting to 1) */
StreamingAudioInterfaceSelected = ((USB_ControlRequest.wValue) != 0);
Endpoint_ClearStatusStage();
}
break;
}
}
/** Task to manage the Audio interface, reading in audio samples from the host, and outputting them to the speakers/LEDs as
* desired.
*/
void USB_Audio_Task(void)
{
/* Device must be connected and configured for the task to run */
if (USB_DeviceState != DEVICE_STATE_Configured)
return;
/* Check to see if the streaming interface is selected, if not the host is not receiving audio */
if (!(StreamingAudioInterfaceSelected))
return;
/* Select the audio stream endpoint */
Endpoint_SelectEndpoint(AUDIO_STREAM_EPNUM);
/* Check if the current endpoint can be read from (contains a packet) and that the next sample should be read */
if (Endpoint_IsOUTReceived() && (TIFR0 & (1 << OCF0A)))
{
/* Clear the sample reload timer */
TIFR0 |= (1 << OCF0A);
/* Retrieve the signed 16-bit left and right audio samples, convert to 8-bit */
int8_t LeftSample_8Bit = ((int16_t)Endpoint_Read_Word_LE() >> 8);
int8_t RightSample_8Bit = ((int16_t)Endpoint_Read_Word_LE() >> 8);
/* Mix the two channels together to produce a mono, 8-bit sample */
int8_t MixedSample_8Bit = (((int16_t)LeftSample_8Bit + (int16_t)RightSample_8Bit) >> 1);
/* Check to see if the bank is now empty */
if (!(Endpoint_IsReadWriteAllowed()))
{
/* Acknowledge the packet, clear the bank ready for the next packet */
Endpoint_ClearOUT();
}
#if defined(AUDIO_OUT_MONO)
/* Load the sample into the PWM timer channel */
OCR3A = (MixedSample_8Bit ^ (1 << 7));
#elif defined(AUDIO_OUT_STEREO)
/* Load the dual 8-bit samples into the PWM timer channels */
OCR3A = (LeftSample_8Bit ^ (1 << 7));
OCR3B = (RightSample_8Bit ^ (1 << 7));
#elif defined(AUDIO_OUT_PORTC)
/* Load the 8-bit mixed sample into PORTC */
PORTC = MixedSample_8Bit;
#endif
uint8_t LEDMask = LEDS_NO_LEDS;
/* Turn on LEDs as the sample amplitude increases */
if (MixedSample_8Bit > 16)
LEDMask = (LEDS_LED1 | LEDS_LED2 | LEDS_LED3 | LEDS_LED4);
else if (MixedSample_8Bit > 8)
LEDMask = (LEDS_LED1 | LEDS_LED2 | LEDS_LED3);
else if (MixedSample_8Bit > 4)
LEDMask = (LEDS_LED1 | LEDS_LED2);
else if (MixedSample_8Bit > 2)
LEDMask = (LEDS_LED1);
LEDs_SetAllLEDs(LEDMask);
}
}
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