/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef MCUCONF_H
#define MCUCONF_H
/*
* STM32F0xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 3...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F0xx_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_HSI_ENABLED TRUE
#define STM32_HSI14_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED FALSE
#define STM32_LSE_ENABLED FALSE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSI_DIV2
#define STM32_PREDIV_VALUE 1
#define STM32_PLLMUL_VALUE 12
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE STM32_PPRE_DIV1
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_PLLNODIV STM32_PLLNODIV_DIV2
#define STM32_USBSW STM32_USBSW_HSI48
#define STM32_CECSW STM32_CECSW_HSI
#define STM32_I2C1SW STM32_I2C1SW_HSI
#define STM32_USART1SW STM32_USART1SW_PCLK
#define STM32_RTCSEL STM32_RTCSEL_LSI
/*
* IRQ system settings.
*/
#define STM32_IRQ_EXTI0_1_IRQ_PRIORITY 3
#define STM32_IRQ_EXTI2_3_IRQ_PRIORITY 3
#define STM32_IRQ_EXTI4_15_IRQ_PRIORITY 3
#define STM32_IRQ_EXTI16_IRQ_PRIORITY 3
#define STM32_IRQ_EXTI17_20_IRQ_PRIORITY 3
#define STM32_IRQ_EXTI21_22_IRQ_PRIORITY 3
/*
* ADC driver system settings.
*/
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
/*
* DAC driver system settings.
*/
#define STM32_DAC_DUAL_MODE FALSE
#define STM32_DAC_USE_DAC1_CH1 TRUE
#define STM32_DAC_USE_DAC1_CH2 FALSE
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 2
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM6 TRUE
#define STM32_GPT_USE_TIM14 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 2
#define STM32_GPT_TIM2_IRQ_PRIORITY 2
#define STM32_GPT_TIM3_IRQ_PRIORITY 2
#define STM32_GPT_TIM6_IRQ_PRIORITY 2
#define STM32_GPT_TIM14_IRQ_PRIORITY 2
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_IRQ_PRIORITY 3
#define STM32_I2C_I2C2_IRQ_PRIORITY 3
#define STM32_I2C_USE_DMA TRUE
#define STM32_I2C_I2C1_DMA_PRIORITY 1
#define STM32_I2C_I2C2_DMA_PRIORITY 1
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* I2S driver system settings.
*/
#define STM32_I2S_USE_SPI1 FALSE
#define STM32_I2S_USE_SPI2 FALSE
#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
STM32_I2S_MODE_RX)
#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
STM32_I2S_MODE_RX)
#define STM32_I2S_SPI1_IRQ_PRIORITY 2
#define STM32_I2S_SPI2_IRQ_PRIORITY 2
#define STM32_I2S_SPI1_DMA_PRIORITY 1
#define STM32_I2S_SPI2_DMA_PRIORITY 1
#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY 3
#define STM32_ICU_TIM2_IRQ_PRIORITY 3
#define STM32_ICU_TIM3_IRQ_PRIORITY 3
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY 3
#define STM32_PWM_TIM2_IRQ_PRIORITY 3
#define STM32_PWM_TIM3_IRQ_PRIORITY 3
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 TRUE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USART1_PRIORITY 3
#define STM32_SERIAL_USART2_PRIORITY 3
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 2
#define STM32_SPI_SPI2_IRQ_PRIORITY 2
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 2
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USART1_IRQ_PRIORITY 3
#define STM32_UART_USART2_IRQ_PRIORITY 3
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
#include "mcuconf_community.h"
#endif /* MCUCONF_H */
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/* Copyright 2017 Jack Humbert
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include "quantum.h"
#if defined(UNICODE_ENABLE) + defined(UNICODEMAP_ENABLE) + defined(UCIS_ENABLE) > 1
#error "Cannot enable more than one Unicode method (UNICODE, UNICODEMAP, UCIS) at the same time"
#endif
// Keycodes used for starting Unicode input on different platforms
#ifndef UNICODE_OSX_KEY
#define UNICODE_OSX_KEY KC_LALT
#endif
#ifndef UNICODE_WINC_KEY
#define UNICODE_WINC_KEY KC_RALT
#endif
// Comma-delimited, ordered list of input modes selected for use (e.g. in cycle)
// Example: #define UNICODE_SELECTED_MODES UC_WINC, UC_LNX
#ifndef UNICODE_SELECTED_MODES
#define UNICODE_SELECTED_MODES -1
#endif
// Whether input mode changes in cycle should be written to EEPROM
#ifndef UNICODE_CYCLE_PERSIST
#define UNICODE_CYCLE_PERSIST true
#endif
// Delay between starting Unicode input and sending a sequence, in ms
#ifndef UNICODE_TYPE_DELAY
#define UNICODE_TYPE_DELAY 10
#endif
enum unicode_input_modes {
UC_OSX, // Mac OS X using Unicode Hex Input
UC_LNX, // Linux using IBus
UC_WIN, // Windows using EnableHexNumpad
UC_BSD, // BSD (not implemented)
UC_WINC, // Windows using WinCompose (https://github.com/samhocevar/wincompose)
UC__COUNT // Number of available input modes (always leave at the end)
};
typedef union {
uint32_t raw;
struct {
uint8_t input_mode : 8;
};
} unicode_config_t;
extern unicode_config_t unicode_config;
void unicode_input_mode_init(void);
uint8_t get_unicode_input_mode(void);
void set_unicode_input_mode(uint8_t mode);
void cycle_unicode_input_mode(uint8_t offset);
void persist_unicode_input_mode(void);
void unicode_input_start(void);
void unicode_input_finish(void);
void register_hex(uint16_t hex);
void send_unicode_hex_string(const char *str);
bool process_unicode_common(uint16_t keycode, keyrecord_t *record);
#define UC_BSPC UC(0x0008)
#define UC_SPC UC(0x0020)
#define UC_EXLM UC(0x0021)
#define UC_DQUT UC(0x0022)
#define UC_HASH UC(0x0023)
#define UC_DLR UC(0x0024)
#define UC_PERC UC(0x0025)
#define UC_AMPR UC(0x0026)
#define UC_QUOT UC(0x0027)
#define UC_LPRN UC(0x0028)
#define UC_RPRN UC(0x0029)
#define UC_ASTR UC(0x002A)
#define UC_PLUS UC(0x002B)
#define UC_COMM UC(0x002C)
#define UC_DASH UC(0x002D)
#define UC_DOT UC(0x002E)
#define UC_SLSH UC(0x002F)
#define UC_0 UC(0x0030)
#define UC_1 UC(0x0031)
#define UC_2 UC(0x0032)
#define UC_3 UC(0x0033)
#define UC_4 UC(0x0034)
#define UC_5 UC(0x0035)
#define UC_6 UC(0x0036)
#define UC_7 UC(0x0037)
#define UC_8 UC(0x0038)
#define UC_9 UC(0x0039)
#define UC_COLN UC(0x003A)
#define UC_SCLN UC(0x003B)
#define UC_LT UC(0x003C)
#define UC_EQL UC(0x003D)
#define UC_GT UC(0x003E)
#define UC_QUES UC(0x003F)
#define UC_AT UC(0x0040)
#define UC_A UC(0x0041)
#define UC_B UC(0x0042)
#define UC_C UC(0x0043)
#define UC_D UC(0x0044)
#define UC_E UC(0x0045)
#define UC_F UC(0x0046)
#define UC_G UC(0x0047)
#define UC_H UC(0x0048)
#define UC_I UC(0x0049)
#define UC_J UC(0x004A)
#define UC_K UC(0x004B)
#define UC_L UC(0x004C)
#define UC_M UC(0x004D)
#define UC_N UC(0x004E)
#define UC_O UC(0x004F)
#define UC_P UC(0x0050)
#define UC_Q UC(0x0051)
#define UC_R UC(0x0052)
#define UC_S UC(0x0053)
#define UC_T UC(0x0054)
#define UC_U UC(0x0055)
#define UC_V UC(0x0056)
#define UC_W UC(0x0057)
#define UC_X UC(0x0058)
#define UC_Y UC(0x0059)
#define UC_Z UC(0x005A)
#define UC_LBRC UC(0x005B)
#define UC_BSLS UC(0x005C)
#define UC_RBRC UC(0x005D)
#define UC_CIRM UC(0x005E)
#define UC_UNDR UC(0x005F)
#define UC_GRV UC(0x0060)
#define UC_a UC(0x0061)
#define UC_b UC(0x0062)
#define UC_c UC(0x0063)
#define UC_d UC(0x0064)
#define UC_e UC(0x0065)
#define UC_f UC(0x0066)
#define UC_g UC(0x0067)
#define UC_h UC(0x0068)
#define UC_i UC(0x0069)
#define UC_j UC(0x006A)
#define UC_k UC(0x006B)
#define UC_l UC(0x006C)
#define UC_m UC(0x006D)
#define UC_n UC(0x006E)
#define UC_o UC(0x006F)
#define UC_p UC(0x0070)
#define UC_q UC(0x0071)
#define UC_r UC(0x0072)
#define UC_s UC(0x0073)
#define UC_t UC(0x0074)
#define UC_u UC(0x0075)
#define UC_v UC(0x0076)
#define UC_w UC(0x0077)
#define UC_x UC(0x0078)
#define UC_y UC(0x0079)
#define UC_z UC(0x007A)
#define UC_LCBR UC(0x007B)
#define UC_PIPE UC(0x007C)
#define UC_RCBR UC(0x007D)
#define UC_TILD UC(0x007E)
#define UC_DEL UC(0x007F)
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