/* * ARM Versatile Platform/Application Baseboard System emulation. * * Copyright (c) 2005-2006 CodeSourcery. * Written by Paul Brook * * This code is licenced under the GPL. */ #include "vl.h" #include "arm_pic.h" #define LOCK_VALUE 0xa05f /* Primary interrupt controller. */ typedef struct vpb_sic_state { arm_pic_handler handler; uint32_t base; uint32_t level; uint32_t mask; uint32_t pic_enable; void *parent; int irq; } vpb_sic_state; static void vpb_sic_update(vpb_sic_state *s) { uint32_t flags; flags = s->level & s->mask; pic_set_irq_new(s->parent, s->irq, flags != 0); } static void vpb_sic_update_pic(vpb_sic_state *s) { int i; uint32_t mask; for (i = 21; i <= 30; i++) { mask = 1u << i; if (!(s->pic_enable & mask)) continue; pic_set_irq_new(s->parent, i, (s->level & mask) != 0); } } static void vpb_sic_set_irq(void *opaque, int irq, int level) { vpb_sic_state *s = (vpb_sic_state *)opaque; if (level) s->level |= 1u << irq; else s->level &= ~(1u << irq); if (s->pic_enable & (1u << irq)) pic_set_irq_new(s->parent, irq, level); vpb_sic_update(s); } static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset) { vpb_sic_state *s = (vpb_sic_state *)opaque; offset -= s->base; switch (offset >> 2) { case 0: /* STATUS */ return s->level & s->mask; case 1: /* RAWSTAT */ return s->level; case 2: /* ENABLE */ return s->mask; case 4: /* SOFTINT */ return s->level & 1; case 8: /* PICENABLE */ return s->pic_enable; default: printf ("vpb_sic_read: Bad register offset 0x%x\n", offset); return 0; } } static void vpb_sic_write(void *opaque, target_phys_addr_t offset, uint32_t value) { vpb_sic_state *s = (vpb_sic_state *)opaque; offset -= s->base; switch (offset >> 2) { case 2: /* ENSET */ s->mask |= value; break; case 3: /* ENCLR */ s->mask &= ~value; break; case 4: /* SOFTINTSET */ if (value) s->mask |= 1; break; case 5: /* SOFTINTCLR */ if (value) s->mask &= ~1u; break; case 8: /* PICENSET */ s->pic_enable |= (value & 0x7fe00000); vpb_sic_update_pic(s); break; case 9: /* PICENCLR */ s->pic_enable &= ~value; vpb_sic_update_pic(s); break; default: printf ("vpb_sic_write: Bad register offset 0x%x\n", offset); return; } vpb_sic_update(s); } static CPUReadMemoryFunc *vpb_sic_readfn[] = { vpb_sic_read, vpb_sic_read, vpb_sic_read }; static CPUWriteMemoryFunc *vpb_sic_writefn[] = { vpb_sic_write, vpb_sic_write, vpb_sic_write }; static vpb_sic_state *vpb_sic_init(uint32_t base, void *parent, int irq) { vpb_sic_state *s; int iomemtype; s = (vpb_sic_state *)qemu_mallocz(sizeof(vpb_sic_state)); if (!s) return NULL; s->handler = vpb_sic_set_irq; s->base = base; s->parent = parent; s->irq = irq; iomemtype = cpu_register_io_memory(0, vpb_sic_readfn, vpb_sic_writefn, s); cpu_register_physical_memory(base, 0x00000fff, iomemtype); /* ??? Save/restore. */ return s; } /* System controller. */ typedef struct { uint32_t base; uint32_t leds; uint16_t lockval; uint32_t cfgdata1; uint32_t cfgdata2; uint32_t flags; uint32_t nvflags; uint32_t resetlevel; } vpb_sys_state; static uint32_t vpb_sys_read(void *opaque, target_phys_addr_t offset) { vpb_sys_state *s = (vpb_sys_state *)opaque; offset -= s->base; switch (offset) { case 0x00: /* ID */ return 0x41007004; case 0x04: /* SW */ /* General purpose hardware switches. We don't have a useful way of exposing these to the user. */ return 0; case 0x08: /* LED */ return s->leds; case 0x20: /* LOCK */ return s->lockval; case 0x0c: /* OSC0 */ case 0x10: /* OSC1 */ case 0x14: /* OSC2 */ case 0x18: /* OSC3 */ case 0x1c: /* OSC4 */ case 0x24: /* 100HZ */ /* ??? Implement these. */ return 0; case 0x28: /* CFGDATA1 */ return s->cfgdata1; case 0x2c: /* CFGDATA2 */ return s->cfgdata2; case 0x30: /* FLAGS */ return s->flags; case 0x38: /* NVFLAGS */ return s->nvflags; case 0x40: /* RESETCTL */ return s->resetlevel; case 0x44: /* PCICTL */ return 1; case 0x48: /* MCI */ return 0; case 0x4c: /* FLASH */ return 0; case 0x50: /* CLCD */ return 0x1000; case 0x54: /* CLCDSER */ return 0; case 0x58: /* BOOTCS */ return 0; case 0x5c: /* 24MHz */ /* ??? not implemented. */ return 0; case 0x60: /* MISC */ return 0; case 0x64: /* DMAPSR0 */ case 0x68: /* DMAPSR1 */ case 0x6c: /* DMAPSR2 */ case 0x8c: /* OSCRESET0 */ case 0x90: /* OSCRESET1 */ case 0x94: /* OSCRESET2 */ case 0x98: /* OSCRESET3 */ case 0x9c: /* OSCRESET4 */ case 0xc0: /* SYS_TEST_OSC0 */ case 0xc4: /* SYS_TEST_OSC1 */ case 0xc8: /* SYS_TEST_OSC2 */ case 0xcc: /* SYS_TEST_OSC3 */ case 0xd0: /* SYS_TEST_OSC
#
#             LUFA Library
#     Copyright (C) Dean Camera, 2017.
#
#  dean [at] fourwalledcubicle [dot] com
#           www.lufa-lib.org
#
# --------------------------------------
#         LUFA Project Makefile.
# --------------------------------------

# Run "make help" for target help.

MCU          = at90usb1287
ARCH         = AVR8
BOARD        = USBKEY
F_CPU        = 8000000
F_USB        = $(F_CPU)
OPTIMIZATION = s
TARGET       = KeyboardHostWithParser
SRC          = $(TARGET).c $(LUFA_SRC_USB) $(LUFA_SRC_USBCLASS) $(LUFA_SRC_SERIAL)
LUFA_PATH    = ../../../../LUFA
CC_FLAGS     = -DUSE_LUFA_CONFIG_HEADER -IConfig/
LD_FLAGS     =

# Default target
all:

# Include LUFA-specific DMBS extension modules
DMBS_LUFA_PATH ?= $(LUFA_PATH)/Build/LUFA
include $(DMBS_LUFA_PATH)/lufa-sources.mk
include $(DMBS_LUFA_PATH)/lufa-gcc.mk

# Include common DMBS build system modules
DMBS_PATH      ?= $(LUFA_PATH)/Build/DMBS/DMBS
include $(DMBS_PATH)/core.mk
include $(DMBS_PATH)/cppcheck.mk
include $(DMBS_PATH)/doxygen.mk
include $(DMBS_PATH)/dfu.mk
include $(DMBS_PATH)/gcc.mk
include $(DMBS_PATH)/hid.mk
include $(DMBS_PATH)/avrdude.mk
include $(DMBS_PATH)/atprogram.mk
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-07 03:32:17 +0000