\section{Introduction to Yosys} \begin{frame} \sectionpage \end{frame} \iffalse %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Representations of (digital) Circuits} \begin{frame}[t]{\subsecname} \begin{itemize} \item Graphical \begin{itemize} \item \alert<1>{Schematic Diagram} \item \alert<2>{Physical Layout} \end{itemize} \bigskip \item Non-graphical \begin{itemize} \item \alert<3>{Netlists} \item \alert<4>{Hardware Description Languages (HDLs)} \end{itemize} \end{itemize} \bigskip \begin{block}{Definition: \only<1>{Schematic Diagram}% \only<2>{Physical Layout}% \only<3>{Netlists}% \only<4>{Hardware Description Languages (HDLs)}} \only<1>{ Graphical representation of the circuit topology. Circuit elements are represented by symbols and electrical connections by lines. The geometric layout is for readability only. }% \only<2>{ The actual physical geometry of the device (PCB or ASIC manufacturing masks). This is the final product of the design process. }% \only<3>{ A list of circuit elements and a list of connections. This is the raw circuit topology. }% \only<4>{ Computer languages (like programming languages) that can be used to describe circuits. HDLs are much more powerful in describing huge circuits than schematic diagrams. }% \end{block} \end{frame} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \fi \subsection{Levels of Abstraction for Digital Circuits} \begin{frame}[t]{\subsecname} \begin{itemize} \item \alert<1>{System Level} \item \alert<2>{High Level} \item \alert<3>{Behavioral Level} \item \alert<4>{Register-Transfer Level (RTL)} \item \alert<5>{Logical Gate Level} \item \alert<6>{Physical Gate Level} \item \alert<7>{Switch Level} \end{itemize} \bigskip \begin{block}{Definition: \only<1>{System Level}% \only<2>{High Level}% \only<3>{Behavioral Level}% \only<4>{Register-Transfer Level (RTL)}% \only<5>{Logical Gate Level}% \only<6>{Physical Gate Level}% \only<7>{Switch Level}} \only<1>{ Overall view of the circuit. E.g. block-diagrams or instruction-set architecture descriptions. }% \only<2>{ Functional implementation of circuit in high-level programming language (C, C++, SystemC, Matlab, Python, etc.). }% \only<3>{ Cycle-accurate description of circuit in hardware description language (Verilog, VHDL, etc.). }% \only<4>{ List of registers (flip-flops) and logic functions that calculate the next state from the previous one. Usually a netlist utilizing high-level cells such as adders, multipliers, multiplexer, etc. }% \only<5>{ Netlist of single-bit registers and basic logic gates (such as AND, OR, NOT, etc.). Popular form: And-Inverter-Graphs (AIGs) with pairs of primary inputs and outputs for each register bit. }% \only<6>{ Netlist of cells that actually are available on the target architecture (such as CMOS gates in an ASIC or LUTs in an FPGA). Optimized for area, power, and/or speed (static timing or number of logic levels). }% \only<7>{ Netlist of individual transistors. }% \end{block} \end{frame} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Digital Circuit Synthesis} \begin{frame}{\subsecname} Synthesis Tools (such as Yosys) can transform HDL code to circuits: \bigskip \begin{center} \begin{tikzpicture}[scale=0.8, every node/.style={transform shape}] \tikzstyle{lvl} = [draw, fill=MyBlue, rectangle, minimum height=2em, minimum width=15em] \node[lvl] (sys) {System Level}; \node[lvl] (hl) [below of=sys] {High Level}; \node[lvl] (beh) [below of=hl] {Behavioral Level}; \node[lvl] (rtl) [below of=beh] {Register-Transfer Level (RTL)}; \node[lvl] (lg) [below of=rtl] {Logical Gate Level}; \node[lvl] (pg) [below of=lg] {Physical Gate Level}; \node[lvl] (sw) [below of=pg] {Switch Level}; \draw[dotted] (sys.east) -- ++(1,0) coordinate (sysx); \draw[dotted] (hl.east) -- ++(1,0) coordinate (hlx); \draw[dotted] (beh.east) -- ++(1,0) coordinate (behx); \draw[dotted] (rtl.east) -- ++(1,0) coordinate (rtlx); \draw[dotted] (lg.east) -- ++(1,0) coordinate (lgx); \draw[dotted] (pg.east) -- ++(1,0) coordinate (pgx); \draw[dotted] (sw.east) -- ++(1,0) coordinate (swx); \draw[gray,|->] (sysx) -- node[right] {System Design} (hlx); \draw[|->|] (hlx) -- node[right] {High Level Synthesis (HLS)} (behx); \draw[->|] (behx) -- node[right] {Behavioral Synthesis} (rtlx); \draw[->|] (rtlx) -- node[right] {RTL Synthesis} (lgx); \draw[->|] (lgx) -- node[right] {Logic Synthesis} (pgx); \draw[gray,->|] (pgx) -- node[right] {Cell Library} (swx); \draw[dotted] (behx) -- ++(4,0) coordinate (a); \draw[dotted] (pgx) -- ++(4,0) coordinate (b); \draw[|->|] (a) -- node[right] {Yosys} (b); \end{tikzpicture} \end{center} \end{frame} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{What Yosys can and can't do} \begin{frame}{\subsecname} Things Yosys can do: \begin{itemize} \item Read and process (most of) modern Verilog-2005 code. \item Perform all kinds of operations on
# Documentation Best Practices
This page exists to document best practices when writing documentation for QMK. Following these guidelines will help to keep a consistent tone and style, which will in turn help other people more easily understand QMK.
# Page Opening
Your documentation page should generally start with an H1 heading, followed by a 1 paragraph description of what the user will find on this page. Keep in mind that this heading and paragraph will sit next to the Table of Contents, so keep the heading short and avoid long strings with no whitespace.
Example:
```
# My Page Title
This page covers my super cool feature. You can use this feature to make coffee, squeeze fresh oj, and have an egg mcmuffin and hashbrowns delivered from your local macca's by drone.
```
# Headings
Your page should generally have multiple "H1" headings. Only H1 and H2 headings will included in the Table of Contents, so plan them out appropriately. Excess width should be avoided in H1 and H2 headings to prevent the Table of Contents from getting too wide.
# Styled Hint Blocks
You can have styled hint blocks drawn around text to draw attention to it.
### Important
```
!> This is important
```
Renders as:
!> This is important
### General Tips
```
?> This is a helpful tip.
```
Renders as:
?> This is a helpful tip.
# Documenting Features
If you create a new feature for QMK, create a documentation page for it. It doesn't have to be very long, a few sentences describing your feature and a table listing any relevant keycodes is enough. Here is a basic template:
```markdown
# My Cool Feature
This page describes my cool feature. You can use my cool feature to make coffee and order cream and sugar to be delivered via drone.
## My Cool Feature Keycodes
|Long Name|Short Name|Description|
|---------|----------|-----------|
|KC_COFFEE||Make Coffee|
|KC_CREAM||Order Cream|
|KC_SUGAR||Order Sugar|
```
Place your documentation into `docs/feature_<my_cool_feature>.md`, and add that file to the appropriate place in `docs/_sidebar.md`. If you have added any keycodes be sure to add them to `docs/keycodes.md` with a link back to your feature page.