/* * QEMU 8259 interrupt controller emulation * * Copyright (c) 2003-2004 Fabrice Bellard * Copyright (c) 2005 Intel Corperation * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include /* set irq level. If an edge is detected, then the IRR is set to 1 */ static inline void pic_set_irq1(PicState *s, int irq, int level) { int mask; mask = 1 << irq; if (s->elcr & mask) { /* level triggered */ if (level) { s->irr |= mask; s->last_irr |= mask; } else { s->irr &= ~mask; s->last_irr &= ~mask; } } else { /* edge triggered */ if (level) { if ((s->last_irr & mask) == 0) { s->irr |= mask; } s->last_irr |= mask; } else { s->last_irr &= ~mask; } } } /* return the highest priority found in mask (highest = smallest number). Return 8 if no irq */ static inline int get_priority(PicState *s, int mask) { int priority; if (mask == 0) return 8; priority = 0; while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) priority++; return priority; } /* return the pic wanted interrupt. return -1 if none */ static int pic_get_irq(PicState *s) { int mask, cur_priority, priority; mask = s->irr & ~s->imr; priority = get_priority(s, mask); if (priority == 8) return -1; /* compute current priority. If special fully nested mode on the master, the IRQ coming from the slave is not taken into account for the priority computation. */ mask = s->isr; if (s->special_fully_nested_mode && s == &s->pics_state->pics[0]) mask &= ~(1 << 2); cur_priority = get_priority(s, mask); if (priority < cur_priority) { /* higher priority found: an irq should be generated */ return (priority + s->priority_add) & 7; } else { return -1; } } /* raise irq to CPU if necessary. must be called every time the active irq may change */ /* XXX: should not export it, but it is needed for an APIC kludge */ void pic_update_irq(struct hvm_virpic *s) { int irq2, irq; /* first look at slave pic */ irq2 = pic_get_irq(&s->pics[1]); if (irq2 >= 0) { /* if irq request by slave pic, signal master PIC */ pic_set_irq1(&s->pics[0], 2, 1); pic_set_irq1(&s->pics[0], 2, 0); } /* look at requested irq */ irq = pic_get_irq(&s->pics[0]); if (irq >= 0) { s->irq_request(s->irq_request_opaque, 1); } } void pic_set_irq_new(void *opaque, int irq, int level) { struct hvm_virpic *s = opaque; hvm_vioapic_set_irq(current->domain, irq, level); pic_set_irq1(&s->pics[irq >> 3], irq & 7, level); /* used for IOAPIC irqs */ if (s->alt_irq_func) s->alt_irq_func(s->alt_irq_opaque, irq, level); pic_update_irq(s); } void do_pic_irqs (struct hvm_virpic *s, uint16_t irqs) { s->pics[1].irr |= (uint8_t)(irqs >> 8); s->pics[0].irr |= (uint8_t) irqs; hvm_vioapic_do_irqs(current->domain, irqs); pic_update_irq(s); } void do_pic_irqs_clear (struct hvm_virpic *s, uint16_t irqs) { s->pics[1].irr &= ~(uint8_t)(irqs >> 8); s->pics[0].irr &= ~(uint8_t) irqs; hvm_vioapic_do_irqs_clear(current->domain, irqs); pic_update_irq(s); } /* obsolete function */ void pic_set_irq(struct hvm_virpic *isa_pic, int irq, int level) { pic_set_irq_new(isa_pic, irq, level); } /* acknowledge interrupt 'irq' */ static inline void pic_intack(PicState *s, int irq) { if (s->auto_eoi) { if (s->rotate_on_auto_eoi) s->priority_add = (irq + 1) & 7; } else { s->isr |= (1 << irq); } /* We don't clear a level sensitive interrupt here */ if (!(s->elcr & (1 << irq))) s->irr &= ~(1 << irq); } int pic_read_irq(struct hvm_virpic *s) { int irq, irq2, intno; irq = pic_get_irq(&s->pics[0]); if (irq >= 0) { pic_intack(&s->pics[0], irq); if (irq == 2) { irq2 = pic_get_irq(&s->pics[1]); if (irq2 >= 0) { pic_intack(&s->pics[1], irq2); } else { /* spurious IRQ on slave controller */ irq2 = 7; } intno = s->pics[1].irq_base + irq2; irq = irq2 + 8; } else { intno = s->pics[0].irq_base + irq; } } else { /* spurious IRQ on host controller */ printk("spurious IRQ irq got=%d\n",irq); irq = 7; intno = s->pics[0].irq_base + irq; } pic_update_irq(s); return intno; } static void update_shared_irr(struct hvm_virpic *s, PicState *c) { uint8_t *pl, *pe; get_sp(current->domain)->sp_global.pic_elcr = s->pics[0].elcr | ((u16)s->pics[1].elcr << 8); pl =(uint8_t*)&get_sp(current->domain)->sp_global.pic_last_irr; pe =(uint8_t*)&get_sp(c
/*
    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
                 2011,2012 Giovanni Di Sirio.

    This file is part of ChibiOS/RT.

    ChibiOS/RT is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3 of the License, or
    (at your option) any later version.

    ChibiOS/RT is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program.  If not, see <http://www.gnu.org/licenses/>.
*/

#include "ch.h"
#include "hal.h"

/*
 * SPI configuration (8MHz, CPHA=0, CPOL=0, MSb first).
 */
static ROMCONST SPIConfig spicfg = {
  NULL,
  GPIOD,
  PD_LD10,
  0
};

/*
 * Transmit data.
 */
static ROMCONST uint8_t digits[32] = {
  0x24, 0xAF, 0xE0, 0xA2, 0x2B, 0x32, 0x30, 0xA7,
  0x20, 0x22, 0x21, 0x38, 0x74, 0xA8, 0x70, 0x71,
  0x04, 0x8F, 0xC0, 0x82, 0x0B, 0x12, 0x10, 0x87,
  0x00, 0x02, 0x01, 0x18, 0x54, 0x88, 0x50, 0x51
};

/*
 * Receive buffer.
 */
static uint8_t buffer[32];

/*
 * Application entry point.
 */
void main(void) {

  /*
   * System initializations.
   * - HAL initialization, this also initializes the configured device drivers
   *   and performs the board-specific initializations.
   * - Kernel initialization, the main() function becomes a thread and the
   *   RTOS is active.
   */
  halInit();
  chSysInit();

  /*
   * OS initialization.
   */
  chSysInit();

  /*
   * Activates the SPI driver 1 using the driver default configuration.
   */
  spiStart(&SPID1, &spicfg);

  /*
   * Normal main() thread activity.
   */
  while (TRUE) {
    volatile uint8_t b;

    chThdSleepMilliseconds(1000);
    /* Exchanging data, if the pins MISO and MOSI are connected then the
       transmitted data is received back into the buffer. On the
       STM8S-Discovery board the pins are CN2-9 and CN2-10.*/
    spiSelect(&SPID1);
    spiExchange(&SPID1, sizeof(digits), digits, buffer);
    /* Polled transfers test.*/
    b = spiPolledExchange(&SPID1, 0x55);    
    b = spiPolledExchange(&SPID1, 0xAA);    
    spiUnselect(&SPID1);
  }
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-24 02:43:55 +0000