/* * SMSC 91C111 Ethernet interface emulation * * Copyright (c) 2005 CodeSourcery, LLC. * Written by Paul Brook * * This code is licenced under the GPL */ #include "vl.h" /* For crc32 */ #include /* Number of 2k memory pages available. */ #define NUM_PACKETS 4 typedef struct { uint32_t base; VLANClientState *vc; uint16_t tcr; uint16_t rcr; uint16_t cr; uint16_t ctr; uint16_t gpr; uint16_t ptr; uint16_t ercv; void *pic; int irq; int bank; int packet_num; int tx_alloc; /* Bitmask of allocated packets. */ int allocated; int tx_fifo_len; int tx_fifo[NUM_PACKETS]; int rx_fifo_len; int rx_fifo[NUM_PACKETS]; int tx_fifo_done_len; int tx_fifo_done[NUM_PACKETS]; /* Packet buffer memory. */ uint8_t data[NUM_PACKETS][2048]; uint8_t int_level; uint8_t int_mask; uint8_t macaddr[6]; } smc91c111_state; #define RCR_SOFT_RST 0x8000 #define RCR_STRIP_CRC 0x0200 #define RCR_RXEN 0x0100 #define TCR_EPH_LOOP 0x2000 #define TCR_NOCRC 0x0100 #define TCR_PAD_EN 0x0080 #define TCR_FORCOL 0x0004 #define TCR_LOOP 0x0002 #define TCR_TXEN 0x0001 #define INT_MD 0x80 #define INT_ERCV 0x40 #define INT_EPH 0x20 #define INT_RX_OVRN 0x10 #define INT_ALLOC 0x08 #define INT_TX_EMPTY 0x04 #define INT_TX 0x02 #define INT_RCV 0x01 #define CTR_AUTO_RELEASE 0x0800 #define CTR_RELOAD 0x0002 #define CTR_STORE 0x0001 #define RS_ALGNERR 0x8000 #define RS_BRODCAST 0x4000 #define RS_BADCRC 0x2000 #define RS_ODDFRAME 0x1000 #define RS_TOOLONG 0x0800 #define RS_TOOSHORT 0x0400 #define RS_MULTICAST 0x0001 /* Update interrupt status. */ static void smc91c111_update(smc91c111_state *s) { int level; if (s->tx_fifo_len == 0) s->int_level |= INT_TX_EMPTY; if (s->tx_fifo_done_len != 0) s->int_level |= INT_TX; level = (s->int_level & s->int_mask) != 0; pic_set_irq_new(s->pic, s->irq, level); } /* Try to allocate a packet. Returns 0x80 on failure. */ static int smc91c111_allocate_packet(smc91c111_state *s) { int i; if (s->allocated == (1 << NUM_PACKETS) - 1) { return 0x80; } for (i = 0; i < NUM_PACKETS; i++) { if ((s->allocated & (1 << i)) == 0) break; } s->allocated |= 1 << i; return i; } /* Process a pending TX allocate. */ static void smc91c111_tx_alloc(smc91c111_state *s) { s->tx_alloc = smc91c111_allocate_packet(s); if (s->tx_alloc == 0x80) return; s->int_level |= INT_ALLOC; smc91c111_update(s); } /* Remove and item from the RX FIFO. */ static void smc91c111_pop_rx_fifo(smc91c111_state *s) { int i; s->rx_fifo_len--; if (s->rx_fifo_len) { for (i = 0; i < s->rx_fifo_len; i++) s->rx_fifo[i] = s->rx_fifo[i + 1]; s->int_level |= INT_RCV; } else { s->int_level &= ~INT_RCV; } smc91c111_update(s); } /* Remove an item from the TX completion FIFO. */ static void smc91c111_pop_tx_fifo_done(smc91c111_state *s) { int i; if (s->tx_fifo_done_len == 0) return; s->tx_fifo_done_len--; for (i = 0; i < s->tx_fifo_done_len; i++) s->tx_fifo_done[i] = s->tx_fifo_done[i + 1]; } /* Release the memory allocated to a packet. */ static void smc91c111_release_packet(smc91c111_state *s, int packet) { s->allocated &= ~(1 << packet); if (s->tx_alloc == 0x80) smc91c111_tx_alloc(s); } /* Flush the TX FIFO. */ static void smc91c111_do_tx(smc91c111_state *s) { int i; int len; int control; int add_crc; int packetnum; uint8_t *p; if ((s->tcr & TCR_TXEN) == 0) return; if (s->tx_fifo_len == 0) return; for (i = 0; i < s->tx_fifo_len; i++) { packetnum = s->tx_fifo[i]; p = &s->data[packetnum][0]; /* Set status word. */ *(p++) = 0x01; *(p++) = 0x40; len = *(p++); len |= ((int)*(p++)) << 8; len -= 6; control = p[len + 1]; if (control & 0x20) len++; /* ??? This overwrites the data following the buffer. Don't know what real hardware does. */ if (len < 64 && (s->tcr & TCR_PAD_EN)) { memset(p + len, 0, 64 - len); len = 64; } #if 0 /* The card is supposed to append the CRC to the frame. However none of the other network traffic has the CRC appended. Suspect this is low level ethernet detail we don't need to worry about. */ add_crc = (control & 0x10) || (s->tcr & TCR_NOCRC) == 0; if (add_crc) { uint32_t crc; crc = crc32(~0, p, len); memcpy(p + len, &crc, 4); len += 4; } #else add_crc = 0; #endif if (s->ctr & CTR_AUTO_RELEASE) /* Race? */ smc91c111_release_packet(s, packetnum); else if (s->tx_fifo_done_len < NUM_PACKETS) s->tx_fifo_done[s->tx_fifo_done_len++] = packetnum; qemu_send_packet(s->vc, p, len); } s->tx_fifo_len = 0; smc91c111_update(s); } /* Add a packet to the TX FIFO. */ static void smc91c111_queue_tx(smc91c111_state *s, int packet) { if (s->tx_fifo_len == NUM_PACKETS) return; s->tx_fifo[s->tx_fifo_len++] = packet; smc91c111_do_tx(s); } static void smc91c111_reset(smc91c111_state *s) { s->bank = 0; s->tx_fifo_len = 0; s->tx_fifo_done_len = 0; s->rx_fifo_len = 0; s->allocated = 0; s->packet_num = 0; s->tx_alloc = 0; s->tcr = 0; s->rcr = 0; s->cr = 0xa0b1; s->ctr = 0x1210; s->ptr = 0; s->ercv = 0x1f; s->int_level = INT_TX_EMPTY; s->int_mask = 0; smc91c111_update(s); } #define SET_LOW(name, val) s->name = (s->name & 0xff00) | val #define SET_HIGH(name, val) s->name = (s->name & 0xff) | (val << 8) static void smc91c111_writeb(void *opaque, target_phys_addr_t offset, uint32_t value) { smc91c111_state *s = (smc91c111_state *)opaque; offset -= s->base; if (offset == 14) { s->bank = value; return; } if (offset == 15) return; switch (s->bank) { case 0: switch (offset) { case 0: /* TCR */ SET_LOW(tcr, value); return; case 1: SET_HIGH(tcr, value); return; case 4: /* RCR */ SET_LOW(rcr, value); return; case 5: SET_HIGH(rcr, value); if (s->rcr & RCR_SOFT_RST) smc91c111_reset(s); return; case 10: case 11: /* RPCR */ /* Ignored */ return; } break; case 1: switch (offset) { case 0: /* CONFIG */ SET_LOW(cr, value); return; case 1: SET_HIGH(cr,value); return; case 2: case 3: /* BASE */ case 4: case 5: case 6: case 7: case 8: case 9: /* IA */ /* Not implemented. */ return; case 10: /* Genral Purpose */ SET_LOW(gpr, value); return; case 11: SET_HIGH(gpr, value); return; case 12: /* Control */ if (value & 1) fprintf(stderr, "smc91c111:EEPROM store not implemented\n"); if (value & 2) fprintf(stderr, "smc91c111:EEPROM reload not implemented\n"); value &= ~3; SET_LOW(ctr, value); return; case 13: SET_HIGH(ctr, value); return; } break; case 2: switch (offset) { case 0: /* MMU Command */ switch (value >> 5) { case 0: /* no-op */ break; case 1: /* Allocate for TX. */ s->tx_alloc = 0x80; s->int_level &= ~INT_ALLOC; smc91c111_update(s); smc91c111_tx_alloc(s); break; case 2: /* Reset MMU. */ s->allocated = 0; s->tx_fifo_len = 0; s->tx_fifo_done_len = 0; s->rx_fifo_len = 0; s->tx_alloc = 0; break; case 3: /* Remove from RX FIFO. */ smc91c111_pop_rx_fifo(s); break; case 4: /* Remove from RX FIFO and release. */ if (s->rx_
/*
    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio

    Licensed under the Apache License, Version 2.0 (the "License");
    you may not use this file except in compliance with the License.
    You may obtain a copy of the License at

        http://www.apache.org/licenses/LICENSE-2.0

    Unless required by applicable law or agreed to in writing, software
    distributed under the License is distributed on an "AS IS" BASIS,
    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    See the License for the specific language governing permissions and
    limitations under the License.
*/

#include "ch.h"
#include "hal.h"

#define DAC_BUFFER_SIZE 360

/*
 * DAC test buffer (sine wave).
 */
static const dacsample_t dac_buffer[DAC_BUFFER_SIZE] = {
  2047, 2082, 2118, 2154, 2189, 2225, 2260, 2296, 2331, 2367, 2402, 2437,
  2472, 2507, 2542, 2576, 2611, 2645, 2679, 2713, 2747, 2780, 2813, 2846,
  2879, 2912, 2944, 2976, 3008, 3039, 3070, 3101, 3131, 3161, 3191, 3221,
  3250, 3278, 3307, 3335, 3362, 3389, 3416, 3443, 3468, 3494, 3519, 3544,
  3568, 3591, 3615, 3637, 3660, 3681, 3703, 3723, 3744, 3763, 3782, 3801,
  3819, 3837, 3854, 3870, 3886, 3902, 3917, 3931, 3944, 3958, 3970, 3982,
  3993, 4004, 4014, 4024, 4033, 4041, 4049, 4056, 4062, 4068, 4074, 4078,
  4082, 4086, 4089, 4091, 4092, 4093, 4094, 4093, 4092, 4091, 4089, 4086,
  4082, 4078, 4074, 4068, 4062, 4056, 4049, 4041, 4033, 4024, 4014, 4004,
  3993, 3982, 3970, 3958, 3944, 3931, 3917, 3902, 3886, 3870, 3854, 3837,
  3819, 3801, 3782, 3763, 3744, 3723, 3703, 3681, 3660, 3637, 3615, 3591,
  3568, 3544, 3519, 3494, 3468, 3443, 3416, 3389, 3362, 3335, 3307, 3278,
  3250, 3221, 3191, 3161, 3131, 3101, 3070, 3039, 3008, 2976, 2944, 2912,
  2879, 2846, 2813, 2780, 2747, 2713, 2679, 2645, 2611, 2576, 2542, 2507,
  2472, 2437, 2402, 2367, 2331, 2296, 2260, 2225, 2189, 2154, 2118, 2082,
  2047, 2012, 1976, 1940, 1905, 1869, 1834, 1798, 1763, 1727, 1692, 1657,
  1622, 1587, 1552, 1518, 1483, 1449, 1415, 1381, 1347, 1314, 1281, 1248,
  1215, 1182, 1150, 1118, 1086, 1055, 1024,  993,  963,  933,  903,  873,
   844,  816,  787,  759,  732,  705,  678,  651,  626,  600,  575,  550,
   526,  503,  479,  457,  434,  413,  391,  371,  350,  331,  312,  293,
   275,  257,  240,  224,  208,  192,  177,  163,  150,  136,  124,  112,
   101,   90,   80,   70,   61,   53,   45,   38,   32,   26,   20,   16,
    12,    8,    5,    3,    2,    1,    0,    1,    2,    3,    5,    8,
    12,   16,   20,   26,   32,   38,   45,   53,   61,   70,   80,   90,
   101,  112,  124,  136,  150,  163,  177,  192,  208,  224,  240,  257,
   275,  293,  312,  331,  350,  371,  391,  413,  434,  457,  479,  503,
   526,  550,  575,  600,  626,  651,  678,  705,  732,  759,  787,  816,
   844,  873,  903,  933,  963,  993, 1024, 1055, 1086, 1118, 1150, 1182,
  1215, 1248, 1281, 1314, 1347, 1381, 1415, 1449, 1483, 1518, 1552, 1587,
  1622, 1657, 1692, 1727, 1763, 1798, 1834, 1869, 1905, 1940, 1976, 2012
};

/*
 * DAC streaming callback.
 */
size_t nx = 0, ny = 0, nz = 0;
static void end_cb1(DACDriver *dacp, dacsample_t *buffer, size_t n) {

  (void)dacp;

  nz++;
  if (dac_buffer == buffer) {
    nx += n;
  }
  else {
    ny += n;
  }

  if ((nz % 1000) == 0) {
    palTogglePad(GPIOB, GPIOB_LED4);
  }
}

/*
 * DAC error callback.
 */
static void error_cb1(DACDriver *dacp, dacerror_t err) {

  (void)dacp;
  (void)err;

  chSysHalt("DAC failure");
}

static const DACConfig dac1cfg1 = {
  .init         = 2047U,
  .datamode     = DAC_DHRM_12BIT_RIGHT,
  .cr           = 0
};

static const DACConversionGroup dacgrpcfg1 = {
  .num_channels = 1U,
  .end_cb       = end_cb1,
  .error_cb     = error_cb1,
  .trigger      = DAC_TRG(0)
};

/*
 * GPT6 configuration.
 */
static const GPTConfig gpt6cfg1 = {
  .frequency    = 1000000U,
  .callback     = NULL,
  .cr2          = TIM_CR2_MMS_1,    /* MMS = 010 = TRGO on Update Event.    */
  .dier         = 0U
};

/*
 * Application entry point.
 */
int main(void) {

  /*
   * System initializations.
   * - HAL initialization, this also initializes the configured device drivers
   *   and performs the board-specific initializations.
   * - Kernel initialization, the main() function becomes a thread and the
   *   RTOS is active.
   */
  halInit();
  chSysInit();

  /*
   * Starting DAC1 driver, setting up the output pin as analog as suggested
   * by the Reference Manual.
   */
  palSetPadMode(GPIOA, 4, PAL_MODE_INPUT_ANALOG);
  dacStart(&DACD1, &dac1cfg1);

  /*
   * Starting GPT6 driver, it is used for triggering the DAC.
   */
  gptStart(&GPTD6, &gpt6cfg1);

  /*
   * Starting a continuous conversion.
   */
  dacStartConversion(&DACD1, &dacgrpcfg1,
                     (dacsample_t *)dac_buffer, DAC_BUFFER_SIZE);
  gptStartContinuous(&GPTD6, 2U);

  /*
   * Normal main() thread activity, if the button is pressed then the DAC
   * transfer is stopped.
   */
  while (true) {
    if (palReadPad(GPIOA, GPIOA_BUTTON)) {
      gptStopTimer(&GPTD6);
      dacStopConversion(&DACD1);
    }
    chThdSleepMilliseconds(500);
  }
  return 0;
}
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