/* LUFA Library Copyright (C) Dean Camera, 2013. dean [at] fourwalledcubicle [dot] com www.lufa-lib.org */ /* Copyright 2013 Dean Camera (dean [at] fourwalledcubicle [dot] com) Permission to use, copy, modify, distribute, and sell this software and its documentation for any purpose is hereby granted without fee, provided that the above copyright notice appear in all copies and that both that the copyright notice and this permission notice and warranty disclaimer appear in supporting documentation, and that the name of the author not be used in advertising or publicity pertaining to distribution of the software without specific, written prior permission. The author disclaims all warranties with regard to this software, including all implied warranties of merchantability and fitness. In no event shall the author be liable for any special, indirect or consequential damages or any damages whatsoever resulting from loss of use, data or profits, whether in an action of contract, negligence or other tortious action, arising out of or in connection with the use or performance of this software. */ /** \file * * Header file for common DHCP defines. */ #ifndef _DHCP_COMMON_H_ #define _DHCP_COMMON_H_ /* Includes: */ #include #include #include #include "Config/AppConfig.h" #include /* Macros: */ /** UDP listen port for a BOOTP server. */ #define DHCP_SERVER_PORT 67 /** UDP listen port for a BOOTP client. */ #define DHCP_CLIENT_PORT 68 /** BOOTP message type for a BOOTP REQUEST message. */ #define DHCP_OP_BOOTREQUEST 0x01 /** BOOTP message type for a BOOTP REPLY message. */ #define DHCP_OP_BOOTREPLY 0x02 /** BOOTP flag for a BOOTP broadcast message. */ #define BOOTP_BROADCAST 0x8000 /** Magic DHCP cookie for a BOOTP message to identify it as a DHCP message. */ #define DHCP_MAGIC_COOKIE 0x63538263 /** Unique transaction ID used to identify DHCP responses to the client. */ #define DHCP_TRANSACTION_ID 0x13245466 /** DHCP message type for a DISCOVER message. */ #define DHCP_DISCOVER 1 /** DHCP message type for an OFFER message. */ #define DHCP_OFFER 2 /** DHCP message type for a REQUEST message. */ #define DHCP_REQUEST 3 /** DHCP message type for a DECLINE message. */ #define DHCP_DECLINE 4 /** DHCP message type for an ACK message. */ #define DHCP_ACK 5 /** DHCP message type for a NAK message. */ #define DHCP_NAK 6 /** DHCP message type for a RELEASE message. */ #define DHCP_RELEASE 7 /** DHCP medium type for standard Ethernet. */ #define DHCP_HTYPE_ETHERNET 1 /** DHCP message option for the network subnet mask. */ #define DHCP_OPTION_SUBNET_MASK 1 /** DHCP message option for the network gateway IP. */ #define DHCP_OPTION_ROUTER 3 /** DHCP message option for the network DNS server. */ #define DHCP_OPTION_DNS_SERVER 6 /** DHCP message option for the requested client IP address. */ #define DHCP_OPTION_REQ_IPADDR 50 /** DHCP message option for the IP address lease time. */ #define DHCP_OPTION_LEASE_TIME 51 /** DHCP message option for the DHCP message type. */ #define DHCP_OPTION_MSG_TYPE 53 /** DHCP message option for the DHCP server IP. */ #define DHCP_OPTION_SERVER_ID 54 /** DHCP message option for the list of required options from the server. */ #define DHCP_OPTION_REQ_LIST 55 /** DHCP message option for the options list terminator. */ #define DHCP_OPTION_END 255 /* Type Defines: */ /** Type define for a DHCP packet inside an Ethernet frame. */ typedef struct { uint8_t Operation; /**< DHCP operation, either DHCP_OP_BOOTREQUEST or DHCP_OP_BOOTREPLY */ uint8_t HardwareType; /**< Hardware carrier type constant */ uint8_t HardwareAddressLength; /**< Length in bytes of a hardware (MAC) address on the network */ uint8_t Hops; /**< Number of hops required to reach the server, unused */ uint32_t TransactionID; /**< Unique ID of the DHCP packet, for positive matching between sent and received packets */ uint16_t ElapsedSeconds; /**< Elapsed seconds since the request was made */ uint16_t Flags; /**< BOOTP packet flags */ uip_ipaddr_t ClientIP; /**< Client IP address, if already leased an IP */ uip_ipaddr_t YourIP; /**< Client IP address */ uip_ipaddr_t NextServerIP; /**< Legacy BOOTP protocol field, unused for DHCP */ uip_ipaddr_t RelayAgentIP; /**< Legacy BOOTP protocol field, unused for DHCP */ uint8_t ClientHardwareAddress[16]; /**< Hardware (MAC) address of the client making a request to the DHCP server */ uint8_t ServerHostnameString[64]; /**< Legacy BOOTP protocol field, unused for DHCP */ uint8_t BootFileName[128]; /**< Legacy BOOTP protocol field, unused for DHCP */ uint32_t Cookie; /**< Magic BOOTP protocol cookie to indicate a valid packet */ uint8_t Options[]; /**< DHCP message options */ } DHCP_Header_t; /* Function Prototypes: */ uint8_t DHCPCommon_SetOption(uint8_t* DHCPOptionList, const uint8_t Option, const uint8_t DataLen, void* const OptionData); bool DHCPCommon_GetOption(const uint8_t* DHCPOptionList, const uint8_t Option, void* const Destination); #endif 'n73' href='#n73'>73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 
/*
    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio

    Licensed under the Apache License, Version 2.0 (the "License");
    you may not use this file except in compliance with the License.
    You may obtain a copy of the License at

        http://www.apache.org/licenses/LICENSE-2.0

    Unless required by applicable law or agreed to in writing, software
    distributed under the License is distributed on an "AS IS" BASIS,
    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    See the License for the specific language governing permissions and
    limitations under the License.
*/

#ifndef _MCUCONF_H_
#define _MCUCONF_H_

/*
 * STM32L1xx drivers configuration.
 * The following settings override the default settings present in
 * the various device driver implementation headers.
 * Note that the settings for each driver only have effect if the whole
 * driver is enabled in halconf.h.
 *
 * IRQ priorities:
 * 15...0       Lowest...Highest.
 *
 * DMA priorities:
 * 0...3        Lowest...Highest.
 */

#define STM32L0xx_MCUCONF

/*
 * HAL driver system settings.
 */
#define STM32_NO_INIT                       FALSE
#define STM32_VOS                           STM32_VOS_1P8
#define STM32_PVD_ENABLE                    FALSE
#define STM32_PLS                           STM32_PLS_LEV0
#define STM32_HSI16_ENABLED                 TRUE
#define STM32_LSI_ENABLED                   FALSE
#define STM32_HSE_ENABLED                   FALSE
#define STM32_LSE_ENABLED                   TRUE
#define STM32_ADC_CLOCK_ENABLED             TRUE
#define STM32_USB_CLOCK_ENABLED             TRUE
#define STM32_MSIRANGE                      STM32_MSIRANGE_2M
#define STM32_SW                            STM32_SW_PLL
#define STM32_PLLSRC                        STM32_PLLSRC_HSI16
#define STM32_PLLMUL_VALUE                  4
#define STM32_PLLDIV_VALUE                  2
#define STM32_HPRE                          STM32_HPRE_DIV1
#define STM32_PPRE1                         STM32_PPRE1_DIV1
#define STM32_PPRE2                         STM32_PPRE2_DIV1
#define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK
#define STM32_MCOPRE                        STM32_MCOPRE_DIV1
#define STM32_RTCSEL                        STM32_RTCSEL_LSE
#define STM32_RTCPRE                        STM32_RTCPRE_DIV2
#define STM32_USART1SEL                     STM32_USART1SEL_APB
#define STM32_USART2SEL                     STM32_USART2SEL_APB
#define STM32_LPUART1SEL                    STM32_LPUART1SEL_APB
#define STM32_I2C1SEL                       STM32_I2C1SEL_APB
#define STM32_LPTIM1SEL                     STM32_LPTIM1SEL_APB
#define STM32_HSI48SEL                      STM32_HSI48SEL_HSI48

/*
 * ADC driver system settings.
 * Note, IRQ is shared with EXT channels 21 and 22.
 */
#define STM32_ADC_USE_ADC1                  FALSE
#define STM32_ADC_ADC1_CKMODE               STM32_ADC_CKMODE_ADCCLK
#define STM32_ADC_ADC1_DMA_PRIORITY         2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     2
#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(1, 1)
#define STM32_ADC_PRESCALER_VALUE           1

/*
 * EXT driver system settings.
 */
#define STM32_EXT_EXTI0_1_IRQ_PRIORITY      3
#define STM32_EXT_EXTI2_3_IRQ_PRIORITY      3
#define STM32_EXT_EXTI4_15_IRQ_PRIORITY     3
#define STM32_EXT_EXTI16_IRQ_PRIORITY       3
#define STM32_EXT_EXTI17_20_IRQ_PRIORITY    3
#define STM32_EXT_EXTI21_22_IRQ_PRIORITY    3

/*
 * GPT driver system settings.
 */
#define STM32_GPT_USE_TIM2                  FALSE
#define STM32_GPT_TIM2_IRQ_PRIORITY         2

/*
 * I2C driver system settings.
 */
#define STM32_I2C_USE_I2C1                  FALSE
#define STM32_I2C_USE_I2C2                  FALSE
#define STM32_I2C_BUSY_TIMEOUT              50
#define STM32_I2C_I2C1_IRQ_PRIORITY         3
#define STM32_I2C_I2C2_IRQ_PRIORITY         3
#define STM32_I2C_USE_DMA                   TRUE
#define STM32_I2C_I2C1_DMA_PRIORITY         1
#define STM32_I2C_I2C2_DMA_PRIORITY         1
#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")

/*
 * ICU driver system settings.
 */
#define STM32_ICU_USE_TIM2                  FALSE
#define STM32_ICU_TIM2_IRQ_PRIORITY         3

/*
 * PWM driver system settings.
 */
#define STM32_PWM_USE_ADVANCED              FALSE
#define STM32_PWM_USE_TIM2                  FALSE
#define STM32_PWM_TIM2_IRQ_PRIORITY         3

/*
 * SERIAL driver system settings.
 */
#define STM32_SERIAL_USE_USART1             FALSE
#define STM32_SERIAL_USE_USART2             FALSE
#define STM32_SERIAL_USE_LPUART1            FALSE
#define STM32_SERIAL_USART1_PRIORITY        3
#define STM32_SERIAL_USART2_PRIORITY        3
#define STM32_SERIAL_LPUART1_PRIORITY       3

/*
 * SPI driver system settings.
 */
#define STM32_SPI_USE_SPI1                  TRUE
#define STM32_SPI_USE_SPI2                  TRUE
#define STM32_SPI_SPI1_DMA_PRIORITY         1
#define STM32_SPI_SPI2_DMA_PRIORITY         1
#define STM32_SPI_SPI1_IRQ_PRIORITY         1
#define STM32_SPI_SPI2_IRQ_PRIORITY         1
#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
#define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")

/*
 * ST driver system settings.
 */
#define STM32_ST_IRQ_PRIORITY               2
#define STM32_ST_USE_TIMER                  21

/*
 * UART driver system settings.
 */
#define STM32_UART_USE_USART1               FALSE
#define STM32_UART_USE_USART2               FALSE
#define STM32_UART_USART1_IRQ_PRIORITY      3
#define STM32_UART_USART2_IRQ_PRIORITY      3
#define STM32_UART_USART1_DMA_PRIORITY      0
#define STM32_UART_USART2_DMA_PRIORITY      0
#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")

/*
 * WDG driver system settings.
 */
#define STM32_WDG_USE_IWDG                  FALSE

#endif /* _MCUCONF_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-18 16:07:49 +0000