/* ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. This file is part of ChibiOS/RT. ChibiOS/RT is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. ChibiOS/RT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see . */ #ifndef _BOARD_H_ #define _BOARD_H_ /* * Tricks required to make the TRUE/FALSE declaration inside the library * compatible. */ #undef FALSE #undef TRUE #include #define FALSE 0 #define TRUE (!FALSE) /* * Uncomment this if you want a 48MHz system clock, else it will be 72MHz. */ //#define SYSCLK_48 /* * NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16. */ #define LSECLK 32768 #define HSECLK 8000000 #define HSICLK 8000000 #define PLLPRE 1 #ifdef SYSCLK_48 #define PLLMUL 6 #else #define PLLMUL 9 #endif #define PLLCLK ((HSECLK / PLLPRE) * PLLMUL) #define SYSCLK PLLCLK #define APB1CLK (SYSCLK / 2) #define APB2CLK (SYSCLK / 2) #define AHB1CLK (SYSCLK / 1) /* * Values derived from the clock settings. */ #define PLLPREBITS ((PLLPRE - 1) << 17) #define PLLMULBITS ((PLLMUL - 2) << 18) #ifdef SYSCLK_48 #define USBPREBITS RCC_CFGR_USBPRE_DIV1_BITS #define FLASHBITS 0x00000011 #else #define USBPREBITS RCC_CFGR_USBPRE_DIV1P5_BITS #define FLASHBITS 0x00000012 #endif /* * Extra definitions for RCC_CR register (missing from the ST header file). */ #define RCC_CR_HSITRIM_RESET_BITS (0x10 << 3) /* * Extra definitions for RCC_CFGR register (missing from the ST header file). */ #define RCC_CFGR_PLLSRC_HSI_BITS (0 << 16) #define RCC_CFGR_PLLSRC_HSE_BITS (1 << 16) #define RCC_CFGR_USBPRE_DIV1P5_BITS (0 << 22) #define RCC_CFGR_USBPRE_DIV1_BITS (1 << 22) /* * IO pins assignments. */ #define GPIOA_BUTTON 0 #define GPIOA_SPI1NSS 4 #define GPIOB_SPI2NSS 12 #define GPIOC_MMCWP 6 #define GPIOC_MMCCP 7 #define GPIOC_CANCNTL 10 #define GPIOC_DISC 11 #define GPIOC_LED 12 /* * All inputs with pullups unless otherwise specified. */ #define VAL_GPIOACRL 0x88888884 // PA0:FI #define VAL_GPIOACRH 0x88888888 #define VAL_GPIOAODR 0xFFFFFFFF #define VAL_GPIOBCRL 0x88883888 // PB3:PP #define VAL_GPIOBCRH 0x88888888 #define VAL_GPIOBODR 0xFFFFFFFF #define VAL_GPIOCCRL 0x44888888 // PC6,PC7:FI #define VAL_GPIOCCRH 0x88833888 // PC11,PC12:PP #define VAL_GPIOCODR 0xFFFFFFFF #define VAL_GPIODCRL 0x88888844 // PD0,PD1:FI #define VAL_GPIODCRH 0x88888888 #define VAL_GPIODODR 0xFFFFFFFF #define VAL_GPIOECRL 0x88888888 #define VAL_GPIOECRH 0x88888888 #define VAL_GPIOEODR 0xFFFFFFFF #endif /* _BOARD_H_ */ /a> 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319