From 573b5e875bd8431963fc3a40885020f7e3310640 Mon Sep 17 00:00:00 2001 From: barthess Date: Fri, 1 Apr 2011 18:23:35 +0000 Subject: I2C. Usage example added. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@2864 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32/I2C/Makefile | 213 +++++++++++++++++++ testhal/STM32/I2C/ch.ld | 113 ++++++++++ testhal/STM32/I2C/chconf.h | 507 ++++++++++++++++++++++++++++++++++++++++++++ testhal/STM32/I2C/halconf.h | 259 ++++++++++++++++++++++ testhal/STM32/I2C/i2c_pns.c | 61 ++++++ testhal/STM32/I2C/i2c_pns.h | 8 + testhal/STM32/I2C/lis3.c | 170 +++++++++++++++ testhal/STM32/I2C/lis3.h | 28 +++ testhal/STM32/I2C/main.c | 120 +++++++++++ testhal/STM32/I2C/main.h | 19 ++ testhal/STM32/I2C/max1236.c | 106 +++++++++ testhal/STM32/I2C/max1236.h | 14 ++ testhal/STM32/I2C/mcuconf.h | 131 ++++++++++++ testhal/STM32/I2C/tmp75.c | 72 +++++++ testhal/STM32/I2C/tmp75.h | 13 ++ 15 files changed, 1834 insertions(+) create mode 100644 testhal/STM32/I2C/Makefile create mode 100644 testhal/STM32/I2C/ch.ld create mode 100644 testhal/STM32/I2C/chconf.h create mode 100644 testhal/STM32/I2C/halconf.h create mode 100644 testhal/STM32/I2C/i2c_pns.c create mode 100644 testhal/STM32/I2C/i2c_pns.h create mode 100644 testhal/STM32/I2C/lis3.c create mode 100644 testhal/STM32/I2C/lis3.h create mode 100644 testhal/STM32/I2C/main.c create mode 100644 testhal/STM32/I2C/main.h create mode 100644 testhal/STM32/I2C/max1236.c create mode 100644 testhal/STM32/I2C/max1236.h create mode 100644 testhal/STM32/I2C/mcuconf.h create mode 100644 testhal/STM32/I2C/tmp75.c create mode 100644 testhal/STM32/I2C/tmp75.h (limited to 'testhal') diff --git a/testhal/STM32/I2C/Makefile b/testhal/STM32/I2C/Makefile new file mode 100644 index 000000000..888e33eb2 --- /dev/null +++ b/testhal/STM32/I2C/Makefile @@ -0,0 +1,213 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 -Wall -Wextra + #USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 -Wall -Wextra +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# Imported source files +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c \ + i2c_pns.c \ + lis3.c\ + tmp75.c\ + max1236.c\ + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +# -lm добавлен именно здесь, потому что больше некуда +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. + +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk + + diff --git a/testhal/STM32/I2C/ch.ld b/testhal/STM32/I2C/ch.ld new file mode 100644 index 000000000..44f494121 --- /dev/null +++ b/testhal/STM32/I2C/ch.ld @@ -0,0 +1,113 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * ST32F103 memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; +__stacks_total_size__ = __main_stack_size__ + __process_stack_size__; + +MEMORY +{ + flash : org = 0x08000000, len = 128k + ram : org = 0x20000000, len = 20k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + + .text : ALIGN(16) SUBALIGN(16) + { + _text = .; + KEEP(*(vectors)) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ctors : + { + PROVIDE(_ctors_start_ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(_ctors_end_ = .); + } > flash + + .dtors : + { + PROVIDE(_dtors_start_ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(_dtors_end_ = .); + } > flash + + .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} + + __exidx_start = .; + .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash + __exidx_end = .; + + .eh_frame_hdr : {*(.eh_frame_hdr)} + + .eh_frame : ONLY_IF_RO {*(.eh_frame)} + + . = ALIGN(4); + _etext = .; + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/testhal/STM32/I2C/chconf.h b/testhal/STM32/I2C/chconf.h new file mode 100644 index 000000000..657ddf887 --- /dev/null +++ b/testhal/STM32/I2C/chconf.h @@ -0,0 +1,507 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * + * @note T he default is @p FALSE. + */ +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) +#define CH_USE_NESTED_LOCKS TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED FALSE +#endif + +/** + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS FALSE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP FALSE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC FALSE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32/I2C/halconf.h b/testhal/STM32/I2C/halconf.h new file mode 100644 index 000000000..9a7979cc9 --- /dev/null +++ b/testhal/STM32/I2C/halconf.h @@ -0,0 +1,259 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC TRUE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C TRUE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/STM32/I2C/i2c_pns.c b/testhal/STM32/I2C/i2c_pns.c new file mode 100644 index 000000000..11982d0a7 --- /dev/null +++ b/testhal/STM32/I2C/i2c_pns.c @@ -0,0 +1,61 @@ +#include "ch.h" +#include "hal.h" + +#include "i2c_pns.h" + +#include "lis3.h" +#include "tmp75.h" +#include "max1236.h" + +/* I2C1 */ +static I2CConfig i2cfg1 = { + opmodeI2C, + 100000, + stdDutyCycle, + 0, + 0, +}; + +/* I2C2 */ +static I2CConfig i2cfg2 = { + opmodeI2C, + 100000, + stdDutyCycle, + 0, + 0, +}; + + + +void I2CInit_pns(void){ + + i2cInit(); + + i2cStart(&I2CD1, &i2cfg1); + while(I2CD1.id_state != I2C_READY){ // wait ready status + chThdSleepMilliseconds(1); + } + + i2cStart(&I2CD2, &i2cfg2); + while(I2CD2.id_state != I2C_READY){ // wait ready status + chThdSleepMilliseconds(1); + } + + /* tune ports for I2C1*/ + palSetPadMode(IOPORT2, 6, PAL_MODE_STM32_ALTERNATE_OPENDRAIN); + palSetPadMode(IOPORT2, 7, PAL_MODE_STM32_ALTERNATE_OPENDRAIN); + + /* tune ports for I2C2*/ + palSetPadMode(IOPORT2, 10, PAL_MODE_STM32_ALTERNATE_OPENDRAIN); + palSetPadMode(IOPORT2, 11, PAL_MODE_STM32_ALTERNATE_OPENDRAIN); + + + /* startups. Pauses added just to be safe */ + init_max1236(); + chThdSleepMilliseconds(100); + + init_lis3(); + chThdSleepMilliseconds(100); +} + + diff --git a/testhal/STM32/I2C/i2c_pns.h b/testhal/STM32/I2C/i2c_pns.h new file mode 100644 index 000000000..4dfdf320e --- /dev/null +++ b/testhal/STM32/I2C/i2c_pns.h @@ -0,0 +1,8 @@ +#ifndef I2C_PNS_H_ +#define I2C_PNS_H_ + + +void I2CInit_pns(void); + + +#endif /* I2C_PNS_H_ */ diff --git a/testhal/STM32/I2C/lis3.c b/testhal/STM32/I2C/lis3.c new file mode 100644 index 000000000..06f6da1d0 --- /dev/null +++ b/testhal/STM32/I2C/lis3.c @@ -0,0 +1,170 @@ +/** + * This is most complex and difficult device. + * It realize "read through write" paradigm. This is not standard, but + * most of I2C devices use this paradigm. + * You must write to device reading address, send restart to bus, + * and then begin reading process. + */ + +#include + +#include "ch.h" +#include "hal.h" + +#include "lis3.h" + + +// buffers +static i2cblock_t accel_rx_data[ACCEL_RX_DEPTH]; +static i2cblock_t accel_tx_data[ACCEL_TX_DEPTH]; + +/* Error trap */ +static void i2c_lis3_error_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){ + (void)i2cscfg; + int status = 0; + status = i2cp->id_i2c->SR1; + while(TRUE); +} + +// Accelerometer lis3lv02dq config +static I2CSlaveConfig lis3 = { + NULL, + i2c_lis3_error_cb, + accel_rx_data, + ACCEL_RX_DEPTH, + 0, + 0, + accel_tx_data, + ACCEL_TX_DEPTH, + 0, + 0, + 0b0011101, + FALSE, +}; + + +/** + * This treading need for convenient realize + * "read through write" process. + */ +static WORKING_AREA(I2CAccelThreadWA, 128); +static Thread *i2c_accel_tp = NULL; +static msg_t I2CAccelThread(void *arg) { + (void)arg; + + int16_t acceleration_x = 0; + int16_t acceleration_y = 0; + int16_t acceleration_z = 0; + + I2CDriver *i2cp; + msg_t msg; + + while (TRUE) { + /* Waiting for wake up */ + chSysLock(); + i2c_accel_tp = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + msg = chThdSelf()->p_msg; /* Retrieving the message, optional.*/ + chSysUnlock(); + + /***************** Perform processing here. ***************************/ + i2cp = (I2CDriver *)msg; + + /* collect measured data */ + acceleration_x = lis3.rxbuf[0] + (lis3.rxbuf[1] << 8); + acceleration_y = lis3.rxbuf[2] + (lis3.rxbuf[3] << 8); + acceleration_z = lis3.rxbuf[4] + (lis3.rxbuf[5] << 8); + } + return 0; +} + + + +/* This callback raise up when transfer finished */ +static void i2c_lis3_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){ + + if (i2cp->id_slave_config->restart){ // is it restart flag set to TRUE + /* reset restart flag */ + i2cp->id_slave_config->restart = FALSE; + /* now send restart and read acceleration data. + * Function i2cMasterReceive() send restart implicitly. */ + i2cMasterReceive(i2cp, i2cscfg); + } + else{ + /* If jump here than requested data have been read. + * Stop communication, release bus and wake up processing thread */ + i2cMasterStop(i2cp); + i2cReleaseBus(&I2CD1); + + // wake up heavy thread for data processing + if (i2c_accel_tp != NULL) { + i2c_accel_tp->p_msg = (msg_t)i2cp; + chSchReadyI(i2c_accel_tp); + i2c_accel_tp = NULL; + } + } +} + +/** + * Init function. Here we will also start personal serving thread. + */ +int init_lis3(void){ + + /* Starting the accelerometer serving thread.*/ + i2c_accel_tp = chThdCreateStatic(I2CAccelThreadWA, + sizeof(I2CAccelThreadWA), + HIGHPRIO, + I2CAccelThread, + NULL); + + /* wait thread statup */ + while (i2c_accel_tp == NULL) + chThdSleepMilliseconds(1); + + lis3.txbufhead = 0; + lis3.rxbufhead = 0; + + + /* Write configuration data */ + lis3.txbytes = 4; + /* fill transmit buffer. See datasheet to understand what we write */ + lis3.txbuf[0] = ACCEL_CTRL_REG1 | AUTO_INCREMENT_BIT; + lis3.txbuf[1] = 0b11100111; + lis3.txbuf[2] = 0b01000001; + lis3.txbuf[3] = 0b00000000; + + /* setting callback */ + lis3.id_callback = i2c_lis3_cb; + + i2cAcquireBus(&I2CD1); + + /* sending */ + i2cMasterTransmit(&I2CD1, &lis3); + + return 0; +} + +/** + * + */ +void request_acceleration_data(void){ + + /* fill transmit buffer with address of register that we want to read */ + lis3.txbufhead = 0; + lis3.txbuf[0] = ACCEL_OUT_DATA | AUTO_INCREMENT_BIT; // register address + lis3.txbytes = 1; + + /* tune receive structures */ + lis3.rxbufhead = 0; + lis3.rxbytes = 6; + + /* Now it is most important action. We must set restart flag to TRUE. + * And in callback function we must reset it to FALSE after sending + * of register address. In TMP75 and MAX1236 this flag does not use. */ + lis3.restart = TRUE; + + /* talk to slave what we want from it */ + i2cAcquireBus(&I2CD1); + i2cMasterTransmit(&I2CD1, &lis3); +} + diff --git a/testhal/STM32/I2C/lis3.h b/testhal/STM32/I2C/lis3.h new file mode 100644 index 000000000..e50359bde --- /dev/null +++ b/testhal/STM32/I2C/lis3.h @@ -0,0 +1,28 @@ +#include +#include "ch.h" + +#ifndef LIS3_H_ +#define LIS3_H_ + + + +/* buffers depth */ +#define ACCEL_RX_DEPTH 8 +#define ACCEL_TX_DEPTH 8 + +/* autoincrement bit position. This bit needs to perform reading of + * multiple bytes at one request */ +#define AUTO_INCREMENT_BIT (1<<7) + +/* slave specific addresses */ +#define ACCEL_STATUS_REG 0x27 +#define ACCEL_CTRL_REG1 0x20 +#define ACCEL_OUT_DATA 0x28 + + + +inline int init_lis3(void); +inline void request_acceleration_data(void); + + +#endif /* LIS3_H_ */ diff --git a/testhal/STM32/I2C/main.c b/testhal/STM32/I2C/main.c new file mode 100644 index 000000000..860e179d4 --- /dev/null +++ b/testhal/STM32/I2C/main.c @@ -0,0 +1,120 @@ +/** + * Lets imagine that we have board with LIS3LV02DL accelerometer on channel #1 + * and MAX1236 ADC, TMP75 thermometer on channel #2. + * + * NOTE: I assume, that you have datasheets on all this stuff. + * + * NOTE: Also, I assume, that you know how to I2C works. + * + * In order from simplicity to complexity: + * TMP75 + * MAX1236 + * LIS3LV02DL + * + * Project splitted to separate source files for each device. + * + * Data from sensors we will be read from different thread sleeping different + * amount of time. + */ + +#include + +#include "ch.h" +#include "hal.h" + +#include "i2c_pns.h" +#include "tmp75.h" +#include "max1236.h" +#include "lis3.h" + + + +/* Temperature polling thread */ +static WORKING_AREA(PollTmp75ThreadWA, 128); +static msg_t PollTmp75Thread(void *arg) { + (void)arg; + systime_t time = chTimeNow(); + + while (TRUE) { + time += MS2ST(1000); + /* Call reading function */ + request_temperature(); + chThdSleepUntil(time); + } + return 0; +} + +/* MAX1236 polling thread */ +static WORKING_AREA(PollMax1236ThreadWA, 128); +static msg_t PollMax1236Thread(void *arg) { + (void)arg; + systime_t time = chTimeNow(); + + while (TRUE) { + time += MS2ST(20); + /* Call reading function */ + read_max1236(); + chThdSleepUntil(time); + } + return 0; +} + + +static WORKING_AREA(PollAccelThreadWA, 128); +static msg_t PollAccelThread(void *arg) { + (void)arg; + systime_t time = chTimeNow(); + + while (TRUE) { + time += MS2ST(2); + request_acceleration_data(); + chThdSleepUntil(time); + } + return 0; +} + + + + +/* + * Entry point, note, the main() function is already a thread in the system + * on entry. + */ +int main(void) { + + halInit(); + chSysInit(); + + I2CInit_pns(); + + /* Create temperature thread */ + chThdCreateStatic(PollTmp75ThreadWA, + sizeof(PollTmp75ThreadWA), + NORMALPRIO, + PollTmp75Thread, + NULL); + + + /* Create max1236 thread */ + chThdCreateStatic(PollMax1236ThreadWA, + sizeof(PollMax1236ThreadWA), + NORMALPRIO, + PollMax1236Thread, + NULL); + + + /* Create accelerometer thread */ + chThdCreateStatic(PollAccelThreadWA, + sizeof(PollAccelThreadWA), + HIGHPRIO, + PollAccelThread, + NULL); + + + /* main loop that do nothing */ + while (TRUE) { + chThdSleepMilliseconds(500); + } + + return 0; +} diff --git a/testhal/STM32/I2C/main.h b/testhal/STM32/I2C/main.h new file mode 100644 index 000000000..1435a05e5 --- /dev/null +++ b/testhal/STM32/I2C/main.h @@ -0,0 +1,19 @@ +/* + * main.h + * + * Created on: 25.03.2011 + * Author: barthess + */ + +#ifndef MAIN_H_ +#define MAIN_H_ + + +// глобальные флаги +#define GET_FILTERED_RAW_GYRO TRUE +#define GET_FILTERED_RAW_ACCEL TRUE + + + + +#endif /* MAIN_H_ */ diff --git a/testhal/STM32/I2C/max1236.c b/testhal/STM32/I2C/max1236.c new file mode 100644 index 000000000..e7e253916 --- /dev/null +++ b/testhal/STM32/I2C/max1236.c @@ -0,0 +1,106 @@ +/** + * Maxim ADC has not so suitable default settings after startup. + * So we will create init function to tune this ADC. + */ + +#include + +#include "ch.h" +#include "hal.h" + +#include "max1236.h" + +// Data buffers +static i2cblock_t max1236_rx_data[MAX1236_RX_DEPTH]; +static i2cblock_t max1236_tx_data[MAX1236_TX_DEPTH]; + +/* Error trap */ +static void i2c_max1236_error_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){ + (void)i2cscfg; + int status = 0; + status = i2cp->id_i2c->SR1; + while(TRUE); +} + + +/* This callback raise up when transfer finished */ +static void i2c_max1236_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){ + uint16_t ch1 = 0; + uint16_t ch2 = 0; + uint16_t ch3 = 0; + uint16_t ch4 = 0; + + /* send stop */ + i2cMasterStop(i2cp); + + /* unlock bus */ + i2cReleaseBus(&I2CD2); + + /* get ADC data */ + ch1 = ((i2cscfg->rxbuf[0] & 0xF) << 8) + i2cscfg->rxbuf[1]; + ch2 = ((i2cscfg->rxbuf[2] & 0xF) << 8) + i2cscfg->rxbuf[3]; + ch3 = ((i2cscfg->rxbuf[4] & 0xF) << 8) + i2cscfg->rxbuf[5]; + ch4 = ((i2cscfg->rxbuf[6] & 0xF) << 8) + i2cscfg->rxbuf[7]; +} + + +// ADC maxim MAX1236 config +static I2CSlaveConfig max1236 = { + NULL, // first set to NULL. We will set this pointer to the function later. + i2c_max1236_error_cb, + max1236_rx_data, + MAX1236_RX_DEPTH, + 0, + 0, + max1236_tx_data, + MAX1236_TX_DEPTH, + 0, + 0, + 0b0110100, + FALSE, +}; + + +/** + * Initilization routine. See datasheet on page 13 to understand + * how to initialize ADC. + */ +void init_max1236(void){ + /* lock bus */ + i2cAcquireBus(&I2CD2); + + /* this data we must send to IC to setup ADC settings */ + max1236.txbufhead = 0; + max1236.txbytes = 2; // total 2 bytes to be sent + max1236.txbuf[0] = 0b10000011; // config register content. Consult datasheet + max1236.txbuf[1] = 0b00000111; // config register content. Consult datasheet + + // transmit out 2 bytes + i2cMasterTransmit(&I2CD2, &max1236); + while(I2CD2.id_state != I2C_READY) // wait + chThdSleepMilliseconds(1); + + /* now add pointer to callback function */ + max1236.id_callback = i2c_max1236_cb; + + /*clear transmitting structures */ + max1236.txbytes = 0; + max1236.txbufhead = 0; + + /* unlock bus */ + i2cReleaseBus(&I2CD2); +} + + +/* Now simply read 8 bytes to get all 4 ADC channels */ +void read_max1236(void){ + /* tune receive buffer */ + max1236.rxbufhead = 0; + max1236.rxbytes = 8; + + /* lock bus */ + i2cAcquireBus(&I2CD2); + + /* start reading */ + i2cMasterReceive(&I2CD2, &max1236); +} diff --git a/testhal/STM32/I2C/max1236.h b/testhal/STM32/I2C/max1236.h new file mode 100644 index 000000000..aff466cf4 --- /dev/null +++ b/testhal/STM32/I2C/max1236.h @@ -0,0 +1,14 @@ +#include "ch.h" + +#ifndef MAX1236_H_ +#define MAX1236_H_ + + +#define MAX1236_RX_DEPTH 8 +#define MAX1236_TX_DEPTH 2 + + +void init_max1236(void); +void read_max1236(void); + +#endif /* MAX1236_H_ */ diff --git a/testhal/STM32/I2C/mcuconf.h b/testhal/STM32/I2C/mcuconf.h new file mode 100644 index 000000000..92f8e17d8 --- /dev/null +++ b/testhal/STM32/I2C/mcuconf.h @@ -0,0 +1,131 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_MCO STM32_MCO_NOCLOCK + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 3 +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_ERROR_HOOK() chSysHalt() + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 2 +#define STM32_SPI_SPI2_DMA_PRIORITY 2 +#define STM32_SPI_SPI3_DMA_PRIORITY 2 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_SPI_SPI2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_SPI_SPI3_DMA_ERROR_HOOK() chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 TRUE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_UART_USART2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_UART_USART3_DMA_ERROR_HOOK() chSysHalt() + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C2 TRUE +#define STM32_I2C_I2C1_IRQ_PRIORITY 11 +#define STM32_I2C_I2C2_IRQ_PRIORITY 11 +#define STM32_I2C_I2C1_DMA_PRIORITY 4 +#define STM32_I2C_I2C2_DMA_PRIORITY 4 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() diff --git a/testhal/STM32/I2C/tmp75.c b/testhal/STM32/I2C/tmp75.c new file mode 100644 index 000000000..4d9923881 --- /dev/null +++ b/testhal/STM32/I2C/tmp75.c @@ -0,0 +1,72 @@ +/** + * TMP75 is most simple I2C device in our case. It is already useful with + * default settings after powerup. + * You only must read 2 sequential bytes from it. + */ + +#include + +#include "ch.h" +#include "hal.h" + +#include "tmp75.h" + + +// input buffer +static i2cblock_t tmp75_rx_data[TMP75_RX_DEPTH]; +static i2cblock_t tmp75_tx_data[TMP75_TX_DEPTH]; + +// Simple error trap +static void i2c_tmp75_error_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){ + (void)i2cscfg; + int status = 0; + status = i2cp->id_i2c->SR1; + while(TRUE); +} + +/* This callback raise up when transfer finished */ +static void i2c_tmp75_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){ + int16_t temperature = 0; + + /* Manually send stop signal to the bus. This is important! */ + i2cMasterStop(i2cp); + /* unlock bus */ + i2cReleaseBus(&I2CD2); + + /* store temperature value */ + temperature = (i2cscfg->rxbuf[0] << 8) + i2cscfg->rxbuf[1]; + +} + +// Fill TMP75 config. +static I2CSlaveConfig tmp75 = { + i2c_tmp75_cb, + i2c_tmp75_error_cb, + tmp75_rx_data, + TMP75_RX_DEPTH, + 0, + 0, + tmp75_tx_data, + TMP75_TX_DEPTH, + 0, + 0, + 0b1001000, + FALSE, +}; + +/* This is main function. */ +void request_temperature(void){ + tmp75.txbytes = 0; // set to zero just to be safe + + /* tune receiving buffer */ + tmp75.rxbufhead = 0;// point to beginig of buffer + tmp75.rxbytes = 2; // we need read 2 bytes + + /* get exclusive access to the bus */ + i2cAcquireBus(&I2CD2); + + /* start receiving process in background and return */ + i2cMasterReceive(&I2CD2, &tmp75); +} + + diff --git a/testhal/STM32/I2C/tmp75.h b/testhal/STM32/I2C/tmp75.h new file mode 100644 index 000000000..ab4b5fa9b --- /dev/null +++ b/testhal/STM32/I2C/tmp75.h @@ -0,0 +1,13 @@ +#ifndef TMP75_H_ +#define TMP75_H_ + + + +/* buffers depth */ +#define TMP75_RX_DEPTH 2 +#define TMP75_TX_DEPTH 2 + +void init_tmp75(void); +void request_temperature(void); + +#endif /* TMP75_H_ */ -- cgit v1.2.3