From 98ef475714df436553966f278e472b8e593401c5 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Sun, 28 Feb 2016 09:03:32 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8979 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/STM32/STM32L4xx/CAN/Makefile | 8 +- testhal/STM32/STM32L4xx/CAN/chconf.h | 44 ++------- testhal/STM32/STM32L4xx/CAN/halconf.h | 2 +- testhal/STM32/STM32L4xx/CAN/main.c | 4 +- testhal/STM32/STM32L4xx/CAN/mcuconf.h | 144 ++++++++++++++++++++++++++++++ testhal/STM32/STM32L4xx/GPT-ADC/Makefile | 8 +- testhal/STM32/STM32L4xx/GPT-ADC/chconf.h | 44 ++------- testhal/STM32/STM32L4xx/GPT-ADC/main.c | 4 +- testhal/STM32/STM32L4xx/GPT-ADC/mcuconf.h | 144 ++++++++++++++++++++++++++++++ 9 files changed, 315 insertions(+), 87 deletions(-) (limited to 'testhal/STM32') diff --git a/testhal/STM32/STM32L4xx/CAN/Makefile b/testhal/STM32/STM32L4xx/CAN/Makefile index 2d650478b..6a6704a36 100644 --- a/testhal/STM32/STM32L4xx/CAN/Makefile +++ b/testhal/STM32/STM32L4xx/CAN/Makefile @@ -69,7 +69,7 @@ ifeq ($(USE_EXCEPTIONS_STACKSIZE),) USE_EXCEPTIONS_STACKSIZE = 0x400 endif -# Enables the use of FPU (no, softfp, hard). +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). ifeq ($(USE_FPU),) USE_FPU = no endif @@ -88,7 +88,7 @@ PROJECT = ch # Imported source files and paths CHIBIOS = ../../../.. # Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l4xx.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32l4xx.mk # HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk include $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/platform.mk @@ -96,7 +96,7 @@ include $(CHIBIOS)/os/hal/boards/ST_NUCLEO_L476RG/board.mk include $(CHIBIOS)/os/hal/osal/rt/osal.mk # RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk # Other files (optional). include $(CHIBIOS)/test/rt/test.mk @@ -212,5 +212,5 @@ ULIBS = # End of user defines ############################################################################## -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC +RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC include $(RULESPATH)/rules.mk diff --git a/testhal/STM32/STM32L4xx/CAN/chconf.h b/testhal/STM32/STM32L4xx/CAN/chconf.h index edd657ac1..405149b3b 100644 --- a/testhal/STM32/STM32L4xx/CAN/chconf.h +++ b/testhal/STM32/STM32L4xx/CAN/chconf.h @@ -28,8 +28,6 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ -#define _CHIBIOS_RT_CONF_ - /*===========================================================================*/ /** * @name System timers settings @@ -327,7 +325,7 @@ * * @note The default is @p FALSE. */ -#define CH_DBG_STATISTICS FALSE +#define CH_DBG_STATISTICS TRUE /** * @brief Debug option, system state check. @@ -362,16 +360,9 @@ * @details If enabled then the context switch circular trace buffer is * activated. * - * @note The default is @p CH_DBG_TRACE_MASK_NONE. - */ -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_NONE. + * @note The default is @p FALSE. */ -#define CH_DBG_TRACE_BUFFER_SIZE 128 +#define CH_DBG_ENABLE_TRACE TRUE /** * @brief Debug option, stack checks. @@ -436,6 +427,10 @@ /** * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #define CH_CFG_THREAD_EXIT_HOOK(tp) { \ /* Add threads finalization code here.*/ \ @@ -449,20 +444,6 @@ /* Context switch code here.*/ \ } -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - /** * @brief Idle thread enter hook. * @note This hook is invoked within a critical zone, no OS functions @@ -470,7 +451,6 @@ * @note This macro can be used to activate a power saving mode. */ #define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ } /** @@ -480,7 +460,6 @@ * @note This macro can be used to deactivate a power saving mode. */ #define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ } /** @@ -509,15 +488,6 @@ /* System halt code here.*/ \ } -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - /** @} */ /*===========================================================================*/ diff --git a/testhal/STM32/STM32L4xx/CAN/halconf.h b/testhal/STM32/STM32L4xx/CAN/halconf.h index d9cfc331f..2f2b659e8 100644 --- a/testhal/STM32/STM32L4xx/CAN/halconf.h +++ b/testhal/STM32/STM32L4xx/CAN/halconf.h @@ -62,7 +62,7 @@ * @brief Enables the EXT subsystem. */ #if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) -#define HAL_USE_EXT TRUE +#define HAL_USE_EXT FALSE #endif /** diff --git a/testhal/STM32/STM32L4xx/CAN/main.c b/testhal/STM32/STM32L4xx/CAN/main.c index db197525a..92278311b 100644 --- a/testhal/STM32/STM32L4xx/CAN/main.c +++ b/testhal/STM32/STM32L4xx/CAN/main.c @@ -47,7 +47,7 @@ static THD_FUNCTION(can_rx, p) { (void)p; chRegSetThreadName("receiver"); chEvtRegister(&cip->canp->rxfull_event, &el, 0); - while (true) { + while(!chThdShouldTerminateX()) { if (chEvtWaitAnyTimeout(ALL_EVENTS, MS2ST(100)) == 0) continue; while (canReceive(cip->canp, CAN_ANY_MAILBOX, @@ -75,7 +75,7 @@ static THD_FUNCTION(can_tx, p) { txmsg.data32[0] = 0x55AA55AA; txmsg.data32[1] = 0x00FF00FF; - while (true) { + while (!chThdShouldTerminateX()) { canTransmit(&CAND1, CAN_ANY_MAILBOX, &txmsg, MS2ST(100)); chThdSleepMilliseconds(500); } diff --git a/testhal/STM32/STM32L4xx/CAN/mcuconf.h b/testhal/STM32/STM32L4xx/CAN/mcuconf.h index c55f31771..08ea64d70 100644 --- a/testhal/STM32/STM32L4xx/CAN/mcuconf.h +++ b/testhal/STM32/STM32L4xx/CAN/mcuconf.h @@ -118,6 +118,36 @@ #define STM32_CAN_USE_CAN1 TRUE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITYv 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2122_IRQ_PRIORITY 15 + + /* * GPT driver system settings. */ @@ -129,6 +159,9 @@ #define STM32_GPT_USE_TIM6 FALSE #define STM32_GPT_USE_TIM7 FALSE #define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM15 FALSE +#define STM32_GPT_USE_TIM16 FALSE +#define STM32_GPT_USE_TIM17 FALSE #define STM32_GPT_TIM1_IRQ_PRIORITY 7 #define STM32_GPT_TIM2_IRQ_PRIORITY 7 #define STM32_GPT_TIM3_IRQ_PRIORITY 7 @@ -137,6 +170,63 @@ #define STM32_GPT_TIM6_IRQ_PRIORITY 7 #define STM32_GPT_TIM7_IRQ_PRIORITY 7 #define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM15_IRQ_PRIORITY 7 +#define STM32_GPT_TIM16_IRQ_PRIORITY 7 +#define STM32_GPT_TIM17_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 /* * SDC driver system settings. @@ -162,12 +252,66 @@ #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_LPUART1_PRIORITY 12 +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + /* * ST driver system settings. */ #define STM32_ST_IRQ_PRIORITY 8 #define STM32_ST_USE_TIMER 2 +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_LPUART1 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_UART_LPUART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_LPUART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_LPUART1_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + /* * USB driver system settings. */ diff --git a/testhal/STM32/STM32L4xx/GPT-ADC/Makefile b/testhal/STM32/STM32L4xx/GPT-ADC/Makefile index 2d650478b..6a6704a36 100644 --- a/testhal/STM32/STM32L4xx/GPT-ADC/Makefile +++ b/testhal/STM32/STM32L4xx/GPT-ADC/Makefile @@ -69,7 +69,7 @@ ifeq ($(USE_EXCEPTIONS_STACKSIZE),) USE_EXCEPTIONS_STACKSIZE = 0x400 endif -# Enables the use of FPU (no, softfp, hard). +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). ifeq ($(USE_FPU),) USE_FPU = no endif @@ -88,7 +88,7 @@ PROJECT = ch # Imported source files and paths CHIBIOS = ../../../.. # Startup files. -include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l4xx.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32l4xx.mk # HAL-OSAL files (optional). include $(CHIBIOS)/os/hal/hal.mk include $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/platform.mk @@ -96,7 +96,7 @@ include $(CHIBIOS)/os/hal/boards/ST_NUCLEO_L476RG/board.mk include $(CHIBIOS)/os/hal/osal/rt/osal.mk # RTOS files (optional). include $(CHIBIOS)/os/rt/rt.mk -include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk # Other files (optional). include $(CHIBIOS)/test/rt/test.mk @@ -212,5 +212,5 @@ ULIBS = # End of user defines ############################################################################## -RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC +RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC include $(RULESPATH)/rules.mk diff --git a/testhal/STM32/STM32L4xx/GPT-ADC/chconf.h b/testhal/STM32/STM32L4xx/GPT-ADC/chconf.h index edd657ac1..405149b3b 100644 --- a/testhal/STM32/STM32L4xx/GPT-ADC/chconf.h +++ b/testhal/STM32/STM32L4xx/GPT-ADC/chconf.h @@ -28,8 +28,6 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ -#define _CHIBIOS_RT_CONF_ - /*===========================================================================*/ /** * @name System timers settings @@ -327,7 +325,7 @@ * * @note The default is @p FALSE. */ -#define CH_DBG_STATISTICS FALSE +#define CH_DBG_STATISTICS TRUE /** * @brief Debug option, system state check. @@ -362,16 +360,9 @@ * @details If enabled then the context switch circular trace buffer is * activated. * - * @note The default is @p CH_DBG_TRACE_MASK_NONE. - */ -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_NONE. + * @note The default is @p FALSE. */ -#define CH_DBG_TRACE_BUFFER_SIZE 128 +#define CH_DBG_ENABLE_TRACE TRUE /** * @brief Debug option, stack checks. @@ -436,6 +427,10 @@ /** * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #define CH_CFG_THREAD_EXIT_HOOK(tp) { \ /* Add threads finalization code here.*/ \ @@ -449,20 +444,6 @@ /* Context switch code here.*/ \ } -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - /** * @brief Idle thread enter hook. * @note This hook is invoked within a critical zone, no OS functions @@ -470,7 +451,6 @@ * @note This macro can be used to activate a power saving mode. */ #define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ } /** @@ -480,7 +460,6 @@ * @note This macro can be used to deactivate a power saving mode. */ #define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ } /** @@ -509,15 +488,6 @@ /* System halt code here.*/ \ } -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - /** @} */ /*===========================================================================*/ diff --git a/testhal/STM32/STM32L4xx/GPT-ADC/main.c b/testhal/STM32/STM32L4xx/GPT-ADC/main.c index 93d4bcff6..790fc50f5 100644 --- a/testhal/STM32/STM32L4xx/GPT-ADC/main.c +++ b/testhal/STM32/STM32L4xx/GPT-ADC/main.c @@ -81,10 +81,10 @@ static const ADCConversionGroup adcgrpcfg1 = { ADC_TR(0, 4095), /* TR1 */ { /* SMPR[2] */ ADC_SMPR1_SMP_AN0(ADC_SMPR_SMP_247P5), - ADC_SMPR2_SMP_AN11(ADC_SMPR_SMP_247P5) + ADC_SMPR1_SMP_AN2(ADC_SMPR_SMP_247P5) }, { /* SQR[4] */ - ADC_SQR1_SQ1_N(ADC_CHANNEL_IN0) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN11), + ADC_SQR1_SQ1_N(ADC_CHANNEL_IN0) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN2), 0, 0, 0 diff --git a/testhal/STM32/STM32L4xx/GPT-ADC/mcuconf.h b/testhal/STM32/STM32L4xx/GPT-ADC/mcuconf.h index 6278027e7..106034d7f 100644 --- a/testhal/STM32/STM32L4xx/GPT-ADC/mcuconf.h +++ b/testhal/STM32/STM32L4xx/GPT-ADC/mcuconf.h @@ -118,6 +118,36 @@ #define STM32_CAN_USE_CAN1 FALSE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITYv 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2122_IRQ_PRIORITY 15 + + /* * GPT driver system settings. */ @@ -129,6 +159,9 @@ #define STM32_GPT_USE_TIM6 FALSE #define STM32_GPT_USE_TIM7 FALSE #define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM15 FALSE +#define STM32_GPT_USE_TIM16 FALSE +#define STM32_GPT_USE_TIM17 FALSE #define STM32_GPT_TIM1_IRQ_PRIORITY 7 #define STM32_GPT_TIM2_IRQ_PRIORITY 7 #define STM32_GPT_TIM3_IRQ_PRIORITY 7 @@ -137,6 +170,63 @@ #define STM32_GPT_TIM6_IRQ_PRIORITY 7 #define STM32_GPT_TIM7_IRQ_PRIORITY 7 #define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM15_IRQ_PRIORITY 7 +#define STM32_GPT_TIM16_IRQ_PRIORITY 7 +#define STM32_GPT_TIM17_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 /* * SDC driver system settings. @@ -162,12 +252,66 @@ #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_LPUART1_PRIORITY 12 +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + /* * ST driver system settings. */ #define STM32_ST_IRQ_PRIORITY 8 #define STM32_ST_USE_TIMER 2 +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_LPUART1 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_UART_LPUART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_LPUART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_LPUART1_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + /* * USB driver system settings. */ -- cgit v1.2.3