From 1d6fc52f437be05281f46ceb25d084a786a4d9a2 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Thu, 7 Mar 2013 11:03:10 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5374
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/ADC/Makefile   | 163 ++++++++++++
 testhal/SPC563Mxx/ADC/chconf.h   | 535 +++++++++++++++++++++++++++++++++++++++
 testhal/SPC563Mxx/ADC/halconf.h  | 316 +++++++++++++++++++++++
 testhal/SPC563Mxx/ADC/main.c     | 146 +++++++++++
 testhal/SPC563Mxx/ADC/mcuconf.h  |  62 +++++
 testhal/SPC563Mxx/ADC/readme.txt |  25 ++
 6 files changed, 1247 insertions(+)
 create mode 100644 testhal/SPC563Mxx/ADC/Makefile
 create mode 100644 testhal/SPC563Mxx/ADC/chconf.h
 create mode 100644 testhal/SPC563Mxx/ADC/halconf.h
 create mode 100644 testhal/SPC563Mxx/ADC/main.c
 create mode 100644 testhal/SPC563Mxx/ADC/mcuconf.h
 create mode 100644 testhal/SPC563Mxx/ADC/readme.txt

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/ADC/Makefile b/testhal/SPC563Mxx/ADC/Makefile
new file mode 100644
index 000000000..4a009578f
--- /dev/null
+++ b/testhal/SPC563Mxx/ADC/Makefile
@@ -0,0 +1,163 @@
+##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+  USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+  USE_COPT = 
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+  USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data.
+ifeq ($(USE_LINK_GC),)
+  USE_LINK_GC = yes
+endif
+
+# If enabled, this option allows to compile the application in VLE mode.
+ifeq ($(USE_VLE),)
+  USE_VLE = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+  USE_VERBOSE_COMPILE = no
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files
+CHIBIOS = ../../..
+include $(CHIBIOS)/boards/GENERIC_SPC563M/board.mk
+include $(CHIBIOS)/os/hal/platforms/SPC563Mxx/platform.mk
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS)/os/ports/GCC/PPC/SPC563Mxx/port.mk
+include $(CHIBIOS)/os/kernel/kernel.mk
+#include $(CHIBIOS)/test/test.mk
+
+# Define linker script file here
+LDSCRIPT= $(PORTLD)/SPC563M64.ld
+
+# C sources here.
+CSRC = $(PORTSRC) \
+       $(KERNSRC) \
+       $(TESTSRC) \
+       $(HALSRC) \
+       $(PLATFORMSRC) \
+       $(BOARDSRC) \
+       $(CHIBIOS)/os/various/evtimer.c \
+       $(CHIBIOS)/os/various/shell.c \
+       $(CHIBIOS)/os/various/chprintf.c \
+       main.c
+
+# C++ sources here.
+CPPSRC =
+
+# List ASM source files here
+ASMSRC = $(PORTASM)
+
+INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
+         $(HALINC) $(PLATFORMINC) $(BOARDINC) \
+         $(CHIBIOS)/os/various
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+#MCU  = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames
+MCU  = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames
+
+#TRGT = powerpc-eabi-
+TRGT = ppc-vle-
+CC   = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+#       runtime support makes code size explode.
+LD   = $(TRGT)gcc
+#LD   = $(TRGT)g++
+CP   = $(TRGT)objcopy
+AS   = $(TRGT)gcc -x assembler-with-cpp
+OD   = $(TRGT)objdump
+HEX  = $(CP) -O ihex
+BIN  = $(CP) -O binary
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of default section
+#
+
+# List all default C defines here, like -D_DEBUG=1
+DDEFS =
+
+# List all default ASM defines here, like -D_DEBUG=1
+DADEFS =
+
+# List all default directories to look for include files here
+DINCDIR =
+
+# List the default directory to look for the libraries here
+DLIBDIR =
+
+# List all default libraries here
+DLIBS =
+
+#
+# End of default section
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+include $(CHIBIOS)/os/ports/GCC/PPC/rules.mk
diff --git a/testhal/SPC563Mxx/ADC/chconf.h b/testhal/SPC563Mxx/ADC/chconf.h
new file mode 100644
index 000000000..5b1e9895f
--- /dev/null
+++ b/testhal/SPC563Mxx/ADC/chconf.h
@@ -0,0 +1,535 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    templates/chconf.h
+ * @brief   Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ *          contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ *          setting also defines the system tick time unit.
+ */
+#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
+#define CH_FREQUENCY                    1000
+#endif
+
+/**
+ * @brief   Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ *          threads before preemption occurs. Setting this value to zero
+ *          disables the preemption for threads with equal priority and the
+ *          round robin becomes cooperative. Note that higher priority
+ *          threads can still preempt, the kernel is always preemptive.
+ *
+ * @note    Disabling the round robin preemption makes the kernel more compact
+ *          and generally faster.
+ */
+#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
+#define CH_TIME_QUANTUM                 20
+#endif
+
+/**
+ * @brief   Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ *          then the whole available RAM is used. The core memory is made
+ *          available to the heap allocator and/or can be used directly through
+ *          the simplified core memory allocator.
+ *
+ * @note    In order to let the OS manage the whole RAM the linker script must
+ *          provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note    Requires @p CH_USE_MEMCORE.
+ */
+#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
+#define CH_MEMCORE_SIZE                 0
+#endif
+
+/**
+ * @brief   Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ *          does not spawn the idle thread automatically. The application has
+ *          then the responsibility to do one of the following:
+ *          - Spawn a custom idle thread at priority @p IDLEPRIO.
+ *          - Change the main() thread priority to @p IDLEPRIO then enter
+ *            an endless loop. In this scenario the @p main() thread acts as
+ *            the idle thread.
+ *          .
+ * @note    Unless an idle thread is spawned the @p main() thread must not
+ *          enter a sleep state.
+ */
+#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
+#define CH_NO_IDLE_THREAD               FALSE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ *          is used when two possible implementations exist.
+ *
+ * @note    This is not related to the compiler optimization options.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
+#define CH_OPTIMIZE_SPEED               TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
+#define CH_USE_REGISTRY                 TRUE
+#endif
+
+/**
+ * @brief   Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ *          the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
+#define CH_USE_WAITEXIT                 TRUE
+#endif
+
+/**
+ * @brief   Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES               TRUE
+#endif
+
+/**
+ * @brief   Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ *          priority rather than in FIFO order.
+ *
+ * @note    The default is @p FALSE. Enable this if you have special requirements.
+ * @note    Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES_PRIORITY      FALSE
+#endif
+
+/**
+ * @brief   Atomic semaphore API.
+ * @details If enabled then the semaphores the @p chSemSignalWait() API
+ *          is included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
+#define CH_USE_SEMSW                    TRUE
+#endif
+
+/**
+ * @brief   Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
+#define CH_USE_MUTEXES                  TRUE
+#endif
+
+/**
+ * @brief   Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_MUTEXES.
+ */
+#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS                 TRUE
+#endif
+
+/**
+ * @brief   Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ *          specification are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_CONDVARS.
+ */
+#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS_TIMEOUT         TRUE
+#endif
+
+/**
+ * @brief   Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS                   TRUE
+#endif
+
+/**
+ * @brief   Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ *          are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_EVENTS.
+ */
+#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS_TIMEOUT           TRUE
+#endif
+
+/**
+ * @brief   Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES                 TRUE
+#endif
+
+/**
+ * @brief   Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ *          FIFO order.
+ *
+ * @note    The default is @p FALSE. Enable this if you have special requirements.
+ * @note    Requires @p CH_USE_MESSAGES.
+ */
+#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES_PRIORITY        FALSE
+#endif
+
+/**
+ * @brief   Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ *          included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
+#define CH_USE_MAILBOXES                TRUE
+#endif
+
+/**
+ * @brief   I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
+#define CH_USE_QUEUES                   TRUE
+#endif
+
+/**
+ * @brief   Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
+#define CH_USE_MEMCORE                  TRUE
+#endif
+
+/**
+ * @brief   Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
+ *          @p CH_USE_SEMAPHORES.
+ * @note    Mutexes are recommended.
+ */
+#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_HEAP                     TRUE
+#endif
+
+/**
+ * @brief   C-runtime allocator.
+ * @details If enabled the the heap allocator APIs just wrap the C-runtime
+ *          @p malloc() and @p free() functions.
+ *
+ * @note    The default is @p FALSE.
+ * @note    Requires @p CH_USE_HEAP.
+ * @note    The C-runtime may or may not require @p CH_USE_MEMCORE, see the
+ *          appropriate documentation.
+ */
+#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_MALLOC_HEAP              FALSE
+#endif
+
+/**
+ * @brief   Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
+#define CH_USE_MEMPOOLS                 TRUE
+#endif
+
+/**
+ * @brief   Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_WAITEXIT.
+ * @note    Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
+ */
+#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
+#define CH_USE_DYNAMIC                  TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ *          at runtime.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_SYSTEM_STATE_CHECK       TRUE
+#endif
+
+/**
+ * @brief   Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ *          parameters are activated.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_CHECKS            TRUE
+#endif
+
+/**
+ * @brief   Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ *          activated. This includes consistency checks inside the kernel,
+ *          runtime anomalies and port-defined checks.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_ASSERTS           TRUE
+#endif
+
+/**
+ * @brief   Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ *          activated.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_TRACE             TRUE
+#endif
+
+/**
+ * @brief   Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note    The default is @p FALSE.
+ * @note    The stack check is performed in a architecture/port dependent way.
+ *          It may not be implemented or some ports.
+ * @note    The default failure mode is to halt the system with the global
+ *          @p panic_msg variable set to @p NULL.
+ */
+#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_STACK_CHECK       FALSE
+#endif
+
+/**
+ * @brief   Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ *          value when a thread is created. This can be useful for the
+ *          runtime measurement of the used stack.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
+#define CH_DBG_FILL_THREADS             TRUE
+#endif
+
+/**
+ * @brief   Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p Thread structure that
+ *          counts the system ticks occurred while executing the thread.
+ *
+ * @note    The default is @p TRUE.
+ * @note    This debug option is defaulted to TRUE because it is required by
+ *          some test cases into the test suite.
+ */
+#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
+#define CH_DBG_THREADS_PROFILING        TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Threads descriptor structure extension.
+ * @details User fields added to the end of the @p Thread structure.
+ */
+#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
+#define THREAD_EXT_FIELDS                                                   \
+  /* Add threads custom fields here.*/
+#endif
+
+/**
+ * @brief   Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note    It is invoked from within @p chThdInit() and implicitly from all
+ *          the threads creation APIs.
+ */
+#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
+#define THREAD_EXT_INIT_HOOK(tp) {                                          \
+  /* Add threads initialization code here.*/                                \
+}
+#endif
+
+/**
+ * @brief   Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note    It is inserted into lock zone.
+ * @note    It is also invoked when the threads simply return in order to
+ *          terminate.
+ */
+#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
+#define THREAD_EXT_EXIT_HOOK(tp) {                                          \
+  /* Add threads finalization code here.*/                                  \
+}
+#endif
+
+/**
+ * @brief   Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
+#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) {                              \
+  /* System halt code here.*/                                               \
+}
+#endif
+
+/**
+ * @brief   Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
+#define IDLE_LOOP_HOOK() {                                                  \
+  /* Idle loop code here.*/                                                 \
+}
+#endif
+
+/**
+ * @brief   System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ *          after processing the virtual timers queue.
+ */
+#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
+#define SYSTEM_TICK_EVENT_HOOK() {                                          \
+  /* System tick event code here.*/                                         \
+}
+#endif
+
+/**
+ * @brief   System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ *          the system is halted.
+ */
+#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
+#define SYSTEM_HALT_HOOK() {                                                \
+  /* System halt code here.*/                                               \
+}
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h).    */
+/*===========================================================================*/
+
+#endif  /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/SPC563Mxx/ADC/halconf.h b/testhal/SPC563Mxx/ADC/halconf.h
new file mode 100644
index 000000000..2721174a3
--- /dev/null
+++ b/testhal/SPC563Mxx/ADC/halconf.h
@@ -0,0 +1,316 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    templates/halconf.h
+ * @brief   HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ *          various device drivers from your application. You may also use
+ *          this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief   Enables the TM subsystem.
+ */
+#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
+#define HAL_USE_TM                  FALSE
+#endif
+
+/**
+ * @brief   Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL                 TRUE
+#endif
+
+/**
+ * @brief   Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC                 TRUE
+#endif
+
+/**
+ * @brief   Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN                 FALSE
+#endif
+
+/**
+ * @brief   Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT                 FALSE
+#endif
+
+/**
+ * @brief   Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT                 FALSE
+#endif
+
+/**
+ * @brief   Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C                 FALSE
+#endif
+
+/**
+ * @brief   Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU                 FALSE
+#endif
+
+/**
+ * @brief   Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI             FALSE
+#endif
+
+/**
+ * @brief   Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM                 FALSE
+#endif
+
+/**
+ * @brief   Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL              FALSE
+#endif
+
+/**
+ * @brief   Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB          FALSE
+#endif
+
+/**
+ * @brief   Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI                 FALSE
+#endif
+
+/**
+ * @brief   Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART                FALSE
+#endif
+
+/**
+ * @brief   Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB                 FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables synchronous APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT                TRUE
+#endif
+
+/**
+ * @brief   Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION    TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE          TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION    TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY           FALSE
+#endif
+
+/**
+ * @brief   Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS              TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings.                                          */
+/*===========================================================================*/
+
+/**
+ * @brief   Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ *          routines releasing some extra CPU time for the threads with
+ *          lower priority, this may slow down the driver a bit however.
+ *          This option is recommended also if the SPI driver does not
+ *          use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING            TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Number of initialization attempts before rejecting the card.
+ * @note    Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY              100
+#endif
+
+/**
+ * @brief   Include support for MMC cards.
+ * @note    MMC support is not yet implemented so this option must be kept
+ *          at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT             FALSE
+#endif
+
+/**
+ * @brief   Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ *          routines releasing some extra CPU time for the threads with
+ *          lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING            TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings.                                           */
+/*===========================================================================*/
+
+/**
+ * @brief   Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ *          default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE      38400
+#endif
+
+/**
+ * @brief   Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ *          buffers depending on the requirements of your application.
+ * @note    The default is 64 bytes for both the transmission and receive
+ *          buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE         16
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables synchronous APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT                TRUE
+#endif
+
+/**
+ * @brief   Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION    TRUE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/SPC563Mxx/ADC/main.c b/testhal/SPC563Mxx/ADC/main.c
new file mode 100644
index 000000000..846eb8f07
--- /dev/null
+++ b/testhal/SPC563Mxx/ADC/main.c
@@ -0,0 +1,146 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+#define ADC_GRP1_NUM_CHANNELS   2
+#define ADC_GRP1_BUF_DEPTH      8
+
+#define ADC_GRP2_NUM_CHANNELS   8
+#define ADC_GRP2_BUF_DEPTH      16
+
+static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH];
+static adcsample_t samples2[ADC_GRP2_NUM_CHANNELS * ADC_GRP2_BUF_DEPTH];
+
+/*
+ * ADC streaming callback.
+ */
+size_t nx = 0, ny = 0;
+static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) {
+
+  (void)adcp;
+  if (samples2 == buffer) {
+    nx += n;
+  }
+  else {
+    ny += n;
+  }
+}
+
+static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) {
+
+  (void)adcp;
+  (void)err;
+}
+
+/*
+ * ADC conversion group.
+ * Mode:        Linear buffer, 8 samples of 2 channels, SW triggered.
+ * Channels:    IN7, IN8.
+ */
+static const ADCConversionGroup adcgrpcfg1 = {
+  FALSE,
+  ADC_GRP1_NUM_CHANNELS,
+  NULL,
+  adcerrorcallback
+};
+
+/*
+ * ADC conversion group.
+ * Mode:        Continuous, 16 samples of 8 channels, SW triggered.
+ * Channels:    IN7, IN8, IN7, IN8, IN7, IN8, Sensor, VBat/2.
+ */
+static const ADCConversionGroup adcgrpcfg2 = {
+  TRUE,
+  ADC_GRP2_NUM_CHANNELS,
+  adccallback,
+  adcerrorcallback,
+};
+
+/*
+ * Red LEDs blinker thread, times are in milliseconds.
+ */
+static WORKING_AREA(waThread1, 128);
+static msg_t Thread1(void *arg) {
+
+  (void)arg;
+  chRegSetThreadName("blinker");
+  while (TRUE) {
+    palSetPad(PORT11, P11_LED1);
+    chThdSleepMilliseconds(500);
+    palClearPad(PORT11, P11_LED1);
+    chThdSleepMilliseconds(500);
+  }
+  return 0;
+}
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+  /*
+   * System initializations.
+   * - HAL initialization, this also initializes the configured device drivers
+   *   and performs the board-specific initializations.
+   * - Kernel initialization, the main() function becomes a thread and the
+   *   RTOS is active.
+   */
+  halInit();
+  chSysInit();
+
+  /*
+   * Setting up analog inputs used by the demo.
+   */
+/*  palSetGroupMode(GPIOC, PAL_PORT_BIT(1) | PAL_PORT_BIT(2),
+                  0, PAL_MODE_INPUT_ANALOG);*/
+
+  /*
+   * Creates the blinker thread.
+   */
+  chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
+
+  /*
+   * Activates the ADC1 driver and the temperature sensor.
+   */
+  adcStart(&ADCD1, NULL);
+
+  /*
+   * Linear conversion.
+   */
+  adcConvert(&ADCD1, &adcgrpcfg1, samples1, ADC_GRP1_BUF_DEPTH);
+  chThdSleepMilliseconds(1000);
+
+  /*
+   * Starts an ADC continuous conversion.
+   */
+  adcStartConversion(&ADCD1, &adcgrpcfg2, samples2, ADC_GRP2_BUF_DEPTH);
+
+  /*
+   * Normal main() thread activity, in this demo it does nothing.
+   */
+  while (TRUE) {
+    if (palReadPad(PORT11, P11_BUTTON1)) {
+      adcStopConversion(&ADCD1);
+    }
+    chThdSleepMilliseconds(500);
+  }
+}
diff --git a/testhal/SPC563Mxx/ADC/mcuconf.h b/testhal/SPC563Mxx/ADC/mcuconf.h
new file mode 100644
index 000000000..bca85fb65
--- /dev/null
+++ b/testhal/SPC563Mxx/ADC/mcuconf.h
@@ -0,0 +1,62 @@
+/*
+ * Licensed under ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ *        http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software 
+ * distributed under the License is distributed on an "AS IS" BASIS, 
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * SPC563Mxx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 1...15       Lowest...Highest.
+ */
+
+#define SPC563Mxx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define SPC5_NO_INIT                        FALSE
+#define SPC5_CLK_BYPASS                     FALSE
+#define SPC5_ALLOW_OVERCLOCK                FALSE
+#define SPC5_CLK_PREDIV_VALUE               2
+#define SPC5_CLK_MFD_VALUE                  80
+#define SPC5_CLK_RFD                        SPC5_RFD_DIV4
+#define SPC5_FLASH_BIUCR                    (BIUCR_BANK1_TOO |              \
+                                             BIUCR_MASTER4_PREFETCH |       \
+                                             BIUCR_MASTER0_PREFETCH |       \
+                                             BIUCR_DPFEN |                  \
+                                             BIUCR_IPFEN |                  \
+                                             BIUCR_PFLIM_ON_MISS |          \
+                                             BIUCR_BFEN)
+
+/*
+ * ADC driver settings.
+ */
+#define SPC5_ADC_USE_ADC0_Q0                TRUE
+#define SPC5_ADC_USE_ADC0_Q1                TRUE
+#define SPC5_ADC_USE_ADC0_Q2                TRUE
+#define SPC5_ADC_USE_ADC1_Q3                TRUE
+#define SPC5_ADC_USE_ADC1_Q4                TRUE
+#define SPC5_ADC_USE_ADC1_Q5                TRUE
+#define SPC5_ADC_CR_CLK_PS                  ADC_CR_CLK_PS(5)
+
+/*
+ * SERIAL driver system settings.
+ */
+#define SPC5_USE_ESCIA                      TRUE
+#define SPC5_USE_ESCIB                      TRUE
+#define SPC5_ESCIA_PRIORITY                 8
+#define SPC5_ESCIB_PRIORITY                 8
diff --git a/testhal/SPC563Mxx/ADC/readme.txt b/testhal/SPC563Mxx/ADC/readme.txt
new file mode 100644
index 000000000..c03dd687c
--- /dev/null
+++ b/testhal/SPC563Mxx/ADC/readme.txt
@@ -0,0 +1,25 @@
+*****************************************************************************
+** ChibiOS/RT HAL - ADC driver demo for SPC563Mxx.                         **
+*****************************************************************************
+
+The demo runs on an STMicroelectronics SPC563Mxx microcontroller installed on 
+XPC56xx EVB Motherboard.
+
+** The Demo **
+
+The application demonstrates the use of the SPC560Pxx ADC driver.
+
+** Board Setup **
+
+None.
+
+** Build Procedure **
+
+The demo has been tested using HighTec compiler.
+
+** Notes **
+
+Some files used by the demo are not part of ChibiOS/RT but are copyright of
+ST Microelectronics and are licensed under a different license.
+
+                             http://www.st.com
-- 
cgit v1.2.3


From d2e3d96b8d5305c9e74a762b22abe403dd726ec2 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Thu, 7 Mar 2013 13:33:42 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5375
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/ADC/main.c | 206 ++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 192 insertions(+), 14 deletions(-)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/ADC/main.c b/testhal/SPC563Mxx/ADC/main.c
index 846eb8f07..33389cba4 100644
--- a/testhal/SPC563Mxx/ADC/main.c
+++ b/testhal/SPC563Mxx/ADC/main.c
@@ -21,19 +21,21 @@
 #include "ch.h"
 #include "hal.h"
 
-#define ADC_GRP1_NUM_CHANNELS   2
+#define ADC_GRP1_NUM_CHANNELS   5
 #define ADC_GRP1_BUF_DEPTH      8
 
-#define ADC_GRP2_NUM_CHANNELS   8
-#define ADC_GRP2_BUF_DEPTH      16
+//#define ADC_GRP2_NUM_CHANNELS   8
+//#define ADC_GRP2_BUF_DEPTH      16
+
+static ADCConfig adccfg1 = {0, 0};
 
 static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH];
-static adcsample_t samples2[ADC_GRP2_NUM_CHANNELS * ADC_GRP2_BUF_DEPTH];
+//static adcsample_t samples2[ADC_GRP2_NUM_CHANNELS * ADC_GRP2_BUF_DEPTH];
 
 /*
  * ADC streaming callback.
  */
-size_t nx = 0, ny = 0;
+/*size_t nx = 0, ny = 0;
 static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) {
 
   (void)adcp;
@@ -43,24 +45,200 @@ static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) {
   else {
     ny += n;
   }
-}
+}*/
 
 static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) {
 
   (void)adcp;
   (void)err;
+
+  palSetPad(PORT11, P11_LED4);
+  chSysHalt();
 }
 
 /*
  * ADC conversion group.
- * Mode:        Linear buffer, 8 samples of 2 channels, SW triggered.
- * Channels:    IN7, IN8.
+ * Mode:        Linear buffer, 8 samples of 5 channels, SW triggered.
+ * Channels:    ADC_CHN_VRL, ADC_CHN_VREF25, ADC_CHN_VREF50,
+ *              ADC_CHN_VREF75, ADC_CHN_VRH.
+ *
+ * NOTE: The configuration of a sequence is very complex in this ADC
+ * implementation. Configurations are meant to be generated by the
+ * SPC5 Studio visual configuration tool and not be written manually.
+ * Writing complex sequences manually requires ad deep knowledge of both
+ * the EQADC peripheral and the driver implementation.
  */
+static const adccommand_t adcgrpcfg1_commands[ADC_GRP1_NUM_CHANNELS *
+                                              ADC_GRP1_BUF_DEPTH] = {
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH)
+};
+
 static const ADCConversionGroup adcgrpcfg1 = {
   FALSE,
   ADC_GRP1_NUM_CHANNELS,
   NULL,
-  adcerrorcallback
+  adcerrorcallback,
+  EQADC_CFCR_SSE | EQADC_CFCR_MODE_SWSS,
+  ADC_GRP1_BUF_DEPTH,
+  adcgrpcfg1_commands
 };
 
 /*
@@ -68,12 +246,12 @@ static const ADCConversionGroup adcgrpcfg1 = {
  * Mode:        Continuous, 16 samples of 8 channels, SW triggered.
  * Channels:    IN7, IN8, IN7, IN8, IN7, IN8, Sensor, VBat/2.
  */
-static const ADCConversionGroup adcgrpcfg2 = {
+/*static const ADCConversionGroup adcgrpcfg2 = {
   TRUE,
   ADC_GRP2_NUM_CHANNELS,
   adccallback,
   adcerrorcallback,
-};
+};*/
 
 /*
  * Red LEDs blinker thread, times are in milliseconds.
@@ -121,7 +299,7 @@ int main(void) {
   /*
    * Activates the ADC1 driver and the temperature sensor.
    */
-  adcStart(&ADCD1, NULL);
+  adcStart(&ADCD1, &adccfg1);
 
   /*
    * Linear conversion.
@@ -132,14 +310,14 @@ int main(void) {
   /*
    * Starts an ADC continuous conversion.
    */
-  adcStartConversion(&ADCD1, &adcgrpcfg2, samples2, ADC_GRP2_BUF_DEPTH);
+//  adcStartConversion(&ADCD1, &adcgrpcfg2, samples2, ADC_GRP2_BUF_DEPTH);
 
   /*
    * Normal main() thread activity, in this demo it does nothing.
    */
   while (TRUE) {
     if (palReadPad(PORT11, P11_BUTTON1)) {
-      adcStopConversion(&ADCD1);
+//      adcStopConversion(&ADCD1);
     }
     chThdSleepMilliseconds(500);
   }
-- 
cgit v1.2.3


From 9528cd80ca233259f91a651ca1d7da9cac5d0bb1 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Fri, 8 Mar 2013 10:42:49 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5381
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/ADC/.cproject | 52 +++++++++++++++++++++++++++++++++++++++++
 testhal/SPC563Mxx/ADC/.project  | 38 ++++++++++++++++++++++++++++++
 testhal/SPC563Mxx/ADC/Makefile  |  2 +-
 testhal/SPC563Mxx/ADC/main.c    |  3 ++-
 4 files changed, 93 insertions(+), 2 deletions(-)
 create mode 100644 testhal/SPC563Mxx/ADC/.cproject
 create mode 100644 testhal/SPC563Mxx/ADC/.project

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/ADC/.cproject b/testhal/SPC563Mxx/ADC/.cproject
new file mode 100644
index 000000000..e53532a36
--- /dev/null
+++ b/testhal/SPC563Mxx/ADC/.cproject
@@ -0,0 +1,52 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="0.1678860195">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="0.1678860195" moduleId="org.eclipse.cdt.core.settings" name="Default">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.VCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactName="${ProjName}" buildProperties="" description="" id="0.1678860195" name="Default" parent="org.eclipse.cdt.build.core.prefbase.cfg">
+					<folderInfo id="0.1678860195." name="/" resourcePath="">
+						<toolChain id="org.eclipse.cdt.build.core.prefbase.toolchain.1571587928" name="No ToolChain" resourceTypeBasedDiscovery="false" superClass="org.eclipse.cdt.build.core.prefbase.toolchain">
+							<targetPlatform id="org.eclipse.cdt.build.core.prefbase.toolchain.1571587928.1795056389" name=""/>
+							<builder autoBuildTarget="all" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="org.eclipse.cdt.build.core.settings.default.builder.1130620788" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.settings.default.builder"/>
+							<tool id="org.eclipse.cdt.build.core.settings.holder.libs.437964627" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/>
+							<tool id="org.eclipse.cdt.build.core.settings.holder.1681283326" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder">
+								<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.760214315" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+							</tool>
+							<tool id="org.eclipse.cdt.build.core.settings.holder.1674700670" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder">
+								<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.916577449" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+							</tool>
+							<tool id="org.eclipse.cdt.build.core.settings.holder.450240264" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder">
+								<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1298250760" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="SPC563Mxx-ADC.null.2088541646" name="SPC563Mxx-ADC"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="0.1678860195">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="refreshScope"/>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+</cproject>
diff --git a/testhal/SPC563Mxx/ADC/.project b/testhal/SPC563Mxx/ADC/.project
new file mode 100644
index 000000000..c315293cf
--- /dev/null
+++ b/testhal/SPC563Mxx/ADC/.project
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>SPC563Mxx-ADC</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>board</name>
+			<type>2</type>
+			<locationURI>CHIBIOS/boards/GENERIC_SPC563M</locationURI>
+		</link>
+		<link>
+			<name>os</name>
+			<type>2</type>
+			<locationURI>CHIBIOS/os</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/testhal/SPC563Mxx/ADC/Makefile b/testhal/SPC563Mxx/ADC/Makefile
index 4a009578f..39c0bca1a 100644
--- a/testhal/SPC563Mxx/ADC/Makefile
+++ b/testhal/SPC563Mxx/ADC/Makefile
@@ -5,7 +5,7 @@
 
 # Compiler options here.
 ifeq ($(USE_OPT),)
-  USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
+  USE_OPT = -O1 -ggdb -fomit-frame-pointer -falign-functions=16
 endif
 
 # C specific options here (added to USE_OPT).
diff --git a/testhal/SPC563Mxx/ADC/main.c b/testhal/SPC563Mxx/ADC/main.c
index 33389cba4..e7e7f8fb3 100644
--- a/testhal/SPC563Mxx/ADC/main.c
+++ b/testhal/SPC563Mxx/ADC/main.c
@@ -236,7 +236,8 @@ static const ADCConversionGroup adcgrpcfg1 = {
   ADC_GRP1_NUM_CHANNELS,
   NULL,
   adcerrorcallback,
-  EQADC_CFCR_SSE | EQADC_CFCR_MODE_SWSS,
+//  EQADC_CFCR_SSE | EQADC_CFCR_MODE_SWSS,
+  EQADC_CFCR_MODE_SWCS,
   ADC_GRP1_BUF_DEPTH,
   adcgrpcfg1_commands
 };
-- 
cgit v1.2.3


From 91e1037e97ff83bbab953c24fc51f14d6e29a02a Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Fri, 8 Mar 2013 11:11:23 +0000
Subject: EQADC driver starts responding.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5382 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 testhal/SPC563Mxx/ADC/.cproject | 6 +++++-
 testhal/SPC563Mxx/ADC/Makefile  | 2 +-
 testhal/SPC563Mxx/ADC/main.c    | 8 +++-----
 3 files changed, 9 insertions(+), 7 deletions(-)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/ADC/.cproject b/testhal/SPC563Mxx/ADC/.cproject
index e53532a36..57b44e9a8 100644
--- a/testhal/SPC563Mxx/ADC/.cproject
+++ b/testhal/SPC563Mxx/ADC/.cproject
@@ -47,6 +47,10 @@
 			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/>
 		</scannerConfigBuildInfo>
 	</storageModule>
-	<storageModule moduleId="refreshScope"/>
+	<storageModule moduleId="refreshScope" versionNumber="2">
+		<configuration configurationName="Default">
+			<resource resourceType="PROJECT" workspacePath="/SPC563Mxx-ADC"/>
+		</configuration>
+	</storageModule>
 	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
 </cproject>
diff --git a/testhal/SPC563Mxx/ADC/Makefile b/testhal/SPC563Mxx/ADC/Makefile
index 39c0bca1a..4a009578f 100644
--- a/testhal/SPC563Mxx/ADC/Makefile
+++ b/testhal/SPC563Mxx/ADC/Makefile
@@ -5,7 +5,7 @@
 
 # Compiler options here.
 ifeq ($(USE_OPT),)
-  USE_OPT = -O1 -ggdb -fomit-frame-pointer -falign-functions=16
+  USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
 endif
 
 # C specific options here (added to USE_OPT).
diff --git a/testhal/SPC563Mxx/ADC/main.c b/testhal/SPC563Mxx/ADC/main.c
index e7e7f8fb3..076d506d7 100644
--- a/testhal/SPC563Mxx/ADC/main.c
+++ b/testhal/SPC563Mxx/ADC/main.c
@@ -27,8 +27,6 @@
 //#define ADC_GRP2_NUM_CHANNELS   8
 //#define ADC_GRP2_BUF_DEPTH      16
 
-static ADCConfig adccfg1 = {0, 0};
-
 static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH];
 //static adcsample_t samples2[ADC_GRP2_NUM_CHANNELS * ADC_GRP2_BUF_DEPTH];
 
@@ -236,8 +234,8 @@ static const ADCConversionGroup adcgrpcfg1 = {
   ADC_GRP1_NUM_CHANNELS,
   NULL,
   adcerrorcallback,
-//  EQADC_CFCR_SSE | EQADC_CFCR_MODE_SWSS,
   EQADC_CFCR_MODE_SWCS,
+  0, 0,                     /* ISEL, EISEL.*/
   ADC_GRP1_BUF_DEPTH,
   adcgrpcfg1_commands
 };
@@ -298,9 +296,9 @@ int main(void) {
   chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
 
   /*
-   * Activates the ADC1 driver and the temperature sensor.
+   * Activates the ADC1 driver (unit zero queue zero).
    */
-  adcStart(&ADCD1, &adccfg1);
+  adcStart(&ADCD1, NULL);
 
   /*
    * Linear conversion.
-- 
cgit v1.2.3


From f7aa043204a98f1a1248f12b870fe2ef697c2516 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Fri, 8 Mar 2013 14:26:44 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5383
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/ADC/Makefile  |   2 +-
 testhal/SPC563Mxx/ADC/adc_cfg.c | 747 ++++++++++++++++++++++++++++++++++++++++
 testhal/SPC563Mxx/ADC/adc_cfg.h |  42 +++
 testhal/SPC563Mxx/ADC/main.c    | 231 +------------
 4 files changed, 803 insertions(+), 219 deletions(-)
 create mode 100644 testhal/SPC563Mxx/ADC/adc_cfg.c
 create mode 100644 testhal/SPC563Mxx/ADC/adc_cfg.h

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/ADC/Makefile b/testhal/SPC563Mxx/ADC/Makefile
index 4a009578f..8d2f2bead 100644
--- a/testhal/SPC563Mxx/ADC/Makefile
+++ b/testhal/SPC563Mxx/ADC/Makefile
@@ -66,7 +66,7 @@ CSRC = $(PORTSRC) \
        $(CHIBIOS)/os/various/evtimer.c \
        $(CHIBIOS)/os/various/shell.c \
        $(CHIBIOS)/os/various/chprintf.c \
-       main.c
+       adc_cfg.c main.c
 
 # C++ sources here.
 CPPSRC =
diff --git a/testhal/SPC563Mxx/ADC/adc_cfg.c b/testhal/SPC563Mxx/ADC/adc_cfg.c
new file mode 100644
index 000000000..4d16e75f9
--- /dev/null
+++ b/testhal/SPC563Mxx/ADC/adc_cfg.c
@@ -0,0 +1,747 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include "ch.h"
+#include "hal.h"
+#include "adc_cfg.h"
+
+/*
+ * ADC conversion group.
+ * Mode:        Linear buffer, 8 samples of 5 channels, SW triggered.
+ * Channels:    ADC_CHN_VRL, ADC_CHN_VREF25, ADC_CHN_VREF50,
+ *              ADC_CHN_VREF75, ADC_CHN_VRH.
+ *
+ * NOTE: The configuration of a sequence is very complex in this ADC
+ * implementation. Configurations are meant to be generated by the
+ * SPC5 Studio visual configuration tool and not be written manually.
+ * Writing complex sequences manually requires ad deep knowledge of both
+ * the EQADC peripheral and the driver implementation.
+ */
+static const adccommand_t adcgrpcfg1_commands[ADC_GRP1_NUM_CHANNELS *
+                                              ADC_GRP1_BUF_DEPTH] = {
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH)
+};
+
+const ADCConversionGroup adcgrpcfg1 = {
+  FALSE,
+  ADC_GRP1_NUM_CHANNELS,
+  NULL,
+  adcerrorcallback,
+  EQADC_CFCR_MODE_SWCS,
+  0, 0,                     /* ISEL, EISEL.*/
+  ADC_GRP1_BUF_DEPTH,
+  adcgrpcfg1_commands
+};
+
+/*
+ * ADC conversion group.
+ * Mode:        Circular buffer, 16 samples of 5 channels, SW triggered.
+ * Channels:    ADC_CHN_VRL, ADC_CHN_VRL, ADC_CHN_VREF25, ADC_CHN_VREF50,
+ *              ADC_CHN_VREF50, ADC_CHN_VREF75, ADC_CHN_VRH, ADC_CHN_VRH.
+ *
+ * NOTE: The configuration of a sequence is very complex in this ADC
+ * implementation. Configurations are meant to be generated by the
+ * SPC5 Studio visual configuration tool and not be written manually.
+ * Writing complex sequences manually requires ad deep knowledge of both
+ * the EQADC peripheral and the driver implementation.
+ */
+static const adccommand_t adcgrpcfg2_commands[ADC_GRP2_NUM_CHANNELS *
+                                              ADC_GRP2_BUF_DEPTH] = {
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+
+  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
+  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(2) |
+  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
+};
+
+const ADCConversionGroup adcgrpcfg2 = {
+  FALSE,
+  ADC_GRP2_NUM_CHANNELS,
+  adccallback,
+  adcerrorcallback,
+  EQADC_CFCR_MODE_SWCS,
+  0, 0,                     /* ISEL, EISEL.*/
+  ADC_GRP2_BUF_DEPTH,
+  adcgrpcfg2_commands
+};
diff --git a/testhal/SPC563Mxx/ADC/adc_cfg.h b/testhal/SPC563Mxx/ADC/adc_cfg.h
new file mode 100644
index 000000000..6e362820f
--- /dev/null
+++ b/testhal/SPC563Mxx/ADC/adc_cfg.h
@@ -0,0 +1,42 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef _ADC_CFG_H_
+#define _ADC_CFG_H_
+
+#define ADC_GRP1_NUM_CHANNELS   5
+#define ADC_GRP1_BUF_DEPTH      8
+
+#define ADC_GRP2_NUM_CHANNELS   8
+#define ADC_GRP2_BUF_DEPTH      16
+
+extern const ADCConversionGroup adcgrpcfg1;
+extern const ADCConversionGroup adcgrpcfg2;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n);
+  void adcerrorcallback(ADCDriver *adcp, adcerror_t err);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ADC_CFG_H_ */
diff --git a/testhal/SPC563Mxx/ADC/main.c b/testhal/SPC563Mxx/ADC/main.c
index 076d506d7..398c56b4f 100644
--- a/testhal/SPC563Mxx/ADC/main.c
+++ b/testhal/SPC563Mxx/ADC/main.c
@@ -20,21 +20,16 @@
 
 #include "ch.h"
 #include "hal.h"
-
-#define ADC_GRP1_NUM_CHANNELS   5
-#define ADC_GRP1_BUF_DEPTH      8
-
-//#define ADC_GRP2_NUM_CHANNELS   8
-//#define ADC_GRP2_BUF_DEPTH      16
+#include "adc_cfg.h"
 
 static adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH];
-//static adcsample_t samples2[ADC_GRP2_NUM_CHANNELS * ADC_GRP2_BUF_DEPTH];
+static adcsample_t samples2[ADC_GRP2_NUM_CHANNELS * ADC_GRP2_BUF_DEPTH];
 
 /*
  * ADC streaming callback.
  */
-/*size_t nx = 0, ny = 0;
-static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) {
+size_t nx = 0, ny = 0;
+void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) {
 
   (void)adcp;
   if (samples2 == buffer) {
@@ -43,9 +38,12 @@ static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) {
   else {
     ny += n;
   }
-}*/
+}
 
-static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) {
+/*
+ * ADC error callback.
+ */
+void adcerrorcallback(ADCDriver *adcp, adcerror_t err) {
 
   (void)adcp;
   (void)err;
@@ -54,204 +52,6 @@ static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) {
   chSysHalt();
 }
 
-/*
- * ADC conversion group.
- * Mode:        Linear buffer, 8 samples of 5 channels, SW triggered.
- * Channels:    ADC_CHN_VRL, ADC_CHN_VREF25, ADC_CHN_VREF50,
- *              ADC_CHN_VREF75, ADC_CHN_VRH.
- *
- * NOTE: The configuration of a sequence is very complex in this ADC
- * implementation. Configurations are meant to be generated by the
- * SPC5 Studio visual configuration tool and not be written manually.
- * Writing complex sequences manually requires ad deep knowledge of both
- * the EQADC peripheral and the driver implementation.
- */
-static const adccommand_t adcgrpcfg1_commands[ADC_GRP1_NUM_CHANNELS *
-                                              ADC_GRP1_BUF_DEPTH] = {
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VRH),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VRL),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VREF25),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VREF50),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VREF75),
-
-  EQADC_CONV_BN_ADC0 | EQADC_CONV_LST_64 | EQADC_CONV_CAL |
-  EQADC_CONV_FMT_RJU | EQADC_CONV_CONFIG_STD | EQADC_CONV_MSG_RFIFO(0) |
-  EQADC_CONV_CHANNEL(ADC_CHN_VRH)
-};
-
-static const ADCConversionGroup adcgrpcfg1 = {
-  FALSE,
-  ADC_GRP1_NUM_CHANNELS,
-  NULL,
-  adcerrorcallback,
-  EQADC_CFCR_MODE_SWCS,
-  0, 0,                     /* ISEL, EISEL.*/
-  ADC_GRP1_BUF_DEPTH,
-  adcgrpcfg1_commands
-};
-
-/*
- * ADC conversion group.
- * Mode:        Continuous, 16 samples of 8 channels, SW triggered.
- * Channels:    IN7, IN8, IN7, IN8, IN7, IN8, Sensor, VBat/2.
- */
-/*static const ADCConversionGroup adcgrpcfg2 = {
-  TRUE,
-  ADC_GRP2_NUM_CHANNELS,
-  adccallback,
-  adcerrorcallback,
-};*/
-
 /*
  * Red LEDs blinker thread, times are in milliseconds.
  */
@@ -284,21 +84,16 @@ int main(void) {
   halInit();
   chSysInit();
 
-  /*
-   * Setting up analog inputs used by the demo.
-   */
-/*  palSetGroupMode(GPIOC, PAL_PORT_BIT(1) | PAL_PORT_BIT(2),
-                  0, PAL_MODE_INPUT_ANALOG);*/
-
   /*
    * Creates the blinker thread.
    */
   chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
 
   /*
-   * Activates the ADC1 driver (unit zero queue zero).
+   * Activates the ADC1, ADC3 drivers.
    */
   adcStart(&ADCD1, NULL);
+  adcStart(&ADCD3, NULL);
 
   /*
    * Linear conversion.
@@ -309,14 +104,14 @@ int main(void) {
   /*
    * Starts an ADC continuous conversion.
    */
-//  adcStartConversion(&ADCD1, &adcgrpcfg2, samples2, ADC_GRP2_BUF_DEPTH);
+  adcStartConversion(&ADCD3, &adcgrpcfg2, samples2, ADC_GRP2_BUF_DEPTH);
 
   /*
    * Normal main() thread activity, in this demo it does nothing.
    */
   while (TRUE) {
     if (palReadPad(PORT11, P11_BUTTON1)) {
-//      adcStopConversion(&ADCD1);
+      adcStopConversion(&ADCD3);
     }
     chThdSleepMilliseconds(500);
   }
-- 
cgit v1.2.3


From 524a5b7b42961f318e998d9131984e395e153e68 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Fri, 8 Mar 2013 14:38:19 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5384
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/ADC/adc_cfg.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/ADC/adc_cfg.c b/testhal/SPC563Mxx/ADC/adc_cfg.c
index 4d16e75f9..f21f4ddce 100644
--- a/testhal/SPC563Mxx/ADC/adc_cfg.c
+++ b/testhal/SPC563Mxx/ADC/adc_cfg.c
@@ -736,7 +736,7 @@ static const adccommand_t adcgrpcfg2_commands[ADC_GRP2_NUM_CHANNELS *
 };
 
 const ADCConversionGroup adcgrpcfg2 = {
-  FALSE,
+  TRUE,
   ADC_GRP2_NUM_CHANNELS,
   adccallback,
   adcerrorcallback,
-- 
cgit v1.2.3


From 5b82050f03ec5574fce2591e24549b9f683ccd37 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 19 Mar 2013 09:14:18 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5453
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/ADC/mcuconf.h | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/ADC/mcuconf.h b/testhal/SPC563Mxx/ADC/mcuconf.h
index bca85fb65..b3f742baf 100644
--- a/testhal/SPC563Mxx/ADC/mcuconf.h
+++ b/testhal/SPC563Mxx/ADC/mcuconf.h
@@ -51,7 +51,27 @@
 #define SPC5_ADC_USE_ADC1_Q3                TRUE
 #define SPC5_ADC_USE_ADC1_Q4                TRUE
 #define SPC5_ADC_USE_ADC1_Q5                TRUE
+#define SPC5_ADC_FIFO0_DMA_PRIO             12
+#define SPC5_ADC_FIFO1_DMA_PRIO             12
+#define SPC5_ADC_FIFO2_DMA_PRIO             12
+#define SPC5_ADC_FIFO3_DMA_PRIO             12
+#define SPC5_ADC_FIFO4_DMA_PRIO             12
+#define SPC5_ADC_FIFO5_DMA_PRIO             12
+#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO         12
+#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO         12
+#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO         12
+#define SPC5_ADC_FIFO3_DMA_IRQ_PRIO         12
+#define SPC5_ADC_FIFO4_DMA_IRQ_PRIO         12
+#define SPC5_ADC_FIFO5_DMA_IRQ_PRIO         12
 #define SPC5_ADC_CR_CLK_PS                  ADC_CR_CLK_PS(5)
+#define SPC5_ADC_PUDCR                      {ADC_PUDCR_NONE,                \
+                                             ADC_PUDCR_NONE,                \
+                                             ADC_PUDCR_NONE,                \
+                                             ADC_PUDCR_NONE,                \
+                                             ADC_PUDCR_NONE,                \
+                                             ADC_PUDCR_NONE,                \
+                                             ADC_PUDCR_NONE,                \
+                                             ADC_PUDCR_NONE}
 
 /*
  * SERIAL driver system settings.
-- 
cgit v1.2.3


From b1c1f94d4ae48d7420c6441cf9f1831dad27c784 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Fri, 22 Mar 2013 15:00:22 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5490
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/ADC/main.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/ADC/main.c b/testhal/SPC563Mxx/ADC/main.c
index 398c56b4f..a8e1bea8d 100644
--- a/testhal/SPC563Mxx/ADC/main.c
+++ b/testhal/SPC563Mxx/ADC/main.c
@@ -53,7 +53,7 @@ void adcerrorcallback(ADCDriver *adcp, adcerror_t err) {
 }
 
 /*
- * Red LEDs blinker thread, times are in milliseconds.
+ * LED blinker thread, times are in milliseconds.
  */
 static WORKING_AREA(waThread1, 128);
 static msg_t Thread1(void *arg) {
@@ -107,7 +107,8 @@ int main(void) {
   adcStartConversion(&ADCD3, &adcgrpcfg2, samples2, ADC_GRP2_BUF_DEPTH);
 
   /*
-   * Normal main() thread activity, in this demo it does nothing.
+   * Normal main() thread activity, once the button is pressed the ADC
+   * conversion is stopped.
    */
   while (TRUE) {
     if (palReadPad(PORT11, P11_BUTTON1)) {
-- 
cgit v1.2.3


From 814bc9e8e7f4593490f9e2e6175ad69e29e682ab Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Mon, 25 Mar 2013 10:54:02 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5504
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/ADC/.project   |   2 +-
 testhal/SPC563Mxx/ADC/Makefile   |   2 +-
 testhal/SPC563Mxx/ADC/readme.txt |   4 +-
 testhal/SPC563Mxx/SPI/.cproject  |  51 ++++
 testhal/SPC563Mxx/SPI/.project   |  38 +++
 testhal/SPC563Mxx/SPI/Makefile   | 163 ++++++++++++
 testhal/SPC563Mxx/SPI/chconf.h   | 535 +++++++++++++++++++++++++++++++++++++++
 testhal/SPC563Mxx/SPI/halconf.h  | 316 +++++++++++++++++++++++
 testhal/SPC563Mxx/SPI/main.c     | 136 ++++++++++
 testhal/SPC563Mxx/SPI/mcuconf.h  |  87 +++++++
 testhal/SPC563Mxx/SPI/readme.txt |  25 ++
 11 files changed, 1356 insertions(+), 3 deletions(-)
 create mode 100644 testhal/SPC563Mxx/SPI/.cproject
 create mode 100644 testhal/SPC563Mxx/SPI/.project
 create mode 100644 testhal/SPC563Mxx/SPI/Makefile
 create mode 100644 testhal/SPC563Mxx/SPI/chconf.h
 create mode 100644 testhal/SPC563Mxx/SPI/halconf.h
 create mode 100644 testhal/SPC563Mxx/SPI/main.c
 create mode 100644 testhal/SPC563Mxx/SPI/mcuconf.h
 create mode 100644 testhal/SPC563Mxx/SPI/readme.txt

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/ADC/.project b/testhal/SPC563Mxx/ADC/.project
index c315293cf..ff4e5ffca 100644
--- a/testhal/SPC563Mxx/ADC/.project
+++ b/testhal/SPC563Mxx/ADC/.project
@@ -27,7 +27,7 @@
 		<link>
 			<name>board</name>
 			<type>2</type>
-			<locationURI>CHIBIOS/boards/GENERIC_SPC563M</locationURI>
+			<locationURI>CHIBIOS/boards/ST_EVB_SPC563M</locationURI>
 		</link>
 		<link>
 			<name>os</name>
diff --git a/testhal/SPC563Mxx/ADC/Makefile b/testhal/SPC563Mxx/ADC/Makefile
index 8d2f2bead..932511e51 100644
--- a/testhal/SPC563Mxx/ADC/Makefile
+++ b/testhal/SPC563Mxx/ADC/Makefile
@@ -46,7 +46,7 @@ PROJECT = ch
 
 # Imported source files
 CHIBIOS = ../../..
-include $(CHIBIOS)/boards/GENERIC_SPC563M/board.mk
+include $(CHIBIOS)/boards/ST_EVB_SPC563M/board.mk
 include $(CHIBIOS)/os/hal/platforms/SPC563Mxx/platform.mk
 include $(CHIBIOS)/os/hal/hal.mk
 include $(CHIBIOS)/os/ports/GCC/PPC/SPC563Mxx/port.mk
diff --git a/testhal/SPC563Mxx/ADC/readme.txt b/testhal/SPC563Mxx/ADC/readme.txt
index c03dd687c..ebe5c0a37 100644
--- a/testhal/SPC563Mxx/ADC/readme.txt
+++ b/testhal/SPC563Mxx/ADC/readme.txt
@@ -2,12 +2,14 @@
 ** ChibiOS/RT HAL - ADC driver demo for SPC563Mxx.                         **
 *****************************************************************************
 
+** TARGET **
+
 The demo runs on an STMicroelectronics SPC563Mxx microcontroller installed on 
 XPC56xx EVB Motherboard.
 
 ** The Demo **
 
-The application demonstrates the use of the SPC560Pxx ADC driver.
+The application demonstrates the use of the SPC563Mxx ADC driver.
 
 ** Board Setup **
 
diff --git a/testhal/SPC563Mxx/SPI/.cproject b/testhal/SPC563Mxx/SPI/.cproject
new file mode 100644
index 000000000..a4ae17c6d
--- /dev/null
+++ b/testhal/SPC563Mxx/SPI/.cproject
@@ -0,0 +1,51 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="0.861226640">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="0.861226640" moduleId="org.eclipse.cdt.core.settings" name="Default">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.VCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactName="${ProjName}" buildProperties="" description="" id="0.861226640" name="Default" parent="org.eclipse.cdt.build.core.prefbase.cfg">
+					<folderInfo id="0.861226640." name="/" resourcePath="">
+						<toolChain id="org.eclipse.cdt.build.core.prefbase.toolchain.1002748249" name="No ToolChain" resourceTypeBasedDiscovery="false" superClass="org.eclipse.cdt.build.core.prefbase.toolchain">
+							<targetPlatform id="org.eclipse.cdt.build.core.prefbase.toolchain.1002748249.660222523" name=""/>
+							<builder autoBuildTarget="all" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="org.eclipse.cdt.build.core.settings.default.builder.662368067" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.settings.default.builder"/>
+							<tool id="org.eclipse.cdt.build.core.settings.holder.libs.1194892762" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/>
+							<tool id="org.eclipse.cdt.build.core.settings.holder.1089722463" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder">
+								<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1861343146" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+							</tool>
+							<tool id="org.eclipse.cdt.build.core.settings.holder.1644189815" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder">
+								<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1045400342" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+							</tool>
+							<tool id="org.eclipse.cdt.build.core.settings.holder.1188847444" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder">
+								<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.263638018" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="SPC563Mxx-SPI.null.1461388361" name="SPC563Mxx-SPI"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="0.861226640">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+</cproject>
diff --git a/testhal/SPC563Mxx/SPI/.project b/testhal/SPC563Mxx/SPI/.project
new file mode 100644
index 000000000..31139adbb
--- /dev/null
+++ b/testhal/SPC563Mxx/SPI/.project
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>SPC563Mxx-SPI</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>board</name>
+			<type>2</type>
+			<locationURI>CHIBIOS/boards/ST_EVB_SPC563M</locationURI>
+		</link>
+		<link>
+			<name>os</name>
+			<type>2</type>
+			<locationURI>CHIBIOS/os</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/testhal/SPC563Mxx/SPI/Makefile b/testhal/SPC563Mxx/SPI/Makefile
new file mode 100644
index 000000000..2cef7b38c
--- /dev/null
+++ b/testhal/SPC563Mxx/SPI/Makefile
@@ -0,0 +1,163 @@
+##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+  USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+  USE_COPT = 
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+  USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data.
+ifeq ($(USE_LINK_GC),)
+  USE_LINK_GC = yes
+endif
+
+# If enabled, this option allows to compile the application in VLE mode.
+ifeq ($(USE_VLE),)
+  USE_VLE = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+  USE_VERBOSE_COMPILE = no
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files
+CHIBIOS = ../../..
+include $(CHIBIOS)/boards/ST_EVB_SPC563M/board.mk
+include $(CHIBIOS)/os/hal/platforms/SPC563Mxx/platform.mk
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS)/os/ports/GCC/PPC/SPC563Mxx/port.mk
+include $(CHIBIOS)/os/kernel/kernel.mk
+#include $(CHIBIOS)/test/test.mk
+
+# Define linker script file here
+LDSCRIPT= $(PORTLD)/SPC563M64.ld
+
+# C sources here.
+CSRC = $(PORTSRC) \
+       $(KERNSRC) \
+       $(TESTSRC) \
+       $(HALSRC) \
+       $(PLATFORMSRC) \
+       $(BOARDSRC) \
+       $(CHIBIOS)/os/various/evtimer.c \
+       $(CHIBIOS)/os/various/shell.c \
+       $(CHIBIOS)/os/various/chprintf.c \
+       main.c
+
+# C++ sources here.
+CPPSRC =
+
+# List ASM source files here
+ASMSRC = $(PORTASM)
+
+INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
+         $(HALINC) $(PLATFORMINC) $(BOARDINC) \
+         $(CHIBIOS)/os/various
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+#MCU  = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames
+MCU  = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames
+
+#TRGT = powerpc-eabi-
+TRGT = ppc-vle-
+CC   = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+#       runtime support makes code size explode.
+LD   = $(TRGT)gcc
+#LD   = $(TRGT)g++
+CP   = $(TRGT)objcopy
+AS   = $(TRGT)gcc -x assembler-with-cpp
+OD   = $(TRGT)objdump
+HEX  = $(CP) -O ihex
+BIN  = $(CP) -O binary
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of default section
+#
+
+# List all default C defines here, like -D_DEBUG=1
+DDEFS =
+
+# List all default ASM defines here, like -D_DEBUG=1
+DADEFS =
+
+# List all default directories to look for include files here
+DINCDIR =
+
+# List the default directory to look for the libraries here
+DLIBDIR =
+
+# List all default libraries here
+DLIBS =
+
+#
+# End of default section
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+include $(CHIBIOS)/os/ports/GCC/PPC/rules.mk
diff --git a/testhal/SPC563Mxx/SPI/chconf.h b/testhal/SPC563Mxx/SPI/chconf.h
new file mode 100644
index 000000000..5b1e9895f
--- /dev/null
+++ b/testhal/SPC563Mxx/SPI/chconf.h
@@ -0,0 +1,535 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    templates/chconf.h
+ * @brief   Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ *          contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ *          setting also defines the system tick time unit.
+ */
+#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
+#define CH_FREQUENCY                    1000
+#endif
+
+/**
+ * @brief   Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ *          threads before preemption occurs. Setting this value to zero
+ *          disables the preemption for threads with equal priority and the
+ *          round robin becomes cooperative. Note that higher priority
+ *          threads can still preempt, the kernel is always preemptive.
+ *
+ * @note    Disabling the round robin preemption makes the kernel more compact
+ *          and generally faster.
+ */
+#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
+#define CH_TIME_QUANTUM                 20
+#endif
+
+/**
+ * @brief   Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ *          then the whole available RAM is used. The core memory is made
+ *          available to the heap allocator and/or can be used directly through
+ *          the simplified core memory allocator.
+ *
+ * @note    In order to let the OS manage the whole RAM the linker script must
+ *          provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note    Requires @p CH_USE_MEMCORE.
+ */
+#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
+#define CH_MEMCORE_SIZE                 0
+#endif
+
+/**
+ * @brief   Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ *          does not spawn the idle thread automatically. The application has
+ *          then the responsibility to do one of the following:
+ *          - Spawn a custom idle thread at priority @p IDLEPRIO.
+ *          - Change the main() thread priority to @p IDLEPRIO then enter
+ *            an endless loop. In this scenario the @p main() thread acts as
+ *            the idle thread.
+ *          .
+ * @note    Unless an idle thread is spawned the @p main() thread must not
+ *          enter a sleep state.
+ */
+#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
+#define CH_NO_IDLE_THREAD               FALSE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ *          is used when two possible implementations exist.
+ *
+ * @note    This is not related to the compiler optimization options.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
+#define CH_OPTIMIZE_SPEED               TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
+#define CH_USE_REGISTRY                 TRUE
+#endif
+
+/**
+ * @brief   Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ *          the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
+#define CH_USE_WAITEXIT                 TRUE
+#endif
+
+/**
+ * @brief   Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES               TRUE
+#endif
+
+/**
+ * @brief   Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ *          priority rather than in FIFO order.
+ *
+ * @note    The default is @p FALSE. Enable this if you have special requirements.
+ * @note    Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES_PRIORITY      FALSE
+#endif
+
+/**
+ * @brief   Atomic semaphore API.
+ * @details If enabled then the semaphores the @p chSemSignalWait() API
+ *          is included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
+#define CH_USE_SEMSW                    TRUE
+#endif
+
+/**
+ * @brief   Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
+#define CH_USE_MUTEXES                  TRUE
+#endif
+
+/**
+ * @brief   Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_MUTEXES.
+ */
+#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS                 TRUE
+#endif
+
+/**
+ * @brief   Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ *          specification are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_CONDVARS.
+ */
+#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS_TIMEOUT         TRUE
+#endif
+
+/**
+ * @brief   Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS                   TRUE
+#endif
+
+/**
+ * @brief   Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ *          are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_EVENTS.
+ */
+#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS_TIMEOUT           TRUE
+#endif
+
+/**
+ * @brief   Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES                 TRUE
+#endif
+
+/**
+ * @brief   Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ *          FIFO order.
+ *
+ * @note    The default is @p FALSE. Enable this if you have special requirements.
+ * @note    Requires @p CH_USE_MESSAGES.
+ */
+#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES_PRIORITY        FALSE
+#endif
+
+/**
+ * @brief   Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ *          included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
+#define CH_USE_MAILBOXES                TRUE
+#endif
+
+/**
+ * @brief   I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
+#define CH_USE_QUEUES                   TRUE
+#endif
+
+/**
+ * @brief   Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
+#define CH_USE_MEMCORE                  TRUE
+#endif
+
+/**
+ * @brief   Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
+ *          @p CH_USE_SEMAPHORES.
+ * @note    Mutexes are recommended.
+ */
+#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_HEAP                     TRUE
+#endif
+
+/**
+ * @brief   C-runtime allocator.
+ * @details If enabled the the heap allocator APIs just wrap the C-runtime
+ *          @p malloc() and @p free() functions.
+ *
+ * @note    The default is @p FALSE.
+ * @note    Requires @p CH_USE_HEAP.
+ * @note    The C-runtime may or may not require @p CH_USE_MEMCORE, see the
+ *          appropriate documentation.
+ */
+#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_MALLOC_HEAP              FALSE
+#endif
+
+/**
+ * @brief   Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
+#define CH_USE_MEMPOOLS                 TRUE
+#endif
+
+/**
+ * @brief   Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_WAITEXIT.
+ * @note    Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
+ */
+#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
+#define CH_USE_DYNAMIC                  TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ *          at runtime.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_SYSTEM_STATE_CHECK       TRUE
+#endif
+
+/**
+ * @brief   Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ *          parameters are activated.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_CHECKS            TRUE
+#endif
+
+/**
+ * @brief   Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ *          activated. This includes consistency checks inside the kernel,
+ *          runtime anomalies and port-defined checks.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_ASSERTS           TRUE
+#endif
+
+/**
+ * @brief   Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ *          activated.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_TRACE             TRUE
+#endif
+
+/**
+ * @brief   Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note    The default is @p FALSE.
+ * @note    The stack check is performed in a architecture/port dependent way.
+ *          It may not be implemented or some ports.
+ * @note    The default failure mode is to halt the system with the global
+ *          @p panic_msg variable set to @p NULL.
+ */
+#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_STACK_CHECK       FALSE
+#endif
+
+/**
+ * @brief   Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ *          value when a thread is created. This can be useful for the
+ *          runtime measurement of the used stack.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
+#define CH_DBG_FILL_THREADS             TRUE
+#endif
+
+/**
+ * @brief   Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p Thread structure that
+ *          counts the system ticks occurred while executing the thread.
+ *
+ * @note    The default is @p TRUE.
+ * @note    This debug option is defaulted to TRUE because it is required by
+ *          some test cases into the test suite.
+ */
+#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
+#define CH_DBG_THREADS_PROFILING        TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Threads descriptor structure extension.
+ * @details User fields added to the end of the @p Thread structure.
+ */
+#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
+#define THREAD_EXT_FIELDS                                                   \
+  /* Add threads custom fields here.*/
+#endif
+
+/**
+ * @brief   Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note    It is invoked from within @p chThdInit() and implicitly from all
+ *          the threads creation APIs.
+ */
+#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
+#define THREAD_EXT_INIT_HOOK(tp) {                                          \
+  /* Add threads initialization code here.*/                                \
+}
+#endif
+
+/**
+ * @brief   Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note    It is inserted into lock zone.
+ * @note    It is also invoked when the threads simply return in order to
+ *          terminate.
+ */
+#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
+#define THREAD_EXT_EXIT_HOOK(tp) {                                          \
+  /* Add threads finalization code here.*/                                  \
+}
+#endif
+
+/**
+ * @brief   Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
+#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) {                              \
+  /* System halt code here.*/                                               \
+}
+#endif
+
+/**
+ * @brief   Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
+#define IDLE_LOOP_HOOK() {                                                  \
+  /* Idle loop code here.*/                                                 \
+}
+#endif
+
+/**
+ * @brief   System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ *          after processing the virtual timers queue.
+ */
+#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
+#define SYSTEM_TICK_EVENT_HOOK() {                                          \
+  /* System tick event code here.*/                                         \
+}
+#endif
+
+/**
+ * @brief   System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ *          the system is halted.
+ */
+#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
+#define SYSTEM_HALT_HOOK() {                                                \
+  /* System halt code here.*/                                               \
+}
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h).    */
+/*===========================================================================*/
+
+#endif  /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/SPC563Mxx/SPI/halconf.h b/testhal/SPC563Mxx/SPI/halconf.h
new file mode 100644
index 000000000..312d99320
--- /dev/null
+++ b/testhal/SPC563Mxx/SPI/halconf.h
@@ -0,0 +1,316 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    templates/halconf.h
+ * @brief   HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ *          various device drivers from your application. You may also use
+ *          this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief   Enables the TM subsystem.
+ */
+#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
+#define HAL_USE_TM                  FALSE
+#endif
+
+/**
+ * @brief   Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL                 TRUE
+#endif
+
+/**
+ * @brief   Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN                 FALSE
+#endif
+
+/**
+ * @brief   Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT                 FALSE
+#endif
+
+/**
+ * @brief   Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT                 FALSE
+#endif
+
+/**
+ * @brief   Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C                 FALSE
+#endif
+
+/**
+ * @brief   Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU                 FALSE
+#endif
+
+/**
+ * @brief   Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI             FALSE
+#endif
+
+/**
+ * @brief   Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM                 FALSE
+#endif
+
+/**
+ * @brief   Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL              FALSE
+#endif
+
+/**
+ * @brief   Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB          FALSE
+#endif
+
+/**
+ * @brief   Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI                 TRUE
+#endif
+
+/**
+ * @brief   Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART                FALSE
+#endif
+
+/**
+ * @brief   Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB                 FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables synchronous APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT                TRUE
+#endif
+
+/**
+ * @brief   Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION    TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE          TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION    TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY           FALSE
+#endif
+
+/**
+ * @brief   Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS              TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings.                                          */
+/*===========================================================================*/
+
+/**
+ * @brief   Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ *          routines releasing some extra CPU time for the threads with
+ *          lower priority, this may slow down the driver a bit however.
+ *          This option is recommended also if the SPI driver does not
+ *          use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING            TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Number of initialization attempts before rejecting the card.
+ * @note    Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY              100
+#endif
+
+/**
+ * @brief   Include support for MMC cards.
+ * @note    MMC support is not yet implemented so this option must be kept
+ *          at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT             FALSE
+#endif
+
+/**
+ * @brief   Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ *          routines releasing some extra CPU time for the threads with
+ *          lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING            TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings.                                           */
+/*===========================================================================*/
+
+/**
+ * @brief   Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ *          default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE      38400
+#endif
+
+/**
+ * @brief   Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ *          buffers depending on the requirements of your application.
+ * @note    The default is 64 bytes for both the transmission and receive
+ *          buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE         16
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables synchronous APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT                TRUE
+#endif
+
+/**
+ * @brief   Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION    TRUE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/SPC563Mxx/SPI/main.c b/testhal/SPC563Mxx/SPI/main.c
new file mode 100644
index 000000000..ad38d01a6
--- /dev/null
+++ b/testhal/SPC563Mxx/SPI/main.c
@@ -0,0 +1,136 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012,2013 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/*
+ * Maximum speed SPI configuration (21MHz, CPHA=0, CPOL=0, MSb first).
+ */
+static const SPIConfig hs_spicfg = {
+  NULL
+};
+
+/*
+ * Low speed SPI configuration (328.125kHz, CPHA=0, CPOL=0, MSb first).
+ */
+static const SPIConfig ls_spicfg = {
+  NULL
+};
+
+/*
+ * SPI TX and RX buffers.
+ */
+static uint8_t txbuf[512];
+static uint8_t rxbuf[512];
+
+/*
+ * SPI bus contender 1.
+ */
+static WORKING_AREA(spi_thread_1_wa, 256);
+static msg_t spi_thread_1(void *p) {
+
+  (void)p;
+  chRegSetThreadName("SPI thread 1");
+  while (TRUE) {
+    spiAcquireBus(&SPID1);              /* Acquire ownership of the bus.    */
+    palSetPad(PORT11, P11_LED1);        /* LED ON.                          */
+    spiStart(&SPID1, &hs_spicfg);       /* Setup transfer parameters.       */
+    spiSelect(&SPID1);                  /* Slave Select assertion.          */
+    spiExchange(&SPID1, 512,
+                txbuf, rxbuf);          /* Atomic transfer operations.      */
+    spiUnselect(&SPID1);                /* Slave Select de-assertion.       */
+    spiReleaseBus(&SPID1);              /* Ownership release.               */
+  }
+  return 0;
+}
+
+/*
+ * SPI bus contender 2.
+ */
+static WORKING_AREA(spi_thread_2_wa, 256);
+static msg_t spi_thread_2(void *p) {
+
+  (void)p;
+  chRegSetThreadName("SPI thread 2");
+  while (TRUE) {
+    spiAcquireBus(&SPID1);              /* Acquire ownership of the bus.    */
+    palClearPad(PORT11, P11_LED1);      /* LED OFF.                         */
+    spiStart(&SPID1, &ls_spicfg);       /* Setup transfer parameters.       */
+    spiSelect(&SPID1);                  /* Slave Select assertion.          */
+    spiExchange(&SPID1, 512,
+                txbuf, rxbuf);          /* Atomic transfer operations.      */
+    spiUnselect(&SPID1);                /* Slave Select de-assertion.       */
+    spiReleaseBus(&SPID1);              /* Ownership release.               */
+  }
+  return 0;
+}
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+  unsigned i;
+
+  /*
+   * System initializations.
+   * - HAL initialization, this also initializes the configured device drivers
+   *   and performs the board-specific initializations.
+   * - Kernel initialization, the main() function becomes a thread and the
+   *   RTOS is active.
+   */
+  halInit();
+  chSysInit();
+
+  /*
+   * SPI2 I/O pins setup.
+   */
+  palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(5) |
+                           PAL_STM32_OSPEED_HIGHEST);       /* New SCK.     */
+  palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(5) |
+                           PAL_STM32_OSPEED_HIGHEST);       /* New MISO.    */
+  palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(5) |
+                           PAL_STM32_OSPEED_HIGHEST);       /* New MOSI.    */
+  palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL |
+                           PAL_STM32_OSPEED_HIGHEST);       /* New CS.      */
+  palSetPad(GPIOB, 12);
+
+  /*
+   * Prepare transmit pattern.
+   */
+  for (i = 0; i < sizeof(txbuf); i++)
+    txbuf[i] = (uint8_t)i;
+
+  /*
+   * Starting the transmitter and receiver threads.
+   */
+  chThdCreateStatic(spi_thread_1_wa, sizeof(spi_thread_1_wa),
+                    NORMALPRIO + 1, spi_thread_1, NULL);
+  chThdCreateStatic(spi_thread_2_wa, sizeof(spi_thread_2_wa),
+                    NORMALPRIO + 1, spi_thread_2, NULL);
+
+  /*
+   * Normal main() thread activity, in this demo it does nothing.
+   */
+  while (TRUE) {
+    chThdSleepMilliseconds(500);
+  }
+  return 0;
+}
diff --git a/testhal/SPC563Mxx/SPI/mcuconf.h b/testhal/SPC563Mxx/SPI/mcuconf.h
new file mode 100644
index 000000000..45501882b
--- /dev/null
+++ b/testhal/SPC563Mxx/SPI/mcuconf.h
@@ -0,0 +1,87 @@
+/*
+ * Licensed under ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ *        http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software 
+ * distributed under the License is distributed on an "AS IS" BASIS, 
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * SPC563Mxx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 1...15       Lowest...Highest.
+ */
+
+#define SPC563Mxx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define SPC5_NO_INIT                        FALSE
+#define SPC5_CLK_BYPASS                     FALSE
+#define SPC5_ALLOW_OVERCLOCK                FALSE
+#define SPC5_CLK_PREDIV_VALUE               2
+#define SPC5_CLK_MFD_VALUE                  80
+#define SPC5_CLK_RFD                        SPC5_RFD_DIV4
+#define SPC5_FLASH_BIUCR                    (BIUCR_BANK1_TOO |              \
+                                             BIUCR_MASTER4_PREFETCH |       \
+                                             BIUCR_MASTER0_PREFETCH |       \
+                                             BIUCR_DPFEN |                  \
+                                             BIUCR_IPFEN |                  \
+                                             BIUCR_PFLIM_ON_MISS |          \
+                                             BIUCR_BFEN)
+
+/*
+ * ADC driver settings.
+ */
+#define SPC5_ADC_USE_ADC0_Q0                TRUE
+#define SPC5_ADC_USE_ADC0_Q1                TRUE
+#define SPC5_ADC_USE_ADC0_Q2                TRUE
+#define SPC5_ADC_USE_ADC1_Q3                TRUE
+#define SPC5_ADC_USE_ADC1_Q4                TRUE
+#define SPC5_ADC_USE_ADC1_Q5                TRUE
+#define SPC5_ADC_FIFO0_DMA_PRIO             12
+#define SPC5_ADC_FIFO1_DMA_PRIO             12
+#define SPC5_ADC_FIFO2_DMA_PRIO             12
+#define SPC5_ADC_FIFO3_DMA_PRIO             12
+#define SPC5_ADC_FIFO4_DMA_PRIO             12
+#define SPC5_ADC_FIFO5_DMA_PRIO             12
+#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO         12
+#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO         12
+#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO         12
+#define SPC5_ADC_FIFO3_DMA_IRQ_PRIO         12
+#define SPC5_ADC_FIFO4_DMA_IRQ_PRIO         12
+#define SPC5_ADC_FIFO5_DMA_IRQ_PRIO         12
+#define SPC5_ADC_CR_CLK_PS                  ADC_CR_CLK_PS(5)
+#define SPC5_ADC_PUDCR                      {ADC_PUDCR_NONE,                \
+                                             ADC_PUDCR_NONE,                \
+                                             ADC_PUDCR_NONE,                \
+                                             ADC_PUDCR_NONE,                \
+                                             ADC_PUDCR_NONE,                \
+                                             ADC_PUDCR_NONE,                \
+                                             ADC_PUDCR_NONE,                \
+                                             ADC_PUDCR_NONE}
+
+/*
+ * SERIAL driver system settings.
+ */
+#define SPC5_USE_ESCIA                      TRUE
+#define SPC5_USE_ESCIB                      TRUE
+#define SPC5_ESCIA_PRIORITY                 8
+#define SPC5_ESCIB_PRIORITY                 8
+
+/*
+ * SPI driver system settings.
+ */
+#define SPC5_SPI_USE_DSPI1                  FALSE
diff --git a/testhal/SPC563Mxx/SPI/readme.txt b/testhal/SPC563Mxx/SPI/readme.txt
new file mode 100644
index 000000000..1e0b7fcc0
--- /dev/null
+++ b/testhal/SPC563Mxx/SPI/readme.txt
@@ -0,0 +1,25 @@
+*****************************************************************************
+** ChibiOS/RT HAL - SPI driver demo for SPC563Mxx.                         **
+*****************************************************************************
+
+** TARGET **
+
+The demo runs on an STMicroelectronics SPC563Mxx microcontroller installed on 
+XPC56xx EVB Motherboard.
+
+** The Demo **
+
+The application demonstrates the use of the SPC563Mxx SPI driver.
+
+** Board Setup **
+
+** Build Procedure **
+
+The demo has been tested using HighTec compiler.
+
+** Notes **
+
+Some files used by the demo are not part of ChibiOS/RT but are copyright of
+ST Microelectronics and are licensed under a different license.
+
+                             http://www.st.com
-- 
cgit v1.2.3


From 4a2b2769363a3ec43a31e3c96ac303d241f3fc5d Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Mon, 25 Mar 2013 11:11:08 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5505
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/SPI/main.c    | 11 +----------
 testhal/SPC563Mxx/SPI/mcuconf.h |  2 +-
 2 files changed, 2 insertions(+), 11 deletions(-)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/SPI/main.c b/testhal/SPC563Mxx/SPI/main.c
index ad38d01a6..b3a5eb524 100644
--- a/testhal/SPC563Mxx/SPI/main.c
+++ b/testhal/SPC563Mxx/SPI/main.c
@@ -100,17 +100,8 @@ int main(void) {
   chSysInit();
 
   /*
-   * SPI2 I/O pins setup.
+   * SPI1 I/O pins setup.
    */
-  palSetPadMode(GPIOB, 13, PAL_MODE_ALTERNATE(5) |
-                           PAL_STM32_OSPEED_HIGHEST);       /* New SCK.     */
-  palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(5) |
-                           PAL_STM32_OSPEED_HIGHEST);       /* New MISO.    */
-  palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(5) |
-                           PAL_STM32_OSPEED_HIGHEST);       /* New MOSI.    */
-  palSetPadMode(GPIOB, 12, PAL_MODE_OUTPUT_PUSHPULL |
-                           PAL_STM32_OSPEED_HIGHEST);       /* New CS.      */
-  palSetPad(GPIOB, 12);
 
   /*
    * Prepare transmit pattern.
diff --git a/testhal/SPC563Mxx/SPI/mcuconf.h b/testhal/SPC563Mxx/SPI/mcuconf.h
index 45501882b..eee35f514 100644
--- a/testhal/SPC563Mxx/SPI/mcuconf.h
+++ b/testhal/SPC563Mxx/SPI/mcuconf.h
@@ -84,4 +84,4 @@
 /*
  * SPI driver system settings.
  */
-#define SPC5_SPI_USE_DSPI1                  FALSE
+#define SPC5_SPI_USE_DSPI1                  TRUE
-- 
cgit v1.2.3


From 0fc403c55a7aa76ef509dffd614ba99785010d1e Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 26 Mar 2013 15:02:45 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5506
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/SPI/main.c    | 24 ++++++++++++------------
 testhal/SPC563Mxx/SPI/mcuconf.h |  5 +++++
 2 files changed, 17 insertions(+), 12 deletions(-)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/SPI/main.c b/testhal/SPC563Mxx/SPI/main.c
index b3a5eb524..cd36b2ad1 100644
--- a/testhal/SPC563Mxx/SPI/main.c
+++ b/testhal/SPC563Mxx/SPI/main.c
@@ -50,14 +50,14 @@ static msg_t spi_thread_1(void *p) {
   (void)p;
   chRegSetThreadName("SPI thread 1");
   while (TRUE) {
-    spiAcquireBus(&SPID1);              /* Acquire ownership of the bus.    */
+    spiAcquireBus(&SPID2);              /* Acquire ownership of the bus.    */
     palSetPad(PORT11, P11_LED1);        /* LED ON.                          */
-    spiStart(&SPID1, &hs_spicfg);       /* Setup transfer parameters.       */
-    spiSelect(&SPID1);                  /* Slave Select assertion.          */
-    spiExchange(&SPID1, 512,
+    spiStart(&SPID2, &hs_spicfg);       /* Setup transfer parameters.       */
+    spiSelect(&SPID2);                  /* Slave Select assertion.          */
+    spiExchange(&SPID2, 512,
                 txbuf, rxbuf);          /* Atomic transfer operations.      */
-    spiUnselect(&SPID1);                /* Slave Select de-assertion.       */
-    spiReleaseBus(&SPID1);              /* Ownership release.               */
+    spiUnselect(&SPID2);                /* Slave Select de-assertion.       */
+    spiReleaseBus(&SPID2);              /* Ownership release.               */
   }
   return 0;
 }
@@ -71,14 +71,14 @@ static msg_t spi_thread_2(void *p) {
   (void)p;
   chRegSetThreadName("SPI thread 2");
   while (TRUE) {
-    spiAcquireBus(&SPID1);              /* Acquire ownership of the bus.    */
+    spiAcquireBus(&SPID2);              /* Acquire ownership of the bus.    */
     palClearPad(PORT11, P11_LED1);      /* LED OFF.                         */
-    spiStart(&SPID1, &ls_spicfg);       /* Setup transfer parameters.       */
-    spiSelect(&SPID1);                  /* Slave Select assertion.          */
-    spiExchange(&SPID1, 512,
+    spiStart(&SPID2, &ls_spicfg);       /* Setup transfer parameters.       */
+    spiSelect(&SPID2);                  /* Slave Select assertion.          */
+    spiExchange(&SPID2, 512,
                 txbuf, rxbuf);          /* Atomic transfer operations.      */
-    spiUnselect(&SPID1);                /* Slave Select de-assertion.       */
-    spiReleaseBus(&SPID1);              /* Ownership release.               */
+    spiUnselect(&SPID2);                /* Slave Select de-assertion.       */
+    spiReleaseBus(&SPID2);              /* Ownership release.               */
   }
   return 0;
 }
diff --git a/testhal/SPC563Mxx/SPI/mcuconf.h b/testhal/SPC563Mxx/SPI/mcuconf.h
index eee35f514..784a14d47 100644
--- a/testhal/SPC563Mxx/SPI/mcuconf.h
+++ b/testhal/SPC563Mxx/SPI/mcuconf.h
@@ -85,3 +85,8 @@
  * SPI driver system settings.
  */
 #define SPC5_SPI_USE_DSPI1                  TRUE
+#define SPC5_SPI_USE_DSPI2                  TRUE
+#define SPC5_SPI_DSPI1_DMA_PRIO             10
+#define SPC5_SPI_DSPI2_DMA_PRIO             10
+#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO         10
+#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO         10
-- 
cgit v1.2.3


From 72fee26a32402aea500c0a925021694f0bb18776 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Wed, 27 Mar 2013 11:54:40 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5507
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/SPI/main.c    | 14 ++++++++++++--
 testhal/SPC563Mxx/SPI/mcuconf.h |  1 +
 2 files changed, 13 insertions(+), 2 deletions(-)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/SPI/main.c b/testhal/SPC563Mxx/SPI/main.c
index cd36b2ad1..9ddb9761a 100644
--- a/testhal/SPC563Mxx/SPI/main.c
+++ b/testhal/SPC563Mxx/SPI/main.c
@@ -25,14 +25,24 @@
  * Maximum speed SPI configuration (21MHz, CPHA=0, CPOL=0, MSb first).
  */
 static const SPIConfig hs_spicfg = {
-  NULL
+  NULL,
+  0,
+  0,
+  0,                                                            /* MCR.     */
+  SPC5_CTAR_FMSZ(8) | SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV2,   /* CTAR0.   */
+  0                                                             /* PUSHR.   */
 };
 
 /*
  * Low speed SPI configuration (328.125kHz, CPHA=0, CPOL=0, MSb first).
  */
 static const SPIConfig ls_spicfg = {
-  NULL
+  NULL,
+  0,
+  0,
+  0,                                                            /* MCR.     */
+  SPC5_CTAR_FMSZ(8) | SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV256, /* CTAR0.   */
+  0                                                             /* PUSHR.   */
 };
 
 /*
diff --git a/testhal/SPC563Mxx/SPI/mcuconf.h b/testhal/SPC563Mxx/SPI/mcuconf.h
index 784a14d47..a7f5046e3 100644
--- a/testhal/SPC563Mxx/SPI/mcuconf.h
+++ b/testhal/SPC563Mxx/SPI/mcuconf.h
@@ -90,3 +90,4 @@
 #define SPC5_SPI_DSPI2_DMA_PRIO             10
 #define SPC5_SPI_DSPI1_DMA_IRQ_PRIO         10
 #define SPC5_SPI_DSPI2_DMA_IRQ_PRIO         10
+#define SPC5_SPI_DMA_ERROR_HOOK(spip)       chSysHalt()
-- 
cgit v1.2.3


From 0a69d7dd419e1d0925c02a7b621e72e44d8c25bb Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Wed, 27 Mar 2013 13:40:49 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5508
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/SPI/Makefile | 2 +-
 testhal/SPC563Mxx/SPI/main.c   | 4 ++++
 2 files changed, 5 insertions(+), 1 deletion(-)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/SPI/Makefile b/testhal/SPC563Mxx/SPI/Makefile
index 2cef7b38c..c52b0f44a 100644
--- a/testhal/SPC563Mxx/SPI/Makefile
+++ b/testhal/SPC563Mxx/SPI/Makefile
@@ -5,7 +5,7 @@
 
 # Compiler options here.
 ifeq ($(USE_OPT),)
-  USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
+  USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
 endif
 
 # C specific options here (added to USE_OPT).
diff --git a/testhal/SPC563Mxx/SPI/main.c b/testhal/SPC563Mxx/SPI/main.c
index 9ddb9761a..23ccd435a 100644
--- a/testhal/SPC563Mxx/SPI/main.c
+++ b/testhal/SPC563Mxx/SPI/main.c
@@ -119,6 +119,10 @@ int main(void) {
   for (i = 0; i < sizeof(txbuf); i++)
     txbuf[i] = (uint8_t)i;
 
+  spiStart(&SPID2, &hs_spicfg);       /* Setup transfer parameters.       */
+  spiExchange(&SPID2, 512,
+              txbuf, rxbuf);          /* Atomic transfer operations.      */
+
   /*
    * Starting the transmitter and receiver threads.
    */
-- 
cgit v1.2.3


From 03331a3fd71c5ea74485e482ea1b5cb7f35890bf Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Thu, 28 Mar 2013 12:09:21 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5513
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/SPI/main.c | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/SPI/main.c b/testhal/SPC563Mxx/SPI/main.c
index 23ccd435a..25c9a2ede 100644
--- a/testhal/SPC563Mxx/SPI/main.c
+++ b/testhal/SPC563Mxx/SPI/main.c
@@ -120,6 +120,8 @@ int main(void) {
     txbuf[i] = (uint8_t)i;
 
   spiStart(&SPID2, &hs_spicfg);       /* Setup transfer parameters.       */
+  spiExchange(&SPID2, 4,
+              txbuf, rxbuf);          /* Atomic transfer operations.      */
   spiExchange(&SPID2, 512,
               txbuf, rxbuf);          /* Atomic transfer operations.      */
 
-- 
cgit v1.2.3


From c450b544c1a35478fd07c093e82ba5cc000f078e Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Fri, 29 Mar 2013 10:18:38 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5514
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/SPI/main.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/SPI/main.c b/testhal/SPC563Mxx/SPI/main.c
index 25c9a2ede..b22eaba64 100644
--- a/testhal/SPC563Mxx/SPI/main.c
+++ b/testhal/SPC563Mxx/SPI/main.c
@@ -30,7 +30,7 @@ static const SPIConfig hs_spicfg = {
   0,
   0,                                                            /* MCR.     */
   SPC5_CTAR_FMSZ(8) | SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV2,   /* CTAR0.   */
-  0                                                             /* PUSHR.   */
+  SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(0)                           /* PUSHR.   */
 };
 
 /*
@@ -42,7 +42,7 @@ static const SPIConfig ls_spicfg = {
   0,
   0,                                                            /* MCR.     */
   SPC5_CTAR_FMSZ(8) | SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV256, /* CTAR0.   */
-  0                                                             /* PUSHR.   */
+  SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(0)                           /* PUSHR.   */
 };
 
 /*
-- 
cgit v1.2.3


From 853216256ad4cdacf5f94edb7d6b738c6be165a1 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 30 Mar 2013 10:32:37 +0000
Subject: Relicensing parts of the tree under the Apache 2.0 license.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5521 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 testhal/SPC563Mxx/ADC/adc_cfg.c | 24 ++++++++++--------------
 testhal/SPC563Mxx/ADC/adc_cfg.h | 24 ++++++++++--------------
 testhal/SPC563Mxx/ADC/chconf.h  | 24 ++++++++++--------------
 testhal/SPC563Mxx/ADC/halconf.h | 24 ++++++++++--------------
 testhal/SPC563Mxx/ADC/main.c    | 24 ++++++++++--------------
 testhal/SPC563Mxx/SPI/chconf.h  | 24 ++++++++++--------------
 testhal/SPC563Mxx/SPI/halconf.h | 24 ++++++++++--------------
 testhal/SPC563Mxx/SPI/main.c    | 24 ++++++++++--------------
 8 files changed, 80 insertions(+), 112 deletions(-)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/ADC/adc_cfg.c b/testhal/SPC563Mxx/ADC/adc_cfg.c
index f21f4ddce..7bb5bbbe6 100644
--- a/testhal/SPC563Mxx/ADC/adc_cfg.c
+++ b/testhal/SPC563Mxx/ADC/adc_cfg.c
@@ -1,21 +1,17 @@
 /*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
 
-    This file is part of ChibiOS/RT.
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
 
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
+        http://www.apache.org/licenses/LICENSE-2.0
 
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
 */
 
 #include "ch.h"
diff --git a/testhal/SPC563Mxx/ADC/adc_cfg.h b/testhal/SPC563Mxx/ADC/adc_cfg.h
index 6e362820f..cf0f411a3 100644
--- a/testhal/SPC563Mxx/ADC/adc_cfg.h
+++ b/testhal/SPC563Mxx/ADC/adc_cfg.h
@@ -1,21 +1,17 @@
 /*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
 
-    This file is part of ChibiOS/RT.
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
 
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
+        http://www.apache.org/licenses/LICENSE-2.0
 
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
 */
 
 #ifndef _ADC_CFG_H_
diff --git a/testhal/SPC563Mxx/ADC/chconf.h b/testhal/SPC563Mxx/ADC/chconf.h
index 5b1e9895f..dc956ef13 100644
--- a/testhal/SPC563Mxx/ADC/chconf.h
+++ b/testhal/SPC563Mxx/ADC/chconf.h
@@ -1,21 +1,17 @@
 /*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
 
-    This file is part of ChibiOS/RT.
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
 
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
+        http://www.apache.org/licenses/LICENSE-2.0
 
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
 */
 
 /**
diff --git a/testhal/SPC563Mxx/ADC/halconf.h b/testhal/SPC563Mxx/ADC/halconf.h
index 2721174a3..a719ec40a 100644
--- a/testhal/SPC563Mxx/ADC/halconf.h
+++ b/testhal/SPC563Mxx/ADC/halconf.h
@@ -1,21 +1,17 @@
 /*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
 
-    This file is part of ChibiOS/RT.
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
 
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
+        http://www.apache.org/licenses/LICENSE-2.0
 
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
 */
 
 /**
diff --git a/testhal/SPC563Mxx/ADC/main.c b/testhal/SPC563Mxx/ADC/main.c
index a8e1bea8d..6ec736309 100644
--- a/testhal/SPC563Mxx/ADC/main.c
+++ b/testhal/SPC563Mxx/ADC/main.c
@@ -1,21 +1,17 @@
 /*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
 
-    This file is part of ChibiOS/RT.
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
 
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
+        http://www.apache.org/licenses/LICENSE-2.0
 
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
 */
 
 #include "ch.h"
diff --git a/testhal/SPC563Mxx/SPI/chconf.h b/testhal/SPC563Mxx/SPI/chconf.h
index 5b1e9895f..dc956ef13 100644
--- a/testhal/SPC563Mxx/SPI/chconf.h
+++ b/testhal/SPC563Mxx/SPI/chconf.h
@@ -1,21 +1,17 @@
 /*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
 
-    This file is part of ChibiOS/RT.
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
 
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
+        http://www.apache.org/licenses/LICENSE-2.0
 
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
 */
 
 /**
diff --git a/testhal/SPC563Mxx/SPI/halconf.h b/testhal/SPC563Mxx/SPI/halconf.h
index 312d99320..fdc079aef 100644
--- a/testhal/SPC563Mxx/SPI/halconf.h
+++ b/testhal/SPC563Mxx/SPI/halconf.h
@@ -1,21 +1,17 @@
 /*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
 
-    This file is part of ChibiOS/RT.
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
 
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
+        http://www.apache.org/licenses/LICENSE-2.0
 
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
 */
 
 /**
diff --git a/testhal/SPC563Mxx/SPI/main.c b/testhal/SPC563Mxx/SPI/main.c
index b22eaba64..f50544b77 100644
--- a/testhal/SPC563Mxx/SPI/main.c
+++ b/testhal/SPC563Mxx/SPI/main.c
@@ -1,21 +1,17 @@
 /*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
 
-    This file is part of ChibiOS/RT.
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
 
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
+        http://www.apache.org/licenses/LICENSE-2.0
 
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
 */
 
 #include "ch.h"
-- 
cgit v1.2.3


From 8813e1654c45a24c07bb756b4565d96132075262 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 2 Apr 2013 09:02:40 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5527
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/ADC/Makefile | 5 +++++
 testhal/SPC563Mxx/SPI/Makefile | 5 +++++
 2 files changed, 10 insertions(+)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/ADC/Makefile b/testhal/SPC563Mxx/ADC/Makefile
index 932511e51..644898587 100644
--- a/testhal/SPC563Mxx/ADC/Makefile
+++ b/testhal/SPC563Mxx/ADC/Makefile
@@ -23,6 +23,11 @@ ifeq ($(USE_LINK_GC),)
   USE_LINK_GC = yes
 endif
 
+# Linker options here.
+ifeq ($(USE_LDOPT),)
+  USE_LDOPT = 
+endif
+
 # If enabled, this option allows to compile the application in VLE mode.
 ifeq ($(USE_VLE),)
   USE_VLE = yes
diff --git a/testhal/SPC563Mxx/SPI/Makefile b/testhal/SPC563Mxx/SPI/Makefile
index c52b0f44a..911a39668 100644
--- a/testhal/SPC563Mxx/SPI/Makefile
+++ b/testhal/SPC563Mxx/SPI/Makefile
@@ -23,6 +23,11 @@ ifeq ($(USE_LINK_GC),)
   USE_LINK_GC = yes
 endif
 
+# Linker options here.
+ifeq ($(USE_LDOPT),)
+  USE_LDOPT = 
+endif
+
 # If enabled, this option allows to compile the application in VLE mode.
 ifeq ($(USE_VLE),)
   USE_VLE = yes
-- 
cgit v1.2.3


From e78992cf5b5d56b9a5e263b471ea441d2cc4610c Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Thu, 11 Apr 2013 12:23:05 +0000
Subject: Relicensed some files.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5588 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 testhal/SPC563Mxx/ADC/mcuconf.h | 26 ++++++++++++++------------
 testhal/SPC563Mxx/SPI/mcuconf.h | 26 ++++++++++++++------------
 2 files changed, 28 insertions(+), 24 deletions(-)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/ADC/mcuconf.h b/testhal/SPC563Mxx/ADC/mcuconf.h
index b3f742baf..43a7662ed 100644
--- a/testhal/SPC563Mxx/ADC/mcuconf.h
+++ b/testhal/SPC563Mxx/ADC/mcuconf.h
@@ -1,16 +1,18 @@
 /*
- * Licensed under ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- *        http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software 
- * distributed under the License is distributed on an "AS IS" BASIS, 
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
+    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
 
 /*
  * SPC563Mxx drivers configuration.
diff --git a/testhal/SPC563Mxx/SPI/mcuconf.h b/testhal/SPC563Mxx/SPI/mcuconf.h
index a7f5046e3..61449eaac 100644
--- a/testhal/SPC563Mxx/SPI/mcuconf.h
+++ b/testhal/SPC563Mxx/SPI/mcuconf.h
@@ -1,16 +1,18 @@
 /*
- * Licensed under ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- *        http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software 
- * distributed under the License is distributed on an "AS IS" BASIS, 
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
+    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
 
 /*
  * SPC563Mxx drivers configuration.
-- 
cgit v1.2.3


From 460ae80f9260fbea7c6b4d94e99a40acfcc018bc Mon Sep 17 00:00:00 2001
From: pcirillo <pcirillo@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Wed, 15 May 2013 13:42:41 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5738
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/ICU-PWM/.cproject  |  51 ++++
 testhal/SPC563Mxx/ICU-PWM/.project   |  38 +++
 testhal/SPC563Mxx/ICU-PWM/Makefile   | 168 +++++++++++
 testhal/SPC563Mxx/ICU-PWM/chconf.h   | 536 +++++++++++++++++++++++++++++++++++
 testhal/SPC563Mxx/ICU-PWM/halconf.h  | 367 ++++++++++++++++++++++++
 testhal/SPC563Mxx/ICU-PWM/main.c     | 147 ++++++++++
 testhal/SPC563Mxx/ICU-PWM/mcuconf.h  | 100 +++++++
 testhal/SPC563Mxx/ICU-PWM/readme.txt |  27 ++
 8 files changed, 1434 insertions(+)
 create mode 100644 testhal/SPC563Mxx/ICU-PWM/.cproject
 create mode 100644 testhal/SPC563Mxx/ICU-PWM/.project
 create mode 100644 testhal/SPC563Mxx/ICU-PWM/Makefile
 create mode 100644 testhal/SPC563Mxx/ICU-PWM/chconf.h
 create mode 100644 testhal/SPC563Mxx/ICU-PWM/halconf.h
 create mode 100644 testhal/SPC563Mxx/ICU-PWM/main.c
 create mode 100644 testhal/SPC563Mxx/ICU-PWM/mcuconf.h
 create mode 100644 testhal/SPC563Mxx/ICU-PWM/readme.txt

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/ICU-PWM/.cproject b/testhal/SPC563Mxx/ICU-PWM/.cproject
new file mode 100644
index 000000000..a4ae17c6d
--- /dev/null
+++ b/testhal/SPC563Mxx/ICU-PWM/.cproject
@@ -0,0 +1,51 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="0.861226640">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="0.861226640" moduleId="org.eclipse.cdt.core.settings" name="Default">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.VCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactName="${ProjName}" buildProperties="" description="" id="0.861226640" name="Default" parent="org.eclipse.cdt.build.core.prefbase.cfg">
+					<folderInfo id="0.861226640." name="/" resourcePath="">
+						<toolChain id="org.eclipse.cdt.build.core.prefbase.toolchain.1002748249" name="No ToolChain" resourceTypeBasedDiscovery="false" superClass="org.eclipse.cdt.build.core.prefbase.toolchain">
+							<targetPlatform id="org.eclipse.cdt.build.core.prefbase.toolchain.1002748249.660222523" name=""/>
+							<builder autoBuildTarget="all" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="org.eclipse.cdt.build.core.settings.default.builder.662368067" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.settings.default.builder"/>
+							<tool id="org.eclipse.cdt.build.core.settings.holder.libs.1194892762" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/>
+							<tool id="org.eclipse.cdt.build.core.settings.holder.1089722463" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder">
+								<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1861343146" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+							</tool>
+							<tool id="org.eclipse.cdt.build.core.settings.holder.1644189815" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder">
+								<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1045400342" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+							</tool>
+							<tool id="org.eclipse.cdt.build.core.settings.holder.1188847444" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder">
+								<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.263638018" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="SPC563Mxx-SPI.null.1461388361" name="SPC563Mxx-SPI"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="0.861226640">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+</cproject>
diff --git a/testhal/SPC563Mxx/ICU-PWM/.project b/testhal/SPC563Mxx/ICU-PWM/.project
new file mode 100644
index 000000000..31139adbb
--- /dev/null
+++ b/testhal/SPC563Mxx/ICU-PWM/.project
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>SPC563Mxx-SPI</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>board</name>
+			<type>2</type>
+			<locationURI>CHIBIOS/boards/ST_EVB_SPC563M</locationURI>
+		</link>
+		<link>
+			<name>os</name>
+			<type>2</type>
+			<locationURI>CHIBIOS/os</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/testhal/SPC563Mxx/ICU-PWM/Makefile b/testhal/SPC563Mxx/ICU-PWM/Makefile
new file mode 100644
index 000000000..911a39668
--- /dev/null
+++ b/testhal/SPC563Mxx/ICU-PWM/Makefile
@@ -0,0 +1,168 @@
+##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+  USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+  USE_COPT = 
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+  USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data.
+ifeq ($(USE_LINK_GC),)
+  USE_LINK_GC = yes
+endif
+
+# Linker options here.
+ifeq ($(USE_LDOPT),)
+  USE_LDOPT = 
+endif
+
+# If enabled, this option allows to compile the application in VLE mode.
+ifeq ($(USE_VLE),)
+  USE_VLE = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+  USE_VERBOSE_COMPILE = no
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files
+CHIBIOS = ../../..
+include $(CHIBIOS)/boards/ST_EVB_SPC563M/board.mk
+include $(CHIBIOS)/os/hal/platforms/SPC563Mxx/platform.mk
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS)/os/ports/GCC/PPC/SPC563Mxx/port.mk
+include $(CHIBIOS)/os/kernel/kernel.mk
+#include $(CHIBIOS)/test/test.mk
+
+# Define linker script file here
+LDSCRIPT= $(PORTLD)/SPC563M64.ld
+
+# C sources here.
+CSRC = $(PORTSRC) \
+       $(KERNSRC) \
+       $(TESTSRC) \
+       $(HALSRC) \
+       $(PLATFORMSRC) \
+       $(BOARDSRC) \
+       $(CHIBIOS)/os/various/evtimer.c \
+       $(CHIBIOS)/os/various/shell.c \
+       $(CHIBIOS)/os/various/chprintf.c \
+       main.c
+
+# C++ sources here.
+CPPSRC =
+
+# List ASM source files here
+ASMSRC = $(PORTASM)
+
+INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
+         $(HALINC) $(PLATFORMINC) $(BOARDINC) \
+         $(CHIBIOS)/os/various
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+#MCU  = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames
+MCU  = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames
+
+#TRGT = powerpc-eabi-
+TRGT = ppc-vle-
+CC   = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+#       runtime support makes code size explode.
+LD   = $(TRGT)gcc
+#LD   = $(TRGT)g++
+CP   = $(TRGT)objcopy
+AS   = $(TRGT)gcc -x assembler-with-cpp
+OD   = $(TRGT)objdump
+HEX  = $(CP) -O ihex
+BIN  = $(CP) -O binary
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of default section
+#
+
+# List all default C defines here, like -D_DEBUG=1
+DDEFS =
+
+# List all default ASM defines here, like -D_DEBUG=1
+DADEFS =
+
+# List all default directories to look for include files here
+DINCDIR =
+
+# List the default directory to look for the libraries here
+DLIBDIR =
+
+# List all default libraries here
+DLIBS =
+
+#
+# End of default section
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+include $(CHIBIOS)/os/ports/GCC/PPC/rules.mk
diff --git a/testhal/SPC563Mxx/ICU-PWM/chconf.h b/testhal/SPC563Mxx/ICU-PWM/chconf.h
new file mode 100644
index 000000000..b4c46c7f6
--- /dev/null
+++ b/testhal/SPC563Mxx/ICU-PWM/chconf.h
@@ -0,0 +1,536 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+                                      ---
+
+    A special exception to the GPL can be applied should you wish to distribute
+    a combined work that includes ChibiOS/RT, without being obliged to provide
+    the source code for any proprietary components. See the file exception.txt
+    for full details of how and when the exception can be applied.
+*/
+
+/**
+ * @file    templates/chconf.h
+ * @brief   Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ *          contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ *          setting also defines the system tick time unit.
+ */
+#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
+#define CH_FREQUENCY                    1000
+#endif
+
+/**
+ * @brief   Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ *          threads before preemption occurs. Setting this value to zero
+ *          disables the preemption for threads with equal priority and the
+ *          round robin becomes cooperative. Note that higher priority
+ *          threads can still preempt, the kernel is always preemptive.
+ *
+ * @note    Disabling the round robin preemption makes the kernel more compact
+ *          and generally faster.
+ */
+#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
+#define CH_TIME_QUANTUM                 20
+#endif
+
+/**
+ * @brief   Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ *          then the whole available RAM is used. The core memory is made
+ *          available to the heap allocator and/or can be used directly through
+ *          the simplified core memory allocator.
+ *
+ * @note    In order to let the OS manage the whole RAM the linker script must
+ *          provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note    Requires @p CH_USE_MEMCORE.
+ */
+#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
+#define CH_MEMCORE_SIZE                 0
+#endif
+
+/**
+ * @brief   Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ *          does not spawn the idle thread automatically. The application has
+ *          then the responsibility to do one of the following:
+ *          - Spawn a custom idle thread at priority @p IDLEPRIO.
+ *          - Change the main() thread priority to @p IDLEPRIO then enter
+ *            an endless loop. In this scenario the @p main() thread acts as
+ *            the idle thread.
+ *          .
+ * @note    Unless an idle thread is spawned the @p main() thread must not
+ *          enter a sleep state.
+ */
+#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
+#define CH_NO_IDLE_THREAD               FALSE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ *          is used when two possible implementations exist.
+ *
+ * @note    This is not related to the compiler optimization options.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
+#define CH_OPTIMIZE_SPEED               TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
+#define CH_USE_REGISTRY                 TRUE
+#endif
+
+/**
+ * @brief   Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ *          the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
+#define CH_USE_WAITEXIT                 TRUE
+#endif
+
+/**
+ * @brief   Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES               TRUE
+#endif
+
+/**
+ * @brief   Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ *          priority rather than in FIFO order.
+ *
+ * @note    The default is @p FALSE. Enable this if you have special requirements.
+ * @note    Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES_PRIORITY      FALSE
+#endif
+
+/**
+ * @brief   Atomic semaphore API.
+ * @details If enabled then the semaphores the @p chSemSignalWait() API
+ *          is included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
+#define CH_USE_SEMSW                    TRUE
+#endif
+
+/**
+ * @brief   Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
+#define CH_USE_MUTEXES                  TRUE
+#endif
+
+/**
+ * @brief   Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_MUTEXES.
+ */
+#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS                 TRUE
+#endif
+
+/**
+ * @brief   Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ *          specification are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_CONDVARS.
+ */
+#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS_TIMEOUT         TRUE
+#endif
+
+/**
+ * @brief   Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS                   TRUE
+#endif
+
+/**
+ * @brief   Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ *          are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_EVENTS.
+ */
+#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS_TIMEOUT           TRUE
+#endif
+
+/**
+ * @brief   Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES                 TRUE
+#endif
+
+/**
+ * @brief   Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ *          FIFO order.
+ *
+ * @note    The default is @p FALSE. Enable this if you have special requirements.
+ * @note    Requires @p CH_USE_MESSAGES.
+ */
+#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES_PRIORITY        FALSE
+#endif
+
+/**
+ * @brief   Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ *          included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
+#define CH_USE_MAILBOXES                TRUE
+#endif
+
+/**
+ * @brief   I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
+#define CH_USE_QUEUES                   FALSE
+#endif
+
+/**
+ * @brief   Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
+#define CH_USE_MEMCORE                  TRUE
+#endif
+
+/**
+ * @brief   Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
+ *          @p CH_USE_SEMAPHORES.
+ * @note    Mutexes are recommended.
+ */
+#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_HEAP                     TRUE
+#endif
+
+/**
+ * @brief   C-runtime allocator.
+ * @details If enabled the the heap allocator APIs just wrap the C-runtime
+ *          @p malloc() and @p free() functions.
+ *
+ * @note    The default is @p FALSE.
+ * @note    Requires @p CH_USE_HEAP.
+ * @note    The C-runtime may or may not require @p CH_USE_MEMCORE, see the
+ *          appropriate documentation.
+ */
+#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_MALLOC_HEAP              FALSE
+#endif
+
+/**
+ * @brief   Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
+#define CH_USE_MEMPOOLS                 TRUE
+#endif
+
+/**
+ * @brief   Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_WAITEXIT.
+ * @note    Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
+ */
+#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
+#define CH_USE_DYNAMIC                  TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ *          at runtime.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_SYSTEM_STATE_CHECK       TRUE
+#endif
+
+/**
+ * @brief   Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ *          parameters are activated.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_CHECKS            TRUE
+#endif
+
+/**
+ * @brief   Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ *          activated. This includes consistency checks inside the kernel,
+ *          runtime anomalies and port-defined checks.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_ASSERTS           TRUE
+#endif
+
+/**
+ * @brief   Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ *          activated.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_TRACE             TRUE
+#endif
+
+/**
+ * @brief   Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note    The default is @p FALSE.
+ * @note    The stack check is performed in a architecture/port dependent way.
+ *          It may not be implemented or some ports.
+ * @note    The default failure mode is to halt the system with the global
+ *          @p panic_msg variable set to @p NULL.
+ */
+#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_STACK_CHECK       FALSE
+#endif
+
+/**
+ * @brief   Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ *          value when a thread is created. This can be useful for the
+ *          runtime measurement of the used stack.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
+#define CH_DBG_FILL_THREADS             TRUE
+#endif
+
+/**
+ * @brief   Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p Thread structure that
+ *          counts the system ticks occurred while executing the thread.
+ *
+ * @note    The default is @p TRUE.
+ * @note    This debug option is defaulted to TRUE because it is required by
+ *          some test cases into the test suite.
+ */
+#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
+#define CH_DBG_THREADS_PROFILING        TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Threads descriptor structure extension.
+ * @details User fields added to the end of the @p Thread structure.
+ */
+#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
+#define THREAD_EXT_FIELDS                                                   \
+
+#endif
+
+/**
+ * @brief   Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note    It is invoked from within @p chThdInit() and implicitly from all
+ *          the threads creation APIs.
+ */
+#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
+#define THREAD_EXT_INIT_HOOK(tp) {                                          \
+}
+#endif
+
+/**
+ * @brief   Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note    It is inserted into lock zone.
+ * @note    It is also invoked when the threads simply return in order to
+ *          terminate.
+ */
+#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
+#define THREAD_EXT_EXIT_HOOK(tp) {                                          \
+}
+#endif
+
+/**
+ * @brief   Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
+#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) {                              \
+}
+#endif
+
+/**
+ * @brief   Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
+#define IDLE_LOOP_HOOK() {                                                  \
+}
+#endif
+
+/**
+ * @brief   System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ *          after processing the virtual timers queue.
+ */
+#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
+#define SYSTEM_TICK_EVENT_HOOK() {                                          \
+}
+#endif
+
+/**
+ * @brief   System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ *          the system is halted.
+ */
+#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
+#define SYSTEM_HALT_HOOK() {                                                \
+}
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h).    */
+/*===========================================================================*/
+
+#endif  /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/SPC563Mxx/ICU-PWM/halconf.h b/testhal/SPC563Mxx/ICU-PWM/halconf.h
new file mode 100644
index 000000000..24462dafd
--- /dev/null
+++ b/testhal/SPC563Mxx/ICU-PWM/halconf.h
@@ -0,0 +1,367 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    templates/halconf.h
+ * @brief   HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ *          various device drivers from your application. You may also use
+ *          this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @name    Drivers enable switches
+ */
+/**
+ * @brief   Enables the TM subsystem.
+ */
+#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
+#define HAL_USE_TM                  FALSE
+#endif
+
+/**
+ * @brief   Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL                 TRUE
+#endif
+
+/**
+ * @brief   Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN                 FALSE
+#endif
+
+/**
+ * @brief   Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT                 FALSE
+#endif
+
+/**
+ * @brief   Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT                 FALSE
+#endif
+
+/**
+ * @brief   Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C                 FALSE
+#endif
+
+/**
+ * @brief   Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU                 TRUE
+#endif
+
+/**
+ * @brief   Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI             FALSE
+#endif
+
+/**
+ * @brief   Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM                 TRUE
+#endif
+
+/**
+ * @brief   Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL              TRUE
+#endif
+
+/**
+ * @brief   Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB          FALSE
+#endif
+
+/**
+ * @brief   Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI                 FALSE
+#endif
+
+/**
+ * @brief   Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART                FALSE
+#endif
+
+/**
+ * @brief   Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB                 FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name ADC driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables synchronous APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT                TRUE
+#endif
+
+/**
+ * @brief   Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION    FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name CAN driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE          TRUE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name I2C driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION    FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name MAC driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY           FALSE
+#endif
+
+/**
+ * @brief   Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS              TRUE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name MMC_SPI driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ *          routines releasing some extra CPU time for the threads with
+ *          lower priority, this may slow down the driver a bit however.
+ *          This option is recommended also if the SPI driver does not
+ *          use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING            TRUE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name SDC driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Number of initialization attempts before rejecting the card.
+ * @note    Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY              1
+#endif
+
+/**
+ * @brief   Include support for MMC cards.
+ * @note    MMC support is not yet implemented so this option must be kept
+ *          at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT             FALSE
+#endif
+
+/**
+ * @brief   Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ *          routines releasing some extra CPU time for the threads with
+ *          lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING            TRUE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name SERIAL driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ *          default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE      38400
+#endif
+
+/**
+ * @brief   Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ *          buffers depending on the requirements of your application.
+ * @note    The default is 64 bytes for both the transmission and receive
+ *          buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE         16
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name SERIAL_USB driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ *          the USB data endpoint maximum packet size.
+ * @note    The default is 64 bytes for both the transmission and receive
+ *          buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE     64
+#endif
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name SPI driver related setting
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables synchronous APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT                TRUE
+#endif
+
+/**
+ * @brief   Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION    FALSE
+#endif
+/** @} */
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/SPC563Mxx/ICU-PWM/main.c b/testhal/SPC563Mxx/ICU-PWM/main.c
new file mode 100644
index 000000000..60c451373
--- /dev/null
+++ b/testhal/SPC563Mxx/ICU-PWM/main.c
@@ -0,0 +1,147 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+static void pwmpcb(PWMDriver *pwmp) {
+
+  (void)pwmp;
+  palClearPad(PORT11, P11_LED1);
+}
+
+static void pwmc1cb(PWMDriver *pwmp) {
+
+  (void)pwmp;
+  palSetPad(PORT11, P11_LED1);
+}
+
+static PWMConfig pwmcfg = {
+  80000,                                    /* 80kHz PWM clock frequency.*/
+  20000,                                    /* Initial PWM period 0.25s.*/
+  pwmpcb,
+  {
+   {PWM_OUTPUT_ACTIVE_HIGH, pwmc1cb}
+  },
+  PWM_ALIGN_EDGE
+};
+
+icucnt_t last_width, last_period;
+icucnt_t last_width2, last_period2;
+
+static void icuwidthcb(ICUDriver *icup) {
+
+  palSetPad(PORT11, P11_LED2);
+  last_width = icuGetWidth(icup);
+}
+
+static void icuperiodcb(ICUDriver *icup) {
+
+  palClearPad(PORT11, P11_LED2);
+  last_period = icuGetPeriod(icup);
+}
+
+static ICUConfig icucfg = {
+  ICU_INPUT_ACTIVE_HIGH,
+  80000,                                    /* 80kHz ICU clock frequency.*/
+  icuwidthcb,
+  icuperiodcb,
+  NULL
+};
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+  /*
+   * System initializations.
+   * - HAL initialization, this also initializes the configured device drivers
+   *   and performs the board-specific initializations.
+   * - Kernel initialization, the main() function becomes a thread and the
+   *   RTOS is active.
+   */
+  halInit();
+  chSysInit();
+
+  /*
+   * Initializes the PWM driver 8 and ICU driver 1.
+   * PIN80 is the PWM output.
+   * PIN63 is the ICU input.
+   * The two pins have to be externally connected together.
+   */
+
+  /* Sets PIN63 alternative function.*/
+  SIU.PCR[179].R = 0b0000010100001100;
+
+  /* Sets PIN80 alternative function.*/
+  SIU.PCR[202].R = 0b0000011000001100;
+
+  icuStart(&ICUD1, &icucfg);
+  icuEnable(&ICUD1);
+  pwmStart(&PWMD8, &pwmcfg);
+
+  chThdSleepMilliseconds(2000);
+
+  /*
+   * Starts the PWM channel 0 using 75% duty cycle.
+   */
+  pwmEnableChannel(&PWMD8, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD8, 7500));
+  chThdSleepMilliseconds(5000);
+
+  /*
+   * Changes the PWM channel 0 to 50% duty cycle.
+   */
+  pwmEnableChannel(&PWMD8, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD8, 5000));
+  chThdSleepMilliseconds(5000);
+
+  /*
+   * Changes the PWM channel 0 to 25% duty cycle.
+   */
+  pwmEnableChannel(&PWMD8, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD8, 2500));
+  chThdSleepMilliseconds(5000);
+
+  /*
+   * Changes PWM period and the PWM channel 0 to 50% duty cycle.
+   */
+  pwmChangePeriod(&PWMD8, 25000);
+  pwmEnableChannel(&PWMD8, 0, PWM_PERCENTAGE_TO_WIDTH(&PWMD8, 5000));
+  chThdSleepMilliseconds(5000);
+
+  /*
+   * Disables PWM channel 0 and stops the drivers.
+   */
+  pwmDisableChannel(&PWMD8, 0);
+  pwmStop(&PWMD8);
+
+  /*
+   * Disables and stops the ICU drivers.
+   */
+
+  icuDisable(&ICUD1);
+  icuStop(&ICUD1);
+
+  palClearPad(PORT11, P11_LED3);
+  palClearPad(PORT11, P11_LED4);
+
+  /*
+   * Normal main() thread activity, in this demo it does nothing.
+   */
+  while (TRUE) {
+    chThdSleepMilliseconds(500);
+  }
+  return 0;
+}
diff --git a/testhal/SPC563Mxx/ICU-PWM/mcuconf.h b/testhal/SPC563Mxx/ICU-PWM/mcuconf.h
new file mode 100644
index 000000000..be3ee85cf
--- /dev/null
+++ b/testhal/SPC563Mxx/ICU-PWM/mcuconf.h
@@ -0,0 +1,100 @@
+/*
+    SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * SPC563Mxx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 1...15       Lowest...Highest.
+ */
+
+#define SPC563Mxx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define SPC5_NO_INIT                        FALSE
+#define SPC5_CLK_BYPASS                     FALSE
+#define SPC5_ALLOW_OVERCLOCK                FALSE
+#define SPC5_CLK_PREDIV_VALUE               2
+#define SPC5_CLK_MFD_VALUE                  80
+#define SPC5_CLK_RFD                        SPC5_RFD_DIV4
+#define SPC5_FLASH_BIUCR                    (BIUCR_BANK1_TOO |              \
+                                             BIUCR_MASTER4_PREFETCH |       \
+                                             BIUCR_MASTER0_PREFETCH |       \
+                                             BIUCR_DPFEN |                  \
+                                             BIUCR_IPFEN |                  \
+                                             BIUCR_PFLIM_ON_MISS |          \
+                                             BIUCR_BFEN)
+
+/*
+ * ADC driver settings.
+ */
+#define SPC5_ADC_USE_ADC0_Q0                FALSE
+#define SPC5_ADC_USE_ADC0_Q1                FALSE
+#define SPC5_ADC_USE_ADC0_Q2                FALSE
+#define SPC5_ADC_USE_ADC1_Q3                FALSE
+#define SPC5_ADC_USE_ADC1_Q4                FALSE
+#define SPC5_ADC_USE_ADC1_Q5                FALSE
+#define SPC5_ADC_FIFO0_DMA_PRIO             12
+#define SPC5_ADC_FIFO1_DMA_PRIO             12
+#define SPC5_ADC_FIFO2_DMA_PRIO             12
+#define SPC5_ADC_FIFO3_DMA_PRIO             12
+#define SPC5_ADC_FIFO4_DMA_PRIO             12
+#define SPC5_ADC_FIFO5_DMA_PRIO             12
+#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO         12
+#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO         12
+#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO         12
+#define SPC5_ADC_FIFO3_DMA_IRQ_PRIO         12
+#define SPC5_ADC_FIFO4_DMA_IRQ_PRIO         12
+#define SPC5_ADC_FIFO5_DMA_IRQ_PRIO         12
+#define SPC5_ADC_CR_CLK_PS                  ADC_CR_CLK_PS(5)
+#define SPC5_ADC_PUDCR                      {ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE,ADC_PUDCR_NONE}
+
+/*
+ * SERIAL driver system settings.
+ */
+#define SPC5_USE_ESCIA                      TRUE
+#define SPC5_USE_ESCIB                      FALSE
+#define SPC5_ESCIA_PRIORITY                 8
+#define SPC5_ESCIB_PRIORITY                 8
+
+/*
+ * ICU - PWM driver system settings.
+ */
+#define SPC5_ICU_USE_EMIOS_CH0              TRUE
+#define SPC5_ICU_USE_EMIOS_CH1              TRUE
+#define SPC5_ICU_USE_EMIOS_CH2              TRUE
+#define SPC5_ICU_USE_EMIOS_CH3              TRUE
+#define SPC5_ICU_USE_EMIOS_CH4              TRUE
+#define SPC5_ICU_USE_EMIOS_CH5              TRUE
+#define SPC5_ICU_USE_EMIOS_CH6              TRUE
+#define SPC5_ICU_USE_EMIOS_CH8              TRUE
+
+#define SPC5_PWM_USE_EMIOS_CH9              TRUE
+#define SPC5_PWM_USE_EMIOS_CH10             TRUE
+#define SPC5_PWM_USE_EMIOS_CH11             TRUE
+#define SPC5_PWM_USE_EMIOS_CH12             TRUE
+#define SPC5_PWM_USE_EMIOS_CH13             TRUE
+#define SPC5_PWM_USE_EMIOS_CH14             TRUE
+#define SPC5_PWM_USE_EMIOS_CH15             TRUE
+#define SPC5_PWM_USE_EMIOS_CH23             TRUE
+
+#define SPC5_EMIOS_GLOBAL_PRESCALER         200
diff --git a/testhal/SPC563Mxx/ICU-PWM/readme.txt b/testhal/SPC563Mxx/ICU-PWM/readme.txt
new file mode 100644
index 000000000..f56bcf55b
--- /dev/null
+++ b/testhal/SPC563Mxx/ICU-PWM/readme.txt
@@ -0,0 +1,27 @@
+*****************************************************************************
+** ChibiOS/RT HAL - SPI driver demo for SPC563Mxx.                         **
+*****************************************************************************
+
+** TARGET **
+
+The demo runs on an STMicroelectronics SPC563Mxx microcontroller installed on 
+XPC56xx EVB Motherboard.
+
+** The Demo **
+
+The application demonstrates the use of the SPC563Mxx ICU and PWM drivers.
+
+** Board Setup **
+
+Connect PIN63 and PIN80 together.
+
+** Build Procedure **
+
+The demo has been tested using HighTec compiler.
+
+** Notes **
+
+Some files used by the demo are not part of ChibiOS/RT but are copyright of
+ST Microelectronics and are licensed under a different license.
+
+                             http://www.st.com
-- 
cgit v1.2.3


From ec80f9b8a4b1e82fdc7896c70064c39374522cd1 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Thu, 23 May 2013 12:19:13 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5749
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/SPI/main.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/SPI/main.c b/testhal/SPC563Mxx/SPI/main.c
index f50544b77..d58cb08c0 100644
--- a/testhal/SPC563Mxx/SPI/main.c
+++ b/testhal/SPC563Mxx/SPI/main.c
@@ -115,12 +115,13 @@ int main(void) {
   for (i = 0; i < sizeof(txbuf); i++)
     txbuf[i] = (uint8_t)i;
 
-  spiStart(&SPID2, &hs_spicfg);       /* Setup transfer parameters.       */
-  spiExchange(&SPID2, 4,
-              txbuf, rxbuf);          /* Atomic transfer operations.      */
-  spiExchange(&SPID2, 512,
-              txbuf, rxbuf);          /* Atomic transfer operations.      */
-
+  spiStart(&SPID2, &hs_spicfg);
+  spiExchange(&SPID2, 4, txbuf, rxbuf);
+  spiExchange(&SPID2, 4, txbuf, rxbuf);
+  spiExchange(&SPID2, 4, txbuf, rxbuf);
+  spiExchange(&SPID2, 4, txbuf, rxbuf);
+  spiExchange(&SPID2, 512, txbuf, rxbuf);
+#if 0
   /*
    * Starting the transmitter and receiver threads.
    */
@@ -128,7 +129,7 @@ int main(void) {
                     NORMALPRIO + 1, spi_thread_1, NULL);
   chThdCreateStatic(spi_thread_2_wa, sizeof(spi_thread_2_wa),
                     NORMALPRIO + 1, spi_thread_2, NULL);
-
+#endif
   /*
    * Normal main() thread activity, in this demo it does nothing.
    */
-- 
cgit v1.2.3


From 141f14c79a836c841b70a9fbf90016db9d947cb9 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Thu, 23 May 2013 15:20:39 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5750
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/SPI/main.c | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/SPI/main.c b/testhal/SPC563Mxx/SPI/main.c
index d58cb08c0..8a21eb918 100644
--- a/testhal/SPC563Mxx/SPI/main.c
+++ b/testhal/SPC563Mxx/SPI/main.c
@@ -116,6 +116,11 @@ int main(void) {
     txbuf[i] = (uint8_t)i;
 
   spiStart(&SPID2, &hs_spicfg);
+  SIU.PCR[102].R = PAL_MODE_OUTPUT_ALTERNATE(1);    /* SCK    */
+  SIU.PCR[103].R = PAL_MODE_OUTPUT_ALTERNATE(1);    /* SIN    */
+  SIU.PCR[104].R = PAL_MODE_OUTPUT_ALTERNATE(1);    /* SOUT   */
+  SIU.PCR[105].R = PAL_MODE_OUTPUT_ALTERNATE(1);    /* PCS[0] */
+
   spiExchange(&SPID2, 4, txbuf, rxbuf);
   spiExchange(&SPID2, 4, txbuf, rxbuf);
   spiExchange(&SPID2, 4, txbuf, rxbuf);
-- 
cgit v1.2.3


From c16062e326d35c438abf719e2371a3a55f868b71 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Mon, 27 May 2013 08:51:18 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5764
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/SPI/main.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/SPI/main.c b/testhal/SPC563Mxx/SPI/main.c
index 8a21eb918..77b6369d0 100644
--- a/testhal/SPC563Mxx/SPI/main.c
+++ b/testhal/SPC563Mxx/SPI/main.c
@@ -24,8 +24,8 @@ static const SPIConfig hs_spicfg = {
   NULL,
   0,
   0,
-  0,                                                            /* MCR.     */
-  SPC5_CTAR_FMSZ(8) | SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV2,   /* CTAR0.   */
+  SPC5_MCR_PCSIS0,                                              /* MCR.     */
+  SPC5_CTAR_FMSZ(8) | SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV128, /* CTAR0.   */
   SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(0)                           /* PUSHR.   */
 };
 
-- 
cgit v1.2.3


From 036f60f497d109038765567bad5b9dbe503e8326 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 28 May 2013 09:51:52 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5765
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/SPI/main.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/SPI/main.c b/testhal/SPC563Mxx/SPI/main.c
index 77b6369d0..b0cbe773b 100644
--- a/testhal/SPC563Mxx/SPI/main.c
+++ b/testhal/SPC563Mxx/SPI/main.c
@@ -25,7 +25,8 @@ static const SPIConfig hs_spicfg = {
   0,
   0,
   SPC5_MCR_PCSIS0,                                              /* MCR.     */
-  SPC5_CTAR_FMSZ(8) | SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV128, /* CTAR0.   */
+  SPC5_CTAR_CSSCK_DIV64 | SPC5_CTAR_ASC_DIV64 | SPC5_CTAR_FMSZ(8) |
+  SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV128,                     /* CTAR0.   */
   SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(0)                           /* PUSHR.   */
 };
 
@@ -125,6 +126,7 @@ int main(void) {
   spiExchange(&SPID2, 4, txbuf, rxbuf);
   spiExchange(&SPID2, 4, txbuf, rxbuf);
   spiExchange(&SPID2, 4, txbuf, rxbuf);
+  spiExchange(&SPID2, 32, txbuf, rxbuf);
   spiExchange(&SPID2, 512, txbuf, rxbuf);
 #if 0
   /*
-- 
cgit v1.2.3


From e9edd478029209ba06f09a380590e4ae3e844985 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 28 May 2013 14:12:55 +0000
Subject: SPC5xx DSPI driver working on SPC563Mxx.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5766 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 testhal/SPC563Mxx/SPI/main.c | 41 ++++++++++++++++++++++++++++-------------
 1 file changed, 28 insertions(+), 13 deletions(-)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/SPI/main.c b/testhal/SPC563Mxx/SPI/main.c
index b0cbe773b..df186e7e7 100644
--- a/testhal/SPC563Mxx/SPI/main.c
+++ b/testhal/SPC563Mxx/SPI/main.c
@@ -18,15 +18,15 @@
 #include "hal.h"
 
 /*
- * Maximum speed SPI configuration (21MHz, CPHA=0, CPOL=0, MSb first).
+ * Maximum speed SPI configuration.
  */
 static const SPIConfig hs_spicfg = {
   NULL,
   0,
   0,
   SPC5_MCR_PCSIS0,                                              /* MCR.     */
-  SPC5_CTAR_CSSCK_DIV64 | SPC5_CTAR_ASC_DIV64 | SPC5_CTAR_FMSZ(8) |
-  SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV128,                     /* CTAR0.   */
+  SPC5_CTAR_CSSCK_DIV2 | SPC5_CTAR_ASC_DIV2 | SPC5_CTAR_FMSZ(8) |
+  SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV2,                     /* CTAR0.   */
   SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(0)                           /* PUSHR.   */
 };
 
@@ -37,8 +37,9 @@ static const SPIConfig ls_spicfg = {
   NULL,
   0,
   0,
-  0,                                                            /* MCR.     */
-  SPC5_CTAR_FMSZ(8) | SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV256, /* CTAR0.   */
+  SPC5_MCR_PCSIS0,                                              /* MCR.     */
+  SPC5_CTAR_CSSCK_DIV64 | SPC5_CTAR_ASC_DIV64 | SPC5_CTAR_FMSZ(8) |
+  SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV256,                     /* CTAR0.   */
   SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(0)                           /* PUSHR.   */
 };
 
@@ -58,7 +59,7 @@ static msg_t spi_thread_1(void *p) {
   chRegSetThreadName("SPI thread 1");
   while (TRUE) {
     spiAcquireBus(&SPID2);              /* Acquire ownership of the bus.    */
-    palSetPad(PORT11, P11_LED1);        /* LED ON.                          */
+    palClearPad(PORT11, P11_LED1);      /* LED ON.                          */
     spiStart(&SPID2, &hs_spicfg);       /* Setup transfer parameters.       */
     spiSelect(&SPID2);                  /* Slave Select assertion.          */
     spiExchange(&SPID2, 512,
@@ -79,7 +80,7 @@ static msg_t spi_thread_2(void *p) {
   chRegSetThreadName("SPI thread 2");
   while (TRUE) {
     spiAcquireBus(&SPID2);              /* Acquire ownership of the bus.    */
-    palClearPad(PORT11, P11_LED1);      /* LED OFF.                         */
+    palSetPad(PORT11, P11_LED1);        /* LED OFF.                         */
     spiStart(&SPID2, &ls_spicfg);       /* Setup transfer parameters.       */
     spiSelect(&SPID2);                  /* Slave Select assertion.          */
     spiExchange(&SPID2, 512,
@@ -116,19 +117,33 @@ int main(void) {
   for (i = 0; i < sizeof(txbuf); i++)
     txbuf[i] = (uint8_t)i;
 
-  spiStart(&SPID2, &hs_spicfg);
+  /* Starting driver for test.*/
+  spiStart(&SPID2, &ls_spicfg);
   SIU.PCR[102].R = PAL_MODE_OUTPUT_ALTERNATE(1);    /* SCK    */
   SIU.PCR[103].R = PAL_MODE_OUTPUT_ALTERNATE(1);    /* SIN    */
   SIU.PCR[104].R = PAL_MODE_OUTPUT_ALTERNATE(1);    /* SOUT   */
   SIU.PCR[105].R = PAL_MODE_OUTPUT_ALTERNATE(1);    /* PCS[0] */
 
-  spiExchange(&SPID2, 4, txbuf, rxbuf);
-  spiExchange(&SPID2, 4, txbuf, rxbuf);
-  spiExchange(&SPID2, 4, txbuf, rxbuf);
+  /* Testing sending and receiving at the same time.*/
   spiExchange(&SPID2, 4, txbuf, rxbuf);
   spiExchange(&SPID2, 32, txbuf, rxbuf);
   spiExchange(&SPID2, 512, txbuf, rxbuf);
-#if 0
+
+  /* Testing clock pulses without data buffering.*/
+  spiIgnore(&SPID2, 4);
+  spiIgnore(&SPID2, 32);
+
+  /* Testing sending data ignoring incoming data.*/
+  spiSend(&SPID2, 4, txbuf);
+  spiSend(&SPID2, 32, txbuf);
+
+  /* Testing receiving data while sending idle bits (high level).*/
+  spiReceive(&SPID2, 4, rxbuf);
+  spiReceive(&SPID2, 32, rxbuf);
+
+  /* Testing stop procedure.*/
+  spiStop(&SPID2);
+
   /*
    * Starting the transmitter and receiver threads.
    */
@@ -136,7 +151,7 @@ int main(void) {
                     NORMALPRIO + 1, spi_thread_1, NULL);
   chThdCreateStatic(spi_thread_2_wa, sizeof(spi_thread_2_wa),
                     NORMALPRIO + 1, spi_thread_2, NULL);
-#endif
+
   /*
    * Normal main() thread activity, in this demo it does nothing.
    */
-- 
cgit v1.2.3


From 37034c5ecf6ac44a7f65ec4e201c3ad551030495 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Wed, 29 May 2013 10:26:01 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5770
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/SPI/mcuconf.h | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/SPI/mcuconf.h b/testhal/SPC563Mxx/SPI/mcuconf.h
index 61449eaac..1b373d2cc 100644
--- a/testhal/SPC563Mxx/SPI/mcuconf.h
+++ b/testhal/SPC563Mxx/SPI/mcuconf.h
@@ -92,4 +92,6 @@
 #define SPC5_SPI_DSPI2_DMA_PRIO             10
 #define SPC5_SPI_DSPI1_DMA_IRQ_PRIO         10
 #define SPC5_SPI_DSPI2_DMA_IRQ_PRIO         10
+#define SPC5_SPI_DSPI1_IRQ_PRIO             10
+#define SPC5_SPI_DSPI2_IRQ_PRIO             10
 #define SPC5_SPI_DMA_ERROR_HOOK(spip)       chSysHalt()
-- 
cgit v1.2.3


From ee5f4545778c7712d0fcc0dfbd8c5b11a89d1027 Mon Sep 17 00:00:00 2001
From: pcirillo <pcirillo@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 1 Jun 2013 08:46:31 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5783
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/ICU-PWM/halconf.h |  2 +-
 testhal/SPC563Mxx/ICU-PWM/main.c    | 53 +++++++++++++++++--------------------
 2 files changed, 25 insertions(+), 30 deletions(-)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/ICU-PWM/halconf.h b/testhal/SPC563Mxx/ICU-PWM/halconf.h
index 24462dafd..3a6d72910 100644
--- a/testhal/SPC563Mxx/ICU-PWM/halconf.h
+++ b/testhal/SPC563Mxx/ICU-PWM/halconf.h
@@ -128,7 +128,7 @@
  * @brief   Enables the SERIAL subsystem.
  */
 #if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
-#define HAL_USE_SERIAL              TRUE
+#define HAL_USE_SERIAL              FALSE
 #endif
 
 /**
diff --git a/testhal/SPC563Mxx/ICU-PWM/main.c b/testhal/SPC563Mxx/ICU-PWM/main.c
index 60c451373..48e02d3f6 100644
--- a/testhal/SPC563Mxx/ICU-PWM/main.c
+++ b/testhal/SPC563Mxx/ICU-PWM/main.c
@@ -1,21 +1,21 @@
 /*
-    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
+ * Licensed under ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ *        http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
 
-#include "ch.h"
-#include "hal.h"
+/* Inclusion of the main header files of all the imported components in the
+   order specified in the application wizard. The file is generated
+   automatically.*/
+#include "components.h"
 
 static void pwmpcb(PWMDriver *pwmp) {
 
@@ -30,8 +30,8 @@ static void pwmc1cb(PWMDriver *pwmp) {
 }
 
 static PWMConfig pwmcfg = {
-  80000,                                    /* 80kHz PWM clock frequency.*/
-  20000,                                    /* Initial PWM period 0.25s.*/
+  100000,                                   /* 100kHz PWM clock frequency.*/
+  20000,                                    /* Initial PWM period 0.2s.*/
   pwmpcb,
   {
    {PWM_OUTPUT_ACTIVE_HIGH, pwmc1cb}
@@ -40,7 +40,6 @@ static PWMConfig pwmcfg = {
 };
 
 icucnt_t last_width, last_period;
-icucnt_t last_width2, last_period2;
 
 static void icuwidthcb(ICUDriver *icup) {
 
@@ -56,7 +55,7 @@ static void icuperiodcb(ICUDriver *icup) {
 
 static ICUConfig icucfg = {
   ICU_INPUT_ACTIVE_HIGH,
-  80000,                                    /* 80kHz ICU clock frequency.*/
+  100000,                                   /* 100kHz ICU clock frequency.*/
   icuwidthcb,
   icuperiodcb,
   NULL
@@ -67,15 +66,11 @@ static ICUConfig icucfg = {
  */
 int main(void) {
 
-  /*
-   * System initializations.
-   * - HAL initialization, this also initializes the configured device drivers
-   *   and performs the board-specific initializations.
-   * - Kernel initialization, the main() function becomes a thread and the
-   *   RTOS is active.
-   */
-  halInit();
-  chSysInit();
+  /* Initialization of all the imported components in the order specified in
+	 the application wizard. The function is generated automatically.*/
+  componentsInit();
+
+  palClearPad(PORT11, P11_LED4);
 
   /*
    * Initializes the PWM driver 8 and ICU driver 1.
-- 
cgit v1.2.3


From bea1f59f1407b52fd68727c665723105dbb8f715 Mon Sep 17 00:00:00 2001
From: pcirillo <pcirillo@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 1 Jun 2013 14:36:29 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5789
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/ICU-PWM/main.c | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/ICU-PWM/main.c b/testhal/SPC563Mxx/ICU-PWM/main.c
index 48e02d3f6..51edb64c8 100644
--- a/testhal/SPC563Mxx/ICU-PWM/main.c
+++ b/testhal/SPC563Mxx/ICU-PWM/main.c
@@ -1,21 +1,21 @@
 /*
- * Licensed under ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- *        http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
 
-/* Inclusion of the main header files of all the imported components in the
-   order specified in the application wizard. The file is generated
-   automatically.*/
-#include "components.h"
+#include "ch.h"
+#include "hal.h"
 
 static void pwmpcb(PWMDriver *pwmp) {
 
-- 
cgit v1.2.3


From 26354ec7b79b2127e737ede467db95f91769dd52 Mon Sep 17 00:00:00 2001
From: pcirillo <pcirillo@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sun, 2 Jun 2013 17:18:51 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5797
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/ICU-PWM/readme.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/ICU-PWM/readme.txt b/testhal/SPC563Mxx/ICU-PWM/readme.txt
index f56bcf55b..90fcf6d5c 100644
--- a/testhal/SPC563Mxx/ICU-PWM/readme.txt
+++ b/testhal/SPC563Mxx/ICU-PWM/readme.txt
@@ -1,5 +1,5 @@
 *****************************************************************************
-** ChibiOS/RT HAL - SPI driver demo for SPC563Mxx.                         **
+** ChibiOS/RT HAL - ICU_PWM driver demo for SPC563Mxx.                         **
 *****************************************************************************
 
 ** TARGET **
-- 
cgit v1.2.3


From cb0364f42a9df0ca6bce07bdc51e0e1d99e9451f Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Mon, 3 Jun 2013 08:58:07 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5802
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/SPI/main.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/SPI/main.c b/testhal/SPC563Mxx/SPI/main.c
index df186e7e7..212642c2f 100644
--- a/testhal/SPC563Mxx/SPI/main.c
+++ b/testhal/SPC563Mxx/SPI/main.c
@@ -26,7 +26,7 @@ static const SPIConfig hs_spicfg = {
   0,
   SPC5_MCR_PCSIS0,                                              /* MCR.     */
   SPC5_CTAR_CSSCK_DIV2 | SPC5_CTAR_ASC_DIV2 | SPC5_CTAR_FMSZ(8) |
-  SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV2,                     /* CTAR0.   */
+  SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV2,                       /* CTAR0.   */
   SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(0)                           /* PUSHR.   */
 };
 
-- 
cgit v1.2.3


From 53d4dfdc100bd69672baeabe5a23b7df851402fb Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Mon, 3 Jun 2013 13:09:13 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5803
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/SPI/main.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/SPI/main.c b/testhal/SPC563Mxx/SPI/main.c
index 212642c2f..b71f85d78 100644
--- a/testhal/SPC563Mxx/SPI/main.c
+++ b/testhal/SPC563Mxx/SPI/main.c
@@ -107,17 +107,13 @@ int main(void) {
   halInit();
   chSysInit();
 
-  /*
-   * SPI1 I/O pins setup.
-   */
-
   /*
    * Prepare transmit pattern.
    */
   for (i = 0; i < sizeof(txbuf); i++)
     txbuf[i] = (uint8_t)i;
 
-  /* Starting driver for test.*/
+  /* Starting driver for test, DSPI_B I/O pins setup.*/
   spiStart(&SPID2, &ls_spicfg);
   SIU.PCR[102].R = PAL_MODE_OUTPUT_ALTERNATE(1);    /* SCK    */
   SIU.PCR[103].R = PAL_MODE_OUTPUT_ALTERNATE(1);    /* SIN    */
-- 
cgit v1.2.3


From 52cac10dbce9b24df71712ed15430387e57dd01e Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Mon, 3 Jun 2013 14:40:57 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5804
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/ADC/mcuconf.h | 29 +++++++++++++++++++++++++++++
 testhal/SPC563Mxx/SPI/main.c    |  5 ++---
 testhal/SPC563Mxx/SPI/mcuconf.h | 28 ++++++++++++++++++++++------
 3 files changed, 53 insertions(+), 9 deletions(-)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/ADC/mcuconf.h b/testhal/SPC563Mxx/ADC/mcuconf.h
index 43a7662ed..49ae96bab 100644
--- a/testhal/SPC563Mxx/ADC/mcuconf.h
+++ b/testhal/SPC563Mxx/ADC/mcuconf.h
@@ -82,3 +82,32 @@
 #define SPC5_USE_ESCIB                      TRUE
 #define SPC5_ESCIA_PRIORITY                 8
 #define SPC5_ESCIB_PRIORITY                 8
+
+/*
+ * SPI driver system settings.
+ */
+#define SPC5_SPI_USE_DSPI1                  FALSE
+#define SPC5_SPI_USE_DSPI2                  FALSE
+#define SPC5_SPI_DSPI1_MCR                  (SPC5_MCR_PCSIS0 |              \
+                                             SPC5_MCR_PCSIS1 |              \
+                                             SPC5_MCR_PCSIS2 |              \
+                                             SPC5_MCR_PCSIS3 |              \
+                                             SPC5_MCR_PCSIS4 |              \
+                                             SPC5_MCR_PCSIS5 |              \
+                                             SPC5_MCR_PCSIS6 |              \
+                                             SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI2_MCR                  (SPC5_MCR_PCSIS0 |              \
+                                             SPC5_MCR_PCSIS1 |              \
+                                             SPC5_MCR_PCSIS2 |              \
+                                             SPC5_MCR_PCSIS3 |              \
+                                             SPC5_MCR_PCSIS4 |              \
+                                             SPC5_MCR_PCSIS5 |              \
+                                             SPC5_MCR_PCSIS6 |              \
+                                             SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI1_DMA_PRIO             10
+#define SPC5_SPI_DSPI2_DMA_PRIO             10
+#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO         10
+#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO         10
+#define SPC5_SPI_DSPI1_IRQ_PRIO             10
+#define SPC5_SPI_DSPI2_IRQ_PRIO             10
+#define SPC5_SPI_DMA_ERROR_HOOK(spip)       chSysHalt()
diff --git a/testhal/SPC563Mxx/SPI/main.c b/testhal/SPC563Mxx/SPI/main.c
index b71f85d78..25b67546b 100644
--- a/testhal/SPC563Mxx/SPI/main.c
+++ b/testhal/SPC563Mxx/SPI/main.c
@@ -24,10 +24,9 @@ static const SPIConfig hs_spicfg = {
   NULL,
   0,
   0,
-  SPC5_MCR_PCSIS0,                                              /* MCR.     */
   SPC5_CTAR_CSSCK_DIV2 | SPC5_CTAR_ASC_DIV2 | SPC5_CTAR_FMSZ(8) |
   SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV2,                       /* CTAR0.   */
-  SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(0)                           /* PUSHR.   */
+  SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(1)                           /* PUSHR.   */
 };
 
 /*
@@ -37,7 +36,6 @@ static const SPIConfig ls_spicfg = {
   NULL,
   0,
   0,
-  SPC5_MCR_PCSIS0,                                              /* MCR.     */
   SPC5_CTAR_CSSCK_DIV64 | SPC5_CTAR_ASC_DIV64 | SPC5_CTAR_FMSZ(8) |
   SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV256,                     /* CTAR0.   */
   SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(0)                           /* PUSHR.   */
@@ -119,6 +117,7 @@ int main(void) {
   SIU.PCR[103].R = PAL_MODE_OUTPUT_ALTERNATE(1);    /* SIN    */
   SIU.PCR[104].R = PAL_MODE_OUTPUT_ALTERNATE(1);    /* SOUT   */
   SIU.PCR[105].R = PAL_MODE_OUTPUT_ALTERNATE(1);    /* PCS[0] */
+  SIU.PCR[106].R = PAL_MODE_OUTPUT_ALTERNATE(1);    /* PCS[1] */
 
   /* Testing sending and receiving at the same time.*/
   spiExchange(&SPID2, 4, txbuf, rxbuf);
diff --git a/testhal/SPC563Mxx/SPI/mcuconf.h b/testhal/SPC563Mxx/SPI/mcuconf.h
index 1b373d2cc..c96d6eea2 100644
--- a/testhal/SPC563Mxx/SPI/mcuconf.h
+++ b/testhal/SPC563Mxx/SPI/mcuconf.h
@@ -47,12 +47,12 @@
 /*
  * ADC driver settings.
  */
-#define SPC5_ADC_USE_ADC0_Q0                TRUE
-#define SPC5_ADC_USE_ADC0_Q1                TRUE
-#define SPC5_ADC_USE_ADC0_Q2                TRUE
-#define SPC5_ADC_USE_ADC1_Q3                TRUE
-#define SPC5_ADC_USE_ADC1_Q4                TRUE
-#define SPC5_ADC_USE_ADC1_Q5                TRUE
+#define SPC5_ADC_USE_ADC0_Q0                FALSE
+#define SPC5_ADC_USE_ADC0_Q1                FALSE
+#define SPC5_ADC_USE_ADC0_Q2                FALSE
+#define SPC5_ADC_USE_ADC1_Q3                FALSE
+#define SPC5_ADC_USE_ADC1_Q4                FALSE
+#define SPC5_ADC_USE_ADC1_Q5                FALSE
 #define SPC5_ADC_FIFO0_DMA_PRIO             12
 #define SPC5_ADC_FIFO1_DMA_PRIO             12
 #define SPC5_ADC_FIFO2_DMA_PRIO             12
@@ -88,6 +88,22 @@
  */
 #define SPC5_SPI_USE_DSPI1                  TRUE
 #define SPC5_SPI_USE_DSPI2                  TRUE
+#define SPC5_SPI_DSPI1_MCR                  (SPC5_MCR_PCSIS0 |              \
+                                             SPC5_MCR_PCSIS1 |              \
+                                             SPC5_MCR_PCSIS2 |              \
+                                             SPC5_MCR_PCSIS3 |              \
+                                             SPC5_MCR_PCSIS4 |              \
+                                             SPC5_MCR_PCSIS5 |              \
+                                             SPC5_MCR_PCSIS6 |              \
+                                             SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI2_MCR                  (SPC5_MCR_PCSIS0 |              \
+                                             SPC5_MCR_PCSIS1 |              \
+                                             SPC5_MCR_PCSIS2 |              \
+                                             SPC5_MCR_PCSIS3 |              \
+                                             SPC5_MCR_PCSIS4 |              \
+                                             SPC5_MCR_PCSIS5 |              \
+                                             SPC5_MCR_PCSIS6 |              \
+                                             SPC5_MCR_PCSIS7)
 #define SPC5_SPI_DSPI1_DMA_PRIO             10
 #define SPC5_SPI_DSPI2_DMA_PRIO             10
 #define SPC5_SPI_DSPI1_DMA_IRQ_PRIO         10
-- 
cgit v1.2.3


From fb0563fbd223cd0bfcddaf1ae4745efc1e5f281b Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 4 Jun 2013 08:03:01 +0000
Subject: Fixed bug #415.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5810 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 testhal/SPC563Mxx/SPI/main.c | 1 +
 1 file changed, 1 insertion(+)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/SPI/main.c b/testhal/SPC563Mxx/SPI/main.c
index 25b67546b..46378a5f8 100644
--- a/testhal/SPC563Mxx/SPI/main.c
+++ b/testhal/SPC563Mxx/SPI/main.c
@@ -152,6 +152,7 @@ int main(void) {
    */
   while (TRUE) {
     chThdSleepMilliseconds(500);
+    palTogglePad(PORT11, P11_LED2);
   }
   return 0;
 }
-- 
cgit v1.2.3


From 126943984c591c952bd0b9f6b2d36d97be823de3 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Fri, 14 Jun 2013 12:34:59 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5848
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/ADC/mcuconf.h | 29 +++++++++++++++++++++--------
 testhal/SPC563Mxx/SPI/mcuconf.h | 29 +++++++++++++++++++++--------
 2 files changed, 42 insertions(+), 16 deletions(-)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/ADC/mcuconf.h b/testhal/SPC563Mxx/ADC/mcuconf.h
index 49ae96bab..db7cfabb1 100644
--- a/testhal/SPC563Mxx/ADC/mcuconf.h
+++ b/testhal/SPC563Mxx/ADC/mcuconf.h
@@ -23,6 +23,8 @@
  *
  * IRQ priorities:
  * 1...15       Lowest...Highest.
+ * DMA priorities:
+ * 0...15       Highest...Lowest.
  */
 
 #define SPC563Mxx_MCUCONF
@@ -44,6 +46,25 @@
                                              BIUCR_PFLIM_ON_MISS |          \
                                              BIUCR_BFEN)
 
+/*
+ * EDMA driver settings.
+ */
+#define SPC5_EDMA_CR_SETTING                (EDMA_CR_GRP3PRI(3) |           \
+                                             EDMA_CR_GRP2PRI(2) |           \
+                                             EDMA_CR_GRP1PRI(1) |           \
+                                             EDMA_CR_GRP0PRI(0) |           \
+                                             EDMA_CR_ERGA)
+#define SPC5_EDMA_GROUP0_PRIORITIES                                         \
+  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_GROUP1_PRIORITIES                                         \
+  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_GROUP2_PRIORITIES                                         \
+  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_GROUP3_PRIORITIES                                         \
+  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_ERROR_IRQ_PRIO            2
+#define SPC5_EDMA_ERROR_HANDLER()           chSysHalt()
+
 /*
  * ADC driver settings.
  */
@@ -53,12 +74,6 @@
 #define SPC5_ADC_USE_ADC1_Q3                TRUE
 #define SPC5_ADC_USE_ADC1_Q4                TRUE
 #define SPC5_ADC_USE_ADC1_Q5                TRUE
-#define SPC5_ADC_FIFO0_DMA_PRIO             12
-#define SPC5_ADC_FIFO1_DMA_PRIO             12
-#define SPC5_ADC_FIFO2_DMA_PRIO             12
-#define SPC5_ADC_FIFO3_DMA_PRIO             12
-#define SPC5_ADC_FIFO4_DMA_PRIO             12
-#define SPC5_ADC_FIFO5_DMA_PRIO             12
 #define SPC5_ADC_FIFO0_DMA_IRQ_PRIO         12
 #define SPC5_ADC_FIFO1_DMA_IRQ_PRIO         12
 #define SPC5_ADC_FIFO2_DMA_IRQ_PRIO         12
@@ -104,8 +119,6 @@
                                              SPC5_MCR_PCSIS5 |              \
                                              SPC5_MCR_PCSIS6 |              \
                                              SPC5_MCR_PCSIS7)
-#define SPC5_SPI_DSPI1_DMA_PRIO             10
-#define SPC5_SPI_DSPI2_DMA_PRIO             10
 #define SPC5_SPI_DSPI1_DMA_IRQ_PRIO         10
 #define SPC5_SPI_DSPI2_DMA_IRQ_PRIO         10
 #define SPC5_SPI_DSPI1_IRQ_PRIO             10
diff --git a/testhal/SPC563Mxx/SPI/mcuconf.h b/testhal/SPC563Mxx/SPI/mcuconf.h
index c96d6eea2..a06df4fdc 100644
--- a/testhal/SPC563Mxx/SPI/mcuconf.h
+++ b/testhal/SPC563Mxx/SPI/mcuconf.h
@@ -23,6 +23,8 @@
  *
  * IRQ priorities:
  * 1...15       Lowest...Highest.
+ * DMA priorities:
+ * 0...15       Highest...Lowest.
  */
 
 #define SPC563Mxx_MCUCONF
@@ -44,6 +46,25 @@
                                              BIUCR_PFLIM_ON_MISS |          \
                                              BIUCR_BFEN)
 
+/*
+ * EDMA driver settings.
+ */
+#define SPC5_EDMA_CR_SETTING                (EDMA_CR_GRP3PRI(3) |           \
+                                             EDMA_CR_GRP2PRI(2) |           \
+                                             EDMA_CR_GRP1PRI(1) |           \
+                                             EDMA_CR_GRP0PRI(0) |           \
+                                             EDMA_CR_ERGA)
+#define SPC5_EDMA_GROUP0_PRIORITIES                                         \
+  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_GROUP1_PRIORITIES                                         \
+  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_GROUP2_PRIORITIES                                         \
+  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_GROUP3_PRIORITIES                                         \
+  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_ERROR_IRQ_PRIO            2
+#define SPC5_EDMA_ERROR_HANDLER()           chSysHalt()
+
 /*
  * ADC driver settings.
  */
@@ -53,12 +74,6 @@
 #define SPC5_ADC_USE_ADC1_Q3                FALSE
 #define SPC5_ADC_USE_ADC1_Q4                FALSE
 #define SPC5_ADC_USE_ADC1_Q5                FALSE
-#define SPC5_ADC_FIFO0_DMA_PRIO             12
-#define SPC5_ADC_FIFO1_DMA_PRIO             12
-#define SPC5_ADC_FIFO2_DMA_PRIO             12
-#define SPC5_ADC_FIFO3_DMA_PRIO             12
-#define SPC5_ADC_FIFO4_DMA_PRIO             12
-#define SPC5_ADC_FIFO5_DMA_PRIO             12
 #define SPC5_ADC_FIFO0_DMA_IRQ_PRIO         12
 #define SPC5_ADC_FIFO1_DMA_IRQ_PRIO         12
 #define SPC5_ADC_FIFO2_DMA_IRQ_PRIO         12
@@ -104,8 +119,6 @@
                                              SPC5_MCR_PCSIS5 |              \
                                              SPC5_MCR_PCSIS6 |              \
                                              SPC5_MCR_PCSIS7)
-#define SPC5_SPI_DSPI1_DMA_PRIO             10
-#define SPC5_SPI_DSPI2_DMA_PRIO             10
 #define SPC5_SPI_DSPI1_DMA_IRQ_PRIO         10
 #define SPC5_SPI_DSPI2_DMA_IRQ_PRIO         10
 #define SPC5_SPI_DSPI1_IRQ_PRIO             10
-- 
cgit v1.2.3


From 8e9ee823a71b5bfe944f7ff4ceaa1d568c610e6e Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Fri, 14 Jun 2013 14:25:39 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5849
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/ADC/mcuconf.h | 4 ----
 testhal/SPC563Mxx/SPI/mcuconf.h | 4 ----
 2 files changed, 8 deletions(-)

(limited to 'testhal/SPC563Mxx')

diff --git a/testhal/SPC563Mxx/ADC/mcuconf.h b/testhal/SPC563Mxx/ADC/mcuconf.h
index db7cfabb1..18cc088ac 100644
--- a/testhal/SPC563Mxx/ADC/mcuconf.h
+++ b/testhal/SPC563Mxx/ADC/mcuconf.h
@@ -58,10 +58,6 @@
   0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
 #define SPC5_EDMA_GROUP1_PRIORITIES                                         \
   0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
-#define SPC5_EDMA_GROUP2_PRIORITIES                                         \
-  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
-#define SPC5_EDMA_GROUP3_PRIORITIES                                         \
-  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
 #define SPC5_EDMA_ERROR_IRQ_PRIO            2
 #define SPC5_EDMA_ERROR_HANDLER()           chSysHalt()
 
diff --git a/testhal/SPC563Mxx/SPI/mcuconf.h b/testhal/SPC563Mxx/SPI/mcuconf.h
index a06df4fdc..6affa7878 100644
--- a/testhal/SPC563Mxx/SPI/mcuconf.h
+++ b/testhal/SPC563Mxx/SPI/mcuconf.h
@@ -58,10 +58,6 @@
   0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
 #define SPC5_EDMA_GROUP1_PRIORITIES                                         \
   0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
-#define SPC5_EDMA_GROUP2_PRIORITIES                                         \
-  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
-#define SPC5_EDMA_GROUP3_PRIORITIES                                         \
-  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
 #define SPC5_EDMA_ERROR_IRQ_PRIO            2
 #define SPC5_EDMA_ERROR_HANDLER()           chSysHalt()
 
-- 
cgit v1.2.3