From e0e31ea7151ac1ed9c7aa8ca9badc9bcbfa36ab0 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 7 Aug 2013 12:54:36 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6096 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/halnew/platforms/STM32/st_lld.c | 2 +- os/kernel/ports/ARMCMx/CMSIS/include/core_cmFunc.h | 3 + os/kernel/ports/ARMCMx/chcore.h | 4 + os/kernel/ports/ARMCMx/chcore_v7m.c | 174 + os/kernel/ports/ARMCMx/chcore_v7m.h | 30 +- .../ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s | 62 +- os/kernel/ports/ARMCMx/compilers/GCC/crt0.c | 354 ++ os/kernel/ports/ARMCMx/compilers/GCC/rules.mk | 220 + os/kernel/ports/ARMCMx/compilers/GCC/vectors.c | 3 +- .../ports/ARMCMx/devices/STM32F30x/cmparams.h | 35 +- os/kernel/ports/ARMCMx/devices/STM32F30x/port.mk | 14 +- .../ports/ARMCMx/devices/STM32F30x/stm32f30x.h | 6205 ++++++++++++++++++++ .../ARMCMx/devices/STM32F30x/system_stm32f30x.h | 105 + 13 files changed, 7180 insertions(+), 31 deletions(-) create mode 100644 os/kernel/ports/ARMCMx/chcore_v7m.c create mode 100644 os/kernel/ports/ARMCMx/compilers/GCC/crt0.c create mode 100644 os/kernel/ports/ARMCMx/compilers/GCC/rules.mk create mode 100644 os/kernel/ports/ARMCMx/devices/STM32F30x/stm32f30x.h create mode 100644 os/kernel/ports/ARMCMx/devices/STM32F30x/system_stm32f30x.h (limited to 'os') diff --git a/os/halnew/platforms/STM32/st_lld.c b/os/halnew/platforms/STM32/st_lld.c index 2c637042f..3498b8854 100644 --- a/os/halnew/platforms/STM32/st_lld.c +++ b/os/halnew/platforms/STM32/st_lld.c @@ -57,7 +57,7 @@ * * @isr */ -OSAL_IRQ_HANDLER(SysTickVector) { +OSAL_IRQ_HANDLER(SysTick_Handler) { OSAL_IRQ_PROLOGUE(); diff --git a/os/kernel/ports/ARMCMx/CMSIS/include/core_cmFunc.h b/os/kernel/ports/ARMCMx/CMSIS/include/core_cmFunc.h index 139bc3c5e..b5936735e 100644 --- a/os/kernel/ports/ARMCMx/CMSIS/include/core_cmFunc.h +++ b/os/kernel/ports/ARMCMx/CMSIS/include/core_cmFunc.h @@ -613,6 +613,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fps __ASM volatile (""); __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); __ASM volatile (""); +#else + /* CHIBIOS FIX */ + (void)fpscr; #endif } diff --git a/os/kernel/ports/ARMCMx/chcore.h b/os/kernel/ports/ARMCMx/chcore.h index e1b626351..62363f3fc 100644 --- a/os/kernel/ports/ARMCMx/chcore.h +++ b/os/kernel/ports/ARMCMx/chcore.h @@ -70,6 +70,8 @@ /* Derived constants and error checks. */ /*===========================================================================*/ +/* The following code is not processed when the file is included from an + asm module.*/ #if !defined(_FROM_ASM_) /* @@ -93,6 +95,8 @@ /* Module data structures and types. */ /*===========================================================================*/ +/* The following code is not processed when the file is included from an + asm module.*/ #if !defined(_FROM_ASM_) /* The following declarations are there just for Doxygen documentation, the diff --git a/os/kernel/ports/ARMCMx/chcore_v7m.c b/os/kernel/ports/ARMCMx/chcore_v7m.c new file mode 100644 index 000000000..af9dcd439 --- /dev/null +++ b/os/kernel/ports/ARMCMx/chcore_v7m.c @@ -0,0 +1,174 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file ARMCMx/chcore_v7m.c + * @brief ARMv7-M architecture port code. + * + * @addtogroup ARMCMx_V7M_CORE + * @{ + */ + +#include "ch.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module interrupt handlers. */ +/*===========================================================================*/ + +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +/** + * @brief SVC vector. + * @details The SVC vector is used for exception mode re-entering after a + * context switch. + * @note The PendSV vector is only used in advanced kernel mode. + */ +void SVC_Handler(void) { + + /* The extctx structure is pointed by the PSP register.*/ + struct extctx *ctxp = (struct extctx *)__get_PSP(); + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + ctxp++; + +#if CORTEX_USE_FPU + /* Restoring the special register SCB_FPCCR.*/ + SCB_FPCCR = (uint32_t)ctxp->fpccr; + SCB_FPCAR = SCB_FPCAR + sizeof (struct extctx); +#endif + + /* Writing back the modified PSP value.*/ + __set_PSP((uint32_t)ctxp); + + /* Restoring the normal interrupts status.*/ + port_unlock_from_isr(); +} +#endif /* !CORTEX_SIMPLIFIED_PRIORITY */ + +#if CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +/** + * @brief PendSV vector. + * @details The PendSV vector is used for exception mode re-entering after a + * context switch. + * @note The PendSV vector is only used in compact kernel mode. + */ +void PendSV_Handler(void) { + + /* The extctx structure is pointed by the PSP register.*/ + struct extctx *ctxp = (struct extctx *)__get_PSP(); + + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + ctxp++; + +#if CORTEX_USE_FPU + /* Restoring the special register SCB_FPCCR.*/ + SCB_FPCCR = (uint32_t)ctxp->fpccr; + SCB_FPCAR = SCB_FPCAR + sizeof (struct extctx); +#endif + + /* Writing back the modified PSP value.*/ + __set_PSP((uint32_t)ctxp); +} +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +/** + * @brief Exception exit redirection to _port_switch_from_isr(). + */ +void _port_irq_epilogue(void) { + + port_lock_from_isr(); + if ((SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) != 0) { + + /* The extctx structure is pointed by the PSP register.*/ + struct extctx *ctxp = (struct extctx *)__get_PSP(); + + /* Adding an artificial exception return context, there is no need to + populate it fully.*/ + ctxp--; + + /* Writing back the modified PSP value.*/ + __set_PSP((uint32_t)ctxp); + + /* Setting up a fake XPSR register value.*/ + ctxp->xpsr = (regarm_t)0x01000000; + + /* The exit sequence is different depending on if a preemption is + required or not.*/ + if (chSchIsPreemptionRequired()) { + /* Preemption is required we need to enforce a context switch.*/ + ctxp->pc = (void *)_port_switch_from_isr; +#if CORTEX_USE_FPU + /* Enforcing a lazy FPU state save by accessing the FPCSR register.*/ + (void) __get_FPSCR(); +#endif + } + else { + /* Preemption not required, we just need to exit the exception + atomically.*/ + ctxp->pc = (void *)_port_exit_from_isr; + } + +#if CORTEX_USE_FPU + { + uint32_t fpccr; + + /* Saving the special register SCB_FPCCR into the reserved offset of + the Cortex-M4 exception frame.*/ + (ctxp + 1)->fpccr = (regarm_t)(fpccr = SCB_FPCCR); + + /* Now the FPCCR is modified in order to not restore the FPU status + from the artificial return context.*/ + SCB_FPCCR = fpccr | FPCCR_LSPACT; + } +#endif + + /* Note, returning without unlocking is intentional, this is done in + order to keep the rest of the context switch atomic.*/ + return; + } + port_unlock_from_isr(); +} + +/** @} */ diff --git a/os/kernel/ports/ARMCMx/chcore_v7m.h b/os/kernel/ports/ARMCMx/chcore_v7m.h index 118638469..cdb393fd4 100644 --- a/os/kernel/ports/ARMCMx/chcore_v7m.h +++ b/os/kernel/ports/ARMCMx/chcore_v7m.h @@ -216,6 +216,8 @@ /* Module data structures and types. */ /*===========================================================================*/ +/* The following code is not processed when the file is included from an + asm module.*/ #if !defined(_FROM_ASM_) /** @@ -418,22 +420,22 @@ extern "C" { static inline void port_init(void) { /* Initialization of the vector table and priority related settings.*/ - SCB_VTOR = CORTEX_VTOR_INIT; - SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(CORTEX_PRIGROUP_INIT); + SCB->VTOR = CORTEX_VTOR_INIT; + + /* Initializing priority grouping.*/ + NVIC_SetPriorityGrouping(CORTEX_PRIGROUP_INIT); /* DWT cycle counter enable.*/ - SCS_DEMCR |= SCS_DEMCR_TRCENA; - DWT_CTRL |= DWT_CTRL_CYCCNTENA; + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; /* Initialization of the system vectors used by the port.*/ - nvicSetSystemHandlerPriority(HANDLER_SVCALL, - CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); - nvicSetSystemHandlerPriority(HANDLER_PENDSV, - CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); -#if CH_CFG_TIMEDELTA == 0 - nvicSetSystemHandlerPriority(HANDLER_SYSTICK, - CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); -#else + NVIC_SetPriority(SVCall_IRQn, CORTEX_PRIORITY_SVCALL); + NVIC_SetPriority(PendSV_IRQn, CORTEX_PRIORITY_PENDSV); + +#if CH_CFG_TIMEDELTA > 0 + /* TODO: Remove initialization, all the timers handling has to be performed + outside the port layer.*/ port_timer_init(); #endif } @@ -595,13 +597,13 @@ static inline void port_enable(void) { static inline void port_wait_for_interrupt(void) { #if CORTEX_ENABLE_WFI_IDLE - asm volatile ("wfi" : : : "memory"); + __WFI; #endif } static inline rtcnt_t port_rt_get_counter_value(void) { - return DWT_CYCCNT; + return DWT->CYCCNT; } #endif /* !defined(_FROM_ASM_) */ diff --git a/os/kernel/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s b/os/kernel/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s index 3d4920b01..6968e3819 100644 --- a/os/kernel/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s +++ b/os/kernel/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s @@ -26,6 +26,7 @@ * @{ */ +#define _FROM_ASM_ #include "chconf.h" #include "chcore.h" @@ -39,6 +40,11 @@ #if !defined(__DOXYGEN__) + + .set CONTEXT_OFFSET, 12 + .set SCB_ICSR, 0xE000ED04 + .set ICSR_PENDSVSET, 0x10000000 + .syntax unified .cpu cortex-m4 .fpu softvfp @@ -46,14 +52,31 @@ .thumb .text -/* - * Thread trampoline code. +/*--------------------------------------------------------------------------* + * Performs a context switch between two threads. + *--------------------------------------------------------------------------*/ + .thumb_func + .globl _port_switch +_port_switch: + push {r4, r5, r6, r7, r8, r9, r10, r11, lr} +#if CORTEX_USE_FPU + vpush {s16-s31} +#endif + str sp, [r1, #CONTEXT_OFFSET] + ldr sp, [r0, #CONTEXT_OFFSET] +#if CORTEX_USE_FPU + vpop {s16-s31} +#endif + pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} + +/*--------------------------------------------------------------------------* + * Start a thread by invoking its work function. * * Threads execution starts here, the code leaves the system critical zone * and then jumps into the thread function passed in register R4. The * register R5 contains the thread parameter. The function chThdExit() is * called on thread function return. - */ + *--------------------------------------------------------------------------*/ .thumb_func .globl _port_thread_start _port_thread_start: @@ -69,6 +92,39 @@ _port_thread_start: blx r4 bl chThdExit +/*--------------------------------------------------------------------------* + * Post-IRQ switch code. + * + * Exception handlers return here for context switching. + *--------------------------------------------------------------------------*/ + .thumb_func + .globl _port_switch_from_isr +_port_switch_from_isr: +#if CH_DBG_STATISTICS + bl _stats_start_measure_crit_thd +#endif +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_lock +#endif + bl chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif +#if CH_DBG_STATISTICS + bl _stats_stop_measure_crit_thd +#endif +_port_exit_from_isr: +#if CORTEX_SIMPLIFIED_PRIORITY + mov r3, #SCB_ICSR :AND: 0xFFFF + movt r3, #SCB_ICSR :SHR: 16 + mov r2, #ICSR_PENDSVSET + str r2, [r3, #0] + cpsie i +#else /* !CORTEX_SIMPLIFIED_PRIORITY */ + svc #0 +#endif /* !CORTEX_SIMPLIFIED_PRIORITY */ +.L1: b .L1 + #endif /* !defined(__DOXYGEN__) */ /** @} */ diff --git a/os/kernel/ports/ARMCMx/compilers/GCC/crt0.c b/os/kernel/ports/ARMCMx/compilers/GCC/crt0.c new file mode 100644 index 000000000..f2aa2f002 --- /dev/null +++ b/os/kernel/ports/ARMCMx/compilers/GCC/crt0.c @@ -0,0 +1,354 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/crt0.c + * @brief Generic GCC ARMvx-M (Cortex-M0/M1/M3/M4) startup file. + * + * @addtogroup ARMCMx_GCC_STARTUP + * @{ + */ + +#include + +#if !defined(FALSE) +#define FALSE 0 +#endif + +#if !defined(TRUE) +#define TRUE (!FALSE) +#endif + +#define SCB_CPACR *((uint32_t *)0xE000ED88U) +#define SCB_FPCCR *((uint32_t *)0xE000EF34U) +#define SCB_FPDSCR *((uint32_t *)0xE000EF3CU) +#define FPCCR_ASPEN (0x1U << 31) +#define FPCCR_LSPEN (0x1U << 30) + +typedef void (*funcp_t)(void); +typedef funcp_t * funcpp_t; + +#define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0)) + +/* + * Area fill code, it is a macro because here functions cannot be called + * until stacks are initialized. + */ +#define fill32(start, end, filler) { \ + uint32_t *p1 = start; \ + uint32_t *p2 = end; \ + while (p1 < p2) \ + *p1++ = filler; \ +} + +/*===========================================================================*/ +/** + * @name Startup settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Control special register initialization value. + * @details The system is setup to run in privileged mode using the PSP + * stack (dual stack mode). + */ +#if !defined(CRT0_CONTROL_INIT) || defined(__DOXYGEN__) +#define CRT0_CONTROL_INIT 0x00000002 +#endif + +/** + * @brief Stack segments initialization switch. + */ +#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__) +#define CRT0_STACKS_FILL_PATTERN 0x55555555 +#endif + +/** + * @brief Stack segments initialization switch. + */ +#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__) +#define CRT0_INIT_STACKS TRUE +#endif + +/** + * @brief DATA segment initialization switch. + */ +#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__) +#define CRT0_INIT_DATA TRUE +#endif + +/** + * @brief BSS segment initialization switch. + */ +#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__) +#define CRT0_INIT_BSS TRUE +#endif + +/** + * @brief Constructors invocation switch. + */ +#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__) +#define CRT0_CALL_CONSTRUCTORS TRUE +#endif + +/** + * @brief Destructors invocation switch. + */ +#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__) +#define CRT0_CALL_DESTRUCTORS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Symbols from the scatter file + */ +/*===========================================================================*/ + +/** + * @brief Main stack lower boundary. + * @details This symbol must be exported by the linker script and represents + * the main stack lower boundary. + */ +extern uint32_t __main_stack_base__; + +/** + * + * @brief Main stack initial position. + * @details This symbol must be exported by the linker script and represents + * the main stack initial position. + */ +extern uint32_t __main_stack_end__; + +/** + * @brief Process stack lower boundary. + * @details This symbol must be exported by the linker script and represents + * the process stack lower boundary. + */ +extern uint32_t __process_stack_base__; + +/** + * @brief Process stack initial position. + * @details This symbol must be exported by the linker script and represents + * the process stack initial position. + */ +extern uint32_t __process_stack_end__; + +/** + * @brief ROM image of the data segment start. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern uint32_t _textdata; + +/** + * @brief Data segment start. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern uint32_t _data; + +/** + * @brief Data segment end. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern uint32_t _edata; + +/** + * @brief BSS segment start. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern uint32_t _bss_start; + +/** + * @brief BSS segment end. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern uint32_t _bss_end; + +/** + * @brief Constructors table start. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern funcp_t __init_array_start; + +/** + * @brief Constructors table end. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern funcp_t __init_array_end; + +/** + * @brief Destructors table start. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern funcp_t __fini_array_start; + +/** + * @brief Destructors table end. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern funcp_t __fini_array_end; + +/** @} */ + +/** + * @brief Application @p main() function. + */ +extern void main(void); + +/** + * @brief Early initialization. + * @details This hook is invoked immediately after the stack initialization + * and before the DATA and BSS segments initialization. The + * default behavior is to do nothing. + * @note This function is a weak symbol. + */ +#if !defined(__DOXYGEN__) +__attribute__((weak)) +#endif +void __early_init(void) {} + +/** + * @brief Late initialization. + * @details This hook is invoked after the DATA and BSS segments + * initialization and before any static constructor. The + * default behavior is to do nothing. + * @note This function is a weak symbol. + */ +#if !defined(__DOXYGEN__) +__attribute__((weak)) +#endif +void __late_init(void) {} + +/** + * @brief Default @p main() function exit handler. + * @details This handler is invoked or the @p main() function exit. The + * default behavior is to enter an infinite loop. + * @note This function is a weak symbol. + */ +#if !defined(__DOXYGEN__) +__attribute__((weak, naked)) +#endif +void _default_exit(void) { + while (1) + ; +} + +/** + * @brief Reset vector. + */ +#if !defined(__DOXYGEN__) +__attribute__((naked)) +#endif +void ResetHandler(void) { + uint32_t psp, reg; + + /* Process Stack initialization, it is allocated starting from the + symbol __process_stack_end__ and its lower limit is the symbol + __process_stack_base__.*/ + asm volatile ("cpsid i"); + psp = SYMVAL(__process_stack_end__); + asm volatile ("msr PSP, %0" : : "r" (psp)); + +#if CORTEX_USE_FPU + /* Initializing the FPU context save in lazy mode.*/ + SCB_FPCCR = FPCCR_ASPEN | FPCCR_LSPEN; + + /* CP10 and CP11 set to full access.*/ + SCB_CPACR |= 0x00F00000; + + /* FPSCR and FPDSCR initially zero.*/ + reg = 0; + asm volatile ("vmsr FPSCR, %0" : : "r" (reg) : "memory"); + SCB_FPDSCR = reg; + + /* CPU mode initialization, enforced FPCA bit.*/ + reg = CRT0_CONTROL_INIT | 4; +#else + /* CPU mode initialization.*/ + reg = CRT0_CONTROL_INIT; +#endif + asm volatile ("msr CONTROL, %0" : : "r" (reg)); + asm volatile ("isb"); + +#if CRT0_INIT_STACKS + /* Main and Process stacks initialization.*/ + fill32(&__main_stack_base__, + &__main_stack_end__, + CRT0_STACKS_FILL_PATTERN); + fill32(&__process_stack_base__, + &__process_stack_end__, + CRT0_STACKS_FILL_PATTERN); +#endif + + /* Early initialization hook invocation.*/ + __early_init(); + +#if CRT0_INIT_DATA + /* DATA segment initialization.*/ + { + uint32_t *tp, *dp; + + tp = &_textdata; + dp = &_data; + while (dp < &_edata) + *dp++ = *tp++; + } +#endif + +#if CRT0_INIT_BSS + /* BSS segment initialization.*/ + fill32(&_bss_start, &_bss_end, 0); +#endif + + /* Late initialization hook invocation.*/ + __late_init(); + +#if CRT0_CALL_CONSTRUCTORS + /* Constructors invocation.*/ + { + funcpp_t fpp = &__init_array_start; + while (fpp < &__init_array_end) { + (*fpp)(); + fpp++; + } + } +#endif + + /* Invoking application main() function.*/ + main(); + +#if CRT0_CALL_DESTRUCTORS + /* Destructors invocation.*/ + { + funcpp_t fpp = &__fini_array_start; + while (fpp < &__fini_array_end) { + (*fpp)(); + fpp++; + } + } +#endif + + /* Invoking the exit handler.*/ + _default_exit(); +} + +/** @} */ diff --git a/os/kernel/ports/ARMCMx/compilers/GCC/rules.mk b/os/kernel/ports/ARMCMx/compilers/GCC/rules.mk new file mode 100644 index 000000000..33531d201 --- /dev/null +++ b/os/kernel/ports/ARMCMx/compilers/GCC/rules.mk @@ -0,0 +1,220 @@ +# ARM Cortex-Mx common makefile scripts and rules. + +# Output directory and files +ifeq ($(BUILDDIR),) + BUILDDIR = build +endif +ifeq ($(BUILDDIR),.) + BUILDDIR = build +endif +OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \ + $(BUILDDIR)/$(PROJECT).bin $(BUILDDIR)/$(PROJECT).dmp + +# Automatic compiler options +OPT = $(USE_OPT) +COPT = $(USE_COPT) +CPPOPT = $(USE_CPPOPT) +ifeq ($(USE_LINK_GC),yes) + OPT += -ffunction-sections -fdata-sections -fno-common +endif + +# Source files groups and paths +ifeq ($(USE_THUMB),yes) + TCSRC += $(CSRC) + TCPPSRC += $(CPPSRC) +else + ACSRC += $(CSRC) + ACPPSRC += $(CPPSRC) +endif +ASRC = $(ACSRC)$(ACPPSRC) +TSRC = $(TCSRC)$(TCPPSRC) +SRCPATHS = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC))) + +# Various directories +OBJDIR = $(BUILDDIR)/obj +LSTDIR = $(BUILDDIR)/lst + +# Object files groups +ACOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACSRC:.c=.o))) +ACPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACPPSRC:.cpp=.o))) +TCOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o))) +TCPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o))) +ASMOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o))) +ASMXOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o))) +OBJS = $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) + +# Paths +IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR)) +LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) + +# Macros +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) + +# Libs +LIBS = $(DLIBS) $(ULIBS) + +# Various settings +MCFLAGS = -mcpu=$(MCU) +ODFLAGS = -x --syms +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS) +ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS) +CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS) +CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS) +ifeq ($(USE_LINK_GC),yes) + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LLIBDIR) +else + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch $(LLIBDIR) +endif + +# Thumb interwork enabled only if needed because it kills performance. +ifneq ($(TSRC),) + CFLAGS += -DTHUMB_PRESENT + CPPFLAGS += -DTHUMB_PRESENT + ASFLAGS += -DTHUMB_PRESENT + ifneq ($(ASRC),) + # Mixed ARM and THUMB mode. + CFLAGS += -mthumb-interwork + CPPFLAGS += -mthumb-interwork + ASFLAGS += -mthumb-interwork + LDFLAGS += -mthumb-interwork + else + # Pure THUMB mode, THUMB C code cannot be called by ARM asm code directly. + CFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING + CPPFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING + ASFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb + LDFLAGS += -mno-thumb-interwork -mthumb + endif +else + # Pure ARM mode + CFLAGS += -mno-thumb-interwork + CPPFLAGS += -mno-thumb-interwork + ASFLAGS += -mno-thumb-interwork + LDFLAGS += -mno-thumb-interwork +endif + +# Generate dependency information +CFLAGS += -MD -MP -MF .dep/$(@F).d +CPPFLAGS += -MD -MP -MF .dep/$(@F).d + +# Paths where to search for sources +VPATH = $(SRCPATHS) + +# +# Makefile rules +# + +all: $(OBJS) $(OUTFILES) MAKE_ALL_RULE_HOOK + +MAKE_ALL_RULE_HOOK: + +$(OBJS): | $(BUILDDIR) + +$(BUILDDIR) $(OBJDIR) $(LSTDIR): +ifneq ($(USE_VERBOSE_COMPILE),yes) + @echo Compiler Options + @echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o + @echo +endif + mkdir -p $(OBJDIR) + mkdir -p $(LSTDIR) + +$(ACPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile +ifeq ($(USE_VERBOSE_COMPILE),yes) + @echo + $(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@ +else + @echo Compiling $( $@ +else + @echo Creating $@ + @$(OD) $(ODFLAGS) $< > $@ + @echo Done +endif + +clean: + @echo Cleaning + -rm -fR .dep $(BUILDDIR) + @echo Done + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/os/kernel/ports/ARMCMx/compilers/GCC/vectors.c b/os/kernel/ports/ARMCMx/compilers/GCC/vectors.c index a5d6d1196..0234bbdd5 100644 --- a/os/kernel/ports/ARMCMx/compilers/GCC/vectors.c +++ b/os/kernel/ports/ARMCMx/compilers/GCC/vectors.c @@ -41,7 +41,7 @@ /** * @brief Type of an IRQ vector. */ -typedef void (*irq_vector_t)(void) __attribute__((weak, alias("_unhandled_exception"))); +typedef void (*irq_vector_t)(void); /** * @brief Type of a structure representing the whole vectors table. @@ -457,6 +457,7 @@ void Vector3F4(void) __attribute__((weak, alias("_unhandled_exception"))); void Vector3F8(void) __attribute__((weak, alias("_unhandled_exception"))); void Vector3FC(void) __attribute__((weak, alias("_unhandled_exception"))); #endif +#endif /* !defined(__DOXYGEN__) */ /** * @brief STM32 vectors table. diff --git a/os/kernel/ports/ARMCMx/devices/STM32F30x/cmparams.h b/os/kernel/ports/ARMCMx/devices/STM32F30x/cmparams.h index 86f654b70..af3161b39 100644 --- a/os/kernel/ports/ARMCMx/devices/STM32F30x/cmparams.h +++ b/os/kernel/ports/ARMCMx/devices/STM32F30x/cmparams.h @@ -37,11 +37,6 @@ */ #define CORTEX_MODEL CORTEX_M4 -/** - * @brief Systick unit presence. - */ -#define CORTEX_HAS_ST TRUE - /** * @brief Memory Protection unit presence. */ @@ -57,6 +52,36 @@ */ #define CORTEX_PRIORITY_BITS 4 +/** + * @brief Number of interrupt vectors. + * @note This number does not include the 16 system vectors and must be + * rounded to a multiple of 4. + */ +#define CORTEX_NUM_VECTORS 84 + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +/* Including the device CMSIS header. Note, we are not using the definitions + from this header because we need this file to be usable also from + assembler source files. We verify that the info matches instead.*/ +#include "stm32f30x.h" + +#if !CORTEX_HAS_MPU != !__MPU_PRESENT +#error "CMSIS __MPU_PRESENT mismatch" +#endif + +#if !CORTEX_HAS_FPU != !__FPU_PRESENT +#error "CMSIS __FPU_PRESENT mismatch" +#endif + +#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS +#error "CMSIS __NVIC_PRIO_BITS mismatch" +#endif + +#endif /* !defined(_FROM_ASM_) */ + #endif /* _CMPARAMS_H_ */ /** @} */ diff --git a/os/kernel/ports/ARMCMx/devices/STM32F30x/port.mk b/os/kernel/ports/ARMCMx/devices/STM32F30x/port.mk index b5836447b..a11a1fa7b 100644 --- a/os/kernel/ports/ARMCMx/devices/STM32F30x/port.mk +++ b/os/kernel/ports/ARMCMx/devices/STM32F30x/port.mk @@ -1,14 +1,14 @@ # List of the ChibiOS/RT Cortex-M4 STM32F30x port files. PORTSRC = ${CHIBIOS}/os/kernel/ports/ARMCMx/chcore.c \ ${CHIBIOS}/os/kernel/ports/ARMCMx/chcore_v7m.c \ - $(CHIBIOS)/os/kernel/ports/ARMCMx/GCC/crt0.c \ - $(CHIBIOS)/os/kernel/ports/ARMCMx/GCC/vectors.c \ + $(CHIBIOS)/os/kernel/ports/ARMCMx/compilers/GCC/crt0.c \ + $(CHIBIOS)/os/kernel/ports/ARMCMx/compilers/GCC/vectors.c \ -PORTASM = $(CHIBIOS)/os/kernel/ports/ARMCMx/GCC/chcoreasm_v7m.s +PORTASM = $(CHIBIOS)/os/kernel/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s PORTINC = ${CHIBIOS}/os/kernel/ports/ARMCMx \ - ${CHIBIOS}/os/kernel/ports/ARMCMx/GCC \ - ${CHIBIOS}/os/kernel/ports/ARMCMx/GCC/STM32F30x \ - ${CHIBIOS}/os/kernel/ports/ARMCMx/common/CMSIS/include + ${CHIBIOS}/os/kernel/ports/ARMCMx/CMSIS/include \ + ${CHIBIOS}/os/kernel/ports/ARMCMx/compilers/GCC \ + ${CHIBIOS}/os/kernel/ports/ARMCMx/devices/STM32F30x -PORTLD = ${CHIBIOS}/os/ports/GCC/ld +PORTLD = ${CHIBIOS}/os/kernel/ports/ARMCMx/compilers/GCC/ld diff --git a/os/kernel/ports/ARMCMx/devices/STM32F30x/stm32f30x.h b/os/kernel/ports/ARMCMx/devices/STM32F30x/stm32f30x.h new file mode 100644 index 000000000..c4dc4714d --- /dev/null +++ b/os/kernel/ports/ARMCMx/devices/STM32F30x/stm32f30x.h @@ -0,0 +1,6205 @@ +/** + ****************************************************************************** + * @file stm32f30x.h + * @author MCD Application Team + * @version V1.0.0 + * @date 04-September-2012 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. + * This file contains all the peripheral registers definitions, bits + * definitions and memory mapping for STM32F30x devices. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripheral registers declarations and bits definition + * - Macros to access peripheral registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2012 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f30x + * @{ + */ + +#ifndef __STM32F30x_H +#define __STM32F30x_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F30X) + #define STM32F30X +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (STM32F30X) + #error "Please select first the target STM32F30X device used in your application (in stm32f30x.h file)" +#endif + +#if !defined (USE_STDPERIPH_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif /* USE_STDPERIPH_DRIVER */ + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup + Timeout value + */ +#if !defined (HSI_STARTUP_TIMEOUT) + #define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */ +#endif /* HSI_STARTUP_TIMEOUT */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) +#endif /* HSI_VALUE */ /*!< Value of the Internal High Speed oscillator in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)40000) +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + + +/** + * @brief STM32F30x Standard Peripherals Library version number V1.0.0 + */ +#define __STM32F30X_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F30X_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32F30X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F30X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F30X_STDPERIPH_VERSION ( (__STM32F30X_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F30X_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F30X_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F30X_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32F30X provide an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F30X uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< STM32F30X provide an FPU */ + + +/** + * @brief STM32F30X Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI lines 17, 19 & 20 */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_TS_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + ADC4_IRQn = 61, /*!< ADC4 global Interrupt */ + COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt */ + COMP4_5_6_IRQn = 65, /*!< COMP5, COMP6 and COMP4 global Interrupt */ + COMP7_IRQn = 66, /*!< COMP7 global Interrupt */ + USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */ + USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */ + USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */ + FPU_IRQn = 81 /*!< Floating point Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32f30x.h" /* STM32F30x System Header */ +#include + +/** @addtogroup Exported_types + * @{ + */ +/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + uint32_t RESERVED0; /*!< Reserved, 0x010 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x01C */ + __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */ + +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1/3 base address + 0x30C */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + + +/** + * @brief Analog Comparators + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */ +}EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */ + uint32_t RESERVED; /*!< Reserved, 0x18 */ + __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */ + __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */ + +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ +typedef struct +{ + __IO uint16_t RDP; /*!
© COPYRIGHT 2012 STMicroelectronics
+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f30x_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F30X_H +#define __SYSTEM_STM32F30X_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F30x_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F30x_System_Exported_types + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * @} + */ + +/** @addtogroup STM32F30x_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F30x_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F30x_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F30X_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -- cgit v1.2.3