From d8edc8d012500fa4b97d7f8f9dc1aa15bfd9014e Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sun, 5 Dec 2010 12:18:15 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2460
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/LPC11xx/spi_lld.h |  3 +--
 os/hal/platforms/LPC13xx/hal_lld.h | 10 +++++-----
 os/hal/platforms/LPC13xx/spi_lld.h |  3 +--
 3 files changed, 7 insertions(+), 9 deletions(-)

(limited to 'os')

diff --git a/os/hal/platforms/LPC11xx/spi_lld.h b/os/hal/platforms/LPC11xx/spi_lld.h
index 64f87c679..7b6374172 100644
--- a/os/hal/platforms/LPC11xx/spi_lld.h
+++ b/os/hal/platforms/LPC11xx/spi_lld.h
@@ -37,7 +37,7 @@
 /**
  * @brief   Hardware FIFO depth.
  */
-#define LPC11xx_SSP_FIFO_DEPTH          8
+#define LPC11xx_SSP_FIFO_DEPTH  8
 
 #define CR0_DSSMASK             0x0F
 #define CR0_DSS4BIT             3
@@ -89,7 +89,6 @@
 #define ICR_ROR                 1
 #define ICR_RT                  2
 
-
 /**
  * @brief   SCK0 signal assigned to pin PIO0_10.
  */
diff --git a/os/hal/platforms/LPC13xx/hal_lld.h b/os/hal/platforms/LPC13xx/hal_lld.h
index da44b5012..386ec44a6 100644
--- a/os/hal/platforms/LPC13xx/hal_lld.h
+++ b/os/hal/platforms/LPC13xx/hal_lld.h
@@ -61,7 +61,7 @@
  * @brief   System PLL clock source.
  */
 #if !defined(LPC13xx_PLLCLK_SOURCE) || defined(__DOXYGEN__)
-#define LPC13xx_PLLCLK_SOURCE   SYSPLLCLKSEL_SYSOSC
+#define LPC13xx_PLLCLK_SOURCE               SYSPLLCLKSEL_SYSOSC
 #endif
 
 /**
@@ -70,7 +70,7 @@
  *          must not exceed the CCO ratings.
  */
 #if !defined(LPC13xx_SYSPLL_MUL) || defined(__DOXYGEN__)
-#define LPC13xx_SYSPLL_MUL      6
+#define LPC13xx_SYSPLL_MUL                  6
 #endif
 
 /**
@@ -78,14 +78,14 @@
  * @note    The value must be chosen between (2, 4, 8, 16).
  */
 #if !defined(LPC13xx_SYSPLL_DIV) || defined(__DOXYGEN__)
-#define LPC13xx_SYSPLL_DIV      4
+#define LPC13xx_SYSPLL_DIV                  4
 #endif
 
 /**
  * @brief   System main clock source.
  */
 #if !defined(LPC13xx_MAINCLK_SOURCE) || defined(__DOXYGEN__)
-#define LPC13xx_MAINCLK_SOURCE  SYSMAINCLKSEL_PLLOUT
+#define LPC13xx_MAINCLK_SOURCE              SYSMAINCLKSEL_PLLOUT
 #endif
 
 /**
@@ -93,7 +93,7 @@
  * @note    The value must be chosen between (1...255).
  */
 #if !defined(LPC13xx_SYSCLK_DIV) || defined(__DOXYGEN__)
-#define LPC13xx_SYSABHCLK_DIV   1
+#define LPC13xx_SYSABHCLK_DIV               1
 #endif
 
 /*===========================================================================*/
diff --git a/os/hal/platforms/LPC13xx/spi_lld.h b/os/hal/platforms/LPC13xx/spi_lld.h
index 5d4dcb334..037627291 100644
--- a/os/hal/platforms/LPC13xx/spi_lld.h
+++ b/os/hal/platforms/LPC13xx/spi_lld.h
@@ -37,7 +37,7 @@
 /**
  * @brief   Hardware FIFO depth.
  */
-#define LPC13xx_SSP_FIFO_DEPTH          8
+#define LPC13xx_SSP_FIFO_DEPTH  8
 
 #define CR0_DSSMASK             0x0F
 #define CR0_DSS4BIT             3
@@ -89,7 +89,6 @@
 #define ICR_ROR                 1
 #define ICR_RT                  2
 
-
 /**
  * @brief   SCK0 signal assigned to pin PIO0_10.
  */
-- 
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