From ae42ff1857ee56d67feca50d379c5f4b66d7fe69 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 21 Sep 2011 17:10:15 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3377 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F1xx/adc_lld.h | 27 +- os/hal/platforms/STM32L1xx/adc_lld.c | 241 ++++++++++++++++++ os/hal/platforms/STM32L1xx/adc_lld.h | 447 +++++++++++++++++++++++++++++++++ os/hal/platforms/STM32L1xx/hal_lld.h | 2 +- os/hal/platforms/STM32L1xx/platform.mk | 1 + os/ports/GCC/ARMCMx/port.dox | 49 ++-- 6 files changed, 746 insertions(+), 21 deletions(-) create mode 100644 os/hal/platforms/STM32L1xx/adc_lld.c create mode 100644 os/hal/platforms/STM32L1xx/adc_lld.h (limited to 'os') diff --git a/os/hal/platforms/STM32F1xx/adc_lld.h b/os/hal/platforms/STM32F1xx/adc_lld.h index 7180c2b83..1d1052f50 100644 --- a/os/hal/platforms/STM32F1xx/adc_lld.h +++ b/os/hal/platforms/STM32F1xx/adc_lld.h @@ -35,9 +35,18 @@ /* Driver constants. */ /*===========================================================================*/ +/** + * @name Triggers selection + * @{ + */ #define ADC_CR2_EXTSEL_SRC(n) ((n) << 17) /**< @brief Trigger source. */ #define ADC_CR2_EXTSEL_SWSTART (7 << 17) /**< @brief Software trigger. */ +/** @} */ +/** + * @name Available analog channels + * @{ + */ #define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ #define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ #define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ @@ -56,7 +65,12 @@ #define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ #define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/ #define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */ +/** @} */ +/** + * @name Sampling rates + * @{ + */ #define ADC_SAMPLE_1P5 0 /**< @brief 1.5 cycles sampling time. */ #define ADC_SAMPLE_7P5 1 /**< @brief 7.5 cycles sampling time. */ #define ADC_SAMPLE_13P5 2 /**< @brief 13.5 cycles sampling time. */ @@ -65,6 +79,7 @@ #define ADC_SAMPLE_55P5 5 /**< @brief 55.5 cycles sampling time. */ #define ADC_SAMPLE_71P5 6 /**< @brief 71.5 cycles sampling time. */ #define ADC_SAMPLE_239P5 7 /**< @brief 239.5 cycles sampling time. */ +/** @} */ /*===========================================================================*/ /* Driver pre-compile time settings. */ @@ -206,7 +221,7 @@ typedef struct { uint32_t sqr2; /** * @brief ADC SQR3 register initialization data. - * @details Conversion group sequence 0...6. + * @details Conversion group sequence 1...6. */ uint32_t sqr3; } ADCConversionGroup; @@ -281,6 +296,10 @@ struct ADCDriver { /* Driver macros. */ /*===========================================================================*/ +/** + * @name Sequences building helper macros + * @{ + */ /** * @brief Number of channels in a conversion sequence. */ @@ -304,7 +323,12 @@ struct ADCDriver { #define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ #define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ #define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ +/** @} */ +/** + * @name Sampling rate settings helper macros + * @{ + */ #define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ #define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ #define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ @@ -326,6 +350,7 @@ struct ADCDriver { sampling time. */ #define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference sampling time. */ +/** @} */ /*===========================================================================*/ /* External declarations. */ diff --git a/os/hal/platforms/STM32L1xx/adc_lld.c b/os/hal/platforms/STM32L1xx/adc_lld.c new file mode 100644 index 000000000..9ccb198e4 --- /dev/null +++ b/os/hal/platforms/STM32L1xx/adc_lld.c @@ -0,0 +1,241 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32L1xx/adc_lld.c + * @brief STM32L1xx ADC subsystem low level driver source. + * + * @addtogroup ADC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief ADC1 driver identifier.*/ +#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) +ADCDriver ADCD1; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief ADC DMA ISR service routine. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { + + /* DMA errors handling.*/ +#if defined(STM32_ADC_DMA_ERROR_HOOK) + if ((flags & STM32_DMA_ISR_TEIF) != 0) { + STM32_ADC_DMA_ERROR_HOOK(spip); + } +#else + (void)flags; +#endif + if ((flags & STM32_DMA_ISR_HTIF) != 0) { + /* Half transfer processing.*/ + _adc_isr_half_code(adcp); + } + if ((flags & STM32_DMA_ISR_TCIF) != 0) { + /* Transfer complete processing.*/ + _adc_isr_full_code(adcp); + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ADC driver initialization. + * + * @notapi + */ +void adc_lld_init(void) { + +#if STM32_ADC_USE_ADC1 + /* Driver initialization.*/ + adcObjectInit(&ADCD1); + ADCD1.adc = ADC1; + ADCD1.dmastp = STM32_DMA1_STREAM1; + ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_TEIE | STM32_DMA_CR_EN; + ADC->CCR = STM32_ADC_ADCPRE; +#endif +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) { + + /* If in stopped state then enables the ADC and DMA clocks.*/ + if (adcp->state == ADC_STOP) { +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + bool_t b; + b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_ADC1_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, + (void *)adcp); + chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); + rccEnableADC1(FALSE); + } +#endif + + /* ADC initial setup, just resetting control registers in this case.*/ + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + } +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) { + + /* If in ready state then disables the ADC clock.*/ + if (adcp->state == ADC_READY) { +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + ADC1->CR2 = 0; + dmaStreamRelease(adcp->dmastp); + rccDisableADC1(FALSE); + } +#endif + } +} + +/** + * @brief Starts an ADC conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) { + uint32_t mode, n; + const ADCConversionGroup *grpp = adcp->grpp; + + /* DMA setup.*/ + mode = adcp->dmamode; + if (grpp->circular) + mode |= STM32_DMA_CR_CIRC; + if (adcp->depth > 1) { + /* If the buffer depth is greater than one then the half transfer interrupt + interrupt is enabled in order to allows streaming processing.*/ + mode |= STM32_DMA_CR_HTIE; + n = (uint32_t)grpp->num_channels * (uint32_t)adcp->depth; + } + else + n = (uint32_t)grpp->num_channels; + dmaStreamSetMemory0(adcp->dmastp, adcp->samples); + dmaStreamSetTransactionSize(adcp->dmastp, n); + dmaStreamSetMode(adcp->dmastp, mode); + + /* ADC setup.*/ + adcp->adc->SR = 0; + adcp->adc->CR1 = grpp->cr1 | ADC_CR1_SCAN; + adcp->adc->SMPR1 = grpp->smpr1; /* Writing SMPRx requires ADON=0. */ + adcp->adc->SMPR2 = grpp->smpr2; + adcp->adc->SMPR3 = grpp->smpr3; + adcp->adc->CR2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_CONT | ADC_CR2_ADON; + adcp->adc->SQR1 = grpp->sqr1; + adcp->adc->SQR2 = grpp->sqr2; + adcp->adc->SQR3 = grpp->sqr3; + adcp->adc->SQR4 = grpp->sqr4; + adcp->adc->SQR5 = grpp->sqr5; + /* Must wait the ADC to be ready for conversion, see 9.3.6 "Timing diagram" + in the Reference Manual.*/ + while ((adcp->adc->SR & ADC_SR_ADONS) == 0) + ; + /* ADC start by raising ADC_CR2_SWSTART.*/ + adcp->adc->CR2 = grpp->cr2 | ADC_CR2_SWSTART | ADC_CR2_DMA | + ADC_CR2_CONT | ADC_CR2_ADON; +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) { + + dmaStreamDisable(adcp->dmastp); + adcp->adc->CR2 = 0; +} + +/** + * @brief Enables the TSVREFE bit. + * @details The TSVREFE bit is required in order to sample the internal + * temperature sensor and internal reference voltage. + * @note This is an STM32-only functionality. + */ +void adcSTM32EnableTSVREFE(void) { + + ADC->CCR |= ADC_CCR_TSVREFE; +} + +/** + * @brief Disables the TSVREFE bit. + * @details The TSVREFE bit is required in order to sample the internal + * temperature sensor and internal reference voltage. + * @note This is an STM32-only functionality. + */ +void adcSTM32DisableTSVREFE(void) { + + ADC->CCR &= ~ADC_CCR_TSVREFE; +} + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/os/hal/platforms/STM32L1xx/adc_lld.h b/os/hal/platforms/STM32L1xx/adc_lld.h new file mode 100644 index 000000000..2889387ab --- /dev/null +++ b/os/hal/platforms/STM32L1xx/adc_lld.h @@ -0,0 +1,447 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32L1xx/adc_lld.h + * @brief STM32L1xx ADC subsystem low level driver header. + * + * @addtogroup ADC + * @{ + */ + +#ifndef _ADC_LLD_H_ +#define _ADC_LLD_H_ + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Triggers selection + * @{ + */ +#define ADC_CR2_EXTSEL_SRC(n) ((n) << 17) /**< @brief Trigger source. */ +#define ADC_CR2_EXTSEL_SWSTART (7 << 17) /**< @brief Software trigger. */ +/** @} */ + +/** + * @name ADC clock divider settings + * @{ + */ +#define ADC_CCR_ADCPRE_DIV1 0 +#define ADC_CCR_ADCPRE_DIV2 1 +#define ADC_CCR_ADCPRE_DIV4 2 +/** @} */ + +/** + * @name Available analog channels + * @{ + */ +#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ +#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ +#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ +#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ +#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ +#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ +#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ +#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ +#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ +#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ +#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ +#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ +#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ +#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ +#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ +#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ +#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/ +#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */ +#define ADC_CHANNEL_IN18 18 /**< @brief External analog input 18. */ +#define ADC_CHANNEL_IN19 19 /**< @brief External analog input 19. */ +#define ADC_CHANNEL_IN20 20 /**< @brief External analog input 20. */ +#define ADC_CHANNEL_IN21 21 /**< @brief External analog input 21. */ +#define ADC_CHANNEL_IN22 22 /**< @brief External analog input 22. */ +#define ADC_CHANNEL_IN23 23 /**< @brief External analog input 23. */ +#define ADC_CHANNEL_IN24 24 /**< @brief External analog input 24. */ +#define ADC_CHANNEL_IN25 25 /**< @brief External analog input 25. */ +/** @} */ + +/** + * @name Sampling rates + * @{ + */ +#define ADC_SAMPLE_4 0 /**< @brief 4 cycles sampling time. */ +#define ADC_SAMPLE_9 1 /**< @brief 9 cycles sampling time. */ +#define ADC_SAMPLE_16 2 /**< @brief 16 cycles sampling time. */ +#define ADC_SAMPLE_24 3 /**< @brief 24 cycles sampling time. */ +#define ADC_SAMPLE_48 4 /**< @brief 48 cycles sampling time. */ +#define ADC_SAMPLE_96 5 /**< @brief 96 cycles sampling time. */ +#define ADC_SAMPLE_192 6 /**< @brief 192 cycles sampling time. */ +#define ADC_SAMPLE_384 7 /**< @brief 384 cycles sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief ADC1 driver enable switch. + * @details If set to @p TRUE the support for ADC1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) +#define STM32_ADC_USE_ADC1 TRUE +#endif + +/** + * @brief ADC common clock divider. + * @note This setting is influenced by the VDDA voltage and other + * external conditions, please refer to the STM32L15x datasheet + * for more info.
+ * See section 6.3.15 "12-bit ADC characteristics". + */ +#if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__) +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV1 +#endif + +/** + * @brief ADC1 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC1 interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#endif + +/** + * @brief ADC DMA error hook. + * @note The default action for DMA errors is a system halt because DMA + * error can only happen because programming errors. + */ +#if !defined(STM32_ADC_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 +#error "ADC1 not present in the selected device" +#endif + +#if !STM32_ADC_USE_ADC1 +#error "ADC driver activated but no ADC peripheral assigned" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ADC sample data type. + */ +typedef uint16_t adcsample_t; + +/** + * @brief Channels number in a conversion group. + */ +typedef uint16_t adc_channels_num_t; + +/** + * @brief Type of a structure representing an ADC driver. + */ +typedef struct ADCDriver ADCDriver; + +/** + * @brief ADC notification callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] buffer pointer to the most recent samples data + * @param[in] n number of buffer rows available starting from @p buffer + */ +typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); + +/** + * @brief Conversion group configuration structure. + * @details This implementation-dependent structure describes a conversion + * operation. + * @note The use of this configuration structure requires knowledge of + * STM32 ADC cell registers interface, please refer to the STM32 + * reference manual for details. + */ +typedef struct { + /** + * @brief Enables the circular buffer mode for the group. + */ + bool_t circular; + /** + * @brief Number of the analog channels belonging to the conversion group. + */ + adc_channels_num_t num_channels; + /** + * @brief Callback function associated to the group or @p NULL. + */ + adccallback_t end_cb; + /* End of the mandatory fields.*/ + /** + * @brief ADC CR1 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR1_SCAN that is enforced inside the driver. + */ + uint32_t cr1; + /** + * @brief ADC CR2 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are + * enforced inside the driver. + */ + uint32_t cr2; + /** + * @brief ADC SMPR1 register initialization data. + * @details In this field must be specified the sample times for channels + * 20...25. + */ + uint32_t smpr1; + /** + * @brief ADC SMPR2 register initialization data. + * @details In this field must be specified the sample times for channels + * 10...19. + */ + uint32_t smpr2; + /** + * @brief ADC SMPR3 register initialization data. + * @details In this field must be specified the sample times for channels + * 0...9. + */ + uint32_t smpr3; + /** + * @brief ADC SQR1 register initialization data. + * @details Conversion group sequence 25...27 + sequence length. + */ + uint32_t sqr1; + /** + * @brief ADC SQR2 register initialization data. + * @details Conversion group sequence 19...24. + */ + uint32_t sqr2; + /** + * @brief ADC SQR3 register initialization data. + * @details Conversion group sequence 13...18. + */ + uint32_t sqr3; + /** + * @brief ADC SQR3 register initialization data. + * @details Conversion group sequence 7...12. + */ + uint32_t sqr4; + /** + * @brief ADC SQR3 register initialization data. + * @details Conversion group sequence 1...6. + */ + uint32_t sqr5; +} ADCConversionGroup; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + uint32_t dummy; +} ADCConfig; + +/** + * @brief Structure representing an ADC driver. + */ +struct ADCDriver { + /** + * @brief Driver state. + */ + adcstate_t state; + /** + * @brief Current configuration data. + */ + const ADCConfig *config; + /** + * @brief Current samples buffer pointer or @p NULL. + */ + adcsample_t *samples; + /** + * @brief Current samples buffer depth or @p 0. + */ + size_t depth; + /** + * @brief Current conversion group pointer or @p NULL. + */ + const ADCConversionGroup *grpp; +#if ADC_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif +#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* ADC_USE_MUTUAL_EXCLUSION */ +#if defined(ADC_DRIVER_EXT_FIELDS) + ADC_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the ADCx registers block. + */ + ADC_TypeDef *adc; + /** + * @brief Pointer to associated SMA channel. + */ + const stm32_dma_stream_t *dmastp; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Sequences building helper macros + * @{ + */ +/** + * @brief Number of channels in a conversion sequence. + */ +#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20) + +#define ADC_SQR5_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ +#define ADC_SQR5_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ +#define ADC_SQR5_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ +#define ADC_SQR5_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ +#define ADC_SQR5_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ +#define ADC_SQR5_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ + +#define ADC_SQR4_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ +#define ADC_SQR4_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ +#define ADC_SQR4_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ +#define ADC_SQR4_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ +#define ADC_SQR4_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ +#define ADC_SQR4_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ + +#define ADC_SQR3_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ +#define ADC_SQR3_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ +#define ADC_SQR3_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ +#define ADC_SQR3_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ +#define ADC_SQR3_SQ17_N(n) ((n) << 20) /**< @brief 17th channel in seq.*/ +#define ADC_SQR3_SQ18_N(n) ((n) << 25) /**< @brief 18th channel in seq.*/ + +#define ADC_SQR2_SQ19_N(n) ((n) << 0) /**< @brief 19th channel in seq.*/ +#define ADC_SQR2_SQ20_N(n) ((n) << 5) /**< @brief 20th channel in seq.*/ +#define ADC_SQR2_SQ21_N(n) ((n) << 10) /**< @brief 21th channel in seq.*/ +#define ADC_SQR2_SQ22_N(n) ((n) << 15) /**< @brief 22th channel in seq.*/ +#define ADC_SQR2_SQ23_N(n) ((n) << 20) /**< @brief 23th channel in seq.*/ +#define ADC_SQR2_SQ24_N(n) ((n) << 25) /**< @brief 24th channel in seq.*/ + +#define ADC_SQR1_SQ25_N(n) ((n) << 0) /**< @brief 25th channel in seq.*/ +#define ADC_SQR1_SQ26_N(n) ((n) << 5) /**< @brief 26th channel in seq.*/ +#define ADC_SQR1_SQ27_N(n) ((n) << 10) /**< @brief 27th channel in seq.*/ +/** @} */ + +/** + * @name Sampling rate settings helper macros + * @{ + */ +#define ADC_SMPR3_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ +#define ADC_SMPR3_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ +#define ADC_SMPR3_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ +#define ADC_SMPR3_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ +#define ADC_SMPR3_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ +#define ADC_SMPR3_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ +#define ADC_SMPR3_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ +#define ADC_SMPR3_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ +#define ADC_SMPR3_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ +#define ADC_SMPR3_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ + +#define ADC_SMPR2_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ +#define ADC_SMPR2_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ +#define ADC_SMPR2_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ +#define ADC_SMPR2_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ +#define ADC_SMPR2_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ +#define ADC_SMPR2_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ +#define ADC_SMPR2_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor + sampling time. */ +#define ADC_SMPR2_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference + sampling time. */ +#define ADC_SMPR2_SMP_AN18(n) ((n) << 24) /**< @brief AN18 sampling time. */ +#define ADC_SMPR2_SMP_AN19(n) ((n) << 27) /**< @brief AN19 sampling time. */ + +#define ADC_SMPR1_SMP_AN20(n) ((n) << 0) /**< @brief AN20 sampling time. */ +#define ADC_SMPR1_SMP_AN21(n) ((n) << 3) /**< @brief AN21 sampling time. */ +#define ADC_SMPR1_SMP_AN22(n) ((n) << 6) /**< @brief AN22 sampling time. */ +#define ADC_SMPR1_SMP_AN23(n) ((n) << 9) /**< @brief AN23 sampling time. */ +#define ADC_SMPR1_SMP_AN24(n) ((n) << 12) /**< @brief AN24 sampling time. */ +#define ADC_SMPR1_SMP_AN25(n) ((n) << 15) /**< @brief AN25 sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) +extern ADCDriver ADCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void adc_lld_init(void); + void adc_lld_start(ADCDriver *adcp); + void adc_lld_stop(ADCDriver *adcp); + void adc_lld_start_conversion(ADCDriver *adcp); + void adc_lld_stop_conversion(ADCDriver *adcp); + void adcSTM32EnableTSVREFE(void); + void adcSTM32DisableTSVREFE(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC */ + +#endif /* _ADC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index 2c3d05138..cf07e8036 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -423,7 +423,7 @@ /** * @brief Maximum HSECLK at current voltage setting. */ -#define STM32_HSECLK_MAX 32000000#if +#define STM32_HSECLK_MAX 32000000 /** * @brief Maximum SYSCLK at current voltage setting. diff --git a/os/hal/platforms/STM32L1xx/platform.mk b/os/hal/platforms/STM32L1xx/platform.mk index 047864a79..45e937ee5 100644 --- a/os/hal/platforms/STM32L1xx/platform.mk +++ b/os/hal/platforms/STM32L1xx/platform.mk @@ -1,5 +1,6 @@ # List of all the STM32L1xx platform files. PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32L1xx/adc_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \ diff --git a/os/ports/GCC/ARMCMx/port.dox b/os/ports/GCC/ARMCMx/port.dox index 13ab36d8a..709332a6b 100644 --- a/os/ports/GCC/ARMCMx/port.dox +++ b/os/ports/GCC/ARMCMx/port.dox @@ -70,8 +70,7 @@ * not globally masked but only interrupts with higher priority can preempt * the current handler. The processor is running in exception-privileged * mode. - * - Serving Fast Interrupt. This state is not implemented in the - * ARMv6-M implementation. + * - Serving Fast Interrupt. Not implemented in compact kernel mode. * - Serving Non-Maskable Interrupt. The Cortex-Mx has a specific * asynchronous NMI vector and several synchronous fault vectors that can * be considered belonging to this category. @@ -109,9 +108,13 @@ * not globally masked but only interrupts with higher priority can preempt * the current handler. The processor is running in exception-privileged * mode. - * - Serving Fast Interrupt. It is basically the same of the SRI state - * but it is not possible to switch to the I-Locked state because fast - * interrupts can preempt the kernel critical zone. + * - Serving Fast Interrupt. Fast interrupts are defined as interrupt + * sources having higher priority level than the kernel + * (@p CORTEX_BASEPRI_KERNEL). In this state is not possible to switch to + * the I-Locked state because fast interrupts can preempt the kernel + * critical zone.
+ * This state is not implemented in the ARMv6-M implementation because + * priority masking is not present in this architecture. * - Serving Non-Maskable Interrupt. The Cortex-Mx has a specific * asynchronous NMI vector and several synchronous fault vectors that can * be considered belonging to this category. @@ -214,20 +217,28 @@ * @section ARMCMx_STARTUP_2 Expected linker symbols * The startup code starts at the symbol @p ResetHandler and expects the * following symbols to be defined in the linker script: - * - @p __ram_end__ End of RAM. - * - @p __main_stack_base__ Main stack lower boundary. - * - @p __main_stack_end__ Main stack initial position. - * - @p __process_stack_base__ Process stack lower boundary. - * - @p __process_stack_end__ Process stack initial position. - * - @p _textdata Address of the data segment source read only data. - * - @p _data Start of the data segment. - * - @p _edata End of the data segment end location. - * - @p _bss_start Start of the BSS. - * - @p _bss_end End of the BSS segment. - * - @p __init_array_start Start of the constructors array. - * - @p __init_array_end End of the constructors array. - * - @p __fini_array_start Start of the destructors array. - * - @p __fini_array_end End of the destructors array. + * - @p __ram_end__, end of RAM. + * - @p __main_stack_base__, main stack lower boundary. + * - @p __main_stack_end__, main stack initial position. + * - @p __process_stack_base__, process stack lower boundary. + * - @p __process_stack_end__, process stack initial position. + * - @p _textdata, address of the data segment source read only data. + * - @p _data, start of the data segment. + * - @p _edata, end of the data segment end location. + * - @p _bss_start, start of the BSS. + * - @p _bss_end, end of the BSS segment. + * - @p __init_array_start, start of the constructors array. + * - @p __init_array_end, end of the constructors array. + * - @p __fini_array_start, start of the destructors array. + * - @p __fini_array_end, end of the destructors array. + * . + * Additionally the kernel expects the following symbols: + * - @p __main_thread_stack_base__, this symbol is required when the + * stack checking is enabled (CH_DBG_ENABLE_STACK_CHECK==TRUE), + * it is an alias of @p __process_stack_base__ in this port. + * - @p __heap_base__ and @p __heap_end__, those symbols are required + * if the memory core manager is enabled (CH_USE_MEMCORE==TRUE) + * with a default core size set to zero (CH_MEMCORE_SIZE==0). * . * @ingroup ARMCMx */ -- cgit v1.2.3