From 9bbb4ac554e3a32d5d9ffad9b4901e2e8ddb99ed Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Mon, 29 Apr 2013 09:17:13 +0000
Subject: Added wait states to the RAM accesses as specified on the DS.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5643 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/SPC564Axx/hal_lld.c | 13 +++++++------
 os/hal/platforms/SPC564Axx/hal_lld.h |  9 +++++++++
 os/ports/GCC/PPC/SPC564Axx/core.s    |  2 +-
 3 files changed, 17 insertions(+), 7 deletions(-)

(limited to 'os')

diff --git a/os/hal/platforms/SPC564Axx/hal_lld.c b/os/hal/platforms/SPC564Axx/hal_lld.c
index 2115116c4..c6c67ba31 100644
--- a/os/hal/platforms/SPC564Axx/hal_lld.c
+++ b/os/hal/platforms/SPC564Axx/hal_lld.c
@@ -53,12 +53,6 @@
 void hal_lld_init(void) {
   uint32_t n;
 
-  /* FLASH wait states and prefetching setup.*/
-  FLASH_A.BIUCR.R  = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
-  FLASH_A.BIUCR2.R = 0;
-  FLASH_B.BIUCR.R  = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
-  FLASH_B.BIUCR2.R = 0;
-
   /* The SRAM is parked on the load/store port, for some unknown reason it
      is defaulted on the instructions port and this kills performance.*/
   XBAR.SGPCR2.B.PARK = 1;               /* RAM slave on load/store port.*/
@@ -110,6 +104,13 @@ void hal_lld_init(void) {
  */
 void spc_clock_init(void) {
 
+  /* Setting up RAM/Flash wait states and the prefetching bits.*/
+  ECSM.MUDCR.R = SPC5_RAM_WS;
+  FLASH_A.BIUCR.R  = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
+  FLASH_A.BIUCR2.R = 0;
+  FLASH_B.BIUCR.R  = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
+  FLASH_B.BIUCR2.R = 0;
+
 #if !SPC5_NO_INIT
   /* PLL activation.*/
   FMPLL.ESYNCR1.B.EMODE     = 1;                    /* Enhanced mode on.    */
diff --git a/os/hal/platforms/SPC564Axx/hal_lld.h b/os/hal/platforms/SPC564Axx/hal_lld.h
index d2ee43f55..5612c3954 100644
--- a/os/hal/platforms/SPC564Axx/hal_lld.h
+++ b/os/hal/platforms/SPC564Axx/hal_lld.h
@@ -241,6 +241,15 @@
 #define SPC5_FLASH_WS       (BIUCR_APC_4 | BIUCR_RWSC_4 | BIUCR_WWSC_3)
 #endif
 
+/**
+ * @brief   RAM wait states are a function of the system clock.
+ */
+#if (SPC5_SYSCLK <= 98000000) || defined(__DOXYGEN__)
+#define SPC5_RAM_WS         0
+#else
+#define SPC5_RAM_WS         0x40000000
+#endif
+
 /*===========================================================================*/
 /* Driver data structures and types.                                         */
 /*===========================================================================*/
diff --git a/os/ports/GCC/PPC/SPC564Axx/core.s b/os/ports/GCC/PPC/SPC564Axx/core.s
index eb07085ae..da14e7236 100644
--- a/os/ports/GCC/PPC/SPC564Axx/core.s
+++ b/os/ports/GCC/PPC/SPC564Axx/core.s
@@ -111,7 +111,7 @@
  */
 #define TLB0_MAS0               (MAS0_TBLMAS_TBL | MAS0_ESEL(0))
 #define TLB0_MAS1               (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K)
-#define TLB0_MAS2               (MAS2_EPN(0x40000000) | MAS2_VLE | MAS2_I)
+#define TLB0_MAS2               (MAS2_EPN(0x40000000) | MAS2_VLE)
 #define TLB0_MAS3               (MAS3_RPN(0x40000000) |                     \
                                  MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW |    \
                                  MAS3_UR | MAS3_SR)
-- 
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