From 92f59d89f168c8e5aa01fee358e1e0d7b8a7aa72 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 21 Apr 2014 09:25:40 +0000 Subject: Fixed STM32F401 support. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6856 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F4xx/ext_lld_isr.c | 6 + os/hal/platforms/STM32F4xx/hal_lld.h | 30 ++++- os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F401xC.ld | 149 ++++++++++++++++++++++++ 3 files changed, 183 insertions(+), 2 deletions(-) create mode 100644 os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F401xC.ld (limited to 'os') diff --git a/os/hal/platforms/STM32F4xx/ext_lld_isr.c b/os/hal/platforms/STM32F4xx/ext_lld_isr.c index 5576ff834..620d7370d 100644 --- a/os/hal/platforms/STM32F4xx/ext_lld_isr.c +++ b/os/hal/platforms/STM32F4xx/ext_lld_isr.c @@ -239,6 +239,7 @@ CH_IRQ_HANDLER(ETH_WKUP_IRQHandler) { CH_IRQ_EPILOGUE(); } +#if !defined(STM32F401xx) /** * @brief EXTI[20] interrupt handler (OTG_HS_WKUP). * @@ -268,6 +269,7 @@ CH_IRQ_HANDLER(TAMPER_STAMP_IRQHandler) { CH_IRQ_EPILOGUE(); } +#endif /* defined(STM32F401xx) */ /** * @brief EXTI[22] interrupt handler (RTC_WKUP). @@ -317,10 +319,12 @@ void ext_lld_exti_irq_enable(void) { CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); nvicEnableVector(ETH_WKUP_IRQn, CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY)); +#if !defined(STM32F401xx) nvicEnableVector(OTG_HS_WKUP_IRQn, CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY)); nvicEnableVector(TAMP_STAMP_IRQn, CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_IRQ_PRIORITY)); +#endif /* defined(STM32F401xx) */ nvicEnableVector(RTC_WKUP_IRQn, CORTEX_PRIORITY_MASK(STM32_EXT_EXTI22_IRQ_PRIORITY)); } @@ -343,8 +347,10 @@ void ext_lld_exti_irq_disable(void) { nvicDisableVector(RTC_Alarm_IRQn); nvicDisableVector(OTG_FS_WKUP_IRQn); nvicDisableVector(ETH_WKUP_IRQn); +#if !defined(STM32F401xx) nvicDisableVector(OTG_HS_WKUP_IRQn); nvicDisableVector(TAMP_STAMP_IRQn); +#endif /* defined(STM32F401xx) */ nvicDisableVector(RTC_WKUP_IRQn); } diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index 18fd29c86..70c333cf8 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -491,7 +491,8 @@ STM32_DMA_STREAM_ID_MSK(1, 7)) #define STM32_SPI3_TX_DMA_CHN 0x00000000 -#if defined(STM32F427_437xx) || defined(STM32F429_439xx) +#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || \ + defined(STM32F401xx) #define STM32_HAS_SPI4 TRUE #define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) | \ STM32_DMA_STREAM_ID_MSK(2, 3)) @@ -499,7 +500,11 @@ #define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) | \ STM32_DMA_STREAM_ID_MSK(2, 4)) #define STM32_SPI4_TX_DMA_CHN 0x00050040 +#else +#define STM32_HAS_SPI4 FALSE +#endif +#if defined(STM32F427_437xx) || defined(STM32F429_439xx) #define STM32_HAS_SPI5 TRUE #define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \ STM32_DMA_STREAM_ID_MSK(2, 5)) @@ -515,7 +520,6 @@ #define STM32_SPI6_TX_DMA_CHN 0x00100000 #else /* !(defined(STM32F427_437xx) || defined(STM32F429_439xx)) */ -#define STM32_HAS_SPI4 FALSE #define STM32_HAS_SPI5 FALSE #define STM32_HAS_SPI6 FALSE #endif /* !(defined(STM32F427_437xx) || defined(STM32F429_439xx)) */ @@ -526,15 +530,27 @@ #define STM32_HAS_TIM3 TRUE #define STM32_HAS_TIM4 TRUE #define STM32_HAS_TIM5 TRUE +#if !defined(STM32F401xx) #define STM32_HAS_TIM6 TRUE #define STM32_HAS_TIM7 TRUE #define STM32_HAS_TIM8 TRUE +#else /* defined(STM32F401xx) */ +#define STM32_HAS_TIM6 FALSE +#define STM32_HAS_TIM7 FALSE +#define STM32_HAS_TIM8 FALSE +#endif /* defined(STM32F401xx) */ #define STM32_HAS_TIM9 TRUE #define STM32_HAS_TIM10 TRUE #define STM32_HAS_TIM11 TRUE +#if !defined(STM32F401xx) #define STM32_HAS_TIM12 TRUE #define STM32_HAS_TIM13 TRUE #define STM32_HAS_TIM14 TRUE +#else /* defined(STM32F401xx) */ +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#endif /* defined(STM32F401xx) */ #define STM32_HAS_TIM15 FALSE #define STM32_HAS_TIM16 FALSE #define STM32_HAS_TIM17 FALSE @@ -555,6 +571,7 @@ #define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) #define STM32_USART2_TX_DMA_CHN 0x04000000 +#if !defined(STM32F401xx) #define STM32_HAS_USART3 TRUE #define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1)) #define STM32_USART3_RX_DMA_CHN 0x00000040 @@ -573,6 +590,11 @@ #define STM32_UART5_RX_DMA_CHN 0x00000004 #define STM32_UART5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) #define STM32_UART5_TX_DMA_CHN 0x40000000 +#else /* defined(STM32F401xx) */ +#define STM32_HAS_USART3 FALSE +#define STM32_HAS_UART4 FALSE +#define STM32_HAS_UART5 FALSE +#endif /* defined(STM32F401xx) */ #define STM32_HAS_USART6 TRUE #define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) | \ @@ -585,7 +607,11 @@ /* USB attributes.*/ #define STM32_HAS_USB FALSE #define STM32_HAS_OTG1 TRUE +#if !defined(STM32F401xx) #define STM32_HAS_OTG2 TRUE +#else /* defined(STM32F401xx) */ +#define STM32_HAS_OTG2 FALSE +#endif /* defined(STM32F401xx) */ /** @} */ /*===========================================================================*/ diff --git a/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F401xC.ld b/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F401xC.ld new file mode 100644 index 000000000..008b0c5dd --- /dev/null +++ b/os/ports/GCC/ARMCMx/STM32F4xx/ld/STM32F401xC.ld @@ -0,0 +1,149 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * ST32F401xC memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; + +MEMORY +{ + flash : org = 0x08000000, len = 256k + ram : org = 0x20000000, len = 64k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +ENTRY(ResetHandler) + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + . = ALIGN(4); + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; -- cgit v1.2.3