From 92c0a0e8514929e351d28e39bb157f61a63f0819 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 12 Nov 2013 10:05:38 +0000
Subject: Fixed bug #439.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6460 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F0xx/stm32_dma.c | 10 +++++-----
 os/hal/platforms/STM32F1xx/stm32_dma.c | 28 ++++++++++++++--------------
 os/hal/platforms/STM32F30x/stm32_dma.c | 24 ++++++++++++------------
 os/hal/platforms/STM32F37x/stm32_dma.c | 24 ++++++++++++------------
 os/hal/platforms/STM32F4xx/stm32_dma.c | 32 ++++++++++++++++----------------
 os/hal/platforms/STM32L1xx/stm32_dma.c | 14 +++++++-------
 6 files changed, 66 insertions(+), 66 deletions(-)

(limited to 'os')

diff --git a/os/hal/platforms/STM32F0xx/stm32_dma.c b/os/hal/platforms/STM32F0xx/stm32_dma.c
index 2305d952d..167321730 100644
--- a/os/hal/platforms/STM32F0xx/stm32_dma.c
+++ b/os/hal/platforms/STM32F0xx/stm32_dma.c
@@ -115,7 +115,7 @@ CH_IRQ_HANDLER(Vector64) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 0;
+  DMA1->IFCR = flags << 0;
   if (dma_isr_redir[0].dma_func)
     dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
 
@@ -135,7 +135,7 @@ CH_IRQ_HANDLER(Vector68) {
   /* Check on channel 2.*/
   flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
   if (flags & STM32_DMA_ISR_MASK) {
-    DMA1->IFCR = STM32_DMA_ISR_MASK << 4;
+    DMA1->IFCR = flags << 4;
     if (dma_isr_redir[1].dma_func)
       dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
   }
@@ -143,7 +143,7 @@ CH_IRQ_HANDLER(Vector68) {
   /* Check on channel 3.*/
   flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
   if (flags & STM32_DMA_ISR_MASK) {
-    DMA1->IFCR = STM32_DMA_ISR_MASK << 8;
+    DMA1->IFCR = flags << 8;
     if (dma_isr_redir[2].dma_func)
       dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
   }
@@ -164,7 +164,7 @@ CH_IRQ_HANDLER(Vector6C) {
   /* Check on channel 4.*/
   flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
   if (flags & STM32_DMA_ISR_MASK) {
-    DMA1->IFCR = STM32_DMA_ISR_MASK << 12;
+    DMA1->IFCR = flags << 12;
     if (dma_isr_redir[3].dma_func)
       dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
   }
@@ -172,7 +172,7 @@ CH_IRQ_HANDLER(Vector6C) {
   /* Check on channel 5.*/
   flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
   if (flags & STM32_DMA_ISR_MASK) {
-    DMA1->IFCR = STM32_DMA_ISR_MASK << 16;
+    DMA1->IFCR = flags << 16;
     if (dma_isr_redir[4].dma_func)
       dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
   }
diff --git a/os/hal/platforms/STM32F1xx/stm32_dma.c b/os/hal/platforms/STM32F1xx/stm32_dma.c
index 5f94f3392..d4141d114 100644
--- a/os/hal/platforms/STM32F1xx/stm32_dma.c
+++ b/os/hal/platforms/STM32F1xx/stm32_dma.c
@@ -129,7 +129,7 @@ CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 0;
+  DMA1->IFCR = flags << 0;
   if (dma_isr_redir[0].dma_func)
     dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
 
@@ -147,7 +147,7 @@ CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 4;
+  DMA1->IFCR = flags << 4;
   if (dma_isr_redir[1].dma_func)
     dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
 
@@ -165,7 +165,7 @@ CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 8;
+  DMA1->IFCR = flags << 8;
   if (dma_isr_redir[2].dma_func)
     dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
 
@@ -183,7 +183,7 @@ CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 12;
+  DMA1->IFCR = flags << 12;
   if (dma_isr_redir[3].dma_func)
     dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
 
@@ -201,7 +201,7 @@ CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 16;
+  DMA1->IFCR = flags << 16;
   if (dma_isr_redir[4].dma_func)
     dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
 
@@ -219,7 +219,7 @@ CH_IRQ_HANDLER(DMA1_Ch6_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 20;
+  DMA1->IFCR = flags << 20;
   if (dma_isr_redir[5].dma_func)
     dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
 
@@ -237,7 +237,7 @@ CH_IRQ_HANDLER(DMA1_Ch7_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 24;
+  DMA1->IFCR = flags << 24;
   if (dma_isr_redir[6].dma_func)
     dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
 
@@ -256,7 +256,7 @@ CH_IRQ_HANDLER(DMA2_Ch1_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 0;
+  DMA2->IFCR = flags << 0;
   if (dma_isr_redir[7].dma_func)
     dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
 
@@ -274,7 +274,7 @@ CH_IRQ_HANDLER(DMA2_Ch2_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 4;
+  DMA2->IFCR = flags << 4;
   if (dma_isr_redir[8].dma_func)
     dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
 
@@ -292,7 +292,7 @@ CH_IRQ_HANDLER(DMA2_Ch3_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 8;
+  DMA2->IFCR = flags << 8;
   if (dma_isr_redir[9].dma_func)
     dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
 
@@ -311,7 +311,7 @@ CH_IRQ_HANDLER(DMA2_Ch4_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 12;
+  DMA2->IFCR = flags << 12;
   if (dma_isr_redir[10].dma_func)
     dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
 
@@ -329,7 +329,7 @@ CH_IRQ_HANDLER(DMA2_Ch5_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 16;
+  DMA2->IFCR = flags << 16;
   if (dma_isr_redir[11].dma_func)
     dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
 
@@ -351,7 +351,7 @@ CH_IRQ_HANDLER(DMA2_Ch4_5_IRQHandler) {
   /* Check on channel 4.*/
   flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
   if (flags & STM32_DMA_ISR_MASK) {
-    DMA2->IFCR = STM32_DMA_ISR_MASK << 12;
+    DMA2->IFCR = flags << 12;
     if (dma_isr_redir[10].dma_func)
       dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
   }
@@ -359,7 +359,7 @@ CH_IRQ_HANDLER(DMA2_Ch4_5_IRQHandler) {
   /* Check on channel 5.*/
   flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
   if (flags & STM32_DMA_ISR_MASK) {
-    DMA2->IFCR = STM32_DMA_ISR_MASK << 16;
+    DMA2->IFCR = flags << 16;
     if (dma_isr_redir[11].dma_func)
       dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
   }
diff --git a/os/hal/platforms/STM32F30x/stm32_dma.c b/os/hal/platforms/STM32F30x/stm32_dma.c
index 71777583d..95181c90f 100644
--- a/os/hal/platforms/STM32F30x/stm32_dma.c
+++ b/os/hal/platforms/STM32F30x/stm32_dma.c
@@ -122,7 +122,7 @@ CH_IRQ_HANDLER(Vector6C) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 0;
+  DMA1->IFCR = flags << 0;
   if (dma_isr_redir[0].dma_func)
     dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
 
@@ -140,7 +140,7 @@ CH_IRQ_HANDLER(Vector70) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 4;
+  DMA1->IFCR = flags << 4;
   if (dma_isr_redir[1].dma_func)
     dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
 
@@ -158,7 +158,7 @@ CH_IRQ_HANDLER(Vector74) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 8;
+  DMA1->IFCR = flags << 8;
   if (dma_isr_redir[2].dma_func)
     dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
 
@@ -176,7 +176,7 @@ CH_IRQ_HANDLER(Vector78) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 12;
+  DMA1->IFCR = flags << 12;
   if (dma_isr_redir[3].dma_func)
     dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
 
@@ -194,7 +194,7 @@ CH_IRQ_HANDLER(Vector7C) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 16;
+  DMA1->IFCR = flags << 16;
   if (dma_isr_redir[4].dma_func)
     dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
 
@@ -212,7 +212,7 @@ CH_IRQ_HANDLER(Vector80) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 20;
+  DMA1->IFCR = flags << 20;
   if (dma_isr_redir[5].dma_func)
     dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
 
@@ -230,7 +230,7 @@ CH_IRQ_HANDLER(Vector84) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 24;
+  DMA1->IFCR = flags << 24;
   if (dma_isr_redir[6].dma_func)
     dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
 
@@ -248,7 +248,7 @@ CH_IRQ_HANDLER(Vector120) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 0;
+  DMA2->IFCR = flags << 0;
   if (dma_isr_redir[7].dma_func)
     dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
 
@@ -266,7 +266,7 @@ CH_IRQ_HANDLER(Vector124) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 4;
+  DMA2->IFCR = flags << 4;
   if (dma_isr_redir[8].dma_func)
     dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
 
@@ -284,7 +284,7 @@ CH_IRQ_HANDLER(Vector128) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 8;
+  DMA2->IFCR = flags << 8;
   if (dma_isr_redir[9].dma_func)
     dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
 
@@ -302,7 +302,7 @@ CH_IRQ_HANDLER(Vector12C) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 12;
+  DMA2->IFCR = flags << 12;
   if (dma_isr_redir[10].dma_func)
     dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
 
@@ -320,7 +320,7 @@ CH_IRQ_HANDLER(Vector130) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 16;
+  DMA2->IFCR = flags << 16;
   if (dma_isr_redir[11].dma_func)
     dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
 
diff --git a/os/hal/platforms/STM32F37x/stm32_dma.c b/os/hal/platforms/STM32F37x/stm32_dma.c
index b9ce0ddfc..7cfabfe72 100644
--- a/os/hal/platforms/STM32F37x/stm32_dma.c
+++ b/os/hal/platforms/STM32F37x/stm32_dma.c
@@ -122,7 +122,7 @@ CH_IRQ_HANDLER(Vector6C) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 0;
+  DMA1->IFCR = flags << 0;
   if (dma_isr_redir[0].dma_func)
     dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
 
@@ -140,7 +140,7 @@ CH_IRQ_HANDLER(Vector70) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 4;
+  DMA1->IFCR = flags << 4;
   if (dma_isr_redir[1].dma_func)
     dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
 
@@ -158,7 +158,7 @@ CH_IRQ_HANDLER(Vector74) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 8;
+  DMA1->IFCR = flags << 8;
   if (dma_isr_redir[2].dma_func)
     dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
 
@@ -176,7 +176,7 @@ CH_IRQ_HANDLER(Vector78) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 12;
+  DMA1->IFCR = flags << 12;
   if (dma_isr_redir[3].dma_func)
     dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
 
@@ -194,7 +194,7 @@ CH_IRQ_HANDLER(Vector7C) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 16;
+  DMA1->IFCR = flags << 16;
   if (dma_isr_redir[4].dma_func)
     dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
 
@@ -212,7 +212,7 @@ CH_IRQ_HANDLER(Vector80) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 20;
+  DMA1->IFCR = flags << 20;
   if (dma_isr_redir[5].dma_func)
     dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
 
@@ -230,7 +230,7 @@ CH_IRQ_HANDLER(Vector84) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 24;
+  DMA1->IFCR = flags << 24;
   if (dma_isr_redir[6].dma_func)
     dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
 
@@ -248,7 +248,7 @@ CH_IRQ_HANDLER(Vector120) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 0;
+  DMA2->IFCR = flags << 0;
   if (dma_isr_redir[7].dma_func)
     dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
 
@@ -266,7 +266,7 @@ CH_IRQ_HANDLER(Vector124) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 4;
+  DMA2->IFCR = flags << 4;
   if (dma_isr_redir[8].dma_func)
     dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
 
@@ -284,7 +284,7 @@ CH_IRQ_HANDLER(Vector128) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 8;
+  DMA2->IFCR = flags << 8;
   if (dma_isr_redir[9].dma_func)
     dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
 
@@ -302,7 +302,7 @@ CH_IRQ_HANDLER(Vector12C) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 12;
+  DMA2->IFCR = flags << 12;
   if (dma_isr_redir[10].dma_func)
     dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
 
@@ -320,7 +320,7 @@ CH_IRQ_HANDLER(Vector130) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 16;
+  DMA2->IFCR = flags << 16;
   if (dma_isr_redir[11].dma_func)
     dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
 
diff --git a/os/hal/platforms/STM32F4xx/stm32_dma.c b/os/hal/platforms/STM32F4xx/stm32_dma.c
index cd5f5b2e1..1d6ce01bd 100644
--- a/os/hal/platforms/STM32F4xx/stm32_dma.c
+++ b/os/hal/platforms/STM32F4xx/stm32_dma.c
@@ -131,7 +131,7 @@ CH_IRQ_HANDLER(DMA1_Stream0_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->LISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA1->LIFCR = STM32_DMA_ISR_MASK << 0;
+  DMA1->LIFCR = flags << 0;
   if (dma_isr_redir[0].dma_func)
     dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
 
@@ -149,7 +149,7 @@ CH_IRQ_HANDLER(DMA1_Stream1_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->LISR >> 6) & STM32_DMA_ISR_MASK;
-  DMA1->LIFCR = STM32_DMA_ISR_MASK << 6;
+  DMA1->LIFCR = flags << 6;
   if (dma_isr_redir[1].dma_func)
     dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
 
@@ -167,7 +167,7 @@ CH_IRQ_HANDLER(DMA1_Stream2_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->LISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA1->LIFCR = STM32_DMA_ISR_MASK << 16;
+  DMA1->LIFCR = flags << 16;
   if (dma_isr_redir[2].dma_func)
     dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
 
@@ -185,7 +185,7 @@ CH_IRQ_HANDLER(DMA1_Stream3_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->LISR >> 22) & STM32_DMA_ISR_MASK;
-  DMA1->LIFCR = STM32_DMA_ISR_MASK << 22;
+  DMA1->LIFCR = flags << 22;
   if (dma_isr_redir[3].dma_func)
     dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
 
@@ -203,7 +203,7 @@ CH_IRQ_HANDLER(DMA1_Stream4_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->HISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA1->HIFCR = STM32_DMA_ISR_MASK << 0;
+  DMA1->HIFCR = flags << 0;
   if (dma_isr_redir[4].dma_func)
     dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
 
@@ -221,7 +221,7 @@ CH_IRQ_HANDLER(DMA1_Stream5_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->HISR >> 6) & STM32_DMA_ISR_MASK;
-  DMA1->HIFCR = STM32_DMA_ISR_MASK << 6;
+  DMA1->HIFCR = flags << 6;
   if (dma_isr_redir[5].dma_func)
     dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
 
@@ -239,7 +239,7 @@ CH_IRQ_HANDLER(DMA1_Stream6_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->HISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA1->HIFCR = STM32_DMA_ISR_MASK << 16;
+  DMA1->HIFCR = flags << 16;
   if (dma_isr_redir[6].dma_func)
     dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
 
@@ -257,7 +257,7 @@ CH_IRQ_HANDLER(DMA1_Stream7_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->HISR >> 22) & STM32_DMA_ISR_MASK;
-  DMA1->HIFCR = STM32_DMA_ISR_MASK << 22;
+  DMA1->HIFCR = flags << 22;
   if (dma_isr_redir[7].dma_func)
     dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
 
@@ -275,7 +275,7 @@ CH_IRQ_HANDLER(DMA2_Stream0_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA2->LISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA2->LIFCR = STM32_DMA_ISR_MASK << 0;
+  DMA2->LIFCR = flags << 0;
   if (dma_isr_redir[8].dma_func)
     dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
 
@@ -293,7 +293,7 @@ CH_IRQ_HANDLER(DMA2_Stream1_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA2->LISR >> 6) & STM32_DMA_ISR_MASK;
-  DMA2->LIFCR = STM32_DMA_ISR_MASK << 6;
+  DMA2->LIFCR = flags << 6;
   if (dma_isr_redir[9].dma_func)
     dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
 
@@ -311,7 +311,7 @@ CH_IRQ_HANDLER(DMA2_Stream2_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA2->LISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA2->LIFCR = STM32_DMA_ISR_MASK << 16;
+  DMA2->LIFCR = flags << 16;
   if (dma_isr_redir[10].dma_func)
     dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
 
@@ -329,7 +329,7 @@ CH_IRQ_HANDLER(DMA2_Stream3_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA2->LISR >> 22) & STM32_DMA_ISR_MASK;
-  DMA2->LIFCR = STM32_DMA_ISR_MASK << 22;
+  DMA2->LIFCR = flags << 22;
   if (dma_isr_redir[11].dma_func)
     dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
 
@@ -347,7 +347,7 @@ CH_IRQ_HANDLER(DMA2_Stream4_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA2->HISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA2->HIFCR = STM32_DMA_ISR_MASK << 0;
+  DMA2->HIFCR = flags << 0;
   if (dma_isr_redir[12].dma_func)
     dma_isr_redir[12].dma_func(dma_isr_redir[12].dma_param, flags);
 
@@ -365,7 +365,7 @@ CH_IRQ_HANDLER(DMA2_Stream5_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA2->HISR >> 6) & STM32_DMA_ISR_MASK;
-  DMA2->HIFCR = STM32_DMA_ISR_MASK << 6;
+  DMA2->HIFCR = flags << 6;
   if (dma_isr_redir[13].dma_func)
     dma_isr_redir[13].dma_func(dma_isr_redir[13].dma_param, flags);
 
@@ -383,7 +383,7 @@ CH_IRQ_HANDLER(DMA2_Stream6_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA2->HISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA2->HIFCR = STM32_DMA_ISR_MASK << 16;
+  DMA2->HIFCR = flags << 16;
   if (dma_isr_redir[14].dma_func)
     dma_isr_redir[14].dma_func(dma_isr_redir[14].dma_param, flags);
 
@@ -401,7 +401,7 @@ CH_IRQ_HANDLER(DMA2_Stream7_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA2->HISR >> 22) & STM32_DMA_ISR_MASK;
-  DMA2->HIFCR = STM32_DMA_ISR_MASK << 22;
+  DMA2->HIFCR = flags << 22;
   if (dma_isr_redir[15].dma_func)
     dma_isr_redir[15].dma_func(dma_isr_redir[15].dma_param, flags);
 
diff --git a/os/hal/platforms/STM32L1xx/stm32_dma.c b/os/hal/platforms/STM32L1xx/stm32_dma.c
index 31b475589..5c74e9227 100644
--- a/os/hal/platforms/STM32L1xx/stm32_dma.c
+++ b/os/hal/platforms/STM32L1xx/stm32_dma.c
@@ -117,7 +117,7 @@ CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 0;
+  DMA1->IFCR = flags << 0;
   if (dma_isr_redir[0].dma_func)
     dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
 
@@ -135,7 +135,7 @@ CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 4;
+  DMA1->IFCR = flags << 4;
   if (dma_isr_redir[1].dma_func)
     dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
 
@@ -153,7 +153,7 @@ CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 8;
+  DMA1->IFCR = flags << 8;
   if (dma_isr_redir[2].dma_func)
     dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
 
@@ -171,7 +171,7 @@ CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 12;
+  DMA1->IFCR = flags << 12;
   if (dma_isr_redir[3].dma_func)
     dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
 
@@ -189,7 +189,7 @@ CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 16;
+  DMA1->IFCR = flags << 16;
   if (dma_isr_redir[4].dma_func)
     dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
 
@@ -207,7 +207,7 @@ CH_IRQ_HANDLER(DMA1_Ch6_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 20;
+  DMA1->IFCR = flags << 20;
   if (dma_isr_redir[5].dma_func)
     dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
 
@@ -225,7 +225,7 @@ CH_IRQ_HANDLER(DMA1_Ch7_IRQHandler) {
   CH_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 24;
+  DMA1->IFCR = flags << 24;
   if (dma_isr_redir[6].dma_func)
     dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
 
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