From 5e18cf994d989b1bed035b98e5957e2c68e518cb Mon Sep 17 00:00:00 2001 From: barthess Date: Sun, 27 Nov 2011 22:18:47 +0000 Subject: I2C. Nop. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3542 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/i2c_lld.c | 5 +++++ os/hal/platforms/STM32F4xx/platform.mk | 1 + 2 files changed, 6 insertions(+) (limited to 'os') diff --git a/os/hal/platforms/STM32/i2c_lld.c b/os/hal/platforms/STM32/i2c_lld.c index c5cd2308f..93b4c4061 100644 --- a/os/hal/platforms/STM32/i2c_lld.c +++ b/os/hal/platforms/STM32/i2c_lld.c @@ -590,8 +590,13 @@ void i2c_lld_set_clock(I2CDriver *i2cp) { regCR2 = i2cp->id_i2c->CR2; /* Get the I2Cx CR2 value */ regCR2 &= (uint16_t)~I2C_CR2_FREQ; /* Clear frequency FREQ[5:0] bits */ freq = (uint16_t)(STM32_PCLK1 / 1000000); /* Set frequency bits depending on pclk1 value */ +#ifdef STM32F4XX + chDbgCheck((freq >= 2) && (freq <= 42), + "i2c_lld_set_clock() : Peripheral clock freq. out of range"); +#else chDbgCheck((freq >= 2) && (freq <= 36), "i2c_lld_set_clock() : Peripheral clock freq. out of range"); +#endif regCR2 |= freq; i2cp->id_i2c->CR2 = regCR2; diff --git a/os/hal/platforms/STM32F4xx/platform.mk b/os/hal/platforms/STM32F4xx/platform.mk index 7acce0172..449b40731 100644 --- a/os/hal/platforms/STM32F4xx/platform.mk +++ b/os/hal/platforms/STM32F4xx/platform.mk @@ -9,6 +9,7 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F4xx/stm32_dma.c \ ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/uart_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/i2c_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c # Required include directories -- cgit v1.2.3 From 2ad41625e0dc9ee78dadba2f2527857f9476e40d Mon Sep 17 00:00:00 2001 From: barthess Date: Thu, 1 Dec 2011 14:32:59 +0000 Subject: I2C. Nop. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3545 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/src/i2c.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'os') diff --git a/os/hal/src/i2c.c b/os/hal/src/i2c.c index 9ce2cc76f..abd3252cf 100644 --- a/os/hal/src/i2c.c +++ b/os/hal/src/i2c.c @@ -182,6 +182,7 @@ void i2cMasterTransmit(I2CDriver *i2cp, /* init slave config field in driver */ i2cp->id_slave_config = i2cscfg; + // TODO: remove this loop. Do only 1 check because mutual exclusion resolve collisions i2c_lld_wait_bus_free(i2cp); chDbgAssert(!(i2c_lld_bus_is_busy(i2cp)), "i2cMasterReceive(), #1", "time is out"); @@ -224,6 +225,7 @@ void i2cMasterReceive(I2CDriver *i2cp, /* init slave config field in driver */ i2cp->id_slave_config = i2cscfg; + // TODO: remove this loop. Do only 1 check because mutual exclusion resolve collisions i2c_lld_wait_bus_free(i2cp); chDbgAssert(!(i2c_lld_bus_is_busy(i2cp)), "i2cMasterReceive(), #1", "time is out"); -- cgit v1.2.3 From 7463a3f1ffd01344e4da4bb9395f887ab6a1ec3f Mon Sep 17 00:00:00 2001 From: barthess Date: Thu, 1 Dec 2011 18:17:30 +0000 Subject: I2C. Totally broken. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3546 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/i2c_lld.c | 365 ++++----------------------------------- os/hal/platforms/STM32/i2c_lld.h | 3 + 2 files changed, 32 insertions(+), 336 deletions(-) (limited to 'os') diff --git a/os/hal/platforms/STM32/i2c_lld.c b/os/hal/platforms/STM32/i2c_lld.c index 93b4c4061..497975d2d 100644 --- a/os/hal/platforms/STM32/i2c_lld.c +++ b/os/hal/platforms/STM32/i2c_lld.c @@ -46,9 +46,6 @@ /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ -#define I2C_STOP_GPT_TIMEOUT 50 /* waiting timer value */ -#define I2C_START_GPT_TIMEOUT 50 /* waiting timer value */ -#define I2C_POLLING_TIMEOUT 0xFFFF /*===========================================================================*/ /* Driver exported variables. */ @@ -77,324 +74,13 @@ static volatile uint16_t dbgCR2 = 0; #endif /* CH_DBG_ENABLE_ASSERTS */ /* defines for convenience purpose */ -#if I2C_SUPPORTS_CALLBACKS #define txBuffp (i2cp->txbuff_p) #define rxBuffp (i2cp->rxbuff_p) -#endif /* I2C_SUPPORTS_CALLBACKS */ /*===========================================================================*/ /* Driver local functions. */ /*===========================================================================*/ -#if I2C_SUPPORTS_CALLBACKS -#if (!(STM32_I2C_I2C1_USE_POLLING_WAIT)) && STM32_I2C_USE_I2C1 -/* I2C1 GPT callback. */ -static void i2c1gptcb(GPTDriver *gptp) { - (void)gptp; - I2CDriver *i2cp = &I2CD1; - - chSysLockFromIsr(); - i2cp->flags &= ~I2C_FLG_TIMER_ARMED; - - switch(i2cp->id_state){ - case I2C_ACTIVE_TRANSMIT: - i2c_lld_master_transmit(i2cp, i2cp->slave_addr, i2cp->txbuf, i2cp->txbytes, i2cp->rxbuf, i2cp->rxbytes); - break; - - case I2C_ACTIVE_RECEIVE: - i2c_lld_master_receive(i2cp, i2cp->slave_addr, i2cp->rxbuf, i2cp->rxbytes); - break; - - case I2C_ACTIVE_TRANSCEIVE: - i2c_lld_master_transceive(i2cp); - break; - - default: - break; - } - chSysUnlockFromIsr(); -} -/* I2C1 GPT configuration. */ -static const GPTConfig i2c1gptcfg = { - 1000000, /* 1MHz timer clock.*/ - i2c1gptcb /* Timer callback.*/ -}; -#endif /* STM32_I2C_I2C1_USE_POLLING_WAIT */ - -#if (!(STM32_I2C_I2C2_USE_POLLING_WAIT)) && STM32_I2C_USE_I2C2 -/* I2C2 GPT callback. */ -static void i2c2gptcb(GPTDriver *gptp) { - (void)gptp; - I2CDriver *i2cp = &I2CD2; - - chSysLockFromIsr(); - i2cp->flags &= ~I2C_FLG_TIMER_ARMED; - - switch(i2cp->id_state){ - case I2C_ACTIVE_TRANSMIT: - i2c_lld_master_transmit(i2cp, i2cp->slave_addr, i2cp->txbuf, i2cp->txbytes, i2cp->rxbuf, i2cp->rxbytes); - break; - - case I2C_ACTIVE_RECEIVE: - i2c_lld_master_receive(i2cp, i2cp->slave_addr, i2cp->rxbuf, i2cp->rxbytes); - break; - - case I2C_ACTIVE_TRANSCEIVE: - i2c_lld_master_transceive(i2cp); - break; - - default: - break; - } - chSysUnlockFromIsr(); -} -/* I2C2 GPT configuration. */ -static const GPTConfig i2c2gptcfg = { - 1000000, /* 1MHz timer clock.*/ - i2c2gptcb /* Timer callback.*/ -}; -#endif /* STM32_I2C_I2C2_USE_POLLING_WAIT */ -#endif /* I2C_SUPPORTS_CALLBACKS */ - -/** - * @brief Function for I2C debugging purpose. - * @note Internal use only. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -#if CH_DBG_ENABLE_ASSERTS -void _i2c_unhandled_case(I2CDriver *i2cp){ - dbgCR1 = i2cp->id_i2c->CR1; - dbgCR2 = i2cp->id_i2c->CR2; - chDbgAssert((dbgSR1 + dbgSR2) == 0, - "i2c_serve_event_interrupt(), #1", - "unhandled case"); -} -#else -#define _i2c_unhandled_case(i2cp) -#endif /* CH_DBG_ENABLE_ASSERTS */ - -#if I2C_SUPPORTS_CALLBACKS -/** - * @brief Return the last event value from I2C status registers. - * @note Internal use only. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -static uint32_t i2c_get_event(I2CDriver *i2cp){ - uint16_t regSR1 = i2cp->id_i2c->SR1; - uint16_t regSR2 = i2cp->id_i2c->SR2; - #if CH_DBG_ENABLE_ASSERTS - dbgSR1 = regSR1; - dbgSR2 = regSR2; - #endif /* CH_DBG_ENABLE_ASSERTS */ - - return (I2C_EV_MASK & (regSR1 | (regSR2 << 16))); -} - -/** - * @brief Handle the flags/interrupts. - * @note Internal use only. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -void _i2c_ev6_master_rec_mode_selected(I2CDriver *i2cp){ - I2C_TypeDef *dp = i2cp->id_i2c; - - switch(i2cp->flags & EV6_SUBEV_MASK) { - - case I2C_EV6_3_MASTER_REC_1BTR_MODE_SELECTED: /* only an single byte to receive */ - dp->CR1 &= (uint16_t)~I2C_CR1_ACK; /* Clear ACK */ - dp->CR1 |= I2C_CR1_STOP; /* Program the STOP */ - break; - - case I2C_EV6_1_MASTER_REC_2BTR_MODE_SELECTED: /* only two bytes to receive */ - dp->CR1 &= (uint16_t)~I2C_CR1_ACK; /* Clear ACK */ - dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN; /* Disable the ITBUF in order to have only the BTF interrupt */ - break; - - default: /* more than 2 bytes to receive */ - break; - } -} - -/** - * @brief Handle cases of 2 or 3 bytes receiving. - * @note Internal use only. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -void _i2c_ev7_master_rec_byte_qued(I2CDriver *i2cp){ - I2C_TypeDef *dp = i2cp->id_i2c; - - switch(i2cp->flags & EV7_SUBEV_MASK) { - - case I2C_EV7_2_MASTER_REC_3BYTES_TO_PROCESS: - /* Only for case of three bytes to be received. - * DataN-2 and DataN-1 already received. */ - dp->CR1 &= (uint16_t)~I2C_CR1_ACK; /* Clear ACK */ - *rxBuffp = dp->DR; /* Read the DataN-2. This clear the RXE & BFT flags and launch the DataN exception in the shift register (ending the SCL stretch) */ - rxBuffp++; - chSysLockFromIsr(); - dp->CR1 |= I2C_CR1_STOP; /* Program the STOP */ - *rxBuffp = dp->DR; /* Read the DataN-1 */ - chSysUnlockFromIsr(); - rxBuffp++; - i2cp->rxbytes -= 2; /* Decrement the number of readed bytes */ - i2cp->flags = 0; - dp->CR2 |= I2C_CR2_ITBUFEN; /* ready for read DataN. Enable interrupt for next (and last) RxNE event*/ - break; - - case I2C_EV7_3_MASTER_REC_2BYTES_TO_PROCESS: - /* only for case of two bytes to be received - * DataN-1 and DataN are received */ - dp->CR2 &= (uint16_t)~I2C_CR2_ITEVTEN; - dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN; - chSysLockFromIsr(); - dp->CR1 |= I2C_CR1_STOP; /* Program the STOP */ - *rxBuffp = dp->DR; /* Read the DataN-1*/ - rxBuffp++; - *rxBuffp = dp->DR; /* Read the DataN*/ - chSysUnlockFromIsr(); - i2cp->rxbytes = 0; - i2cp->flags = 0; - _i2c_isr_code(i2cp, i2cp->id_slave_config); /* Portable I2C ISR code defined in the high level driver. */ - break; - - case I2C_FLG_MASTER_RECEIVER: - /* Some times in hi load scenarions it is possible to "miss" interrupt - * because STM32 I2C has OR'ed interrupt sources. This case handle that - * scenario. */ - if (i2cp->rxbytes > 3){ - *rxBuffp = dp->DR; - rxBuffp++; - (i2cp->rxbytes)--; - } - else{ - _i2c_unhandled_case(i2cp); - } - break; - - default: - _i2c_unhandled_case(i2cp); - break; - } -} - -/** - * @brief Main I2C interrupt handler. - * @note Internal use only. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -static void i2c_serve_event_interrupt(I2CDriver *i2cp) { - I2C_TypeDef *dp = i2cp->id_i2c; - switch(i2c_get_event(i2cp)) { - - case I2C_EV5_MASTER_MODE_SELECT: - i2cp->flags &= ~I2C_FLG_HEADER_SENT; - dp->DR = i2cp->slave_addr1; - break; - - case I2C_EV9_MASTER_ADDR_10BIT: - if(i2cp->flags & I2C_FLG_MASTER_RECEIVER) { - i2cp->slave_addr1 |= 0x01; - i2cp->flags |= I2C_FLG_HEADER_SENT; - } - dp->DR = i2cp->slave_addr2; - break; - - /************************************************************************** - * Master Transmitter part - */ - case I2C_EV6_MASTER_TRA_MODE_SELECTED: - if(i2cp->flags & I2C_FLG_HEADER_SENT){ - dp->CR1 |= I2C_CR1_START; /* re-send the start in 10-Bit address mode */ - break; - } - txBuffp = (uint8_t*)i2cp->txbuf; /* Initialize the transmit buffer pointer */ - i2cp->txbytes--; - if(i2cp->txbytes == 0) { /* If no further data to be sent, disable the I2C ITBUF in order to not have a TxE interrupt */ - dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN; - } - dp->DR = *txBuffp; /* EV8_1 write the first data */ - txBuffp++; - break; - - case I2C_EV8_MASTER_BYTE_TRANSMITTING: - if(i2cp->txbytes > 0) { - i2cp->txbytes--; - if(i2cp->txbytes == 0) { /* If no further data to be sent, disable the ITBUF in order to not have a TxE interrupt */ - dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN; - } - dp->DR = *txBuffp; - txBuffp++; - } - break; - - case I2C_EV8_2_MASTER_BYTE_TRANSMITTED: - dp->CR2 &= (uint16_t)~I2C_CR2_ITEVTEN; /* Disable ITEVT In order to not have again a BTF IT */ - if (i2cp->rxbytes == 0){ /* if nothing to read then generate stop */ - dp->CR1 |= I2C_CR1_STOP; - _i2c_isr_code(i2cp, i2cp->id_slave_config); /* Portable I2C ISR code defined in the high level driver. */ - } - else{ /* start reading operation */ - i2cp->id_i2c->CR1 |= I2C_CR1_START; /* send start bit */ - i2c_lld_master_transceive(i2cp); - } - break; - - /************************************************************************** - * Master Receiver part - */ - case I2C_EV6_MASTER_REC_MODE_SELECTED: - _i2c_ev6_master_rec_mode_selected(i2cp); - rxBuffp = i2cp->rxbuf; /* Initialize receive buffer pointer */ - break; - - case I2C_EV7_MASTER_REC_BYTE_RECEIVED: - if(i2cp->rxbytes > 3) { - *rxBuffp = dp->DR; /* Read the data register */ - rxBuffp++; - i2cp->rxbytes--; - if(i2cp->rxbytes == 3){ /* Disable the ITBUF in order to have only the BTF interrupt */ - dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN; - i2cp->flags |= I2C_FLG_3BTR; - } - } - else if (i2cp->rxbytes == 3){ /* Disable the ITBUF in order to have only the BTF interrupt */ - dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN; - i2cp->flags |= I2C_FLG_3BTR; - } - break; - - case I2C_EV7_MASTER_REC_BYTE_QUEUED: - _i2c_ev7_master_rec_byte_qued(i2cp); - break; - - default: /* only 1 byte must to be read to complete trasfer. Stop already sent to bus. */ - chDbgAssert((i2cp->rxbytes) == 1, - "i2c_serve_event_interrupt(), #1", - "more than 1 byte to be received"); - *rxBuffp = dp->DR; /* Read the data register */ - i2cp->rxbytes = 0; - dp->CR2 &= (uint16_t)~I2C_CR2_ITEVTEN; /* disable interrupts */ - dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN; - _i2c_isr_code(i2cp, i2cp->id_slave_config); /* Portable I2C ISR code defined in the high level driver.*/ - break; - } -} -#endif /* I2C_SUPPORTS_CALLBACKS */ static void i2c_serve_error_interrupt(I2CDriver *i2cp) { i2cflags_t flags; @@ -447,28 +133,10 @@ static void i2c_serve_error_interrupt(I2CDriver *i2cp) { #if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__) -/** - * @brief I2C1 event interrupt handler. - */ -#if I2C_SUPPORTS_CALLBACKS -CH_IRQ_HANDLER(VectorBC) { - - CH_IRQ_PROLOGUE(); - i2c_serve_event_interrupt(&I2CD1); - CH_IRQ_EPILOGUE(); -} -#endif /* I2C_SUPPORTS_CALLBACKS */ -/** - * @brief I2C1 error interrupt handler. - */ -CH_IRQ_HANDLER(VectorC0) { - - CH_IRQ_PROLOGUE(); - i2c_serve_error_interrupt(&I2CD1); - CH_IRQ_EPILOGUE(); -} +#error "Unrealized yet" #endif /* STM32_I2C_USE_I2C1 */ + #if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__) /** * @brief I2C2 event interrupt handler. @@ -546,10 +214,10 @@ void i2c_lld_start(I2CDriver *i2cp) { if (&I2CD2 == i2cp) { #if I2C_SUPPORTS_CALLBACKS NVICEnableVector(I2C2_EV_IRQn, - CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); + CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); #endif /* I2C_SUPPORTS_CALLBACKS */ NVICEnableVector(I2C2_ER_IRQn, - CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); + CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); rccEnableI2C2(FALSE); } #endif @@ -566,7 +234,9 @@ void i2c_lld_reset(I2CDriver *i2cp){ chDbgCheck((i2cp->id_state == I2C_STOP)||(i2cp->id_state == I2C_READY), "i2c_lld_reset: invalid state"); + /*TODO: Check what interface we must reset */ rccResetI2C1(); + rccResetI2C2(); } @@ -717,6 +387,29 @@ void i2c_lld_stop(I2CDriver *i2cp) { #if I2C_SUPPORTS_CALLBACKS + + +/** + * @brief Transmits data via the I2C bus as master. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] slave_addr Slave device address. Bits 0-9 contain slave + * device address. Bit 15 must be set to 1 if 10-bit + * addressing modes used. Otherwise keep it cleared. + * Bits 10-14 unused. + * @param[in] txbuf pointer to the transmit buffer + * @param[in] txbytes number of bytes to be transmitted + * @param[in] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + */ +void i2c_lld_master_transmit_dma(I2CDriver *i2cp, uint16_t slave_addr, + uint8_t *txbuf, size_t txbytes, uint8_t *rxbuf, size_t rxbytes) { + +} + + + + /** * @brief Transmits data via the I2C bus as master. * diff --git a/os/hal/platforms/STM32/i2c_lld.h b/os/hal/platforms/STM32/i2c_lld.h index 81a9f62dc..24195147a 100644 --- a/os/hal/platforms/STM32/i2c_lld.h +++ b/os/hal/platforms/STM32/i2c_lld.h @@ -308,6 +308,9 @@ void i2c_lld_master_receive(I2CDriver *i2cp, uint16_t slave_addr, uint8_t *rxbuf, size_t rxbytes); void i2c_lld_master_transceive(I2CDriver *i2cp); +void i2c_lld_master_transmit_dma(I2CDriver *i2cp, uint16_t slave_addr, + uint8_t *txbuf, size_t txbytes, uint8_t *rxbuf, size_t rxbytes); + #ifdef __cplusplus } #endif -- cgit v1.2.3 From 750f1f4ae6ce75e0cbd8d6923b026376b607ffad Mon Sep 17 00:00:00 2001 From: barthess Date: Thu, 1 Dec 2011 18:21:22 +0000 Subject: I2C. Old driver moved to I2Cv1 dir. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3547 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/I2Cv1/i2c_lld.c | 1100 ++++++++++++++++++++++++++++++++ os/hal/platforms/STM32/I2Cv1/i2c_lld.h | 318 +++++++++ 2 files changed, 1418 insertions(+) create mode 100644 os/hal/platforms/STM32/I2Cv1/i2c_lld.c create mode 100644 os/hal/platforms/STM32/I2Cv1/i2c_lld.h (limited to 'os') diff --git a/os/hal/platforms/STM32/I2Cv1/i2c_lld.c b/os/hal/platforms/STM32/I2Cv1/i2c_lld.c new file mode 100644 index 000000000..93b4c4061 --- /dev/null +++ b/os/hal/platforms/STM32/I2Cv1/i2c_lld.c @@ -0,0 +1,1100 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32/i2c_lld.c + * @brief STM32 I2C subsystem low level driver source. Slave mode not implemented. + * @addtogroup I2C + * @{ + */ + +#include "ch.h" +#include "hal.h" +#include "i2c_lld.h" + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Datasheet notes. */ +/*===========================================================================*/ +/** + * From RM0008.pdf + * + * Note: + * When the STOP, START or PEC bit is set, the software must NOT perform + * any write access to I2C_CR1 before this bit is cleared by hardware. + * Otherwise there is a risk of setting a second STOP, START or PEC request. + */ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ +#define I2C_STOP_GPT_TIMEOUT 50 /* waiting timer value */ +#define I2C_START_GPT_TIMEOUT 50 /* waiting timer value */ +#define I2C_POLLING_TIMEOUT 0xFFFF + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief I2C1 driver identifier.*/ +#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__) +I2CDriver I2CD1; +#endif + +/** @brief I2C2 driver identifier.*/ +#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__) +I2CDriver I2CD2; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/* Debugging variables */ +#if CH_DBG_ENABLE_ASSERTS +static volatile uint16_t dbgSR1 = 0; +static volatile uint16_t dbgSR2 = 0; +static volatile uint16_t dbgCR1 = 0; +static volatile uint16_t dbgCR2 = 0; +#endif /* CH_DBG_ENABLE_ASSERTS */ + +/* defines for convenience purpose */ +#if I2C_SUPPORTS_CALLBACKS +#define txBuffp (i2cp->txbuff_p) +#define rxBuffp (i2cp->rxbuff_p) +#endif /* I2C_SUPPORTS_CALLBACKS */ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ +#if I2C_SUPPORTS_CALLBACKS +#if (!(STM32_I2C_I2C1_USE_POLLING_WAIT)) && STM32_I2C_USE_I2C1 +/* I2C1 GPT callback. */ +static void i2c1gptcb(GPTDriver *gptp) { + (void)gptp; + I2CDriver *i2cp = &I2CD1; + + chSysLockFromIsr(); + i2cp->flags &= ~I2C_FLG_TIMER_ARMED; + + switch(i2cp->id_state){ + case I2C_ACTIVE_TRANSMIT: + i2c_lld_master_transmit(i2cp, i2cp->slave_addr, i2cp->txbuf, i2cp->txbytes, i2cp->rxbuf, i2cp->rxbytes); + break; + + case I2C_ACTIVE_RECEIVE: + i2c_lld_master_receive(i2cp, i2cp->slave_addr, i2cp->rxbuf, i2cp->rxbytes); + break; + + case I2C_ACTIVE_TRANSCEIVE: + i2c_lld_master_transceive(i2cp); + break; + + default: + break; + } + chSysUnlockFromIsr(); +} +/* I2C1 GPT configuration. */ +static const GPTConfig i2c1gptcfg = { + 1000000, /* 1MHz timer clock.*/ + i2c1gptcb /* Timer callback.*/ +}; +#endif /* STM32_I2C_I2C1_USE_POLLING_WAIT */ + +#if (!(STM32_I2C_I2C2_USE_POLLING_WAIT)) && STM32_I2C_USE_I2C2 +/* I2C2 GPT callback. */ +static void i2c2gptcb(GPTDriver *gptp) { + (void)gptp; + I2CDriver *i2cp = &I2CD2; + + chSysLockFromIsr(); + i2cp->flags &= ~I2C_FLG_TIMER_ARMED; + + switch(i2cp->id_state){ + case I2C_ACTIVE_TRANSMIT: + i2c_lld_master_transmit(i2cp, i2cp->slave_addr, i2cp->txbuf, i2cp->txbytes, i2cp->rxbuf, i2cp->rxbytes); + break; + + case I2C_ACTIVE_RECEIVE: + i2c_lld_master_receive(i2cp, i2cp->slave_addr, i2cp->rxbuf, i2cp->rxbytes); + break; + + case I2C_ACTIVE_TRANSCEIVE: + i2c_lld_master_transceive(i2cp); + break; + + default: + break; + } + chSysUnlockFromIsr(); +} +/* I2C2 GPT configuration. */ +static const GPTConfig i2c2gptcfg = { + 1000000, /* 1MHz timer clock.*/ + i2c2gptcb /* Timer callback.*/ +}; +#endif /* STM32_I2C_I2C2_USE_POLLING_WAIT */ +#endif /* I2C_SUPPORTS_CALLBACKS */ + +/** + * @brief Function for I2C debugging purpose. + * @note Internal use only. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +#if CH_DBG_ENABLE_ASSERTS +void _i2c_unhandled_case(I2CDriver *i2cp){ + dbgCR1 = i2cp->id_i2c->CR1; + dbgCR2 = i2cp->id_i2c->CR2; + chDbgAssert((dbgSR1 + dbgSR2) == 0, + "i2c_serve_event_interrupt(), #1", + "unhandled case"); +} +#else +#define _i2c_unhandled_case(i2cp) +#endif /* CH_DBG_ENABLE_ASSERTS */ + +#if I2C_SUPPORTS_CALLBACKS +/** + * @brief Return the last event value from I2C status registers. + * @note Internal use only. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static uint32_t i2c_get_event(I2CDriver *i2cp){ + uint16_t regSR1 = i2cp->id_i2c->SR1; + uint16_t regSR2 = i2cp->id_i2c->SR2; + #if CH_DBG_ENABLE_ASSERTS + dbgSR1 = regSR1; + dbgSR2 = regSR2; + #endif /* CH_DBG_ENABLE_ASSERTS */ + + return (I2C_EV_MASK & (regSR1 | (regSR2 << 16))); +} + +/** + * @brief Handle the flags/interrupts. + * @note Internal use only. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void _i2c_ev6_master_rec_mode_selected(I2CDriver *i2cp){ + I2C_TypeDef *dp = i2cp->id_i2c; + + switch(i2cp->flags & EV6_SUBEV_MASK) { + + case I2C_EV6_3_MASTER_REC_1BTR_MODE_SELECTED: /* only an single byte to receive */ + dp->CR1 &= (uint16_t)~I2C_CR1_ACK; /* Clear ACK */ + dp->CR1 |= I2C_CR1_STOP; /* Program the STOP */ + break; + + case I2C_EV6_1_MASTER_REC_2BTR_MODE_SELECTED: /* only two bytes to receive */ + dp->CR1 &= (uint16_t)~I2C_CR1_ACK; /* Clear ACK */ + dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN; /* Disable the ITBUF in order to have only the BTF interrupt */ + break; + + default: /* more than 2 bytes to receive */ + break; + } +} + +/** + * @brief Handle cases of 2 or 3 bytes receiving. + * @note Internal use only. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void _i2c_ev7_master_rec_byte_qued(I2CDriver *i2cp){ + I2C_TypeDef *dp = i2cp->id_i2c; + + switch(i2cp->flags & EV7_SUBEV_MASK) { + + case I2C_EV7_2_MASTER_REC_3BYTES_TO_PROCESS: + /* Only for case of three bytes to be received. + * DataN-2 and DataN-1 already received. */ + dp->CR1 &= (uint16_t)~I2C_CR1_ACK; /* Clear ACK */ + *rxBuffp = dp->DR; /* Read the DataN-2. This clear the RXE & BFT flags and launch the DataN exception in the shift register (ending the SCL stretch) */ + rxBuffp++; + chSysLockFromIsr(); + dp->CR1 |= I2C_CR1_STOP; /* Program the STOP */ + *rxBuffp = dp->DR; /* Read the DataN-1 */ + chSysUnlockFromIsr(); + rxBuffp++; + i2cp->rxbytes -= 2; /* Decrement the number of readed bytes */ + i2cp->flags = 0; + dp->CR2 |= I2C_CR2_ITBUFEN; /* ready for read DataN. Enable interrupt for next (and last) RxNE event*/ + break; + + case I2C_EV7_3_MASTER_REC_2BYTES_TO_PROCESS: + /* only for case of two bytes to be received + * DataN-1 and DataN are received */ + dp->CR2 &= (uint16_t)~I2C_CR2_ITEVTEN; + dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN; + chSysLockFromIsr(); + dp->CR1 |= I2C_CR1_STOP; /* Program the STOP */ + *rxBuffp = dp->DR; /* Read the DataN-1*/ + rxBuffp++; + *rxBuffp = dp->DR; /* Read the DataN*/ + chSysUnlockFromIsr(); + i2cp->rxbytes = 0; + i2cp->flags = 0; + _i2c_isr_code(i2cp, i2cp->id_slave_config); /* Portable I2C ISR code defined in the high level driver. */ + break; + + case I2C_FLG_MASTER_RECEIVER: + /* Some times in hi load scenarions it is possible to "miss" interrupt + * because STM32 I2C has OR'ed interrupt sources. This case handle that + * scenario. */ + if (i2cp->rxbytes > 3){ + *rxBuffp = dp->DR; + rxBuffp++; + (i2cp->rxbytes)--; + } + else{ + _i2c_unhandled_case(i2cp); + } + break; + + default: + _i2c_unhandled_case(i2cp); + break; + } +} + +/** + * @brief Main I2C interrupt handler. + * @note Internal use only. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_serve_event_interrupt(I2CDriver *i2cp) { + I2C_TypeDef *dp = i2cp->id_i2c; + + switch(i2c_get_event(i2cp)) { + + case I2C_EV5_MASTER_MODE_SELECT: + i2cp->flags &= ~I2C_FLG_HEADER_SENT; + dp->DR = i2cp->slave_addr1; + break; + + case I2C_EV9_MASTER_ADDR_10BIT: + if(i2cp->flags & I2C_FLG_MASTER_RECEIVER) { + i2cp->slave_addr1 |= 0x01; + i2cp->flags |= I2C_FLG_HEADER_SENT; + } + dp->DR = i2cp->slave_addr2; + break; + + /************************************************************************** + * Master Transmitter part + */ + case I2C_EV6_MASTER_TRA_MODE_SELECTED: + if(i2cp->flags & I2C_FLG_HEADER_SENT){ + dp->CR1 |= I2C_CR1_START; /* re-send the start in 10-Bit address mode */ + break; + } + txBuffp = (uint8_t*)i2cp->txbuf; /* Initialize the transmit buffer pointer */ + i2cp->txbytes--; + if(i2cp->txbytes == 0) { /* If no further data to be sent, disable the I2C ITBUF in order to not have a TxE interrupt */ + dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN; + } + dp->DR = *txBuffp; /* EV8_1 write the first data */ + txBuffp++; + break; + + case I2C_EV8_MASTER_BYTE_TRANSMITTING: + if(i2cp->txbytes > 0) { + i2cp->txbytes--; + if(i2cp->txbytes == 0) { /* If no further data to be sent, disable the ITBUF in order to not have a TxE interrupt */ + dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN; + } + dp->DR = *txBuffp; + txBuffp++; + } + break; + + case I2C_EV8_2_MASTER_BYTE_TRANSMITTED: + dp->CR2 &= (uint16_t)~I2C_CR2_ITEVTEN; /* Disable ITEVT In order to not have again a BTF IT */ + if (i2cp->rxbytes == 0){ /* if nothing to read then generate stop */ + dp->CR1 |= I2C_CR1_STOP; + _i2c_isr_code(i2cp, i2cp->id_slave_config); /* Portable I2C ISR code defined in the high level driver. */ + } + else{ /* start reading operation */ + i2cp->id_i2c->CR1 |= I2C_CR1_START; /* send start bit */ + i2c_lld_master_transceive(i2cp); + } + break; + + /************************************************************************** + * Master Receiver part + */ + case I2C_EV6_MASTER_REC_MODE_SELECTED: + _i2c_ev6_master_rec_mode_selected(i2cp); + rxBuffp = i2cp->rxbuf; /* Initialize receive buffer pointer */ + break; + + case I2C_EV7_MASTER_REC_BYTE_RECEIVED: + if(i2cp->rxbytes > 3) { + *rxBuffp = dp->DR; /* Read the data register */ + rxBuffp++; + i2cp->rxbytes--; + if(i2cp->rxbytes == 3){ /* Disable the ITBUF in order to have only the BTF interrupt */ + dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN; + i2cp->flags |= I2C_FLG_3BTR; + } + } + else if (i2cp->rxbytes == 3){ /* Disable the ITBUF in order to have only the BTF interrupt */ + dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN; + i2cp->flags |= I2C_FLG_3BTR; + } + break; + + case I2C_EV7_MASTER_REC_BYTE_QUEUED: + _i2c_ev7_master_rec_byte_qued(i2cp); + break; + + default: /* only 1 byte must to be read to complete trasfer. Stop already sent to bus. */ + chDbgAssert((i2cp->rxbytes) == 1, + "i2c_serve_event_interrupt(), #1", + "more than 1 byte to be received"); + *rxBuffp = dp->DR; /* Read the data register */ + i2cp->rxbytes = 0; + dp->CR2 &= (uint16_t)~I2C_CR2_ITEVTEN; /* disable interrupts */ + dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN; + _i2c_isr_code(i2cp, i2cp->id_slave_config); /* Portable I2C ISR code defined in the high level driver.*/ + break; + } +} +#endif /* I2C_SUPPORTS_CALLBACKS */ + +static void i2c_serve_error_interrupt(I2CDriver *i2cp) { + i2cflags_t flags; + I2C_TypeDef *reg; + + reg = i2cp->id_i2c; + flags = I2CD_NO_ERROR; + + if(reg->SR1 & I2C_SR1_BERR) { /* Bus error */ + reg->SR1 &= ~I2C_SR1_BERR; + flags |= I2CD_BUS_ERROR; + } + if(reg->SR1 & I2C_SR1_ARLO) { /* Arbitration lost */ + reg->SR1 &= ~I2C_SR1_ARLO; + flags |= I2CD_ARBITRATION_LOST; + } + if(reg->SR1 & I2C_SR1_AF) { /* Acknowledge fail */ + reg->SR1 &= ~I2C_SR1_AF; + reg->CR1 |= I2C_CR1_STOP; /* setting stop bit */ + while(i2cp->id_i2c->CR1 & I2C_CR1_STOP) + ; + flags |= I2CD_ACK_FAILURE; + } + if(reg->SR1 & I2C_SR1_OVR) { /* Overrun */ + reg->SR1 &= ~I2C_SR1_OVR; + flags |= I2CD_OVERRUN; + } + if(reg->SR1 & I2C_SR1_PECERR) { /* PEC error */ + reg->SR1 &= ~I2C_SR1_PECERR; + flags |= I2CD_PEC_ERROR; + } + if(reg->SR1 & I2C_SR1_TIMEOUT) { /* SMBus Timeout */ + reg->SR1 &= ~I2C_SR1_TIMEOUT; + flags |= I2CD_TIMEOUT; + } + if(reg->SR1 & I2C_SR1_SMBALERT) { /* SMBus alert */ + reg->SR1 &= ~I2C_SR1_SMBALERT; + flags |= I2CD_SMB_ALERT; + } + + if(flags != I2CD_NO_ERROR) { /* send communication end signal */ + chSysLockFromIsr(); + i2cAddFlagsI(i2cp, flags); + chSysUnlockFromIsr(); + #if I2C_SUPPORTS_CALLBACKS + _i2c_isr_err_code(i2cp, i2cp->id_slave_config); + #endif /* I2C_SUPPORTS_CALLBACKS */ + } +} + + +#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__) +/** + * @brief I2C1 event interrupt handler. + */ +#if I2C_SUPPORTS_CALLBACKS +CH_IRQ_HANDLER(VectorBC) { + + CH_IRQ_PROLOGUE(); + i2c_serve_event_interrupt(&I2CD1); + CH_IRQ_EPILOGUE(); +} +#endif /* I2C_SUPPORTS_CALLBACKS */ +/** + * @brief I2C1 error interrupt handler. + */ +CH_IRQ_HANDLER(VectorC0) { + + CH_IRQ_PROLOGUE(); + i2c_serve_error_interrupt(&I2CD1); + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_I2C_USE_I2C1 */ + +#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__) +/** + * @brief I2C2 event interrupt handler. + */ +#if I2C_SUPPORTS_CALLBACKS +CH_IRQ_HANDLER(VectorC4) { + + CH_IRQ_PROLOGUE(); + i2c_serve_event_interrupt(&I2CD2); + CH_IRQ_EPILOGUE(); +} +#endif /* I2C_SUPPORTS_CALLBACKS */ +/** + * @brief I2C2 error interrupt handler. + */ +CH_IRQ_HANDLER(VectorC8) { + + CH_IRQ_PROLOGUE(); + i2c_serve_error_interrupt(&I2CD2); + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_I2C_USE_I2C2 */ + +/** + * @brief Low level I2C driver initialization. + */ +void i2c_lld_init(void) { + +#if STM32_I2C_USE_I2C1 + i2cObjectInit(&I2CD1); + I2CD1.id_i2c = I2C1; + +#if I2C_SUPPORTS_CALLBACKS +#if !(STM32_I2C_I2C1_USE_POLLING_WAIT) + I2CD1.timer = &(STM32_I2C_I2C1_USE_GPT_TIM); + I2CD1.timer_cfg = &i2c1gptcfg; +#endif /* !(STM32_I2C_I2C1_USE_POLLING_WAIT) */ +#endif /* I2C_SUPPORTS_CALLBACKS */ + +#endif /* STM32_I2C_USE_I2C */ + +#if STM32_I2C_USE_I2C2 + i2cObjectInit(&I2CD2); + I2CD2.id_i2c = I2C2; + +#if I2C_SUPPORTS_CALLBACKS +#if !(STM32_I2C_I2C2_USE_POLLING_WAIT) + I2CD2.timer = &(STM32_I2C_I2C2_USE_GPT_TIM); + I2CD2.timer_cfg = &i2c2gptcfg; +#endif /* !(STM32_I2C_I2C2_USE_POLLING_WAIT) */ +#endif /* I2C_SUPPORTS_CALLBACKS */ + +#endif /* STM32_I2C_USE_I2C2 */ +} + +/** + * @brief Configures and activates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + */ +void i2c_lld_start(I2CDriver *i2cp) { + if (i2cp->id_state == I2C_STOP) { /* If in stopped state then enables the I2C clock.*/ +#if STM32_I2C_USE_I2C1 + if (&I2CD1 == i2cp) { +#if I2C_SUPPORTS_CALLBACKS + NVICEnableVector(I2C1_EV_IRQn, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); +#endif /* I2C_SUPPORTS_CALLBACKS */ + NVICEnableVector(I2C1_ER_IRQn, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); + rccEnableI2C1(FALSE); + } +#endif +#if STM32_I2C_USE_I2C2 + if (&I2CD2 == i2cp) { +#if I2C_SUPPORTS_CALLBACKS + NVICEnableVector(I2C2_EV_IRQn, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); +#endif /* I2C_SUPPORTS_CALLBACKS */ + NVICEnableVector(I2C2_ER_IRQn, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); + rccEnableI2C2(FALSE); + } +#endif + } + + i2cp->id_i2c->CR1 = I2C_CR1_SWRST; /* reset i2c peripherial */ + i2cp->id_i2c->CR1 = 0; + i2c_lld_set_clock(i2cp); + i2c_lld_set_opmode(i2cp); + i2cp->id_i2c->CR1 |= 1; /* enable interface */ +} + +void i2c_lld_reset(I2CDriver *i2cp){ + chDbgCheck((i2cp->id_state == I2C_STOP)||(i2cp->id_state == I2C_READY), + "i2c_lld_reset: invalid state"); + + rccResetI2C1(); +} + + +/** + * @brief Set clock speed. + * + * @param[in] i2cp pointer to the @p I2CDriver object + */ +void i2c_lld_set_clock(I2CDriver *i2cp) { + volatile uint16_t regCCR, regCR2, freq, clock_div; + volatile uint16_t pe_bit_saved; + int32_t clock_speed = i2cp->id_config->clock_speed; + i2cdutycycle_t duty = i2cp->id_config->duty_cycle; + + chDbgCheck((i2cp != NULL) && (clock_speed > 0) && (clock_speed <= 4000000), + "i2c_lld_set_clock"); + + /************************************************************************** + * CR2 Configuration + */ + regCR2 = i2cp->id_i2c->CR2; /* Get the I2Cx CR2 value */ + regCR2 &= (uint16_t)~I2C_CR2_FREQ; /* Clear frequency FREQ[5:0] bits */ + freq = (uint16_t)(STM32_PCLK1 / 1000000); /* Set frequency bits depending on pclk1 value */ +#ifdef STM32F4XX + chDbgCheck((freq >= 2) && (freq <= 42), + "i2c_lld_set_clock() : Peripheral clock freq. out of range"); +#else + chDbgCheck((freq >= 2) && (freq <= 36), + "i2c_lld_set_clock() : Peripheral clock freq. out of range"); +#endif + regCR2 |= freq; + i2cp->id_i2c->CR2 = regCR2; + + /************************************************************************** + * CCR Configuration + */ + pe_bit_saved = (i2cp->id_i2c->CR1 & I2C_CR1_PE); + i2cp->id_i2c->CR1 &= (uint16_t)~I2C_CR1_PE; /* Disable the selected I2C peripheral to configure TRISE */ + regCCR = 0; /* Clear F/S, DUTY and CCR[11:0] bits */ + clock_div = I2C_CCR_CCR; + + if (clock_speed <= 100000) { /* Configure clock_div in standard mode */ + chDbgAssert(duty == STD_DUTY_CYCLE, + "i2c_lld_set_clock(), #1", + "Invalid standard mode duty cycle"); + clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 2)); /* Standard mode clock_div calculate: Tlow/Thigh = 1/1 */ + if (clock_div < 0x04) clock_div = 0x04; /* Test if CCR value is under 0x4, and set the minimum allowed value */ + regCCR |= (clock_div & I2C_CCR_CCR); /* Set clock_div value for standard mode */ + i2cp->id_i2c->TRISE = freq + 1; /* Set Maximum Rise Time for standard mode */ + } + else if(clock_speed <= 400000) { /* Configure clock_div in fast mode */ + chDbgAssert((duty == FAST_DUTY_CYCLE_2) || + (duty == FAST_DUTY_CYCLE_16_9), + "i2c_lld_set_clock(), #2", + "Invalid fast mode duty cycle"); + if(duty == FAST_DUTY_CYCLE_2) { + clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 3)); /* Fast mode clock_div calculate: Tlow/Thigh = 2/1 */ + } + else if(duty == FAST_DUTY_CYCLE_16_9) { + clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 25)); /* Fast mode clock_div calculate: Tlow/Thigh = 16/9 */ + regCCR |= I2C_CCR_DUTY; /* Set DUTY bit */ + } + if(clock_div < 0x01) clock_div = 0x01; /* Test if CCR value is under 0x1, and set the minimum allowed value */ + regCCR |= (I2C_CCR_FS | (clock_div & I2C_CCR_CCR)); /* Set clock_div value and F/S bit for fast mode*/ + i2cp->id_i2c->TRISE = (freq * 300 / 1000) + 1; /* Set Maximum Rise Time for fast mode */ + } + chDbgAssert((clock_div <= I2C_CCR_CCR), + "i2c_lld_set_clock(), #3", "Too low clock clock speed selected"); + + i2cp->id_i2c->CCR = regCCR; /* Write to I2Cx CCR */ + i2cp->id_i2c->CR1 |= pe_bit_saved; /* restore the I2C peripheral enabled state */ +} + +/** + * @brief Set operation mode of I2C hardware. + * + * @param[in] i2cp pointer to the @p I2CDriver object + */ +void i2c_lld_set_opmode(I2CDriver *i2cp) { + i2copmode_t opmode = i2cp->id_config->op_mode; + uint16_t regCR1; + + regCR1 = i2cp->id_i2c->CR1; /* Get the I2Cx CR1 value */ + switch(opmode){ + case OPMODE_I2C: + regCR1 &= (uint16_t)~(I2C_CR1_SMBUS|I2C_CR1_SMBTYPE); + break; + case OPMODE_SMBUS_DEVICE: + regCR1 |= I2C_CR1_SMBUS; + regCR1 &= (uint16_t)~(I2C_CR1_SMBTYPE); + break; + case OPMODE_SMBUS_HOST: + regCR1 |= (I2C_CR1_SMBUS|I2C_CR1_SMBTYPE); + break; + } + + i2cp->id_i2c->CR1 = regCR1; /* Write to I2Cx CR1 */ +} + +/** + * @brief Set own address. + * + * @param[in] i2cp pointer to the @p I2CDriver object + */ +void i2c_lld_set_own_address(I2CDriver *i2cp) { + /* TODO: dual address mode */ + + i2cp->id_i2c->OAR1 |= 1 << 14; + + if (&(i2cp->id_config->own_addr_10) == NULL){ /* only 7-bit address */ + i2cp->id_i2c->OAR1 &= (~I2C_OAR1_ADDMODE); + i2cp->id_i2c->OAR1 |= i2cp->id_config->own_addr_7 << 1; + } + else { + chDbgAssert((i2cp->id_config->own_addr_10 < 1024), + "i2c_lld_set_own_address(), #1", "10-bit address longer then 10 bit") + i2cp->id_i2c->OAR1 |= I2C_OAR1_ADDMODE; + i2cp->id_i2c->OAR1 |= i2cp->id_config->own_addr_10; + } +} + + +/** + * @brief Deactivates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + */ +void i2c_lld_stop(I2CDriver *i2cp) { + if (i2cp->id_state == I2C_READY) { /* If in ready state then disables the I2C clock.*/ +#if STM32_I2C_USE_I2C1 + if (&I2CD1 == i2cp) { + NVICDisableVector(I2C1_EV_IRQn); + NVICDisableVector(I2C1_ER_IRQn); + rccDisableI2C1(FALSE); + } +#endif +#if STM32_I2C_USE_I2C2 + if (&I2CD2 == i2cp) { + NVICDisableVector(I2C2_EV_IRQn); + NVICDisableVector(I2C2_ER_IRQn); + rccDisableI2C2(FALSE); + } +#endif + } + + i2cp->id_state = I2C_STOP; +} + + +#if I2C_SUPPORTS_CALLBACKS +/** + * @brief Transmits data via the I2C bus as master. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] slave_addr Slave device address. Bits 0-9 contain slave + * device address. Bit 15 must be set to 1 if 10-bit + * addressing modes used. Otherwise keep it cleared. + * Bits 10-14 unused. + * @param[in] txbuf pointer to the transmit buffer + * @param[in] txbytes number of bytes to be transmitted + * @param[in] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + */ +void i2c_lld_master_transmit(I2CDriver *i2cp, uint16_t slave_addr, + uint8_t *txbuf, size_t txbytes, uint8_t *rxbuf, size_t rxbytes) { + + /* "waiting" for STOP bit routine*/ + #if STM32_I2C_I2C1_USE_POLLING_WAIT + uint32_t timeout = I2C_POLLING_TIMEOUT; + while((i2cp->id_i2c->CR1 & I2C_CR1_STOP) && timeout) + timeout--; + chDbgAssert((timeout > 0), "i2c_lld_master_transmit(), #1", "time to STOP is out"); + #else + chDbgAssert(!(i2cp->flags & I2C_FLG_TIMER_ARMED), "i2c_lld_master_transmit(), #1", "time to STOP is out"); + if ((i2cp->id_i2c->CR1 & I2C_CR1_STOP) && i2cp->timer != NULL && i2cp->timer_cfg != NULL){ + chSysLockFromIsr(); + gptStartOneShotI(i2cp->timer, I2C_STOP_GPT_TIMEOUT); + i2cp->flags |= I2C_FLG_TIMER_ARMED; + chSysUnlockFromIsr(); + return; + } + #endif /* STM32_I2C_I2C1_USE_POLLING_WAIT */ + + /* init driver fields */ + i2cp->slave_addr = slave_addr; + i2cp->txbytes = txbytes; + i2cp->rxbytes = rxbytes; + i2cp->txbuf = txbuf; + i2cp->rxbuf = rxbuf; + + /* init address fields */ + if(slave_addr & 0x8000){ /* 10-bit mode used */ + i2cp->slave_addr1 = ((slave_addr >>7) & 0x0006); /* add the two msb of 10-bit address to the header */ + i2cp->slave_addr1 |= 0xF0; /* add the header bits with LSB = 0 -> write */ + i2cp->slave_addr2 = slave_addr & 0x00FF; /* the remaining 8 bit of 10-bit address */ + } + else{ + i2cp->slave_addr1 = ((slave_addr <<1) & 0x00FE); /* LSB = 0 -> write */ + } + + /* setting flags and register bits */ + i2cp->flags = 0; + i2cp->errors = 0; + i2cp->id_i2c->CR1 &= ~I2C_CR1_POS; + i2cp->id_i2c->CR1 |= I2C_CR1_START; + i2cp->id_i2c->CR2 |= (I2C_CR2_ITERREN|I2C_CR2_ITEVTEN|I2C_CR2_ITBUFEN); /* enable ERR, EVT & BUF ITs */ +} + +/** + * @brief Receives data from the I2C bus. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] slave_addr Slave device address. Bits 0-9 contain slave + * device address. Bit 15 must be set to 1 if 10-bit + * addressing modes used. Otherwise keep it cleared. + * Bits 10-14 unused. + * @param[in] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + */ +void i2c_lld_master_receive(I2CDriver *i2cp, uint16_t slave_addr, + uint8_t *rxbuf, size_t rxbytes){ + + chDbgAssert((i2cp->id_i2c->SR1 + i2cp->id_i2c->SR2) == 0, + "i2c_lld_master_receive(), #1", + "some interrupt sources not clear"); + + /* "waiting" for STOP bit routine*/ + #if STM32_I2C_I2C1_USE_POLLING_WAIT + uint32_t timeout = I2C_POLLING_TIMEOUT; + while((i2cp->id_i2c->CR1 & I2C_CR1_STOP) && timeout) + timeout--; + chDbgAssert((timeout > 0), "i2c_lld_master_receive(), #1", "time to STOP is out"); + #else + chDbgAssert(!(i2cp->flags & I2C_FLG_TIMER_ARMED), "i2c_lld_master_receive(), #1", "time to STOP is out"); + if ((i2cp->id_i2c->CR1 & I2C_CR1_STOP) && i2cp->timer != NULL && i2cp->timer_cfg != NULL){ + chSysLockFromIsr(); + gptStartOneShotI(i2cp->timer, I2C_STOP_GPT_TIMEOUT); + i2cp->flags |= I2C_FLG_TIMER_ARMED; + chSysUnlockFromIsr(); + return; + } + #endif /* STM32_I2C_I2C1_USE_POLLING_WAIT */ + + /* init driver fields */ + i2cp->slave_addr = slave_addr; + i2cp->rxbytes = rxbytes; + i2cp->rxbuf = rxbuf; + + /* init address fields */ + if(slave_addr & 0x8000){ /* 10-bit mode used */ + i2cp->slave_addr1 = ((slave_addr >>7) & 0x0006); /* add the two msb of 10-bit address to the header */ + i2cp->slave_addr1 |= 0xF0; /* add the header bits (the LSB -> 1 will be add to second */ + i2cp->slave_addr2 = slave_addr & 0x00FF; /* the remaining 8 bit of 10-bit address */ + } + else{ + i2cp->slave_addr1 = ((slave_addr <<1) | 0x01); /* LSB = 1 -> receive */ + } + + /* setting flags and register bits */ + i2cp->flags |= I2C_FLG_MASTER_RECEIVER; + i2cp->errors = 0; + + i2cp->id_i2c->CR1 |= I2C_CR1_ACK; /* acknowledge returned */ + i2cp->id_i2c->CR1 &= ~I2C_CR1_POS; + + if(i2cp->rxbytes == 1) { /* Only one byte to be received */ + i2cp->flags |= I2C_FLG_1BTR; + } + else if(i2cp->rxbytes == 2) { /* Only two bytes to be received */ + i2cp->flags |= I2C_FLG_2BTR; + i2cp->id_i2c->CR1 |= I2C_CR1_POS; /* Acknowledge Position */ + } + + i2cp->id_i2c->CR1 |= I2C_CR1_START; /* send start bit */ + i2cp->id_i2c->CR2 |= (I2C_CR2_ITERREN|I2C_CR2_ITEVTEN|I2C_CR2_ITBUFEN); /* enable ERR, EVT & BUF ITs */ +} + + +/** + * @brief Realize read-though-write behavior. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_master_transceive(I2CDriver *i2cp){ + + chDbgAssert((i2cp != NULL) && (i2cp->slave_addr1 != 0) &&\ + (i2cp->rxbytes > 0) && (i2cp->rxbuf != NULL), + "i2c_lld_master_transceive(), #1", + ""); + + i2cp->id_state = I2C_ACTIVE_TRANSCEIVE; + + /* "waiting" for START bit routine*/ + #if STM32_I2C_I2C1_USE_POLLING_WAIT + uint32_t timeout = I2C_POLLING_TIMEOUT; + while((i2cp->id_i2c->CR1 & I2C_CR1_START) && timeout); + timeout--; + chDbgAssert((timeout > 0), "i2c_lld_master_transceive(), #1", "time to START is out"); + #else + chDbgAssert(!(i2cp->flags & I2C_FLG_TIMER_ARMED), "i2c_lld_master_transceive(), #1", "time to START is out"); + if ((i2cp->id_i2c->CR1 & I2C_CR1_START) && i2cp->timer != NULL && i2cp->timer_cfg != NULL){ + chSysLockFromIsr(); + gptStartOneShotI(i2cp->timer, I2C_START_GPT_TIMEOUT); + i2cp->flags |= I2C_FLG_TIMER_ARMED; + chSysUnlockFromIsr(); + return; + } + #endif /* STM32_I2C_I2C1_USE_POLLING_WAIT */ + + /* init address fields */ + if(i2cp->slave_addr & 0x8000){ /* 10-bit mode used */ + i2cp->slave_addr1 = ((i2cp->slave_addr >>7) & 0x0006);/* add the two msb of 10-bit address to the header */ + i2cp->slave_addr1 |= 0xF0; /* add the header bits (the LSB -> 1 will be add to second */ + i2cp->slave_addr2 = i2cp->slave_addr & 0x00FF; /* the remaining 8 bit of 10-bit address */ + } + else{ + i2cp->slave_addr1 |= 0x01; + } + + /* setting flags and register bits */ + i2cp->flags |= I2C_FLG_MASTER_RECEIVER; + i2cp->errors = 0; + i2cp->id_i2c->CR1 |= I2C_CR1_ACK; /* acknowledge returned */ + i2cp->id_i2c->CR1 &= ~I2C_CR1_POS; + + if(i2cp->rxbytes == 1) { /* Only one byte to be received */ + i2cp->flags |= I2C_FLG_1BTR; + } + else if(i2cp->rxbytes == 2) { /* Only two bytes to be received */ + i2cp->flags |= I2C_FLG_2BTR; + i2cp->id_i2c->CR1 |= I2C_CR1_POS; /* Acknowledge Position */ + } + + i2cp->id_i2c->CR2 |= (I2C_CR2_ITERREN|I2C_CR2_ITEVTEN|I2C_CR2_ITBUFEN); /* enable ERR, EVT & BUF ITs */ +} + +#else /*I2C_SUPPORTS_CALLBACKS*/ + +/** + * @brief Synchronously transmits data via the I2C bus as master. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] slave_addr Slave device address. Bits 0-9 contain slave + * device address. Bit 15 must be set to 1 if 10-bit + * addressing modes used. Otherwise keep it cleared. + * Bits 10-14 unused. + * @param[in] txbuf pointer to the transmit buffer + * @param[in] txbytes number of bytes to be transmitted + * @param[in] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + */ +void i2c_lld_master_transmit(I2CDriver *i2cp, uint16_t slave_addr, + uint8_t *txbuf, size_t txbytes, uint8_t *rxbuf, size_t rxbytes) { + + /* init driver fields */ + i2cp->slave_addr = slave_addr; + i2cp->txbytes = txbytes; + i2cp->rxbytes = rxbytes; + i2cp->txbuf = txbuf; + i2cp->rxbuf = rxbuf; + + /* init address fields */ + if(slave_addr & 0x8000){ /* 10-bit mode used */ + i2cp->slave_addr1 = ((slave_addr >>7) & 0x0006); /* add the two msb of 10-bit address to the header */ + i2cp->slave_addr1 |= 0xF0; /* add the header bits with LSB = 0 -> write */ + i2cp->slave_addr2 = slave_addr & 0x00FF; /* the remaining 8 bit of 10-bit address */ + } + else{ + i2cp->slave_addr1 = ((slave_addr <<1) & 0x00FE); /* LSB = 0 -> write */ + } + + i2cp->flags = 0; + i2cp->errors = 0; + i2cp->id_i2c->CR1 &= ~I2C_CR1_POS; + i2cp->id_i2c->CR2 &= ~I2C_CR2_ITEVTEN; /* disable event interrupts */ + i2cp->id_i2c->CR2 |= I2C_CR2_ITERREN; /* enable error interrupts */ + + i2cp->id_i2c->CR1 |= I2C_CR1_START; + while (!(i2cp->id_i2c->SR1 & I2C_SR1_SB)) + ; + i2cp->id_i2c->DR = i2cp->slave_addr1; + while (!(i2cp->id_i2c->SR1 & I2C_SR1_ADDR)) + ; + while (!(i2cp->id_i2c->SR2 & I2C_SR2_BUSY)) + ; + i2cp->id_i2c->DR = *txbuf; + txbuf++; + i2cp->txbytes--; + while(i2cp->txbytes > 0){ + while(!(i2cp->id_i2c->SR1 & I2C_SR1_BTF)) + ; + i2cp->id_i2c->DR = *txbuf; + txbuf++; + i2cp->txbytes--; + } + while(!(i2cp->id_i2c->SR1 & I2C_SR1_BTF)) + ; + if(rxbytes == 0){ + i2cp->id_i2c->CR1 |= I2C_CR1_STOP; + while (i2cp->id_i2c->CR1 & I2C_CR1_STOP) + ; + } + else{ + i2c_lld_master_receive(i2cp, slave_addr, rxbuf, rxbytes); + } +} + + +/** + * @brief Synchronously receives data from the I2C bus. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] slave_addr Slave device address. Bits 0-9 contain slave + * device address. Bit 15 must be set to 1 if 10-bit + * addressing modes used. Otherwise keep it cleared. + * Bits 10-14 unused. + * @param[in] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + */ +void i2c_lld_master_receive(I2CDriver *i2cp, uint16_t slave_addr, + uint8_t *rxbuf, size_t rxbytes){ + + /* init driver fields */ + i2cp->slave_addr = slave_addr; + i2cp->rxbytes = rxbytes; + i2cp->rxbuf = rxbuf; + + /* init address fields */ + if(slave_addr & 0x8000){ /* 10-bit mode used */ + i2cp->slave_addr1 = ((slave_addr >>7) & 0x0006); /* add the two msb of 10-bit address to the header */ + i2cp->slave_addr1 |= 0xF0; /* add the header bits (the LSB -> 1 will be add to second */ + i2cp->slave_addr2 = slave_addr & 0x00FF; /* the remaining 8 bit of 10-bit address */ + } + else{ + i2cp->slave_addr1 = ((slave_addr <<1) | 0x01); /* LSB = 1 -> receive */ + } + + + /* setting flags and register bits */ + i2cp->flags = 0; + i2cp->errors = 0; + i2cp->id_i2c->CR1 &= ~I2C_CR1_POS; + i2cp->id_i2c->CR2 &= ~I2C_CR2_ITEVTEN; /* disable event interrupts */ + i2cp->id_i2c->CR2 |= I2C_CR2_ITERREN; /* enable error interrupts */ + + i2cp->id_i2c->CR1 |= I2C_CR1_START; + while (!(i2cp->id_i2c->SR1 & I2C_SR1_SB)) + ; + + i2cp->id_i2c->DR = i2cp->slave_addr1; + while (!(i2cp->id_i2c->SR1 & I2C_SR1_ADDR)) + ; + + if(i2cp->rxbytes >= 3){ /* more than 2 bytes receiving procedure */ + while(!(i2cp->id_i2c->SR2 & I2C_SR2_BUSY)) /* to clear ADDR bit */ + ; + while(i2cp->rxbytes > 3){ + while(!(i2cp->id_i2c->SR1 & I2C_SR1_BTF)) + ; + *rxbuf = i2cp->id_i2c->DR; + rxbuf++; + i2cp->rxbytes--; + } + while(!(i2cp->id_i2c->SR1 & I2C_SR1_BTF)) /* stopping procedure */ + ; + i2cp->id_i2c->CR1 &= ~I2C_CR1_ACK; + chSysLock(); + i2cp->id_i2c->CR1 |= I2C_CR1_STOP; + *rxbuf = i2cp->id_i2c->DR; + rxbuf++; + i2cp->rxbytes--; + chSysUnlock(); + while(!(i2cp->id_i2c->SR1 & I2C_SR1_RXNE)) + ; + *rxbuf = i2cp->id_i2c->DR; + rxbuf++; + i2cp->rxbytes--; + while (i2cp->id_i2c->CR1 & I2C_CR1_STOP) + ; + i2cp->id_i2c->CR1 |= I2C_CR1_ACK; + } + else{ /* 1 or 2 bytes receiving procedure */ + if(i2cp->rxbytes == 2){ + i2cp->id_i2c->CR1 |= I2C_CR1_POS; + chSysLock(); + while(!(i2cp->id_i2c->SR2 & I2C_SR2_BUSY)) /* to clear ADDR bit */ + ; + i2cp->id_i2c->CR1 &= ~I2C_CR1_ACK; + chSysUnlock(); + while(!(i2cp->id_i2c->SR1 & I2C_SR1_BTF)) + ; + chSysLock(); + i2cp->id_i2c->CR1 |= I2C_CR1_STOP; + *rxbuf = i2cp->id_i2c->DR; + rxbuf++; + i2cp->rxbytes--; + chSysUnlock(); + *rxbuf = i2cp->id_i2c->DR; + rxbuf++; + i2cp->rxbytes--; + while (i2cp->id_i2c->CR1 & I2C_CR1_STOP) + ; + i2cp->id_i2c->CR1 &= ~I2C_CR1_POS; + i2cp->id_i2c->CR1 |= I2C_CR1_ACK; + } + else{ /* 1 byte */ + i2cp->id_i2c->CR1 &= ~I2C_CR1_ACK; + chSysLock(); + while(!(i2cp->id_i2c->SR2 & I2C_SR2_BUSY)) /* to clear ADDR bit */ + ; + i2cp->id_i2c->CR1 |= I2C_CR1_STOP; + chSysUnlock(); + while(!(i2cp->id_i2c->SR1 & I2C_SR1_RXNE)) + ; + *rxbuf = i2cp->id_i2c->DR; + rxbuf++; + i2cp->rxbytes--; + while (i2cp->id_i2c->CR1 & I2C_CR1_STOP) + ; + i2cp->id_i2c->CR1 |= I2C_CR1_ACK; + } + } +} +#endif /* I2C_SUPPORTS_CALLBACKS */ + +#undef rxBuffp +#undef txBuffp + +#endif /* HAL_USE_I2C */ diff --git a/os/hal/platforms/STM32/I2Cv1/i2c_lld.h b/os/hal/platforms/STM32/I2Cv1/i2c_lld.h new file mode 100644 index 000000000..81a9f62dc --- /dev/null +++ b/os/hal/platforms/STM32/I2Cv1/i2c_lld.h @@ -0,0 +1,318 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32/i2c_lld.h + * @brief STM32 I2C subsystem low level driver header. + * @addtogroup I2C + * @{ + */ + +#ifndef _I2C_LLD_H_ +#define _I2C_LLD_H_ + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Switch between callback based and synchronouse driver. + * @note The default is synchronouse. + */ +#if !defined(I2C_SUPPORTS_CALLBACKS) || defined(__DOXYGEN__) +#define I2C_SUPPORTS_CALLBACKS TRUE +#endif + +/** + * @brief I2C1 driver synchronization choice between GPT and polling. + * @note The default is polling wait. + */ +#if !defined(STM32_I2C_I2C1_USE_GPT_TIM) || \ + !defined(STM32_I2C_I2C1_USE_POLLING_WAIT) || \ + defined(__DOXYGEN__) +#define STM32_I2C_I2C1_USE_POLLING_WAIT TRUE +#endif + +/** + * @brief I2C2 driver synchronization choice between GPT and polling. + * @note The default is polling wait. + */ +#if !defined(STM32_I2C_I2C2_USE_GPT_TIM) || \ + !defined(STM32_I2C_I2C2_USE_POLLING_WAIT) || \ + defined(__DOXYGEN__) +#define STM32_I2C_I2C2_USE_POLLING_WAIT TRUE +#endif + +/** + * @brief I2C1 driver enable switch. + * @details If set to @p TRUE the support for I2C1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__) +#define STM32_I2C_USE_I2C1 TRUE +#endif + +/** + * @brief I2C2 driver enable switch. + * @details If set to @p TRUE the support for I2C2 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__) +#define STM32_I2C_USE_I2C2 TRUE +#endif + +/** + * @brief I2C1 interrupt priority level setting. + * @note @p BASEPRI_KERNEL >= @p STM32_I2C_I2C1_IRQ_PRIORITY > @p PRIORITY_PENDSV. + */ +#if !defined(STM32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2C_I2C1_IRQ_PRIORITY 0xA0 +#endif + +/** + * @brief I2C2 interrupt priority level setting. + * @note @p BASEPRI_KERNEL >= @p STM32_I2C_I2C2_IRQ_PRIORITY > @p PRIORITY_PENDSV. + */ +#if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2C_I2C2_IRQ_PRIORITY 0xA0 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/** @brief EV5 */ +#define I2C_EV5_MASTER_MODE_SELECT ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_SB)) /* BUSY, MSL and SB flag */ +/** @brief EV6 */ +#define I2C_EV6_MASTER_TRA_MODE_SELECTED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY|I2C_SR2_TRA)<< 16)|I2C_SR1_ADDR|I2C_SR1_TXE)) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EV6_MASTER_REC_MODE_SELECTED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_ADDR)) /* BUSY, MSL and ADDR flags */ +/** @brief EV7 */ +#define I2C_EV7_MASTER_REC_BYTE_RECEIVED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_RXNE)) /* BUSY, MSL and RXNE flags */ +#define I2C_EV7_MASTER_REC_BYTE_QUEUED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_BTF|I2C_SR1_RXNE)) /* BUSY, MSL, RXNE and BTF flags*/ +/** @brief EV8 */ +#define I2C_EV8_MASTER_BYTE_TRANSMITTING ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY|I2C_SR2_TRA)<< 16)|I2C_SR1_TXE)) /* TRA, BUSY, MSL, TXE flags */ +/** @brief EV8_2 */ +#define I2C_EV8_2_MASTER_BYTE_TRANSMITTED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY|I2C_SR2_TRA)<< 16)|I2C_SR1_BTF|I2C_SR1_TXE)) /* TRA, BUSY, MSL, TXE and BTF flags */ +/** @brief EV9 */ +#define I2C_EV9_MASTER_ADDR_10BIT ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_ADD10)) /* BUSY, MSL and ADD10 flags */ +#define I2C_EV_MASK 0x00FFFFFF /* First byte zeroed because there is no need of PEC register part from SR2 */ + +#define I2C_FLG_1BTR 0x01 /* Single byte to be received and processed */ +#define I2C_FLG_2BTR 0x02 /* Two bytes to be received and processed */ +#define I2C_FLG_3BTR 0x04 /* Last three received bytes to be processed */ +#define I2C_FLG_MASTER_RECEIVER 0x10 +#define I2C_FLG_HEADER_SENT 0x80 +#define I2C_FLG_TIMER_ARMED 0x40 /* Used to check locks on the bus */ + +#define EV6_SUBEV_MASK (I2C_FLG_1BTR|I2C_FLG_2BTR|I2C_FLG_MASTER_RECEIVER) +#define EV7_SUBEV_MASK (I2C_FLG_2BTR|I2C_FLG_3BTR|I2C_FLG_MASTER_RECEIVER) + +#define I2C_EV6_1_MASTER_REC_2BTR_MODE_SELECTED (I2C_FLG_2BTR|I2C_FLG_MASTER_RECEIVER) +#define I2C_EV6_3_MASTER_REC_1BTR_MODE_SELECTED (I2C_FLG_1BTR|I2C_FLG_MASTER_RECEIVER) +#define I2C_EV7_2_MASTER_REC_3BYTES_TO_PROCESS (I2C_FLG_3BTR|I2C_FLG_MASTER_RECEIVER) +#define I2C_EV7_3_MASTER_REC_2BYTES_TO_PROCESS (I2C_FLG_2BTR|I2C_FLG_MASTER_RECEIVER) + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief I2C Driver condition flags type. + */ +typedef uint32_t i2cflags_t; + +typedef enum { + OPMODE_I2C = 1, + OPMODE_SMBUS_DEVICE = 2, + OPMODE_SMBUS_HOST = 3, +} i2copmode_t; + +typedef enum { + STD_DUTY_CYCLE = 1, + FAST_DUTY_CYCLE_2 = 2, + FAST_DUTY_CYCLE_16_9 = 3, +} i2cdutycycle_t; + +/** + * @brief Driver configuration structure. + */ +typedef struct { + i2copmode_t op_mode; /**< @brief Specifies the I2C mode.*/ + uint32_t clock_speed; /**< @brief Specifies the clock frequency. Must be set to a value lower than 400kHz */ + i2cdutycycle_t duty_cycle; /**< @brief Specifies the I2C fast mode duty cycle */ + uint8_t own_addr_7; /**< @brief Specifies the first device 7-bit own address. */ + uint16_t own_addr_10; /**< @brief Specifies the second part of device own address in 10-bit mode. Set to NULL if not used. */ + uint8_t nbit_own_addr; /**< @brief Specifies if 7-bit or 10-bit address is acknowledged */ +} I2CConfig; + + +/** + * @brief Type of a structure representing an I2C driver. + */ +typedef struct I2CDriver I2CDriver; + +/** + * @brief Type of a structure representing an I2C slave config. + */ +typedef struct I2CSlaveConfig I2CSlaveConfig; + +/** + * @brief Structure representing an I2C driver. + */ +struct I2CDriver{ + /** + * @brief Driver state. + */ + i2cstate_t id_state; + +#if I2C_USE_WAIT + /** + * @brief Thread waiting for I/O completion. + */ + Thread *id_thread; +#endif /* I2C_USE_WAIT */ +#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex id_mutex; +#elif CH_USE_SEMAPHORES + Semaphore id_semaphore; +#endif +#endif /* I2C_USE_MUTUAL_EXCLUSION */ + + /** + * @brief Current configuration data. + */ + const I2CConfig *id_config; + /** + * @brief Current slave configuration data. + */ + const I2CSlaveConfig *id_slave_config; + + __IO size_t txbytes; /*!< @brief Number of bytes to be transmitted. */ + __IO size_t rxbytes; /*!< @brief Number of bytes to be received. */ + uint8_t *rxbuf; /*!< @brief Pointer to receive buffer. */ + uint8_t *txbuf; /*!< @brief Pointer to transmit buffer.*/ + uint8_t *rxbuff_p; /*!< @brief Pointer to the current byte in slave rx buffer. */ + uint8_t *txbuff_p; /*!< @brief Pointer to the current byte in slave tx buffer. */ + + __IO i2cflags_t errors; /*!< @brief Error flags.*/ + __IO i2cflags_t flags; /*!< @brief State flags.*/ + + uint16_t slave_addr; /*!< @brief Current slave address. */ + uint8_t slave_addr1;/*!< @brief 7-bit address of the slave with r\w bit.*/ + uint8_t slave_addr2;/*!< @brief Uses in 10-bit address mode. */ + +#if CH_USE_EVENTS + EventSource sevent; /*!< @brief Status Change @p EventSource.*/ +#endif + + /*********** End of the mandatory fields. **********************************/ + + /** + * @brief Pointer to the I2Cx registers block. + */ + I2C_TypeDef *id_i2c; + +#if !(STM32_I2C_I2C1_USE_POLLING_WAIT) + /* TODO: capability to switch this GPT fields off */ + /** + * @brief Timer for waiting STOP condition on the bus. + * @details This is workaround for STM32 buggy I2C cell. + */ + GPTDriver *timer; + + /** + * @brief Config for workaround timer. + */ + const GPTConfig *timer_cfg; +#endif /* !(STM32_I2C_I2C1_USE_POLLING_WAIT) */ +}; + + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +#define i2c_lld_bus_is_busy(i2cp) \ + (i2cp->id_i2c->SR2 & I2C_SR2_BUSY) + + +/* Wait until BUSY flag is reset: a STOP has been generated on the bus + * signaling the end of transmission. Normally this wait function + * does not block thread, only if slave not response it does. + */ +#define i2c_lld_wait_bus_free(i2cp) { \ + uint32_t tmo = 0xfffff; \ + while((i2cp->id_i2c->SR2 & I2C_SR2_BUSY) && tmo--) \ + ; \ +} + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/** @cond never*/ +#if STM32_I2C_USE_I2C1 +extern I2CDriver I2CD1; +#endif + +#if STM32_I2C_USE_I2C2 +extern I2CDriver I2CD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +void i2c_lld_init(void); +void i2c_lld_reset(I2CDriver *i2cp); +void i2c_lld_set_clock(I2CDriver *i2cp); +void i2c_lld_set_opmode(I2CDriver *i2cp); +void i2c_lld_set_own_address(I2CDriver *i2cp); +void i2c_lld_start(I2CDriver *i2cp); +void i2c_lld_stop(I2CDriver *i2cp); +void i2c_lld_master_transmit(I2CDriver *i2cp, uint16_t slave_addr, + uint8_t *txbuf, size_t txbytes, uint8_t *rxbuf, size_t rxbytes); +void i2c_lld_master_receive(I2CDriver *i2cp, uint16_t slave_addr, + uint8_t *rxbuf, size_t rxbytes); +void i2c_lld_master_transceive(I2CDriver *i2cp); + +#ifdef __cplusplus +} +#endif +/** @endcond*/ + +#endif /* CH_HAL_USE_I2C */ + +#endif /* _I2C_LLD_H_ */ -- cgit v1.2.3 From 62608271adb730505a4a3d0a9ef49ef2efe91552 Mon Sep 17 00:00:00 2001 From: barthess Date: Thu, 1 Dec 2011 20:17:58 +0000 Subject: I2C. Code compiles but does not work. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3548 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/i2c_lld.c | 472 +++++---------------------------------- os/hal/platforms/STM32/i2c_lld.h | 53 +---- os/hal/src/i2c.c | 8 - 3 files changed, 68 insertions(+), 465 deletions(-) (limited to 'os') diff --git a/os/hal/platforms/STM32/i2c_lld.c b/os/hal/platforms/STM32/i2c_lld.c index 497975d2d..ccec33dbc 100644 --- a/os/hal/platforms/STM32/i2c_lld.c +++ b/os/hal/platforms/STM32/i2c_lld.c @@ -82,6 +82,12 @@ static volatile uint16_t dbgCR2 = 0; /*===========================================================================*/ +static void i2c_serve_event_interrupt(I2CDriver *i2cp) { + +} + + + static void i2c_serve_error_interrupt(I2CDriver *i2cp) { i2cflags_t flags; I2C_TypeDef *reg; @@ -132,63 +138,54 @@ static void i2c_serve_error_interrupt(I2CDriver *i2cp) { } +static void i2c_lld_serve_rx_end_irq(UARTDriver *i2cp, uint32_t flags) { + +} + +static void i2c_lld_serve_tx_end_irq(UARTDriver *i2cp, uint32_t flags) { + +} + + + #if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__) #error "Unrealized yet" #endif /* STM32_I2C_USE_I2C1 */ - #if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__) /** * @brief I2C2 event interrupt handler. */ -#if I2C_SUPPORTS_CALLBACKS -CH_IRQ_HANDLER(VectorC4) { - +CH_IRQ_HANDLER(I2C2_EV_IRQHandler) { CH_IRQ_PROLOGUE(); i2c_serve_event_interrupt(&I2CD2); CH_IRQ_EPILOGUE(); } -#endif /* I2C_SUPPORTS_CALLBACKS */ /** * @brief I2C2 error interrupt handler. */ -CH_IRQ_HANDLER(VectorC8) { - +CH_IRQ_HANDLER(I2C2_ER_IRQHandler) { CH_IRQ_PROLOGUE(); i2c_serve_error_interrupt(&I2CD2); CH_IRQ_EPILOGUE(); } #endif /* STM32_I2C_USE_I2C2 */ + /** * @brief Low level I2C driver initialization. */ void i2c_lld_init(void) { #if STM32_I2C_USE_I2C1 - i2cObjectInit(&I2CD1); - I2CD1.id_i2c = I2C1; - -#if I2C_SUPPORTS_CALLBACKS -#if !(STM32_I2C_I2C1_USE_POLLING_WAIT) - I2CD1.timer = &(STM32_I2C_I2C1_USE_GPT_TIM); - I2CD1.timer_cfg = &i2c1gptcfg; -#endif /* !(STM32_I2C_I2C1_USE_POLLING_WAIT) */ -#endif /* I2C_SUPPORTS_CALLBACKS */ - +#error "Unrealized yet" #endif /* STM32_I2C_USE_I2C */ #if STM32_I2C_USE_I2C2 i2cObjectInit(&I2CD2); - I2CD2.id_i2c = I2C2; - -#if I2C_SUPPORTS_CALLBACKS -#if !(STM32_I2C_I2C2_USE_POLLING_WAIT) - I2CD2.timer = &(STM32_I2C_I2C2_USE_GPT_TIM); - I2CD2.timer_cfg = &i2c2gptcfg; -#endif /* !(STM32_I2C_I2C2_USE_POLLING_WAIT) */ -#endif /* I2C_SUPPORTS_CALLBACKS */ - + I2CD2.id_i2c = I2C2; + I2CD2.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C2_RX_DMA_STREAM); + I2CD2.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C2_TX_DMA_STREAM); #endif /* STM32_I2C_USE_I2C2 */ } @@ -198,30 +195,49 @@ void i2c_lld_init(void) { * @param[in] i2cp pointer to the @p I2CDriver object */ void i2c_lld_start(I2CDriver *i2cp) { + i2cp->dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + if (i2cp->id_state == I2C_STOP) { /* If in stopped state then enables the I2C clock.*/ #if STM32_I2C_USE_I2C1 - if (&I2CD1 == i2cp) { -#if I2C_SUPPORTS_CALLBACKS - NVICEnableVector(I2C1_EV_IRQn, - CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); -#endif /* I2C_SUPPORTS_CALLBACKS */ - NVICEnableVector(I2C1_ER_IRQn, - CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); - rccEnableI2C1(FALSE); - } +// if (&I2CD1 == i2cp) { +// NVICEnableVector(I2C1_EV_IRQn, +// CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); +// NVICEnableVector(I2C1_ER_IRQn, +// CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); +// rccEnableI2C1(FALSE); +// } +#error "Unrealized yet" #endif + #if STM32_I2C_USE_I2C2 if (&I2CD2 == i2cp) { -#if I2C_SUPPORTS_CALLBACKS + + bool_t b; + b = dmaStreamAllocate(i2cp->dmarx, + STM32_I2C_I2C2_IRQ_PRIORITY, + (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, + (void *)i2cp); + chDbgAssert(!b, "uart_lld_start(), #3", "stream already allocated"); + b = dmaStreamAllocate(i2cp->dmatx, + STM32_I2C_I2C2_IRQ_PRIORITY, + (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, + (void *)i2cp); + chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated"); + rccEnableI2C2(FALSE); NVICEnableVector(I2C2_EV_IRQn, CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); -#endif /* I2C_SUPPORTS_CALLBACKS */ NVICEnableVector(I2C2_ER_IRQn, CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); - rccEnableI2C2(FALSE); + + //i2cp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY); + // TODO: remove hardcoded "7" + i2cp->dmamode |= STM32_DMA_CR_CHSEL(7) | STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY); } -#endif +#endif /* STM32_I2C_USE_I2C2 */ } + i2cp->dmamode |= STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; + dmaStreamSetPeripheral(i2cp->dmarx, &i2cp->id_i2c->DR); + dmaStreamSetPeripheral(i2cp->dmatx, &i2cp->id_i2c->DR); i2cp->id_i2c->CR1 = I2C_CR1_SWRST; /* reset i2c peripherial */ i2cp->id_i2c->CR1 = 0; @@ -230,6 +246,9 @@ void i2c_lld_start(I2CDriver *i2cp) { i2cp->id_i2c->CR1 |= 1; /* enable interface */ } + + + void i2c_lld_reset(I2CDriver *i2cp){ chDbgCheck((i2cp->id_state == I2C_STOP)||(i2cp->id_state == I2C_READY), "i2c_lld_reset: invalid state"); @@ -386,9 +405,6 @@ void i2c_lld_stop(I2CDriver *i2cp) { } -#if I2C_SUPPORTS_CALLBACKS - - /** * @brief Transmits data via the I2C bus as master. * @@ -402,390 +418,18 @@ void i2c_lld_stop(I2CDriver *i2cp) { * @param[in] rxbuf pointer to the receive buffer * @param[in] rxbytes number of bytes to be received */ -void i2c_lld_master_transmit_dma(I2CDriver *i2cp, uint16_t slave_addr, - uint8_t *txbuf, size_t txbytes, uint8_t *rxbuf, size_t rxbytes) { - -} - - - - -/** - * @brief Transmits data via the I2C bus as master. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] slave_addr Slave device address. Bits 0-9 contain slave - * device address. Bit 15 must be set to 1 if 10-bit - * addressing modes used. Otherwise keep it cleared. - * Bits 10-14 unused. - * @param[in] txbuf pointer to the transmit buffer - * @param[in] txbytes number of bytes to be transmitted - * @param[in] rxbuf pointer to the receive buffer - * @param[in] rxbytes number of bytes to be received - */ void i2c_lld_master_transmit(I2CDriver *i2cp, uint16_t slave_addr, uint8_t *txbuf, size_t txbytes, uint8_t *rxbuf, size_t rxbytes) { - /* "waiting" for STOP bit routine*/ - #if STM32_I2C_I2C1_USE_POLLING_WAIT - uint32_t timeout = I2C_POLLING_TIMEOUT; - while((i2cp->id_i2c->CR1 & I2C_CR1_STOP) && timeout) - timeout--; - chDbgAssert((timeout > 0), "i2c_lld_master_transmit(), #1", "time to STOP is out"); - #else - chDbgAssert(!(i2cp->flags & I2C_FLG_TIMER_ARMED), "i2c_lld_master_transmit(), #1", "time to STOP is out"); - if ((i2cp->id_i2c->CR1 & I2C_CR1_STOP) && i2cp->timer != NULL && i2cp->timer_cfg != NULL){ - chSysLockFromIsr(); - gptStartOneShotI(i2cp->timer, I2C_STOP_GPT_TIMEOUT); - i2cp->flags |= I2C_FLG_TIMER_ARMED; - chSysUnlockFromIsr(); - return; - } - #endif /* STM32_I2C_I2C1_USE_POLLING_WAIT */ - - /* init driver fields */ - i2cp->slave_addr = slave_addr; - i2cp->txbytes = txbytes; - i2cp->rxbytes = rxbytes; - i2cp->txbuf = txbuf; - i2cp->rxbuf = rxbuf; - - /* init address fields */ - if(slave_addr & 0x8000){ /* 10-bit mode used */ - i2cp->slave_addr1 = ((slave_addr >>7) & 0x0006); /* add the two msb of 10-bit address to the header */ - i2cp->slave_addr1 |= 0xF0; /* add the header bits with LSB = 0 -> write */ - i2cp->slave_addr2 = slave_addr & 0x00FF; /* the remaining 8 bit of 10-bit address */ - } - else{ - i2cp->slave_addr1 = ((slave_addr <<1) & 0x00FE); /* LSB = 0 -> write */ - } - - /* setting flags and register bits */ - i2cp->flags = 0; - i2cp->errors = 0; - i2cp->id_i2c->CR1 &= ~I2C_CR1_POS; - i2cp->id_i2c->CR1 |= I2C_CR1_START; - i2cp->id_i2c->CR2 |= (I2C_CR2_ITERREN|I2C_CR2_ITEVTEN|I2C_CR2_ITBUFEN); /* enable ERR, EVT & BUF ITs */ } -/** - * @brief Receives data from the I2C bus. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] slave_addr Slave device address. Bits 0-9 contain slave - * device address. Bit 15 must be set to 1 if 10-bit - * addressing modes used. Otherwise keep it cleared. - * Bits 10-14 unused. - * @param[in] rxbuf pointer to the receive buffer - * @param[in] rxbytes number of bytes to be received - */ void i2c_lld_master_receive(I2CDriver *i2cp, uint16_t slave_addr, uint8_t *rxbuf, size_t rxbytes){ - - chDbgAssert((i2cp->id_i2c->SR1 + i2cp->id_i2c->SR2) == 0, - "i2c_lld_master_receive(), #1", - "some interrupt sources not clear"); - - /* "waiting" for STOP bit routine*/ - #if STM32_I2C_I2C1_USE_POLLING_WAIT - uint32_t timeout = I2C_POLLING_TIMEOUT; - while((i2cp->id_i2c->CR1 & I2C_CR1_STOP) && timeout) - timeout--; - chDbgAssert((timeout > 0), "i2c_lld_master_receive(), #1", "time to STOP is out"); - #else - chDbgAssert(!(i2cp->flags & I2C_FLG_TIMER_ARMED), "i2c_lld_master_receive(), #1", "time to STOP is out"); - if ((i2cp->id_i2c->CR1 & I2C_CR1_STOP) && i2cp->timer != NULL && i2cp->timer_cfg != NULL){ - chSysLockFromIsr(); - gptStartOneShotI(i2cp->timer, I2C_STOP_GPT_TIMEOUT); - i2cp->flags |= I2C_FLG_TIMER_ARMED; - chSysUnlockFromIsr(); - return; - } - #endif /* STM32_I2C_I2C1_USE_POLLING_WAIT */ - - /* init driver fields */ - i2cp->slave_addr = slave_addr; - i2cp->rxbytes = rxbytes; - i2cp->rxbuf = rxbuf; - - /* init address fields */ - if(slave_addr & 0x8000){ /* 10-bit mode used */ - i2cp->slave_addr1 = ((slave_addr >>7) & 0x0006); /* add the two msb of 10-bit address to the header */ - i2cp->slave_addr1 |= 0xF0; /* add the header bits (the LSB -> 1 will be add to second */ - i2cp->slave_addr2 = slave_addr & 0x00FF; /* the remaining 8 bit of 10-bit address */ - } - else{ - i2cp->slave_addr1 = ((slave_addr <<1) | 0x01); /* LSB = 1 -> receive */ - } - - /* setting flags and register bits */ - i2cp->flags |= I2C_FLG_MASTER_RECEIVER; - i2cp->errors = 0; - - i2cp->id_i2c->CR1 |= I2C_CR1_ACK; /* acknowledge returned */ - i2cp->id_i2c->CR1 &= ~I2C_CR1_POS; - - if(i2cp->rxbytes == 1) { /* Only one byte to be received */ - i2cp->flags |= I2C_FLG_1BTR; - } - else if(i2cp->rxbytes == 2) { /* Only two bytes to be received */ - i2cp->flags |= I2C_FLG_2BTR; - i2cp->id_i2c->CR1 |= I2C_CR1_POS; /* Acknowledge Position */ - } - - i2cp->id_i2c->CR1 |= I2C_CR1_START; /* send start bit */ - i2cp->id_i2c->CR2 |= (I2C_CR2_ITERREN|I2C_CR2_ITEVTEN|I2C_CR2_ITBUFEN); /* enable ERR, EVT & BUF ITs */ } - -/** - * @brief Realize read-though-write behavior. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ void i2c_lld_master_transceive(I2CDriver *i2cp){ - chDbgAssert((i2cp != NULL) && (i2cp->slave_addr1 != 0) &&\ - (i2cp->rxbytes > 0) && (i2cp->rxbuf != NULL), - "i2c_lld_master_transceive(), #1", - ""); - - i2cp->id_state = I2C_ACTIVE_TRANSCEIVE; - - /* "waiting" for START bit routine*/ - #if STM32_I2C_I2C1_USE_POLLING_WAIT - uint32_t timeout = I2C_POLLING_TIMEOUT; - while((i2cp->id_i2c->CR1 & I2C_CR1_START) && timeout); - timeout--; - chDbgAssert((timeout > 0), "i2c_lld_master_transceive(), #1", "time to START is out"); - #else - chDbgAssert(!(i2cp->flags & I2C_FLG_TIMER_ARMED), "i2c_lld_master_transceive(), #1", "time to START is out"); - if ((i2cp->id_i2c->CR1 & I2C_CR1_START) && i2cp->timer != NULL && i2cp->timer_cfg != NULL){ - chSysLockFromIsr(); - gptStartOneShotI(i2cp->timer, I2C_START_GPT_TIMEOUT); - i2cp->flags |= I2C_FLG_TIMER_ARMED; - chSysUnlockFromIsr(); - return; - } - #endif /* STM32_I2C_I2C1_USE_POLLING_WAIT */ - - /* init address fields */ - if(i2cp->slave_addr & 0x8000){ /* 10-bit mode used */ - i2cp->slave_addr1 = ((i2cp->slave_addr >>7) & 0x0006);/* add the two msb of 10-bit address to the header */ - i2cp->slave_addr1 |= 0xF0; /* add the header bits (the LSB -> 1 will be add to second */ - i2cp->slave_addr2 = i2cp->slave_addr & 0x00FF; /* the remaining 8 bit of 10-bit address */ - } - else{ - i2cp->slave_addr1 |= 0x01; - } - - /* setting flags and register bits */ - i2cp->flags |= I2C_FLG_MASTER_RECEIVER; - i2cp->errors = 0; - i2cp->id_i2c->CR1 |= I2C_CR1_ACK; /* acknowledge returned */ - i2cp->id_i2c->CR1 &= ~I2C_CR1_POS; - - if(i2cp->rxbytes == 1) { /* Only one byte to be received */ - i2cp->flags |= I2C_FLG_1BTR; - } - else if(i2cp->rxbytes == 2) { /* Only two bytes to be received */ - i2cp->flags |= I2C_FLG_2BTR; - i2cp->id_i2c->CR1 |= I2C_CR1_POS; /* Acknowledge Position */ - } - - i2cp->id_i2c->CR2 |= (I2C_CR2_ITERREN|I2C_CR2_ITEVTEN|I2C_CR2_ITBUFEN); /* enable ERR, EVT & BUF ITs */ -} - -#else /*I2C_SUPPORTS_CALLBACKS*/ - -/** - * @brief Synchronously transmits data via the I2C bus as master. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] slave_addr Slave device address. Bits 0-9 contain slave - * device address. Bit 15 must be set to 1 if 10-bit - * addressing modes used. Otherwise keep it cleared. - * Bits 10-14 unused. - * @param[in] txbuf pointer to the transmit buffer - * @param[in] txbytes number of bytes to be transmitted - * @param[in] rxbuf pointer to the receive buffer - * @param[in] rxbytes number of bytes to be received - */ -void i2c_lld_master_transmit(I2CDriver *i2cp, uint16_t slave_addr, - uint8_t *txbuf, size_t txbytes, uint8_t *rxbuf, size_t rxbytes) { - - /* init driver fields */ - i2cp->slave_addr = slave_addr; - i2cp->txbytes = txbytes; - i2cp->rxbytes = rxbytes; - i2cp->txbuf = txbuf; - i2cp->rxbuf = rxbuf; - - /* init address fields */ - if(slave_addr & 0x8000){ /* 10-bit mode used */ - i2cp->slave_addr1 = ((slave_addr >>7) & 0x0006); /* add the two msb of 10-bit address to the header */ - i2cp->slave_addr1 |= 0xF0; /* add the header bits with LSB = 0 -> write */ - i2cp->slave_addr2 = slave_addr & 0x00FF; /* the remaining 8 bit of 10-bit address */ - } - else{ - i2cp->slave_addr1 = ((slave_addr <<1) & 0x00FE); /* LSB = 0 -> write */ - } - - i2cp->flags = 0; - i2cp->errors = 0; - i2cp->id_i2c->CR1 &= ~I2C_CR1_POS; - i2cp->id_i2c->CR2 &= ~I2C_CR2_ITEVTEN; /* disable event interrupts */ - i2cp->id_i2c->CR2 |= I2C_CR2_ITERREN; /* enable error interrupts */ - - i2cp->id_i2c->CR1 |= I2C_CR1_START; - while (!(i2cp->id_i2c->SR1 & I2C_SR1_SB)) - ; - i2cp->id_i2c->DR = i2cp->slave_addr1; - while (!(i2cp->id_i2c->SR1 & I2C_SR1_ADDR)) - ; - while (!(i2cp->id_i2c->SR2 & I2C_SR2_BUSY)) - ; - i2cp->id_i2c->DR = *txbuf; - txbuf++; - i2cp->txbytes--; - while(i2cp->txbytes > 0){ - while(!(i2cp->id_i2c->SR1 & I2C_SR1_BTF)) - ; - i2cp->id_i2c->DR = *txbuf; - txbuf++; - i2cp->txbytes--; - } - while(!(i2cp->id_i2c->SR1 & I2C_SR1_BTF)) - ; - if(rxbytes == 0){ - i2cp->id_i2c->CR1 |= I2C_CR1_STOP; - while (i2cp->id_i2c->CR1 & I2C_CR1_STOP) - ; - } - else{ - i2c_lld_master_receive(i2cp, slave_addr, rxbuf, rxbytes); - } -} - - -/** - * @brief Synchronously receives data from the I2C bus. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] slave_addr Slave device address. Bits 0-9 contain slave - * device address. Bit 15 must be set to 1 if 10-bit - * addressing modes used. Otherwise keep it cleared. - * Bits 10-14 unused. - * @param[in] rxbuf pointer to the receive buffer - * @param[in] rxbytes number of bytes to be received - */ -void i2c_lld_master_receive(I2CDriver *i2cp, uint16_t slave_addr, - uint8_t *rxbuf, size_t rxbytes){ - - /* init driver fields */ - i2cp->slave_addr = slave_addr; - i2cp->rxbytes = rxbytes; - i2cp->rxbuf = rxbuf; - - /* init address fields */ - if(slave_addr & 0x8000){ /* 10-bit mode used */ - i2cp->slave_addr1 = ((slave_addr >>7) & 0x0006); /* add the two msb of 10-bit address to the header */ - i2cp->slave_addr1 |= 0xF0; /* add the header bits (the LSB -> 1 will be add to second */ - i2cp->slave_addr2 = slave_addr & 0x00FF; /* the remaining 8 bit of 10-bit address */ - } - else{ - i2cp->slave_addr1 = ((slave_addr <<1) | 0x01); /* LSB = 1 -> receive */ - } - - - /* setting flags and register bits */ - i2cp->flags = 0; - i2cp->errors = 0; - i2cp->id_i2c->CR1 &= ~I2C_CR1_POS; - i2cp->id_i2c->CR2 &= ~I2C_CR2_ITEVTEN; /* disable event interrupts */ - i2cp->id_i2c->CR2 |= I2C_CR2_ITERREN; /* enable error interrupts */ - - i2cp->id_i2c->CR1 |= I2C_CR1_START; - while (!(i2cp->id_i2c->SR1 & I2C_SR1_SB)) - ; - - i2cp->id_i2c->DR = i2cp->slave_addr1; - while (!(i2cp->id_i2c->SR1 & I2C_SR1_ADDR)) - ; - - if(i2cp->rxbytes >= 3){ /* more than 2 bytes receiving procedure */ - while(!(i2cp->id_i2c->SR2 & I2C_SR2_BUSY)) /* to clear ADDR bit */ - ; - while(i2cp->rxbytes > 3){ - while(!(i2cp->id_i2c->SR1 & I2C_SR1_BTF)) - ; - *rxbuf = i2cp->id_i2c->DR; - rxbuf++; - i2cp->rxbytes--; - } - while(!(i2cp->id_i2c->SR1 & I2C_SR1_BTF)) /* stopping procedure */ - ; - i2cp->id_i2c->CR1 &= ~I2C_CR1_ACK; - chSysLock(); - i2cp->id_i2c->CR1 |= I2C_CR1_STOP; - *rxbuf = i2cp->id_i2c->DR; - rxbuf++; - i2cp->rxbytes--; - chSysUnlock(); - while(!(i2cp->id_i2c->SR1 & I2C_SR1_RXNE)) - ; - *rxbuf = i2cp->id_i2c->DR; - rxbuf++; - i2cp->rxbytes--; - while (i2cp->id_i2c->CR1 & I2C_CR1_STOP) - ; - i2cp->id_i2c->CR1 |= I2C_CR1_ACK; - } - else{ /* 1 or 2 bytes receiving procedure */ - if(i2cp->rxbytes == 2){ - i2cp->id_i2c->CR1 |= I2C_CR1_POS; - chSysLock(); - while(!(i2cp->id_i2c->SR2 & I2C_SR2_BUSY)) /* to clear ADDR bit */ - ; - i2cp->id_i2c->CR1 &= ~I2C_CR1_ACK; - chSysUnlock(); - while(!(i2cp->id_i2c->SR1 & I2C_SR1_BTF)) - ; - chSysLock(); - i2cp->id_i2c->CR1 |= I2C_CR1_STOP; - *rxbuf = i2cp->id_i2c->DR; - rxbuf++; - i2cp->rxbytes--; - chSysUnlock(); - *rxbuf = i2cp->id_i2c->DR; - rxbuf++; - i2cp->rxbytes--; - while (i2cp->id_i2c->CR1 & I2C_CR1_STOP) - ; - i2cp->id_i2c->CR1 &= ~I2C_CR1_POS; - i2cp->id_i2c->CR1 |= I2C_CR1_ACK; - } - else{ /* 1 byte */ - i2cp->id_i2c->CR1 &= ~I2C_CR1_ACK; - chSysLock(); - while(!(i2cp->id_i2c->SR2 & I2C_SR2_BUSY)) /* to clear ADDR bit */ - ; - i2cp->id_i2c->CR1 |= I2C_CR1_STOP; - chSysUnlock(); - while(!(i2cp->id_i2c->SR1 & I2C_SR1_RXNE)) - ; - *rxbuf = i2cp->id_i2c->DR; - rxbuf++; - i2cp->rxbytes--; - while (i2cp->id_i2c->CR1 & I2C_CR1_STOP) - ; - i2cp->id_i2c->CR1 |= I2C_CR1_ACK; - } - } } -#endif /* I2C_SUPPORTS_CALLBACKS */ #undef rxBuffp #undef txBuffp diff --git a/os/hal/platforms/STM32/i2c_lld.h b/os/hal/platforms/STM32/i2c_lld.h index 24195147a..e4fb8970f 100644 --- a/os/hal/platforms/STM32/i2c_lld.h +++ b/os/hal/platforms/STM32/i2c_lld.h @@ -42,33 +42,6 @@ * @name Configuration options * @{ */ -/** - * @brief Switch between callback based and synchronouse driver. - * @note The default is synchronouse. - */ -#if !defined(I2C_SUPPORTS_CALLBACKS) || defined(__DOXYGEN__) -#define I2C_SUPPORTS_CALLBACKS TRUE -#endif - -/** - * @brief I2C1 driver synchronization choice between GPT and polling. - * @note The default is polling wait. - */ -#if !defined(STM32_I2C_I2C1_USE_GPT_TIM) || \ - !defined(STM32_I2C_I2C1_USE_POLLING_WAIT) || \ - defined(__DOXYGEN__) -#define STM32_I2C_I2C1_USE_POLLING_WAIT TRUE -#endif - -/** - * @brief I2C2 driver synchronization choice between GPT and polling. - * @note The default is polling wait. - */ -#if !defined(STM32_I2C_I2C2_USE_GPT_TIM) || \ - !defined(STM32_I2C_I2C2_USE_POLLING_WAIT) || \ - defined(__DOXYGEN__) -#define STM32_I2C_I2C2_USE_POLLING_WAIT TRUE -#endif /** * @brief I2C1 driver enable switch. @@ -238,25 +211,22 @@ struct I2CDriver{ #endif /*********** End of the mandatory fields. **********************************/ - /** - * @brief Pointer to the I2Cx registers block. + * @brief DMA mode bit mask. */ - I2C_TypeDef *id_i2c; - -#if !(STM32_I2C_I2C1_USE_POLLING_WAIT) - /* TODO: capability to switch this GPT fields off */ + uint32_t dmamode; /** - * @brief Timer for waiting STOP condition on the bus. - * @details This is workaround for STM32 buggy I2C cell. + * @brief Receive DMA channel. */ - GPTDriver *timer; - + const stm32_dma_stream_t *dmarx; /** - * @brief Config for workaround timer. + * @brief Transmit DMA channel. */ - const GPTConfig *timer_cfg; -#endif /* !(STM32_I2C_I2C1_USE_POLLING_WAIT) */ + const stm32_dma_stream_t *dmatx; + /** + * @brief Pointer to the I2Cx registers block. + */ + I2C_TypeDef *id_i2c; }; @@ -308,9 +278,6 @@ void i2c_lld_master_receive(I2CDriver *i2cp, uint16_t slave_addr, uint8_t *rxbuf, size_t rxbytes); void i2c_lld_master_transceive(I2CDriver *i2cp); -void i2c_lld_master_transmit_dma(I2CDriver *i2cp, uint16_t slave_addr, - uint8_t *txbuf, size_t txbytes, uint8_t *rxbuf, size_t rxbytes); - #ifdef __cplusplus } #endif diff --git a/os/hal/src/i2c.c b/os/hal/src/i2c.c index abd3252cf..0f46e4e64 100644 --- a/os/hal/src/i2c.c +++ b/os/hal/src/i2c.c @@ -111,10 +111,6 @@ void i2cStart(I2CDriver *i2cp, const I2CConfig *config) { "i2cStart(), #1", "invalid state"); -#if (!(STM32_I2C_I2C2_USE_POLLING_WAIT) && I2C_SUPPORTS_CALLBACKS) - gptStart(i2cp->timer, i2cp->timer_cfg); -#endif /* !(STM32_I2C_I2C2_USE_POLLING_WAIT) */ - chSysLock(); i2cp->id_config = config; i2c_lld_start(i2cp); @@ -136,10 +132,6 @@ void i2cStop(I2CDriver *i2cp) { "i2cStop(), #1", "invalid state"); -#if (!(STM32_I2C_I2C2_USE_POLLING_WAIT) && I2C_SUPPORTS_CALLBACKS) - gptStop(i2cp->timer); -#endif /* !(STM32_I2C_I2C2_USE_POLLING_WAIT) */ - chSysLock(); i2c_lld_stop(i2cp); i2cp->id_state = I2C_STOP; -- cgit v1.2.3 From c995ee2bd31d5ee7173668c57f9c2c80ae7cc1b3 Mon Sep 17 00:00:00 2001 From: barthess Date: Fri, 2 Dec 2011 08:29:27 +0000 Subject: I2C. Added attributes. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3549 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F4xx/hal_lld.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'os') diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index 0650c84f8..1310738d4 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -292,8 +292,24 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) | \ + STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C1_RX_DMA_CHN 0x00100001 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_TX_DMA_CHN 0x10000000 + #define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) | \ + STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_I2C2_RX_DMA_CHN 0x00007700 +#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C2_TX_DMA_CHN 0x70000000 + #define STM32_HAS_I2C3 TRUE +#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_I2C3_RX_DMA_CHN 0x00000300 +#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_I2C3_TX_DMA_CHN 0x00030000 /* RTC attributes.*/ #define STM32_HAS_RTC TRUE -- cgit v1.2.3 From dbac0ef26b2977c9862ec6ddc22f10dac76b3239 Mon Sep 17 00:00:00 2001 From: barthess Date: Fri, 2 Dec 2011 15:01:31 +0000 Subject: I2C. DMA works. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3550 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/i2c_lld.c | 200 +++++++++++++++++++++++++++++++++++++-- os/hal/src/i2c.c | 2 +- 2 files changed, 191 insertions(+), 11 deletions(-) (limited to 'os') diff --git a/os/hal/platforms/STM32/i2c_lld.c b/os/hal/platforms/STM32/i2c_lld.c index ccec33dbc..9afdc8619 100644 --- a/os/hal/platforms/STM32/i2c_lld.c +++ b/os/hal/platforms/STM32/i2c_lld.c @@ -43,6 +43,25 @@ * Otherwise there is a risk of setting a second STOP, START or PEC request. */ +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ +#define I2C1_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_RX_DMA_STREAM, \ + STM32_I2C1_RX_DMA_CHN) + +#define I2C1_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_TX_DMA_STREAM, \ + STM32_I2C1_TX_DMA_CHN) + +#define I2C2_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_RX_DMA_STREAM, \ + STM32_I2C2_RX_DMA_CHN) + +#define I2C2_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_TX_DMA_STREAM, \ + STM32_I2C2_TX_DMA_CHN) + /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ @@ -82,12 +101,71 @@ static volatile uint16_t dbgCR2 = 0; /*===========================================================================*/ + + +#if CH_DBG_ENABLE_ASSERTS +void _i2c_unhandled_case(I2CDriver *i2cp){ + dbgCR1 = i2cp->id_i2c->CR1; + dbgCR2 = i2cp->id_i2c->CR2; + chDbgAssert((dbgSR1 + dbgSR2) == 0, + "i2c_serve_event_interrupt(), #1", + "unhandled case"); +} +#else +#define _i2c_unhandled_case(i2cp) +#endif /* CH_DBG_ENABLE_ASSERTS */ + + + + +/** + * @brief Return the last event value from I2C status registers. + * @note Internal use only. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static uint32_t i2c_get_event(I2CDriver *i2cp){ + uint16_t regSR1 = i2cp->id_i2c->SR1; + uint16_t regSR2 = i2cp->id_i2c->SR2; + #if CH_DBG_ENABLE_ASSERTS + dbgSR1 = regSR1; + dbgSR2 = regSR2; + #endif /* CH_DBG_ENABLE_ASSERTS */ + + return (I2C_EV_MASK & (regSR1 | (regSR2 << 16))); +} + + + + + static void i2c_serve_event_interrupt(I2CDriver *i2cp) { + I2C_TypeDef *dp = i2cp->id_i2c; + switch(i2c_get_event(i2cp)){ + case I2C_EV5_MASTER_MODE_SELECT: + i2cp->flags &= ~I2C_FLG_HEADER_SENT; + dp->DR = i2cp->slave_addr1; + break; + + case I2C_EV6_MASTER_REC_MODE_SELECTED: + /* begin receiving via DMA */ + i2cp->id_i2c->CR2 &= ~I2C_CR2_ITBUFEN; /* switch off interrupt because we use DMA*/ + break; + + + + default: + break; + } } + + static void i2c_serve_error_interrupt(I2CDriver *i2cp) { i2cflags_t flags; I2C_TypeDef *reg; @@ -138,16 +216,32 @@ static void i2c_serve_error_interrupt(I2CDriver *i2cp) { } -static void i2c_lld_serve_rx_end_irq(UARTDriver *i2cp, uint32_t flags) { + + + +static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp, uint32_t flags){ + (void)flags; + + dmaStreamDisable(i2cp->dmarx); + i2cp->id_i2c->CR1 |= I2C_CR1_STOP; + while(i2cp->id_i2c->CR1 & I2C_CR1_STOP) + ; + _i2c_isr_code(i2cp, i2cp->id_slave_config); } -static void i2c_lld_serve_tx_end_irq(UARTDriver *i2cp, uint32_t flags) { + +static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp, uint32_t flags) { + (void)i2cp; + (void)flags; } + + + #if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__) #error "Unrealized yet" #endif /* STM32_I2C_USE_I2C1 */ @@ -172,6 +266,9 @@ CH_IRQ_HANDLER(I2C2_ER_IRQHandler) { #endif /* STM32_I2C_USE_I2C2 */ + + + /** * @brief Low level I2C driver initialization. */ @@ -189,6 +286,11 @@ void i2c_lld_init(void) { #endif /* STM32_I2C_USE_I2C2 */ } + + + + + /** * @brief Configures and activates the I2C peripheral. * @@ -229,9 +331,8 @@ void i2c_lld_start(I2CDriver *i2cp) { NVICEnableVector(I2C2_ER_IRQn, CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); - //i2cp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY); - // TODO: remove hardcoded "7" - i2cp->dmamode |= STM32_DMA_CR_CHSEL(7) | STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY); + i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY); } #endif /* STM32_I2C_USE_I2C2 */ } @@ -243,12 +344,15 @@ void i2c_lld_start(I2CDriver *i2cp) { i2cp->id_i2c->CR1 = 0; i2c_lld_set_clock(i2cp); i2c_lld_set_opmode(i2cp); + i2cp->id_i2c->CR1 |= 1; /* enable interface */ } + + void i2c_lld_reset(I2CDriver *i2cp){ chDbgCheck((i2cp->id_state == I2C_STOP)||(i2cp->id_state == I2C_READY), "i2c_lld_reset: invalid state"); @@ -259,6 +363,11 @@ void i2c_lld_reset(I2CDriver *i2cp){ } + + + + + /** * @brief Set clock speed. * @@ -329,6 +438,12 @@ void i2c_lld_set_clock(I2CDriver *i2cp) { i2cp->id_i2c->CR1 |= pe_bit_saved; /* restore the I2C peripheral enabled state */ } + + + + + + /** * @brief Set operation mode of I2C hardware. * @@ -355,6 +470,14 @@ void i2c_lld_set_opmode(I2CDriver *i2cp) { i2cp->id_i2c->CR1 = regCR1; /* Write to I2Cx CR1 */ } + + + + + + + + /** * @brief Set own address. * @@ -378,6 +501,11 @@ void i2c_lld_set_own_address(I2CDriver *i2cp) { } + + + + + /** * @brief Deactivates the I2C peripheral. * @@ -405,6 +533,52 @@ void i2c_lld_stop(I2CDriver *i2cp) { } + + + + +void i2c_lld_master_receive(I2CDriver *i2cp, uint16_t slave_addr, uint8_t *rxbuf, size_t rxbytes){ + (void)slave_addr; + + uint32_t mode = 0; + + /* init driver fields */ + i2cp->slave_addr = slave_addr; + i2cp->rxbytes = rxbytes; + i2cp->rxbuf = rxbuf; + + /* init address fields */ + if(slave_addr & 0x8000){ /* 10-bit mode used */ + i2cp->slave_addr1 = ((slave_addr >>7) & 0x0006); /* add the two msb of 10-bit address to the header */ + i2cp->slave_addr1 |= 0xF0; /* add the header bits (the LSB -> 1 will be add to second */ + i2cp->slave_addr2 = slave_addr & 0x00FF; /* the remaining 8 bit of 10-bit address */ + } + else{ + i2cp->slave_addr1 = ((slave_addr <<1) | 0x01); /* LSB = 1 -> receive */ + } + + /* setting flags and register bits */ + i2cp->flags |= I2C_FLG_MASTER_RECEIVER; + i2cp->errors = 0; + + mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE; + // TODO: DMA error handling + dmaStreamSetMemory0(i2cp->dmarx, rxbuf); + dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); + dmaStreamSetMode(i2cp->dmarx, ((i2cp->dmamode) | mode)); + dmaStreamEnable(i2cp->dmarx); + + i2cp->id_i2c->CR2 |= I2C_CR2_DMAEN | I2C_CR2_LAST; + + i2cp->id_i2c->CR2 |= I2C_CR2_ITERREN | I2C_CR2_ITEVTEN; + i2cp->id_i2c->CR1 |= I2C_CR1_START | I2C_CR1_ACK; +} + + + + + + /** * @brief Transmits data via the I2C bus as master. * @@ -420,15 +594,21 @@ void i2c_lld_stop(I2CDriver *i2cp) { */ void i2c_lld_master_transmit(I2CDriver *i2cp, uint16_t slave_addr, uint8_t *txbuf, size_t txbytes, uint8_t *rxbuf, size_t rxbytes) { - + (void)i2cp; + (void)slave_addr; + (void)txbuf; + (void)txbytes; + (void)rxbuf; + (void)rxbytes; } -void i2c_lld_master_receive(I2CDriver *i2cp, uint16_t slave_addr, - uint8_t *rxbuf, size_t rxbytes){ -} -void i2c_lld_master_transceive(I2CDriver *i2cp){ + + + +void i2c_lld_master_transceive(I2CDriver *i2cp){ + (void)i2cp; } #undef rxBuffp diff --git a/os/hal/src/i2c.c b/os/hal/src/i2c.c index 0f46e4e64..3add2af98 100644 --- a/os/hal/src/i2c.c +++ b/os/hal/src/i2c.c @@ -210,7 +210,7 @@ void i2cMasterReceive(I2CDriver *i2cp, chDbgCheck((i2cp != NULL) && (i2cscfg != NULL) &&\ (slave_addr != 0) &&\ - (rxbytes > 0) && \ + (rxbytes > 1) && \ (rxbuf != NULL), "i2cMasterReceive"); -- cgit v1.2.3 From 59014aa2be0488eba89c6ec0fb1934aa43aeb224 Mon Sep 17 00:00:00 2001 From: barthess Date: Sun, 4 Dec 2011 17:46:19 +0000 Subject: I2C. Tested on tmp75, mma8451, max1236. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3553 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/include/i2c.h | 17 +- os/hal/platforms/STM32/i2c_lld.c | 353 +++++++++++++++++++-------------------- os/hal/platforms/STM32/i2c_lld.h | 85 +++------- os/hal/src/i2c.c | 40 ++--- 4 files changed, 212 insertions(+), 283 deletions(-) (limited to 'os') diff --git a/os/hal/include/i2c.h b/os/hal/include/i2c.h index cf4d47713..18e93119e 100644 --- a/os/hal/include/i2c.h +++ b/os/hal/include/i2c.h @@ -66,6 +66,13 @@ #define I2C_USE_MUTUAL_EXCLUSION TRUE #endif +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_WAIT) || defined(__DOXYGEN__) +#define I2C_USE_WAIT TRUE +#endif + /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ @@ -87,7 +94,6 @@ typedef enum { I2C_READY = 2, /**< Ready. */ I2C_ACTIVE_TRANSMIT = 3, /**< Transmitting. */ I2C_ACTIVE_RECEIVE = 4, /**< Receiving. */ - I2C_ACTIVE_TRANSCEIVE = 5, /**< Receiving after transmit. */ } i2cstate_t; #include "i2c_lld.h" @@ -115,11 +121,6 @@ typedef void (*i2ccallback_t)(I2CDriver *i2cp, const I2CSlaveConfig *i2cscfg); typedef void (*i2cerrorcallback_t)(I2CDriver *i2cp, const I2CSlaveConfig *i2cscfg); -/** - * @brief I2C transmission data block size. - */ -typedef uint8_t i2cblock_t; - /** * @brief Structure representing an I2C slave configuration. * @details Each slave device has its own config structure with input and @@ -252,11 +253,11 @@ extern "C" { void i2cStart(I2CDriver *i2cp, const I2CConfig *config); void i2cStop(I2CDriver *i2cp); void i2cMasterTransmit(I2CDriver *i2cp, const I2CSlaveConfig *i2cscfg, - uint16_t slave_addr, + uint8_t slave_addr, uint8_t *txbuf, size_t txbytes, uint8_t *rxbuf, size_t rxbytes); void i2cMasterReceive(I2CDriver *i2cp, const I2CSlaveConfig *i2cscfg, - uint16_t slave_addr, uint8_t *rxbuf, size_t rxbytes); + uint8_t slave_addr, uint8_t *rxbuf, size_t rxbytes); void i2cMasterStart(I2CDriver *i2cp); void i2cMasterStop(I2CDriver *i2cp); void i2cAddFlagsI(I2CDriver *i2cp, i2cflags_t mask); diff --git a/os/hal/platforms/STM32/i2c_lld.c b/os/hal/platforms/STM32/i2c_lld.c index 9afdc8619..b49f4b588 100644 --- a/os/hal/platforms/STM32/i2c_lld.c +++ b/os/hal/platforms/STM32/i2c_lld.c @@ -35,7 +35,7 @@ /* Datasheet notes. */ /*===========================================================================*/ /** - * From RM0008.pdf + * From reference manuals from ST: * * Note: * When the STOP, START or PEC bit is set, the software must NOT perform @@ -49,7 +49,6 @@ #define I2C1_RX_DMA_CHANNEL \ STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_RX_DMA_STREAM, \ STM32_I2C1_RX_DMA_CHN) - #define I2C1_TX_DMA_CHANNEL \ STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_TX_DMA_STREAM, \ STM32_I2C1_TX_DMA_CHN) @@ -57,11 +56,17 @@ #define I2C2_RX_DMA_CHANNEL \ STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_RX_DMA_STREAM, \ STM32_I2C2_RX_DMA_CHN) - #define I2C2_TX_DMA_CHANNEL \ STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_TX_DMA_STREAM, \ STM32_I2C2_TX_DMA_CHN) +#define I2C3_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_RX_DMA_STREAM, \ + STM32_I2C3_RX_DMA_CHN) +#define I2C3_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_I2C_I2C3_TX_DMA_STREAM, \ + STM32_I2C3_TX_DMA_CHN) + /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ @@ -80,10 +85,14 @@ I2CDriver I2CD1; I2CDriver I2CD2; #endif +/** @brief I2C2 driver identifier.*/ +#if STM32_I2C_USE_I2C3 || defined(__DOXYGEN__) +I2CDriver I2CD3; +#endif + /*===========================================================================*/ /* Driver local variables. */ /*===========================================================================*/ - /* Debugging variables */ #if CH_DBG_ENABLE_ASSERTS static volatile uint16_t dbgSR1 = 0; @@ -92,34 +101,13 @@ static volatile uint16_t dbgCR1 = 0; static volatile uint16_t dbgCR2 = 0; #endif /* CH_DBG_ENABLE_ASSERTS */ -/* defines for convenience purpose */ -#define txBuffp (i2cp->txbuff_p) -#define rxBuffp (i2cp->rxbuff_p) - /*===========================================================================*/ /* Driver local functions. */ /*===========================================================================*/ - - - -#if CH_DBG_ENABLE_ASSERTS -void _i2c_unhandled_case(I2CDriver *i2cp){ - dbgCR1 = i2cp->id_i2c->CR1; - dbgCR2 = i2cp->id_i2c->CR2; - chDbgAssert((dbgSR1 + dbgSR2) == 0, - "i2c_serve_event_interrupt(), #1", - "unhandled case"); -} -#else -#define _i2c_unhandled_case(i2cp) -#endif /* CH_DBG_ENABLE_ASSERTS */ - - - - /** * @brief Return the last event value from I2C status registers. + * @details Important but implicit function is clearing interrpts flags. * @note Internal use only. * * @param[in] i2cp pointer to the @p I2CDriver object @@ -146,17 +134,26 @@ static void i2c_serve_event_interrupt(I2CDriver *i2cp) { switch(i2c_get_event(i2cp)){ case I2C_EV5_MASTER_MODE_SELECT: + /* catch start generated event */ i2cp->flags &= ~I2C_FLG_HEADER_SENT; - dp->DR = i2cp->slave_addr1; + dp->DR = i2cp->slave_addr; break; - case I2C_EV6_MASTER_REC_MODE_SELECTED: - /* begin receiving via DMA */ - i2cp->id_i2c->CR2 &= ~I2C_CR2_ITBUFEN; /* switch off interrupt because we use DMA*/ + case I2C_EV8_2_MASTER_BYTE_TRANSMITTED: + /* catch BTF event after the end of trasmission */ + if (i2cp->rxbytes > 1){ + /* start "read after write" operation */ + i2c_lld_master_receive(i2cp, (i2cp->slave_addr >> 1), i2cp->rxbuf, i2cp->rxbytes); + return; + } + else + i2cp->id_i2c->CR1 |= I2C_CR1_STOP; + // FIXME: change this polling to something else + while(i2cp->id_i2c->CR1 & I2C_CR1_STOP) + ; + _i2c_isr_code(i2cp, i2cp->id_slave_config); break; - - default: break; } @@ -165,6 +162,26 @@ static void i2c_serve_event_interrupt(I2CDriver *i2cp) { +static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp){ + dmaStreamDisable(i2cp->dmarx); + + i2cp->id_i2c->CR1 |= I2C_CR1_STOP; + // FIXME: change this polling to something else + while(i2cp->id_i2c->CR1 & I2C_CR1_STOP) + ; + _i2c_isr_code(i2cp, i2cp->id_slave_config); +} + + + + + +static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp){ + dmaStreamDisable(i2cp->dmatx); +} + + + static void i2c_serve_error_interrupt(I2CDriver *i2cp) { i2cflags_t flags; @@ -209,39 +226,13 @@ static void i2c_serve_error_interrupt(I2CDriver *i2cp) { chSysLockFromIsr(); i2cAddFlagsI(i2cp, flags); chSysUnlockFromIsr(); - #if I2C_SUPPORTS_CALLBACKS _i2c_isr_err_code(i2cp, i2cp->id_slave_config); - #endif /* I2C_SUPPORTS_CALLBACKS */ } } - - -static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp, uint32_t flags){ - (void)flags; - - dmaStreamDisable(i2cp->dmarx); - i2cp->id_i2c->CR1 |= I2C_CR1_STOP; - while(i2cp->id_i2c->CR1 & I2C_CR1_STOP) - ; - _i2c_isr_code(i2cp, i2cp->id_slave_config); -} - - - -static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp, uint32_t flags) { - (void)i2cp; - (void)flags; -} - - - - - - #if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__) #error "Unrealized yet" #endif /* STM32_I2C_USE_I2C1 */ @@ -265,7 +256,9 @@ CH_IRQ_HANDLER(I2C2_ER_IRQHandler) { } #endif /* STM32_I2C_USE_I2C2 */ - +#if STM32_I2C_USE_I2C3 || defined(__DOXYGEN__) +#error "Unrealized yet" +#endif /* STM32_I2C_USE_I2C3 */ @@ -286,7 +279,9 @@ void i2c_lld_init(void) { #endif /* STM32_I2C_USE_I2C2 */ } - +#if STM32_I2C_USE_I2C3 +#error "Unrealized yet" +#endif /* STM32_I2C_USE_I2C */ @@ -336,7 +331,10 @@ void i2c_lld_start(I2CDriver *i2cp) { } #endif /* STM32_I2C_USE_I2C2 */ } - i2cp->dmamode |= STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; + i2cp->dmamode |= STM32_DMA_CR_PSIZE_BYTE | + STM32_DMA_CR_MSIZE_BYTE | + STM32_DMA_CR_MINC | + STM32_DMA_CR_TCIE; dmaStreamSetPeripheral(i2cp->dmarx, &i2cp->id_i2c->DR); dmaStreamSetPeripheral(i2cp->dmatx, &i2cp->id_i2c->DR); @@ -348,7 +346,16 @@ void i2c_lld_start(I2CDriver *i2cp) { i2cp->id_i2c->CR1 |= 1; /* enable interface */ } - +#if STM32_I2C_USE_I2C3 +// if (&I2CD1 == i2cp) { +// NVICEnableVector(I2C1_EV_IRQn, +// CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); +// NVICEnableVector(I2C1_ER_IRQn, +// CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); +// rccEnableI2C1(FALSE); +// } +#error "Unrealized yet" +#endif /* STM32_I2C_USE_I2C3 */ @@ -357,9 +364,20 @@ void i2c_lld_reset(I2CDriver *i2cp){ chDbgCheck((i2cp->id_state == I2C_STOP)||(i2cp->id_state == I2C_READY), "i2c_lld_reset: invalid state"); - /*TODO: Check what interface we must reset */ - rccResetI2C1(); - rccResetI2C2(); + #if STM32_I2C_USE_I2C1 + if (&I2CD1 == i2cp) + rccResetI2C1(); + #endif /* STM32_I2C_USE_I2C1 */ + + #if STM32_I2C_USE_I2C2 + if (&I2CD2 == i2cp) + rccResetI2C2(); + #endif /* STM32_I2C_USE_I2C2 */ + + #if STM32_I2C_USE_I2C3 + if (&I2CD3 == i2cp) + rccResetI2C3(); + #endif /* STM32_I2C_USE_I2C3 */ } @@ -368,6 +386,80 @@ void i2c_lld_reset(I2CDriver *i2cp){ +void i2c_lld_master_receive(I2CDriver *i2cp, uint8_t slave_addr, + uint8_t *rxbuf, size_t rxbytes){ + + uint32_t mode = 0; + + /* init driver fields */ + i2cp->slave_addr = (slave_addr << 1) | 0x01; /* LSB = 1 -> receive */ + i2cp->rxbytes = rxbytes; + i2cp->rxbuf = rxbuf; + i2cp->flags = 0; + + /* setting flags and register bits */ + i2cp->flags |= I2C_FLG_MASTER_RECEIVER; + i2cp->errors = 0; + + mode = STM32_DMA_CR_DIR_P2M; + // TODO: DMA error handling + dmaStreamSetMemory0(i2cp->dmarx, rxbuf); + dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); + dmaStreamSetMode(i2cp->dmarx, ((i2cp->dmamode) | mode)); + dmaStreamEnable(i2cp->dmarx); + + i2cp->id_i2c->CR2 |= I2C_CR2_DMAEN | I2C_CR2_LAST; + i2cp->id_i2c->CR2 |= I2C_CR2_ITERREN | I2C_CR2_ITEVTEN; + i2cp->id_i2c->CR1 |= I2C_CR1_START | I2C_CR1_ACK; +} + + + + + + +/** + * @brief Transmits data via the I2C bus as master. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] slave_addr slave device address + * @param[in] txbuf pointer to the transmit buffer + * @param[in] txbytes number of bytes to be transmitted + * @param[in] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + */ +void i2c_lld_master_transmit(I2CDriver *i2cp, uint8_t slave_addr, + uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes){ + + uint32_t mode = 0; + + /* init driver fields */ + i2cp->slave_addr = (slave_addr << 1) & 0x00FE; /* LSB = 0 -> write */ + i2cp->txbytes = txbytes; + i2cp->rxbytes = rxbytes; + i2cp->txbuf = txbuf; + i2cp->rxbuf = rxbuf; + + /* setting flags and register bits */ + i2cp->flags = 0; + i2cp->errors = 0; + + mode = STM32_DMA_CR_DIR_M2P; + // TODO: DMA error handling + dmaStreamSetMemory0(i2cp->dmatx, txbuf); + dmaStreamSetTransactionSize(i2cp->dmatx, txbytes); + dmaStreamSetMode(i2cp->dmatx, ((i2cp->dmamode) | mode)); + dmaStreamEnable(i2cp->dmatx); + + i2cp->id_i2c->CR2 |= I2C_CR2_DMAEN | I2C_CR2_LAST; + i2cp->id_i2c->CR2 |= I2C_CR2_ITERREN | I2C_CR2_ITEVTEN; + i2cp->id_i2c->CR1 |= I2C_CR1_START; +} + + + + /** * @brief Set clock speed. * @@ -394,7 +486,7 @@ void i2c_lld_set_clock(I2CDriver *i2cp) { #else chDbgCheck((freq >= 2) && (freq <= 36), "i2c_lld_set_clock() : Peripheral clock freq. out of range"); -#endif +#endif /* define STM32F4XX */ regCR2 |= freq; i2cp->id_i2c->CR2 = regCR2; @@ -439,11 +531,6 @@ void i2c_lld_set_clock(I2CDriver *i2cp) { } - - - - - /** * @brief Set operation mode of I2C hardware. * @@ -473,39 +560,6 @@ void i2c_lld_set_opmode(I2CDriver *i2cp) { - - - - - -/** - * @brief Set own address. - * - * @param[in] i2cp pointer to the @p I2CDriver object - */ -void i2c_lld_set_own_address(I2CDriver *i2cp) { - /* TODO: dual address mode */ - - i2cp->id_i2c->OAR1 |= 1 << 14; - - if (&(i2cp->id_config->own_addr_10) == NULL){ /* only 7-bit address */ - i2cp->id_i2c->OAR1 &= (~I2C_OAR1_ADDMODE); - i2cp->id_i2c->OAR1 |= i2cp->id_config->own_addr_7 << 1; - } - else { - chDbgAssert((i2cp->id_config->own_addr_10 < 1024), - "i2c_lld_set_own_address(), #1", "10-bit address longer then 10 bit") - i2cp->id_i2c->OAR1 |= I2C_OAR1_ADDMODE; - i2cp->id_i2c->OAR1 |= i2cp->id_config->own_addr_10; - } -} - - - - - - - /** * @brief Deactivates the I2C peripheral. * @@ -513,6 +567,7 @@ void i2c_lld_set_own_address(I2CDriver *i2cp) { */ void i2c_lld_stop(I2CDriver *i2cp) { if (i2cp->id_state == I2C_READY) { /* If in ready state then disables the I2C clock.*/ + #if STM32_I2C_USE_I2C1 if (&I2CD1 == i2cp) { NVICDisableVector(I2C1_EV_IRQn); @@ -520,6 +575,7 @@ void i2c_lld_stop(I2CDriver *i2cp) { rccDisableI2C1(FALSE); } #endif + #if STM32_I2C_USE_I2C2 if (&I2CD2 == i2cp) { NVICDisableVector(I2C2_EV_IRQn); @@ -527,91 +583,18 @@ void i2c_lld_stop(I2CDriver *i2cp) { rccDisableI2C2(FALSE); } #endif - } - - i2cp->id_state = I2C_STOP; -} - - - - - -void i2c_lld_master_receive(I2CDriver *i2cp, uint16_t slave_addr, uint8_t *rxbuf, size_t rxbytes){ - (void)slave_addr; - - uint32_t mode = 0; - - /* init driver fields */ - i2cp->slave_addr = slave_addr; - i2cp->rxbytes = rxbytes; - i2cp->rxbuf = rxbuf; - - /* init address fields */ - if(slave_addr & 0x8000){ /* 10-bit mode used */ - i2cp->slave_addr1 = ((slave_addr >>7) & 0x0006); /* add the two msb of 10-bit address to the header */ - i2cp->slave_addr1 |= 0xF0; /* add the header bits (the LSB -> 1 will be add to second */ - i2cp->slave_addr2 = slave_addr & 0x00FF; /* the remaining 8 bit of 10-bit address */ - } - else{ - i2cp->slave_addr1 = ((slave_addr <<1) | 0x01); /* LSB = 1 -> receive */ +#if STM32_I2C_USE_I2C3 + if (&I2CD3 == i2cp) { + NVICDisableVector(I2C3_EV_IRQn); + NVICDisableVector(I2C3_ER_IRQn); + rccDisableI2C3(FALSE); + } +#endif } - /* setting flags and register bits */ - i2cp->flags |= I2C_FLG_MASTER_RECEIVER; - i2cp->errors = 0; - - mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE; - // TODO: DMA error handling - dmaStreamSetMemory0(i2cp->dmarx, rxbuf); - dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); - dmaStreamSetMode(i2cp->dmarx, ((i2cp->dmamode) | mode)); - dmaStreamEnable(i2cp->dmarx); - - i2cp->id_i2c->CR2 |= I2C_CR2_DMAEN | I2C_CR2_LAST; - - i2cp->id_i2c->CR2 |= I2C_CR2_ITERREN | I2C_CR2_ITEVTEN; - i2cp->id_i2c->CR1 |= I2C_CR1_START | I2C_CR1_ACK; -} - - - - - - -/** - * @brief Transmits data via the I2C bus as master. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] slave_addr Slave device address. Bits 0-9 contain slave - * device address. Bit 15 must be set to 1 if 10-bit - * addressing modes used. Otherwise keep it cleared. - * Bits 10-14 unused. - * @param[in] txbuf pointer to the transmit buffer - * @param[in] txbytes number of bytes to be transmitted - * @param[in] rxbuf pointer to the receive buffer - * @param[in] rxbytes number of bytes to be received - */ -void i2c_lld_master_transmit(I2CDriver *i2cp, uint16_t slave_addr, - uint8_t *txbuf, size_t txbytes, uint8_t *rxbuf, size_t rxbytes) { - (void)i2cp; - (void)slave_addr; - (void)txbuf; - (void)txbytes; - (void)rxbuf; - (void)rxbytes; -} - - - - - - -void i2c_lld_master_transceive(I2CDriver *i2cp){ - (void)i2cp; + i2cp->id_state = I2C_STOP; } -#undef rxBuffp -#undef txBuffp #endif /* HAL_USE_I2C */ diff --git a/os/hal/platforms/STM32/i2c_lld.h b/os/hal/platforms/STM32/i2c_lld.h index e4fb8970f..00eef923d 100644 --- a/os/hal/platforms/STM32/i2c_lld.h +++ b/os/hal/platforms/STM32/i2c_lld.h @@ -83,35 +83,13 @@ /*===========================================================================*/ /** @brief EV5 */ -#define I2C_EV5_MASTER_MODE_SELECT ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_SB)) /* BUSY, MSL and SB flag */ -/** @brief EV6 */ -#define I2C_EV6_MASTER_TRA_MODE_SELECTED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY|I2C_SR2_TRA)<< 16)|I2C_SR1_ADDR|I2C_SR1_TXE)) /* BUSY, MSL, ADDR, TXE and TRA flags */ -#define I2C_EV6_MASTER_REC_MODE_SELECTED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_ADDR)) /* BUSY, MSL and ADDR flags */ -/** @brief EV7 */ -#define I2C_EV7_MASTER_REC_BYTE_RECEIVED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_RXNE)) /* BUSY, MSL and RXNE flags */ -#define I2C_EV7_MASTER_REC_BYTE_QUEUED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_BTF|I2C_SR1_RXNE)) /* BUSY, MSL, RXNE and BTF flags*/ -/** @brief EV8 */ -#define I2C_EV8_MASTER_BYTE_TRANSMITTING ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY|I2C_SR2_TRA)<< 16)|I2C_SR1_TXE)) /* TRA, BUSY, MSL, TXE flags */ -/** @brief EV8_2 */ -#define I2C_EV8_2_MASTER_BYTE_TRANSMITTED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY|I2C_SR2_TRA)<< 16)|I2C_SR1_BTF|I2C_SR1_TXE)) /* TRA, BUSY, MSL, TXE and BTF flags */ -/** @brief EV9 */ -#define I2C_EV9_MASTER_ADDR_10BIT ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_ADD10)) /* BUSY, MSL and ADD10 flags */ +#define I2C_EV5_MASTER_MODE_SELECT ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY) << 16) | I2C_SR1_SB)) /* BUSY, MSL and SB flag */ +#define I2C_EV8_2_MASTER_BYTE_TRANSMITTED ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA) << 16) | I2C_SR1_BTF | I2C_SR1_TXE)) /* TRA, BUSY, MSL, TXE and BTF flags */ #define I2C_EV_MASK 0x00FFFFFF /* First byte zeroed because there is no need of PEC register part from SR2 */ -#define I2C_FLG_1BTR 0x01 /* Single byte to be received and processed */ -#define I2C_FLG_2BTR 0x02 /* Two bytes to be received and processed */ -#define I2C_FLG_3BTR 0x04 /* Last three received bytes to be processed */ #define I2C_FLG_MASTER_RECEIVER 0x10 #define I2C_FLG_HEADER_SENT 0x80 -#define I2C_FLG_TIMER_ARMED 0x40 /* Used to check locks on the bus */ -#define EV6_SUBEV_MASK (I2C_FLG_1BTR|I2C_FLG_2BTR|I2C_FLG_MASTER_RECEIVER) -#define EV7_SUBEV_MASK (I2C_FLG_2BTR|I2C_FLG_3BTR|I2C_FLG_MASTER_RECEIVER) - -#define I2C_EV6_1_MASTER_REC_2BTR_MODE_SELECTED (I2C_FLG_2BTR|I2C_FLG_MASTER_RECEIVER) -#define I2C_EV6_3_MASTER_REC_1BTR_MODE_SELECTED (I2C_FLG_1BTR|I2C_FLG_MASTER_RECEIVER) -#define I2C_EV7_2_MASTER_REC_3BYTES_TO_PROCESS (I2C_FLG_3BTR|I2C_FLG_MASTER_RECEIVER) -#define I2C_EV7_3_MASTER_REC_2BYTES_TO_PROCESS (I2C_FLG_2BTR|I2C_FLG_MASTER_RECEIVER) /*===========================================================================*/ /* Driver data structures and types. */ @@ -141,9 +119,6 @@ typedef struct { i2copmode_t op_mode; /**< @brief Specifies the I2C mode.*/ uint32_t clock_speed; /**< @brief Specifies the clock frequency. Must be set to a value lower than 400kHz */ i2cdutycycle_t duty_cycle; /**< @brief Specifies the I2C fast mode duty cycle */ - uint8_t own_addr_7; /**< @brief Specifies the first device 7-bit own address. */ - uint16_t own_addr_10; /**< @brief Specifies the second part of device own address in 10-bit mode. Set to NULL if not used. */ - uint8_t nbit_own_addr; /**< @brief Specifies if 7-bit or 10-bit address is acknowledged */ } I2CConfig; @@ -186,47 +161,33 @@ struct I2CDriver{ /** * @brief Current configuration data. */ - const I2CConfig *id_config; + const I2CConfig *id_config; /** * @brief Current slave configuration data. */ - const I2CSlaveConfig *id_slave_config; + const I2CSlaveConfig *id_slave_config; - __IO size_t txbytes; /*!< @brief Number of bytes to be transmitted. */ - __IO size_t rxbytes; /*!< @brief Number of bytes to be received. */ - uint8_t *rxbuf; /*!< @brief Pointer to receive buffer. */ - uint8_t *txbuf; /*!< @brief Pointer to transmit buffer.*/ - uint8_t *rxbuff_p; /*!< @brief Pointer to the current byte in slave rx buffer. */ - uint8_t *txbuff_p; /*!< @brief Pointer to the current byte in slave tx buffer. */ + __IO size_t txbytes; /*!< @brief Number of bytes to be transmitted. */ + __IO size_t rxbytes; /*!< @brief Number of bytes to be received. */ + uint8_t *rxbuf; /*!< @brief Pointer to receive buffer. */ + uint8_t *txbuf; /*!< @brief Pointer to transmit buffer.*/ - __IO i2cflags_t errors; /*!< @brief Error flags.*/ - __IO i2cflags_t flags; /*!< @brief State flags.*/ + __IO i2cflags_t errors; /*!< @brief Error flags.*/ + __IO i2cflags_t flags; /*!< @brief State flags.*/ - uint16_t slave_addr; /*!< @brief Current slave address. */ - uint8_t slave_addr1;/*!< @brief 7-bit address of the slave with r\w bit.*/ - uint8_t slave_addr2;/*!< @brief Uses in 10-bit address mode. */ + uint8_t slave_addr; /*!< @brief Current slave address without R/W bit. */ #if CH_USE_EVENTS - EventSource sevent; /*!< @brief Status Change @p EventSource.*/ + EventSource sevent; /*!< @brief Status Change @p EventSource.*/ #endif /*********** End of the mandatory fields. **********************************/ - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; - /** - * @brief Receive DMA channel. - */ - const stm32_dma_stream_t *dmarx; - /** - * @brief Transmit DMA channel. - */ - const stm32_dma_stream_t *dmatx; - /** - * @brief Pointer to the I2Cx registers block. - */ - I2C_TypeDef *id_i2c; + + uint32_t dmamode; /*!< @brief DMA mode bit mask.*/ + const stm32_dma_stream_t *dmarx; /*!< @brief Receive DMA channel.*/ + const stm32_dma_stream_t *dmatx; /*!< @brief Transmit DMA channel.*/ + + I2C_TypeDef *id_i2c; /*!< @brief Pointer to the I2Cx registers block. */ }; @@ -261,6 +222,10 @@ extern I2CDriver I2CD1; extern I2CDriver I2CD2; #endif +#if STM32_I2C_USE_I2C3 +extern I2CDriver I2CD3; +#endif + #ifdef __cplusplus extern "C" { #endif @@ -269,14 +234,12 @@ void i2c_lld_init(void); void i2c_lld_reset(I2CDriver *i2cp); void i2c_lld_set_clock(I2CDriver *i2cp); void i2c_lld_set_opmode(I2CDriver *i2cp); -void i2c_lld_set_own_address(I2CDriver *i2cp); void i2c_lld_start(I2CDriver *i2cp); void i2c_lld_stop(I2CDriver *i2cp); -void i2c_lld_master_transmit(I2CDriver *i2cp, uint16_t slave_addr, +void i2c_lld_master_transmit(I2CDriver *i2cp, uint8_t slave_addr, uint8_t *txbuf, size_t txbytes, uint8_t *rxbuf, size_t rxbytes); -void i2c_lld_master_receive(I2CDriver *i2cp, uint16_t slave_addr, +void i2c_lld_master_receive(I2CDriver *i2cp, uint8_t slave_addr, uint8_t *rxbuf, size_t rxbytes); -void i2c_lld_master_transceive(I2CDriver *i2cp); #ifdef __cplusplus } diff --git a/os/hal/src/i2c.c b/os/hal/src/i2c.c index 3add2af98..9f443be6c 100644 --- a/os/hal/src/i2c.c +++ b/os/hal/src/i2c.c @@ -73,8 +73,6 @@ void i2cObjectInit(I2CDriver *i2cp) { i2cp->id_state = I2C_STOP; i2cp->id_config = NULL; - i2cp->rxbuff_p = NULL; - i2cp->txbuff_p = NULL; i2cp->rxbuf = NULL; i2cp->txbuf = NULL; i2cp->id_slave_config = NULL; @@ -145,12 +143,12 @@ void i2cStop(I2CDriver *i2cp) { * paradigm. If you want transmit data without any further read, * than set @b rxbytes field to 0. * + * @details Number of receiving byts must be 0 or more than 1 because of stm32 + * hardware restrictions. + * * @param[in] i2cp pointer to the @p I2CDriver object * @param[in] i2cscfg pointer to the @p I2C slave config - * @param[in] slave_addr Slave device address. Bits 0-9 contain slave - * device address. Bit 15 must be set to 1 if 10-bit - * addressing mode used. Otherwise keep it cleared. - * Bits 10-14 unused. + * @param[in] slave_addr Slave device address (7 bits) without R/W bit * @param[in] txbuf pointer to transmit buffer * @param[in] txbytes number of bytes to be transmitted * @param[in] rxbuf pointer to receive buffer @@ -159,7 +157,7 @@ void i2cStop(I2CDriver *i2cp) { */ void i2cMasterTransmit(I2CDriver *i2cp, const I2CSlaveConfig *i2cscfg, - uint16_t slave_addr, + uint8_t slave_addr, uint8_t *txbuf, size_t txbytes, uint8_t *rxbuf, @@ -168,7 +166,8 @@ void i2cMasterTransmit(I2CDriver *i2cp, chDbgCheck((i2cp != NULL) && (i2cscfg != NULL) &&\ (slave_addr != 0) &&\ (txbytes > 0) &&\ - (txbuf != NULL), + (txbuf != NULL) &&\ + ((rxbytes == 0) || ((rxbytes > 1) && (rxbuf != NULL))), "i2cMasterTransmit"); /* init slave config field in driver */ @@ -183,28 +182,23 @@ void i2cMasterTransmit(I2CDriver *i2cp, i2cp->id_state = I2C_ACTIVE_TRANSMIT; i2c_lld_master_transmit(i2cp, slave_addr, txbuf, txbytes, rxbuf, rxbytes); -#if I2C_SUPPORTS_CALLBACKS _i2c_wait_s(i2cp); -#else - i2cp->id_state = I2C_READY; -#endif /* I2C_SUPPORTS_CALLBACKS */ } /** * @brief Receives data from the I2C bus. + * @details Number of receiving byts must be more than 1 because of stm32 + * hardware restrictions. * * @param[in] i2cp pointer to the @p I2CDriver object * @param[in] i2cscfg pointer to the @p I2C slave config - * @param[in] slave_addr Slave device address. Bits 0-9 contain slave - * device address. Bit 15 must be set to 1 if 10-bit - * addressing mode used. Otherwise keep it cleared. - * Bits 10-14 unused. + * @param[in] slave_addr slave device address (7 bits) without R/W bit * @param[in] rxbytes number of bytes to be received * @param[in] rxbuf pointer to receive buffer */ void i2cMasterReceive(I2CDriver *i2cp, const I2CSlaveConfig *i2cscfg, - uint16_t slave_addr, + uint8_t slave_addr, uint8_t *rxbuf, size_t rxbytes){ @@ -226,21 +220,9 @@ void i2cMasterReceive(I2CDriver *i2cp, i2cp->id_state = I2C_ACTIVE_RECEIVE; i2c_lld_master_receive(i2cp, slave_addr, rxbuf, rxbytes); -#if I2C_SUPPORTS_CALLBACKS _i2c_wait_s(i2cp); -#else - i2cp->id_state = I2C_READY; -#endif /* I2C_SUPPORTS_CALLBACKS */ } - -/* FIXME: I do not know what this function must do. And can not test it -uint16_t i2cSMBusAlertResponse(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg) { - i2cMasterReceive(i2cp, i2cscfg); - return i2cp->id_slave_config->slave_addr; -} -*/ - /** * @brief Handles communication events/errors. * @details Must be called from the I/O interrupt service routine in order to -- cgit v1.2.3 From e05d85d2bd73adbdde8174b5ed7edc564808ca5e Mon Sep 17 00:00:00 2001 From: barthess Date: Mon, 5 Dec 2011 17:17:52 +0000 Subject: I2C. Added startup functions for I2C1 and I2C3 interfaces. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3554 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/i2c_lld.c | 178 +++++++++++++++++++++++++++------------ 1 file changed, 123 insertions(+), 55 deletions(-) (limited to 'os') diff --git a/os/hal/platforms/STM32/i2c_lld.c b/os/hal/platforms/STM32/i2c_lld.c index b49f4b588..78a2b334a 100644 --- a/os/hal/platforms/STM32/i2c_lld.c +++ b/os/hal/platforms/STM32/i2c_lld.c @@ -126,9 +126,11 @@ static uint32_t i2c_get_event(I2CDriver *i2cp){ } - - - +/** + * @brief I2C interrupts handler. + * + * @param[in] i2cp pointer to the @p I2CDriver object + */ static void i2c_serve_event_interrupt(I2CDriver *i2cp) { I2C_TypeDef *dp = i2cp->id_i2c; @@ -160,8 +162,11 @@ static void i2c_serve_event_interrupt(I2CDriver *i2cp) { } - - +/** + * @brief DMA rx end IRQ handler. + * + * @param[in] i2cp pointer to the @p I2CDriver object + */ static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp){ dmaStreamDisable(i2cp->dmarx); @@ -173,16 +178,21 @@ static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp){ } - - - +/** + * @brief DMA tx enr IRQ handler. + * + * @param[in] i2cp pointer to the @p I2CDriver object + */ static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp){ dmaStreamDisable(i2cp->dmatx); } - - +/** + * @brief I2C error handler. + * + * @param[in] i2cp pointer to the @p I2CDriver object + */ static void i2c_serve_error_interrupt(I2CDriver *i2cp) { i2cflags_t flags; I2C_TypeDef *reg; @@ -231,10 +241,23 @@ static void i2c_serve_error_interrupt(I2CDriver *i2cp) { } - - #if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__) -#error "Unrealized yet" +/** + * @brief I2C1 event interrupt handler. + */ +CH_IRQ_HANDLER(I2C1_EV_IRQHandler) { + CH_IRQ_PROLOGUE(); + i2c_serve_event_interrupt(&I2CD1); + CH_IRQ_EPILOGUE(); +} +/** + * @brief I2C1 error interrupt handler. + */ +CH_IRQ_HANDLER(I2C1_ER_IRQHandler) { + CH_IRQ_PROLOGUE(); + i2c_serve_error_interrupt(&I2CD1); + CH_IRQ_EPILOGUE(); +} #endif /* STM32_I2C_USE_I2C1 */ #if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__) @@ -257,19 +280,36 @@ CH_IRQ_HANDLER(I2C2_ER_IRQHandler) { #endif /* STM32_I2C_USE_I2C2 */ #if STM32_I2C_USE_I2C3 || defined(__DOXYGEN__) -#error "Unrealized yet" +/** + * @brief I2C3 event interrupt handler. + */ +CH_IRQ_HANDLER(I2C3_EV_IRQHandler) { + CH_IRQ_PROLOGUE(); + i2c_serve_event_interrupt(&I2CD3); + CH_IRQ_EPILOGUE(); +} +/** + * @brief I2C3 error interrupt handler. + */ +CH_IRQ_HANDLER(I2C3_ER_IRQHandler) { + CH_IRQ_PROLOGUE(); + i2c_serve_error_interrupt(&I2CD3); + CH_IRQ_EPILOGUE(); +} #endif /* STM32_I2C_USE_I2C3 */ - /** * @brief Low level I2C driver initialization. */ void i2c_lld_init(void) { #if STM32_I2C_USE_I2C1 -#error "Unrealized yet" -#endif /* STM32_I2C_USE_I2C */ + i2cObjectInit(&I2CD1); + I2CD1.id_i2c = I2C1; + I2CD1.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C1_RX_DMA_STREAM); + I2CD1.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C1_TX_DMA_STREAM); +#endif /* STM32_I2C_USE_I2C1 */ #if STM32_I2C_USE_I2C2 i2cObjectInit(&I2CD2); @@ -277,13 +317,14 @@ void i2c_lld_init(void) { I2CD2.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C2_RX_DMA_STREAM); I2CD2.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C2_TX_DMA_STREAM); #endif /* STM32_I2C_USE_I2C2 */ -} #if STM32_I2C_USE_I2C3 -#error "Unrealized yet" -#endif /* STM32_I2C_USE_I2C */ - - + i2cObjectInit(&I2CD3); + I2CD3.id_i2c = I2C3; + I2CD3.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C3_RX_DMA_STREAM); + I2CD3.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C3_TX_DMA_STREAM); +#endif /* STM32_I2C_USE_I2C3 */ +} /** @@ -296,15 +337,29 @@ void i2c_lld_start(I2CDriver *i2cp) { if (i2cp->id_state == I2C_STOP) { /* If in stopped state then enables the I2C clock.*/ #if STM32_I2C_USE_I2C1 -// if (&I2CD1 == i2cp) { -// NVICEnableVector(I2C1_EV_IRQn, -// CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); -// NVICEnableVector(I2C1_ER_IRQn, -// CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); -// rccEnableI2C1(FALSE); -// } -#error "Unrealized yet" -#endif + if (&I2CD1 == i2cp) { + + bool_t b; + b = dmaStreamAllocate(i2cp->dmarx, + STM32_I2C_I2C1_IRQ_PRIORITY, + (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, + (void *)i2cp); + chDbgAssert(!b, "uart_lld_start(), #3", "stream already allocated"); + b = dmaStreamAllocate(i2cp->dmatx, + STM32_I2C_I2C1_IRQ_PRIORITY, + (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, + (void *)i2cp); + chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated"); + rccEnableI2C1(FALSE); + NVICEnableVector(I2C1_EV_IRQn, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); + NVICEnableVector(I2C1_ER_IRQn, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); + + i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY); + } +#endif /* STM32_I2C_USE_I2C1 */ #if STM32_I2C_USE_I2C2 if (&I2CD2 == i2cp) { @@ -330,6 +385,32 @@ void i2c_lld_start(I2CDriver *i2cp) { STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY); } #endif /* STM32_I2C_USE_I2C2 */ + +#if STM32_I2C_USE_I2C3 + if (&I2CD3 == i2cp) { + + bool_t b; + b = dmaStreamAllocate(i2cp->dmarx, + STM32_I2C_I2C3_IRQ_PRIORITY, + (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, + (void *)i2cp); + chDbgAssert(!b, "uart_lld_start(), #3", "stream already allocated"); + b = dmaStreamAllocate(i2cp->dmatx, + STM32_I2C_I2C3_IRQ_PRIORITY, + (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, + (void *)i2cp); + chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated"); + rccEnableI2C3(FALSE); + NVICEnableVector(I2C3_EV_IRQn, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C3_IRQ_PRIORITY)); + NVICEnableVector(I2C3_ER_IRQn, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C3_IRQ_PRIORITY)); + + i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C3_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY); + } +#endif /* STM32_I2C_USE_I2C2 */ + } i2cp->dmamode |= STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE | @@ -346,20 +427,10 @@ void i2c_lld_start(I2CDriver *i2cp) { i2cp->id_i2c->CR1 |= 1; /* enable interface */ } -#if STM32_I2C_USE_I2C3 -// if (&I2CD1 == i2cp) { -// NVICEnableVector(I2C1_EV_IRQn, -// CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); -// NVICEnableVector(I2C1_ER_IRQn, -// CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); -// rccEnableI2C1(FALSE); -// } -#error "Unrealized yet" -#endif /* STM32_I2C_USE_I2C3 */ - - - +/** + * @brief Reset interface via RCC. + */ void i2c_lld_reset(I2CDriver *i2cp){ chDbgCheck((i2cp->id_state == I2C_STOP)||(i2cp->id_state == I2C_READY), "i2c_lld_reset: invalid state"); @@ -381,11 +452,14 @@ void i2c_lld_reset(I2CDriver *i2cp){ } - - - - - +/** + * @brief Receive data via the I2C bus as master. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] slave_addr slave device address + * @param[in] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + */ void i2c_lld_master_receive(I2CDriver *i2cp, uint8_t slave_addr, uint8_t *rxbuf, size_t rxbytes){ @@ -414,10 +488,6 @@ void i2c_lld_master_receive(I2CDriver *i2cp, uint8_t slave_addr, } - - - - /** * @brief Transmits data via the I2C bus as master. * @@ -458,8 +528,6 @@ void i2c_lld_master_transmit(I2CDriver *i2cp, uint8_t slave_addr, } - - /** * @brief Set clock speed. * -- cgit v1.2.3 From 23d0cbc3b552533bf2b627e42aa55c82f5abc522 Mon Sep 17 00:00:00 2001 From: barthess Date: Tue, 6 Dec 2011 07:13:26 +0000 Subject: I2C. Added forgotten I2C3 interface git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3555 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/i2c_lld.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'os') diff --git a/os/hal/platforms/STM32/i2c_lld.h b/os/hal/platforms/STM32/i2c_lld.h index 00eef923d..0e77dadb8 100644 --- a/os/hal/platforms/STM32/i2c_lld.h +++ b/os/hal/platforms/STM32/i2c_lld.h @@ -61,6 +61,15 @@ #define STM32_I2C_USE_I2C2 TRUE #endif +/** + * @brief I2C3 driver enable switch. + * @details If set to @p TRUE the support for I2C3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_I2C_USE_I2C3) || defined(__DOXYGEN__) +#define STM32_I2C_USE_I2C3 TRUE +#endif + /** * @brief I2C1 interrupt priority level setting. * @note @p BASEPRI_KERNEL >= @p STM32_I2C_I2C1_IRQ_PRIORITY > @p PRIORITY_PENDSV. @@ -76,6 +85,14 @@ #if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__) #define STM32_I2C_I2C2_IRQ_PRIORITY 0xA0 #endif + +/** + * @brief I2C2 interrupt priority level setting. + * @note @p BASEPRI_KERNEL >= @p STM32_I2C_I2C2_IRQ_PRIORITY > @p PRIORITY_PENDSV. + */ +#if !defined(STM32_I2C_I2C3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2C_I2C3_IRQ_PRIORITY 0xA0 +#endif /** @} */ /*===========================================================================*/ -- cgit v1.2.3 From dbee267868ee52517dd465aee0078619dc68f584 Mon Sep 17 00:00:00 2001 From: barthess Date: Tue, 6 Dec 2011 09:08:26 +0000 Subject: I2C. Added support of stm32f1x. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3557 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/i2c_lld.h | 176 ++++++++++++++++++++++++++++-- os/hal/platforms/STM32F1xx/hal_lld_f103.h | 16 +++ 2 files changed, 183 insertions(+), 9 deletions(-) (limited to 'os') diff --git a/os/hal/platforms/STM32/i2c_lld.h b/os/hal/platforms/STM32/i2c_lld.h index 0e77dadb8..f57bead5f 100644 --- a/os/hal/platforms/STM32/i2c_lld.h +++ b/os/hal/platforms/STM32/i2c_lld.h @@ -46,28 +46,28 @@ /** * @brief I2C1 driver enable switch. * @details If set to @p TRUE the support for I2C1 is included. - * @note The default is @p TRUE. + * @note The default is @p FALSE. */ #if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__) -#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C1 FALSE #endif /** * @brief I2C2 driver enable switch. * @details If set to @p TRUE the support for I2C2 is included. - * @note The default is @p TRUE. + * @note The default is @p FALSE. */ #if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__) -#define STM32_I2C_USE_I2C2 TRUE +#define STM32_I2C_USE_I2C2 FALSE #endif /** * @brief I2C3 driver enable switch. * @details If set to @p TRUE the support for I2C3 is included. - * @note The default is @p TRUE. + * @note The default is @p FALSE. */ #if !defined(STM32_I2C_USE_I2C3) || defined(__DOXYGEN__) -#define STM32_I2C_USE_I2C3 TRUE +#define STM32_I2C_USE_I2C3 FALSE #endif /** @@ -93,21 +93,179 @@ #if !defined(STM32_I2C_I2C3_IRQ_PRIORITY) || defined(__DOXYGEN__) #define STM32_I2C_I2C3_IRQ_PRIORITY 0xA0 #endif + +/** + * @brief I2C1 DMA error hook. + * @note The default action for DMA errors is a system halt because DMA + * error can only happen because programming errors. + */ +#if !defined(STM32_I2C_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM32_I2C_DMA_ERROR_HOOK(uartp) chSysHalt() +#endif + +#if STM32_ADVANCED_DMA || defined(__DOXYGEN__) + +/** + * @brief DMA stream used for I2C1 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_I2C_I2C1_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#endif + +/** + * @brief DMA stream used for I2C1 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_I2C_I2C1_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#endif + +/** + * @brief DMA stream used for I2C2 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_I2C_I2C2_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#endif + +/** + * @brief DMA stream used for I2C2 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_I2C_I2C2_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#endif + +/** + * @brief DMA stream used for I2C3 RX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_I2C_I2C3_RX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#endif + +/** + * @brief DMA stream used for I2C3 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_I2C_I2C3_TX_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#endif + +#else /* !STM32_ADVANCED_DMA */ + +/* Fixed streams for platforms using the old DMA peripheral, the values are + valid for both STM32F1xx and STM32L1xx.*/ +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) + +#endif /* !STM32_ADVANCED_DMA*/ /** @} */ /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ -/** @brief EV5 */ +/** @brief flags for interrupt handling */ #define I2C_EV5_MASTER_MODE_SELECT ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY) << 16) | I2C_SR1_SB)) /* BUSY, MSL and SB flag */ #define I2C_EV8_2_MASTER_BYTE_TRANSMITTED ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA) << 16) | I2C_SR1_BTF | I2C_SR1_TXE)) /* TRA, BUSY, MSL, TXE and BTF flags */ #define I2C_EV_MASK 0x00FFFFFF /* First byte zeroed because there is no need of PEC register part from SR2 */ -#define I2C_FLG_MASTER_RECEIVER 0x10 -#define I2C_FLG_HEADER_SENT 0x80 +#define I2C_FLG_MASTER_RECEIVER 0x10 +#define I2C_FLG_HEADER_SENT 0x80 + +#if STM32_I2C_USE_I2C1 && !STM32_HAS_I2C1 +#error "I2C1 not present in the selected device" +#endif + +#if STM32_I2C_USE_I2C2 && !STM32_HAS_I2C2 +#error "I2C2 not present in the selected device" +#endif + +#if STM32_I2C_USE_I2C3 && !STM32_HAS_I2C3 +#error "I2C3 not present in the selected device" +#endif + +#if !STM32_I2C_USE_I2C1 && !STM32_I2C_USE_I2C2 && \ + !STM32_I2C_USE_I2C3 +#error "I2C driver activated but no I2C peripheral assigned" +#endif + + + + + + + + + + + + + +#if STM32_I2C_USE_I2C1 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_RX_DMA_STREAM, \ + STM32_I2C1_RX_DMA_MSK) +#error "invalid DMA stream associated to USART1 RX" +#endif + +#if STM32_I2C_USE_I2C1 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_TX_DMA_STREAM, \ + STM32_I2C1_TX_DMA_MSK) +#error "invalid DMA stream associated to USART1 TX" +#endif + +#if STM32_I2C_USE_I2C2 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_RX_DMA_STREAM, \ + STM32_I2C2_RX_DMA_MSK) +#error "invalid DMA stream associated to USART2 RX" +#endif + +#if STM32_I2C_USE_I2C2 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_TX_DMA_STREAM, \ + STM32_I2C2_TX_DMA_MSK) +#error "invalid DMA stream associated to USART2 TX" +#endif + +#if STM32_I2C_USE_I2C3 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_RX_DMA_STREAM, \ + STM32_I2C3_RX_DMA_MSK) +#error "invalid DMA stream associated to USART3 RX" +#endif + +#if STM32_I2C_USE_I2C3 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_TX_DMA_STREAM, \ + STM32_I2C3_TX_DMA_MSK) +#error "invalid DMA stream associated to USART3 TX" +#endif + + + + + + + + + + + + + + + + + + + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/os/hal/platforms/STM32F1xx/hal_lld_f103.h index 22d955c65..d251e6a5d 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f103.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f103.h @@ -306,8 +306,24 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 + #define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_I2C2_TX_DMA_CHN 0x00000000 + #define STM32_HAS_I2C3 FALSE +#define STM32_I2C3_RX_DMA_MSK 0 +#define STM32_I2C3_RX_DMA_CHN 0x00000000 +#define STM32_I2C3_TX_DMA_MSK 0 +#define STM32_I2C3_TX_DMA_CHN 0x00000000 + + /* RTC attributes.*/ #define STM32_HAS_RTC TRUE -- cgit v1.2.3 From 6777c09f08b8c20f67879a59aaefc588bb6e7371 Mon Sep 17 00:00:00 2001 From: barthess Date: Tue, 6 Dec 2011 13:37:08 +0000 Subject: I2C. Added checks. Cleaned copypaste errors. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3559 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/i2c_lld.c | 5 +++-- os/hal/platforms/STM32/i2c_lld.h | 14 -------------- 2 files changed, 3 insertions(+), 16 deletions(-) (limited to 'os') diff --git a/os/hal/platforms/STM32/i2c_lld.c b/os/hal/platforms/STM32/i2c_lld.c index 78a2b334a..3b8650dde 100644 --- a/os/hal/platforms/STM32/i2c_lld.c +++ b/os/hal/platforms/STM32/i2c_lld.c @@ -356,8 +356,9 @@ void i2c_lld_start(I2CDriver *i2cp) { NVICEnableVector(I2C1_ER_IRQn, CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); - i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY); + i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) | \ + STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY); + __NOP(); } #endif /* STM32_I2C_USE_I2C1 */ diff --git a/os/hal/platforms/STM32/i2c_lld.h b/os/hal/platforms/STM32/i2c_lld.h index f57bead5f..b2b346c7d 100644 --- a/os/hal/platforms/STM32/i2c_lld.h +++ b/os/hal/platforms/STM32/i2c_lld.h @@ -194,20 +194,6 @@ #error "I2C driver activated but no I2C peripheral assigned" #endif - - - - - - - - - - - - - - #if STM32_I2C_USE_I2C1 && \ !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_RX_DMA_STREAM, \ STM32_I2C1_RX_DMA_MSK) -- cgit v1.2.3 From 2db3c769f1abba36a1e7a843d83e5006de58cbd5 Mon Sep 17 00:00:00 2001 From: barthess Date: Tue, 6 Dec 2011 18:09:34 +0000 Subject: I2C. Bug fixes. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3562 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/i2c_lld.c | 22 ++++++++++++++--- os/hal/platforms/STM32/i2c_lld.h | 47 +++++++++++------------------------- os/hal/platforms/STM32F4xx/hal_lld.h | 11 +++++---- os/hal/src/i2c.c | 1 - 4 files changed, 38 insertions(+), 43 deletions(-) (limited to 'os') diff --git a/os/hal/platforms/STM32/i2c_lld.c b/os/hal/platforms/STM32/i2c_lld.c index 3b8650dde..d843591e1 100644 --- a/os/hal/platforms/STM32/i2c_lld.c +++ b/os/hal/platforms/STM32/i2c_lld.c @@ -141,6 +141,16 @@ static void i2c_serve_event_interrupt(I2CDriver *i2cp) { dp->DR = i2cp->slave_addr; break; + case I2C_EV6_MASTER_REC_MODE_SELECTED: + dmaStreamEnable(i2cp->dmarx); + i2cp->id_i2c->CR2 |= I2C_CR2_DMAEN | I2C_CR2_LAST; + break; + + case I2C_EV6_MASTER_TRA_MODE_SELECTED: + dmaStreamEnable(i2cp->dmatx); + i2cp->id_i2c->CR2 |= I2C_CR2_DMAEN | I2C_CR2_LAST; + break; + case I2C_EV8_2_MASTER_BYTE_TRANSMITTED: /* catch BTF event after the end of trasmission */ if (i2cp->rxbytes > 1){ @@ -197,6 +207,14 @@ static void i2c_serve_error_interrupt(I2CDriver *i2cp) { i2cflags_t flags; I2C_TypeDef *reg; + chSysLockFromIsr(); + /* clear interrupt falgs just to be safe */ + dmaStreamClearInterrupt(i2cp->dmatx); + dmaStreamClearInterrupt(i2cp->dmarx); + dmaStreamDisable(i2cp->dmatx); + dmaStreamDisable(i2cp->dmarx); + chSysUnlockFromIsr(); + reg = i2cp->id_i2c; flags = I2CD_NO_ERROR; @@ -481,9 +499,7 @@ void i2c_lld_master_receive(I2CDriver *i2cp, uint8_t slave_addr, dmaStreamSetMemory0(i2cp->dmarx, rxbuf); dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); dmaStreamSetMode(i2cp->dmarx, ((i2cp->dmamode) | mode)); - dmaStreamEnable(i2cp->dmarx); - i2cp->id_i2c->CR2 |= I2C_CR2_DMAEN | I2C_CR2_LAST; i2cp->id_i2c->CR2 |= I2C_CR2_ITERREN | I2C_CR2_ITEVTEN; i2cp->id_i2c->CR1 |= I2C_CR1_START | I2C_CR1_ACK; } @@ -521,9 +537,7 @@ void i2c_lld_master_transmit(I2CDriver *i2cp, uint8_t slave_addr, dmaStreamSetMemory0(i2cp->dmatx, txbuf); dmaStreamSetTransactionSize(i2cp->dmatx, txbytes); dmaStreamSetMode(i2cp->dmatx, ((i2cp->dmamode) | mode)); - dmaStreamEnable(i2cp->dmatx); - i2cp->id_i2c->CR2 |= I2C_CR2_DMAEN | I2C_CR2_LAST; i2cp->id_i2c->CR2 |= I2C_CR2_ITERREN | I2C_CR2_ITEVTEN; i2cp->id_i2c->CR1 |= I2C_CR1_START; } diff --git a/os/hal/platforms/STM32/i2c_lld.h b/os/hal/platforms/STM32/i2c_lld.h index b2b346c7d..2ca6b872a 100644 --- a/os/hal/platforms/STM32/i2c_lld.h +++ b/os/hal/platforms/STM32/i2c_lld.h @@ -171,12 +171,15 @@ /** @brief flags for interrupt handling */ #define I2C_EV5_MASTER_MODE_SELECT ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY) << 16) | I2C_SR1_SB)) /* BUSY, MSL and SB flag */ +#define I2C_EV6_MASTER_TRA_MODE_SELECTED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY|I2C_SR2_TRA)<< 16)|I2C_SR1_ADDR|I2C_SR1_TXE)) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EV6_MASTER_REC_MODE_SELECTED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_ADDR)) /* BUSY, MSL and ADDR flags */ #define I2C_EV8_2_MASTER_BYTE_TRANSMITTED ((uint32_t)(((I2C_SR2_MSL | I2C_SR2_BUSY | I2C_SR2_TRA) << 16) | I2C_SR1_BTF | I2C_SR1_TXE)) /* TRA, BUSY, MSL, TXE and BTF flags */ #define I2C_EV_MASK 0x00FFFFFF /* First byte zeroed because there is no need of PEC register part from SR2 */ #define I2C_FLG_MASTER_RECEIVER 0x10 #define I2C_FLG_HEADER_SENT 0x80 +/** @brief error checks */ #if STM32_I2C_USE_I2C1 && !STM32_HAS_I2C1 #error "I2C1 not present in the selected device" #endif @@ -197,57 +200,39 @@ #if STM32_I2C_USE_I2C1 && \ !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_RX_DMA_STREAM, \ STM32_I2C1_RX_DMA_MSK) -#error "invalid DMA stream associated to USART1 RX" +#error "invalid DMA stream associated to I2C1 RX" #endif #if STM32_I2C_USE_I2C1 && \ !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_TX_DMA_STREAM, \ STM32_I2C1_TX_DMA_MSK) -#error "invalid DMA stream associated to USART1 TX" +#error "invalid DMA stream associated to I2C1 TX" #endif #if STM32_I2C_USE_I2C2 && \ !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_RX_DMA_STREAM, \ STM32_I2C2_RX_DMA_MSK) -#error "invalid DMA stream associated to USART2 RX" +#error "invalid DMA stream associated to I2C2 RX" #endif #if STM32_I2C_USE_I2C2 && \ !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_TX_DMA_STREAM, \ STM32_I2C2_TX_DMA_MSK) -#error "invalid DMA stream associated to USART2 TX" +#error "invalid DMA stream associated to I2C2 TX" #endif #if STM32_I2C_USE_I2C3 && \ !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_RX_DMA_STREAM, \ STM32_I2C3_RX_DMA_MSK) -#error "invalid DMA stream associated to USART3 RX" +#error "invalid DMA stream associated to I2C3 RX" #endif #if STM32_I2C_USE_I2C3 && \ !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C3_TX_DMA_STREAM, \ STM32_I2C3_TX_DMA_MSK) -#error "invalid DMA stream associated to USART3 TX" +#error "invalid DMA stream associated to I2C3 TX" #endif - - - - - - - - - - - - - - - - - - #if !defined(STM32_DMA_REQUIRED) #define STM32_DMA_REQUIRED #endif @@ -300,22 +285,22 @@ struct I2CDriver{ /** * @brief Driver state. */ - i2cstate_t id_state; + i2cstate_t id_state; #if I2C_USE_WAIT /** * @brief Thread waiting for I/O completion. */ - Thread *id_thread; + Thread *id_thread; #endif /* I2C_USE_WAIT */ #if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) #if CH_USE_MUTEXES || defined(__DOXYGEN__) /** * @brief Mutex protecting the bus. */ - Mutex id_mutex; + Mutex id_mutex; #elif CH_USE_SEMAPHORES - Semaphore id_semaphore; + Semaphore id_semaphore; #endif #endif /* I2C_USE_MUTUAL_EXCLUSION */ @@ -338,17 +323,13 @@ struct I2CDriver{ uint8_t slave_addr; /*!< @brief Current slave address without R/W bit. */ -#if CH_USE_EVENTS - EventSource sevent; /*!< @brief Status Change @p EventSource.*/ -#endif - /*********** End of the mandatory fields. **********************************/ uint32_t dmamode; /*!< @brief DMA mode bit mask.*/ const stm32_dma_stream_t *dmarx; /*!< @brief Receive DMA channel.*/ const stm32_dma_stream_t *dmatx; /*!< @brief Transmit DMA channel.*/ - I2C_TypeDef *id_i2c; /*!< @brief Pointer to the I2Cx registers block. */ + I2C_TypeDef *id_i2c; /*!< @brief Pointer to the I2Cx registers block. */ }; diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index 1310738d4..577e37834 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -292,15 +292,16 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) | \ - STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C1_RX_DMA_MSK ((STM32_DMA_STREAM_ID_MSK(1, 0) | \ + STM32_DMA_STREAM_ID_MSK(1, 5))) #define STM32_I2C1_RX_DMA_CHN 0x00100001 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_TX_DMA_MSK ((STM32_DMA_STREAM_ID_MSK(1, 7)) | \ + (STM32_DMA_STREAM_ID_MSK(1, 6))) #define STM32_I2C1_TX_DMA_CHN 0x10000000 #define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) | \ - STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_I2C2_RX_DMA_MSK ((STM32_DMA_STREAM_ID_MSK(1, 2) | \ + STM32_DMA_STREAM_ID_MSK(1, 3))) #define STM32_I2C2_RX_DMA_CHN 0x00007700 #define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) #define STM32_I2C2_TX_DMA_CHN 0x70000000 diff --git a/os/hal/src/i2c.c b/os/hal/src/i2c.c index 9f443be6c..4b9160a68 100644 --- a/os/hal/src/i2c.c +++ b/os/hal/src/i2c.c @@ -238,7 +238,6 @@ void i2cAddFlagsI(I2CDriver *i2cp, i2cflags_t mask) { chDbgCheck(i2cp != NULL, "i2cAddFlagsI"); i2cp->errors |= mask; - chEvtBroadcastI(&i2cp->sevent); } /** -- cgit v1.2.3 From 80043ff2a01e97bacf9b2f30833b196e031cb20d Mon Sep 17 00:00:00 2001 From: barthess Date: Wed, 7 Dec 2011 05:44:33 +0000 Subject: I2C. Minor code improvements. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3564 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/include/i2c.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'os') diff --git a/os/hal/include/i2c.h b/os/hal/include/i2c.h index 18e93119e..1923742c7 100644 --- a/os/hal/include/i2c.h +++ b/os/hal/include/i2c.h @@ -211,8 +211,9 @@ struct I2CSlaveConfig{ ((i2cp)->id_slave_config)->id_callback(i2cp, i2cscfg); \ (i2cp)->id_state = I2C_READY; \ } \ - else \ + else{ \ (i2cp)->id_state = I2C_READY; \ + } \ _i2c_wakeup_isr(i2cp); \ } @@ -236,8 +237,9 @@ struct I2CSlaveConfig{ ((i2cp)->id_slave_config)->id_err_callback(i2cp, i2cscfg); \ (i2cp)->id_state = I2C_READY; \ } \ - else \ + else{ \ (i2cp)->id_state = I2C_READY; \ + } \ _i2c_wakeup_isr(i2cp); \ } -- cgit v1.2.3 From 46d388fb246bbba56f75e15a0514376580c0c2fb Mon Sep 17 00:00:00 2001 From: barthess Date: Wed, 7 Dec 2011 07:52:42 +0000 Subject: I2C. Added DMA masks for other MCUs. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3565 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F1xx/hal_lld_f100.h | 14 ++++++++++++++ os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h | 14 ++++++++++++++ os/hal/platforms/STM32F2xx/hal_lld.h | 19 +++++++++++++++++++ os/hal/platforms/STM32L1xx/hal_lld.h | 14 ++++++++++++++ 4 files changed, 61 insertions(+) (limited to 'os') diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h index 3f5d9502b..96f5a7f33 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h @@ -295,8 +295,22 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 + #define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_I2C2_TX_DMA_CHN 0x00000000 + #define STM32_HAS_I2C3 FALSE +#define STM32_I2C3_RX_DMA_MSK 0 +#define STM32_I2C3_RX_DMA_CHN 0x00000000 +#define STM32_I2C3_TX_DMA_MSK 0 +#define STM32_I2C3_TX_DMA_CHN 0x00000000 /* RTC attributes.*/ #define STM32_HAS_RTC TRUE diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h index 882ec6094..9a612b0ee 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h @@ -166,8 +166,22 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 + #define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_I2C2_TX_DMA_CHN 0x00000000 + #define STM32_HAS_I2C3 FALSE +#define STM32_I2C3_RX_DMA_MSK 0 +#define STM32_I2C3_RX_DMA_CHN 0x00000000 +#define STM32_I2C3_TX_DMA_MSK 0 +#define STM32_I2C3_TX_DMA_CHN 0x00000000 /* RTC attributes.*/ #define STM32_HAS_RTC TRUE diff --git a/os/hal/platforms/STM32F2xx/hal_lld.h b/os/hal/platforms/STM32F2xx/hal_lld.h index 91135950f..cad926330 100644 --- a/os/hal/platforms/STM32F2xx/hal_lld.h +++ b/os/hal/platforms/STM32F2xx/hal_lld.h @@ -157,8 +157,27 @@ #define STM32_HAS_GPIOH TRUE #define STM32_HAS_GPIOI TRUE +/* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK ((STM32_DMA_STREAM_ID_MSK(1, 0) | \ + STM32_DMA_STREAM_ID_MSK(1, 5))) +#define STM32_I2C1_RX_DMA_CHN 0x00100001 +#define STM32_I2C1_TX_DMA_MSK ((STM32_DMA_STREAM_ID_MSK(1, 7)) | \ + (STM32_DMA_STREAM_ID_MSK(1, 6))) +#define STM32_I2C1_TX_DMA_CHN 0x10000000 + #define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK ((STM32_DMA_STREAM_ID_MSK(1, 2) | \ + STM32_DMA_STREAM_ID_MSK(1, 3))) +#define STM32_I2C2_RX_DMA_CHN 0x00007700 +#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C2_TX_DMA_CHN 0x70000000 + +#define STM32_HAS_I2C3 TRUE +#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_I2C3_RX_DMA_CHN 0x00000300 +#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_I2C3_TX_DMA_CHN 0x00030000 #define STM32_HAS_RTC TRUE diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index b25bad51d..8d6cfd6f0 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -198,8 +198,22 @@ /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 + #define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_I2C2_TX_DMA_CHN 0x00000000 + #define STM32_HAS_I2C3 FALSE +#define STM32_I2C3_RX_DMA_MSK 0 +#define STM32_I2C3_RX_DMA_CHN 0x00000000 +#define STM32_I2C3_TX_DMA_MSK 0 +#define STM32_I2C3_TX_DMA_CHN 0x00000000 /* RTC attributes.*/ #define STM32_HAS_RTC TRUE -- cgit v1.2.3 From 6562e684cd3942eb0273a13bd6c8b7027a868745 Mon Sep 17 00:00:00 2001 From: barthess Date: Wed, 7 Dec 2011 12:23:33 +0000 Subject: GPT on F4x. Typo fixed. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3566 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/gpt_lld.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'os') diff --git a/os/hal/platforms/STM32/gpt_lld.c b/os/hal/platforms/STM32/gpt_lld.c index e40843ccb..34468ccc3 100644 --- a/os/hal/platforms/STM32/gpt_lld.c +++ b/os/hal/platforms/STM32/gpt_lld.c @@ -249,7 +249,7 @@ void gpt_lld_init(void) { #if STM32_GPT_USE_TIM8 /* Driver initialization.*/ - GPTD5.tim = STM32_TIM8; + GPTD8.tim = STM32_TIM8; gptObjectInit(&GPTD8); #endif } -- cgit v1.2.3 From 11ed726e41afe47beace358939d44118ece4661e Mon Sep 17 00:00:00 2001 From: barthess Date: Wed, 7 Dec 2011 12:30:52 +0000 Subject: GPT on F4x. MCU has TIM6 and TIM7, fixed. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3567 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F4xx/hal_lld.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'os') diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index 577e37834..061ce1304 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -347,8 +347,8 @@ #define STM32_HAS_TIM3 TRUE #define STM32_HAS_TIM4 TRUE #define STM32_HAS_TIM5 TRUE -#define STM32_HAS_TIM6 FALSE -#define STM32_HAS_TIM7 FALSE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 TRUE #define STM32_HAS_TIM8 TRUE #define STM32_HAS_TIM9 TRUE #define STM32_HAS_TIM10 TRUE -- cgit v1.2.3 From ac8123d2da74ac0bb6cb2d968bf79fe48905ad87 Mon Sep 17 00:00:00 2001 From: barthess Date: Wed, 7 Dec 2011 14:13:57 +0000 Subject: I2C. Added note about different API classes usage. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3569 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/i2c_lld.c | 47 ++++++++++++++++++++++++++++++++-------- 1 file changed, 38 insertions(+), 9 deletions(-) (limited to 'os') diff --git a/os/hal/platforms/STM32/i2c_lld.c b/os/hal/platforms/STM32/i2c_lld.c index d843591e1..f3291f819 100644 --- a/os/hal/platforms/STM32/i2c_lld.c +++ b/os/hal/platforms/STM32/i2c_lld.c @@ -43,6 +43,30 @@ * Otherwise there is a risk of setting a second STOP, START or PEC request. */ +/*===========================================================================*/ +/* Knowledge base. */ +/*===========================================================================*/ +/* +Not all system functions are usable in a given context. + +The most restrictive type are the i-class, an I-class function is a function that must: +- Not access the "current" thread in any way (from an ISR the current thread +is random so it is meaningless). +- Not reschedule internally (from an ISR the reschedule is done at the end of +the ISR chain, rescheduling from within an ISR is forbidden because would +leave the IRQ stack not empty with all kind of funny consequences. +- Not try to change state for the current thread. +- Must be invoked between a lock() and an unlock() but never lock/unlock internally. + +A bit less restrictive are the S-class that must simply: +- Be invoked between a lock() and an unlock() but never lock/unlock internally. +S-class can reschedule internally, access the current thread implicitly and +also change state so are not eligible for ISR context. + +Normal functions can be invoked from thread context only but have no internal +restrictions. +*/ + /*===========================================================================*/ /* Driver local definitions. */ /*===========================================================================*/ @@ -155,12 +179,12 @@ static void i2c_serve_event_interrupt(I2CDriver *i2cp) { /* catch BTF event after the end of trasmission */ if (i2cp->rxbytes > 1){ /* start "read after write" operation */ - i2c_lld_master_receive(i2cp, (i2cp->slave_addr >> 1), i2cp->rxbuf, i2cp->rxbytes); + i2c_lld_master_receive(i2cp, (i2cp->slave_addr >> 1), + i2cp->rxbuf, i2cp->rxbytes); return; } else i2cp->id_i2c->CR1 |= I2C_CR1_STOP; - // FIXME: change this polling to something else while(i2cp->id_i2c->CR1 & I2C_CR1_STOP) ; _i2c_isr_code(i2cp, i2cp->id_slave_config); @@ -181,7 +205,6 @@ static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp){ dmaStreamDisable(i2cp->dmarx); i2cp->id_i2c->CR1 |= I2C_CR1_STOP; - // FIXME: change this polling to something else while(i2cp->id_i2c->CR1 & I2C_CR1_STOP) ; _i2c_isr_code(i2cp, i2cp->id_slave_config); @@ -209,10 +232,10 @@ static void i2c_serve_error_interrupt(I2CDriver *i2cp) { chSysLockFromIsr(); /* clear interrupt falgs just to be safe */ - dmaStreamClearInterrupt(i2cp->dmatx); - dmaStreamClearInterrupt(i2cp->dmarx); dmaStreamDisable(i2cp->dmatx); dmaStreamDisable(i2cp->dmarx); + dmaStreamClearInterrupt(i2cp->dmatx); + dmaStreamClearInterrupt(i2cp->dmarx); chSysUnlockFromIsr(); reg = i2cp->id_i2c; @@ -344,13 +367,13 @@ void i2c_lld_init(void) { #endif /* STM32_I2C_USE_I2C3 */ } - /** * @brief Configures and activates the I2C peripheral. * * @param[in] i2cp pointer to the @p I2CDriver object */ void i2c_lld_start(I2CDriver *i2cp) { + i2cp->dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; if (i2cp->id_state == I2C_STOP) { /* If in stopped state then enables the I2C clock.*/ @@ -641,15 +664,21 @@ void i2c_lld_set_opmode(I2CDriver *i2cp) { } - - /** * @brief Deactivates the I2C peripheral. * * @param[in] i2cp pointer to the @p I2CDriver object */ void i2c_lld_stop(I2CDriver *i2cp) { - if (i2cp->id_state == I2C_READY) { /* If in ready state then disables the I2C clock.*/ + + if (i2cp->id_state != I2C_STOP) { /* If in ready state then disables the I2C clock.*/ + + dmaStreamDisable(i2cp->dmatx); + dmaStreamDisable(i2cp->dmarx); + dmaStreamClearInterrupt(i2cp->dmatx); + dmaStreamClearInterrupt(i2cp->dmarx); + dmaStreamRelease(i2cp->dmatx); + dmaStreamRelease(i2cp->dmarx); #if STM32_I2C_USE_I2C1 if (&I2CD1 == i2cp) { -- cgit v1.2.3 From 0738591b023a4e2c6cacebadebfef08aafea4d6e Mon Sep 17 00:00:00 2001 From: barthess Date: Wed, 7 Dec 2011 17:57:42 +0000 Subject: I2C. Switch to synchronous model. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3570 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/include/i2c.h | 85 +++------------------------------------- os/hal/platforms/STM32/i2c_lld.c | 36 +++++++++-------- os/hal/platforms/STM32/i2c_lld.h | 15 +------ os/hal/src/i2c.c | 21 +--------- 4 files changed, 29 insertions(+), 128 deletions(-) (limited to 'os') diff --git a/os/hal/include/i2c.h b/os/hal/include/i2c.h index 1923742c7..8cfd97e75 100644 --- a/os/hal/include/i2c.h +++ b/os/hal/include/i2c.h @@ -66,13 +66,6 @@ #define I2C_USE_MUTUAL_EXCLUSION TRUE #endif -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_WAIT) || defined(__DOXYGEN__) -#define I2C_USE_WAIT TRUE -#endif - /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ @@ -98,57 +91,11 @@ typedef enum { #include "i2c_lld.h" -/** - * @brief I2C notification callback type. - * @details This callback invoked when byte transfer finish event occurs, - * no matter if sending or reading. - * - * @param[in] i2cp pointer to the @p I2CDriver object triggering the - * callback - * @param[in] i2cscfg pointer to the @p I2CSlaveConfig object triggering the - * callback - */ -typedef void (*i2ccallback_t)(I2CDriver *i2cp, const I2CSlaveConfig *i2cscfg); - -/** - * @brief I2C error notification callback type. - * - * @param[in] i2cp pointer to the @p I2CDriver object triggering the - * callback - * @param[in] i2cscfg pointer to the @p I2CSlaveConfig object triggering the - * callback - */ -typedef void (*i2cerrorcallback_t)(I2CDriver *i2cp, - const I2CSlaveConfig *i2cscfg); - -/** - * @brief Structure representing an I2C slave configuration. - * @details Each slave device has its own config structure with input and - * output buffers for temporally storing data. - */ -struct I2CSlaveConfig{ - /** - * @brief Callback pointer. - * @note Transfer finished callback. Invoke when all data transferred. - * If set to @p NULL then the callback is disabled. - */ - i2ccallback_t id_callback; - /** - * @brief Callback pointer. - * @note This callback will be invoked when error condition occur. - * If set to @p NULL then the callback is disabled. - */ - i2cerrorcallback_t id_err_callback; -#if defined(I2C_SLAVECONFIG_EXT_FIELDS) - I2C_SLAVECONFIG_EXT_FIELDS -#endif -}; /*===========================================================================*/ /* Driver macros. */ /*===========================================================================*/ -#if I2C_USE_WAIT || defined(__DOXYGEN__) /** * @brief Waits for operation completion. * @details This function waits for the driver to complete the current @@ -186,60 +133,40 @@ struct I2CSlaveConfig{ chSysUnlockFromIsr(); \ } \ } -#else /* !I2C_USE_WAIT */ -#define _i2c_wait_s(i2cp) -#define _i2c_wakeup_isr(i2cp) -#endif /* !I2C_USE_WAIT */ /** * @brief Common ISR code. * @details This code handles the portable part of the ISR code: - * - Callback invocation. - * - Waiting thread wakeup, if any. + * - Waiting thread wakeup. * - Driver state transitions. * * @note This macro is meant to be used in the low level drivers * implementation only. * * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] i2cscfg pointer to the @p I2CSlaveConfig object * * @notapi */ #define _i2c_isr_code(i2cp, i2cscfg) { \ - if(((i2cp)->id_slave_config)->id_callback) { \ - ((i2cp)->id_slave_config)->id_callback(i2cp, i2cscfg); \ - (i2cp)->id_state = I2C_READY; \ - } \ - else{ \ - (i2cp)->id_state = I2C_READY; \ - } \ + (i2cp)->id_state = I2C_READY; \ _i2c_wakeup_isr(i2cp); \ } /** * @brief Error ISR code. * @details This code handles the portable part of the ISR code: - * - Error callback invocation. - * - Waiting thread wakeup, if any. + * - Waiting thread wakeup. * - Driver state transitions. * * @note This macro is meant to be used in the low level drivers * implementation only. * * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] i2cscfg pointer to the @p I2CSlaveConfig object * * @notapi */ #define _i2c_isr_err_code(i2cp, i2cscfg) { \ - if(((i2cp)->id_slave_config)->id_err_callback) { \ - ((i2cp)->id_slave_config)->id_err_callback(i2cp, i2cscfg); \ - (i2cp)->id_state = I2C_READY; \ - } \ - else{ \ - (i2cp)->id_state = I2C_READY; \ - } \ + (i2cp)->id_state = I2C_READY; \ _i2c_wakeup_isr(i2cp); \ } @@ -254,11 +181,11 @@ extern "C" { void i2cObjectInit(I2CDriver *i2cp); void i2cStart(I2CDriver *i2cp, const I2CConfig *config); void i2cStop(I2CDriver *i2cp); - void i2cMasterTransmit(I2CDriver *i2cp, const I2CSlaveConfig *i2cscfg, + void i2cMasterTransmit(I2CDriver *i2cp, uint8_t slave_addr, uint8_t *txbuf, size_t txbytes, uint8_t *rxbuf, size_t rxbytes); - void i2cMasterReceive(I2CDriver *i2cp, const I2CSlaveConfig *i2cscfg, + void i2cMasterReceive(I2CDriver *i2cp, uint8_t slave_addr, uint8_t *rxbuf, size_t rxbytes); void i2cMasterStart(I2CDriver *i2cp); void i2cMasterStop(I2CDriver *i2cp); diff --git a/os/hal/platforms/STM32/i2c_lld.c b/os/hal/platforms/STM32/i2c_lld.c index f3291f819..1345c847b 100644 --- a/os/hal/platforms/STM32/i2c_lld.c +++ b/os/hal/platforms/STM32/i2c_lld.c @@ -185,8 +185,6 @@ static void i2c_serve_event_interrupt(I2CDriver *i2cp) { } else i2cp->id_i2c->CR1 |= I2C_CR1_STOP; - while(i2cp->id_i2c->CR1 & I2C_CR1_STOP) - ; _i2c_isr_code(i2cp, i2cp->id_slave_config); break; @@ -205,8 +203,6 @@ static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp){ dmaStreamDisable(i2cp->dmarx); i2cp->id_i2c->CR1 |= I2C_CR1_STOP; - while(i2cp->id_i2c->CR1 & I2C_CR1_STOP) - ; _i2c_isr_code(i2cp, i2cp->id_slave_config); } @@ -227,7 +223,7 @@ static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp){ * @param[in] i2cp pointer to the @p I2CDriver object */ static void i2c_serve_error_interrupt(I2CDriver *i2cp) { - i2cflags_t flags; + i2cflags_t errors; I2C_TypeDef *reg; chSysLockFromIsr(); @@ -239,43 +235,41 @@ static void i2c_serve_error_interrupt(I2CDriver *i2cp) { chSysUnlockFromIsr(); reg = i2cp->id_i2c; - flags = I2CD_NO_ERROR; + errors = I2CD_NO_ERROR; if(reg->SR1 & I2C_SR1_BERR) { /* Bus error */ reg->SR1 &= ~I2C_SR1_BERR; - flags |= I2CD_BUS_ERROR; + errors |= I2CD_BUS_ERROR; } if(reg->SR1 & I2C_SR1_ARLO) { /* Arbitration lost */ reg->SR1 &= ~I2C_SR1_ARLO; - flags |= I2CD_ARBITRATION_LOST; + errors |= I2CD_ARBITRATION_LOST; } if(reg->SR1 & I2C_SR1_AF) { /* Acknowledge fail */ reg->SR1 &= ~I2C_SR1_AF; reg->CR1 |= I2C_CR1_STOP; /* setting stop bit */ - while(i2cp->id_i2c->CR1 & I2C_CR1_STOP) - ; - flags |= I2CD_ACK_FAILURE; + errors |= I2CD_ACK_FAILURE; } if(reg->SR1 & I2C_SR1_OVR) { /* Overrun */ reg->SR1 &= ~I2C_SR1_OVR; - flags |= I2CD_OVERRUN; + errors |= I2CD_OVERRUN; } if(reg->SR1 & I2C_SR1_PECERR) { /* PEC error */ reg->SR1 &= ~I2C_SR1_PECERR; - flags |= I2CD_PEC_ERROR; + errors |= I2CD_PEC_ERROR; } if(reg->SR1 & I2C_SR1_TIMEOUT) { /* SMBus Timeout */ reg->SR1 &= ~I2C_SR1_TIMEOUT; - flags |= I2CD_TIMEOUT; + errors |= I2CD_TIMEOUT; } if(reg->SR1 & I2C_SR1_SMBALERT) { /* SMBus alert */ reg->SR1 &= ~I2C_SR1_SMBALERT; - flags |= I2CD_SMB_ALERT; + errors |= I2CD_SMB_ALERT; } - if(flags != I2CD_NO_ERROR) { /* send communication end signal */ + if(errors != I2CD_NO_ERROR) { /* send communication end signal */ chSysLockFromIsr(); - i2cAddFlagsI(i2cp, flags); + i2cAddFlagsI(i2cp, errors); chSysUnlockFromIsr(); _i2c_isr_err_code(i2cp, i2cp->id_slave_config); } @@ -523,6 +517,10 @@ void i2c_lld_master_receive(I2CDriver *i2cp, uint8_t slave_addr, dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); dmaStreamSetMode(i2cp->dmarx, ((i2cp->dmamode) | mode)); + /* wait stop bit from previouse transaction*/ + while(i2cp->id_i2c->CR1 & I2C_CR1_STOP) + ; + i2cp->id_i2c->CR2 |= I2C_CR2_ITERREN | I2C_CR2_ITEVTEN; i2cp->id_i2c->CR1 |= I2C_CR1_START | I2C_CR1_ACK; } @@ -561,6 +559,10 @@ void i2c_lld_master_transmit(I2CDriver *i2cp, uint8_t slave_addr, dmaStreamSetTransactionSize(i2cp->dmatx, txbytes); dmaStreamSetMode(i2cp->dmatx, ((i2cp->dmamode) | mode)); + /* wait stop bit from previouse transaction*/ + while(i2cp->id_i2c->CR1 & I2C_CR1_STOP) + ; + i2cp->id_i2c->CR2 |= I2C_CR2_ITERREN | I2C_CR2_ITEVTEN; i2cp->id_i2c->CR1 |= I2C_CR1_START; } diff --git a/os/hal/platforms/STM32/i2c_lld.h b/os/hal/platforms/STM32/i2c_lld.h index 2ca6b872a..4e9051e39 100644 --- a/os/hal/platforms/STM32/i2c_lld.h +++ b/os/hal/platforms/STM32/i2c_lld.h @@ -273,11 +273,6 @@ typedef struct { */ typedef struct I2CDriver I2CDriver; -/** - * @brief Type of a structure representing an I2C slave config. - */ -typedef struct I2CSlaveConfig I2CSlaveConfig; - /** * @brief Structure representing an I2C driver. */ @@ -287,12 +282,11 @@ struct I2CDriver{ */ i2cstate_t id_state; -#if I2C_USE_WAIT /** * @brief Thread waiting for I/O completion. */ Thread *id_thread; -#endif /* I2C_USE_WAIT */ + #if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) #if CH_USE_MUTEXES || defined(__DOXYGEN__) /** @@ -308,10 +302,6 @@ struct I2CDriver{ * @brief Current configuration data. */ const I2CConfig *id_config; - /** - * @brief Current slave configuration data. - */ - const I2CSlaveConfig *id_slave_config; __IO size_t txbytes; /*!< @brief Number of bytes to be transmitted. */ __IO size_t rxbytes; /*!< @brief Number of bytes to be received. */ @@ -341,8 +331,7 @@ struct I2CDriver{ (i2cp->id_i2c->SR2 & I2C_SR2_BUSY) -/* Wait until BUSY flag is reset: a STOP has been generated on the bus - * signaling the end of transmission. Normally this wait function +/* Wait until BUSY flag is reset. Normally this wait function * does not block thread, only if slave not response it does. */ #define i2c_lld_wait_bus_free(i2cp) { \ diff --git a/os/hal/src/i2c.c b/os/hal/src/i2c.c index 4b9160a68..996343104 100644 --- a/os/hal/src/i2c.c +++ b/os/hal/src/i2c.c @@ -75,11 +75,7 @@ void i2cObjectInit(I2CDriver *i2cp) { i2cp->id_config = NULL; i2cp->rxbuf = NULL; i2cp->txbuf = NULL; - i2cp->id_slave_config = NULL; - -#if I2C_USE_WAIT i2cp->id_thread = NULL; -#endif /* I2C_USE_WAIT */ #if I2C_USE_MUTUAL_EXCLUSION #if CH_USE_MUTEXES @@ -147,7 +143,6 @@ void i2cStop(I2CDriver *i2cp) { * hardware restrictions. * * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] i2cscfg pointer to the @p I2C slave config * @param[in] slave_addr Slave device address (7 bits) without R/W bit * @param[in] txbuf pointer to transmit buffer * @param[in] txbytes number of bytes to be transmitted @@ -156,24 +151,19 @@ void i2cStop(I2CDriver *i2cp) { * you want transmit only */ void i2cMasterTransmit(I2CDriver *i2cp, - const I2CSlaveConfig *i2cscfg, uint8_t slave_addr, uint8_t *txbuf, size_t txbytes, uint8_t *rxbuf, size_t rxbytes) { - chDbgCheck((i2cp != NULL) && (i2cscfg != NULL) &&\ + chDbgCheck((i2cp != NULL) &&\ (slave_addr != 0) &&\ (txbytes > 0) &&\ (txbuf != NULL) &&\ ((rxbytes == 0) || ((rxbytes > 1) && (rxbuf != NULL))), "i2cMasterTransmit"); - /* init slave config field in driver */ - i2cp->id_slave_config = i2cscfg; - - // TODO: remove this loop. Do only 1 check because mutual exclusion resolve collisions i2c_lld_wait_bus_free(i2cp); chDbgAssert(!(i2c_lld_bus_is_busy(i2cp)), "i2cMasterReceive(), #1", "time is out"); @@ -191,27 +181,21 @@ void i2cMasterTransmit(I2CDriver *i2cp, * hardware restrictions. * * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] i2cscfg pointer to the @p I2C slave config * @param[in] slave_addr slave device address (7 bits) without R/W bit * @param[in] rxbytes number of bytes to be received * @param[in] rxbuf pointer to receive buffer */ void i2cMasterReceive(I2CDriver *i2cp, - const I2CSlaveConfig *i2cscfg, uint8_t slave_addr, uint8_t *rxbuf, size_t rxbytes){ - chDbgCheck((i2cp != NULL) && (i2cscfg != NULL) &&\ + chDbgCheck((i2cp != NULL) &&\ (slave_addr != 0) &&\ (rxbytes > 1) && \ (rxbuf != NULL), "i2cMasterReceive"); - /* init slave config field in driver */ - i2cp->id_slave_config = i2cscfg; - - // TODO: remove this loop. Do only 1 check because mutual exclusion resolve collisions i2c_lld_wait_bus_free(i2cp); chDbgAssert(!(i2c_lld_bus_is_busy(i2cp)), "i2cMasterReceive(), #1", "time is out"); @@ -298,7 +282,6 @@ void i2cReleaseBus(I2CDriver *i2cp) { chDbgCheck(i2cp != NULL, "i2cReleaseBus"); #if CH_USE_MUTEXES - (void)i2cp; chMtxUnlock(); #elif CH_USE_SEMAPHORES chSemSignal(&i2cp->id_semaphore); -- cgit v1.2.3 From 3799bf56f52f7a5be9eeda6757c6642105c4ed66 Mon Sep 17 00:00:00 2001 From: barthess Date: Wed, 7 Dec 2011 19:23:09 +0000 Subject: I2C. Error handling from userland code added. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3572 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/include/i2c.h | 5 +++-- os/hal/src/i2c.c | 12 ++++++++++-- 2 files changed, 13 insertions(+), 4 deletions(-) (limited to 'os') diff --git a/os/hal/include/i2c.h b/os/hal/include/i2c.h index 8cfd97e75..5ee4887e9 100644 --- a/os/hal/include/i2c.h +++ b/os/hal/include/i2c.h @@ -181,15 +181,16 @@ extern "C" { void i2cObjectInit(I2CDriver *i2cp); void i2cStart(I2CDriver *i2cp, const I2CConfig *config); void i2cStop(I2CDriver *i2cp); - void i2cMasterTransmit(I2CDriver *i2cp, + i2cflags_t i2cMasterTransmit(I2CDriver *i2cp, uint8_t slave_addr, uint8_t *txbuf, size_t txbytes, uint8_t *rxbuf, size_t rxbytes); - void i2cMasterReceive(I2CDriver *i2cp, + i2cflags_t i2cMasterReceive(I2CDriver *i2cp, uint8_t slave_addr, uint8_t *rxbuf, size_t rxbytes); void i2cMasterStart(I2CDriver *i2cp); void i2cMasterStop(I2CDriver *i2cp); void i2cAddFlagsI(I2CDriver *i2cp, i2cflags_t mask); + i2cflags_t i2cGetAndClearFlags(I2CDriver *i2cp); #if I2C_USE_MUTUAL_EXCLUSION void i2cAcquireBus(I2CDriver *i2cp); diff --git a/os/hal/src/i2c.c b/os/hal/src/i2c.c index 996343104..f20932ef3 100644 --- a/os/hal/src/i2c.c +++ b/os/hal/src/i2c.c @@ -149,8 +149,10 @@ void i2cStop(I2CDriver *i2cp) { * @param[in] rxbuf pointer to receive buffer * @param[in] rxbytes number of bytes to be received, set it to 0 if * you want transmit only + * + * @return Zero if no errors, otherwise return error code. */ -void i2cMasterTransmit(I2CDriver *i2cp, +i2cflags_t i2cMasterTransmit(I2CDriver *i2cp, uint8_t slave_addr, uint8_t *txbuf, size_t txbytes, @@ -173,6 +175,8 @@ void i2cMasterTransmit(I2CDriver *i2cp, i2cp->id_state = I2C_ACTIVE_TRANSMIT; i2c_lld_master_transmit(i2cp, slave_addr, txbuf, txbytes, rxbuf, rxbytes); _i2c_wait_s(i2cp); + + return i2cGetAndClearFlags(i2cp); } /** @@ -184,8 +188,10 @@ void i2cMasterTransmit(I2CDriver *i2cp, * @param[in] slave_addr slave device address (7 bits) without R/W bit * @param[in] rxbytes number of bytes to be received * @param[in] rxbuf pointer to receive buffer + * + * @return Zero if no errors, otherwise return error code. */ -void i2cMasterReceive(I2CDriver *i2cp, +i2cflags_t i2cMasterReceive(I2CDriver *i2cp, uint8_t slave_addr, uint8_t *rxbuf, size_t rxbytes){ @@ -205,6 +211,8 @@ void i2cMasterReceive(I2CDriver *i2cp, i2cp->id_state = I2C_ACTIVE_RECEIVE; i2c_lld_master_receive(i2cp, slave_addr, rxbuf, rxbytes); _i2c_wait_s(i2cp); + + return i2cGetAndClearFlags(i2cp); } /** -- cgit v1.2.3