From 80c4c3fd6d619efb27271dbeabcf10856558ea7c Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Wed, 13 Aug 2014 14:26:59 +0000
Subject: Fixed bug #525.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7172 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/ports/STM32/STM32F30x/hal_lld.c |  9 ++++++---
 os/hal/ports/STM32/STM32F30x/hal_lld.h | 14 ++++++++++++++
 2 files changed, 20 insertions(+), 3 deletions(-)

(limited to 'os')

diff --git a/os/hal/ports/STM32/STM32F30x/hal_lld.c b/os/hal/ports/STM32/STM32F30x/hal_lld.c
index 7ccac7bcf..53ac4d11b 100644
--- a/os/hal/ports/STM32/STM32F30x/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F30x/hal_lld.c
@@ -170,9 +170,6 @@ void stm32_clock_init(void) {
                STM32_PLLSRC    | STM32_PPRE1     | STM32_PPRE2    |
                STM32_HPRE;
   RCC->CFGR2 = STM32_ADC34PRES | STM32_ADC12PRES | STM32_PREDIV;
-  RCC->CFGR3 = STM32_UART5SW   | STM32_UART4SW   | STM32_USART3SW |
-               STM32_USART2SW  | STM32_TIM8SW    | STM32_TIM1SW   |
-               STM32_I2C2SW    | STM32_I2C1SW    | STM32_USART1SW;
 
 #if STM32_ACTIVATE_PLL
   /* PLL activation.*/
@@ -181,6 +178,12 @@ void stm32_clock_init(void) {
     ;                                       /* Waits until PLL is stable.   */
 #endif
 
+  /* After PLL activation because the special requirements for TIM1 and
+     TIM8 bits.*/
+  RCC->CFGR3 = STM32_UART5SW   | STM32_UART4SW   | STM32_USART3SW |
+               STM32_USART2SW  | STM32_TIM8SW    | STM32_TIM1SW   |
+               STM32_I2C2SW    | STM32_I2C1SW    | STM32_USART1SW;
+
   /* Flash setup and final clock selection.   */
   FLASH->ACR = STM32_FLASHBITS;
 
diff --git a/os/hal/ports/STM32/STM32F30x/hal_lld.h b/os/hal/ports/STM32/STM32F30x/hal_lld.h
index 5a9baf9e7..0d567e0ed 100644
--- a/os/hal/ports/STM32/STM32F30x/hal_lld.h
+++ b/os/hal/ports/STM32/STM32F30x/hal_lld.h
@@ -1017,8 +1017,15 @@
  */
 #if STM32_TIM1SW == STM32_TIM1SW_PCLK2
 #define STM32_TIM1CLK               STM32_PCLK2
+
 #elif STM32_TIM1SW == STM32_TIM1SW_PLLX2
+#if (STM32_SW != STM32_SW_PLL) ||                                           \
+    (STM32_HPRE != STM32_HPRE_DIV1) ||                                      \
+    (STM32_PPRE2 != STM32_PPRE2_DIV2)
+#error "double clock mode cannot be activated for TIM1 under the current settings"
+#endif
 #define STM32_TIM1CLK               (STM32_PLLCLKOUT * 2)
+
 #else
 #error "invalid source selected for TIM1 clock"
 #endif
@@ -1028,8 +1035,15 @@
  */
 #if STM32_TIM8SW == STM32_TIM8SW_PCLK2
 #define STM32_TIM8CLK               STM32_PCLK2
+
 #elif STM32_TIM8SW == STM32_TIM8SW_PLLX2
+#if (STM32_SW != STM32_SW_PLL) ||                                           \
+    (STM32_HPRE != STM32_HPRE_DIV1) ||                                      \
+    (STM32_PPRE2 != STM32_PPRE2_DIV2)
+#error "double clock mode cannot be activated for TIM8 under the current settings"
+#endif
 #define STM32_TIM8CLK               (STM32_PLLCLKOUT * 2)
+
 #else
 #error "invalid source selected for TIM8 clock"
 #endif
-- 
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