From 6ef7af471057d28b3f444094949b08ac06b249a7 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 6 Feb 2013 10:25:53 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5117 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/ports/GCC/PPC/SPC560BCxx/ppcparams.h | 17 ++- os/ports/GCC/PPC/SPC560Pxx/ppcparams.h | 15 ++- os/ports/GCC/PPC/SPC563Mxx/ppcparams.h | 15 ++- os/ports/GCC/PPC/SPC56ELxx/bam.s | 84 +++++-------- os/ports/GCC/PPC/SPC56ELxx/hwconf.s | 8 +- os/ports/GCC/PPC/SPC56ELxx/ivor.s | 213 ++++++-------------------------- os/ports/GCC/PPC/SPC56ELxx/port.mk | 5 +- os/ports/GCC/PPC/SPC56ELxx/ppcparams.h | 17 ++- 8 files changed, 117 insertions(+), 257 deletions(-) (limited to 'os') diff --git a/os/ports/GCC/PPC/SPC560BCxx/ppcparams.h b/os/ports/GCC/PPC/SPC560BCxx/ppcparams.h index c50b644e0..5d4d9a37e 100644 --- a/os/ports/GCC/PPC/SPC560BCxx/ppcparams.h +++ b/os/ports/GCC/PPC/SPC560BCxx/ppcparams.h @@ -35,32 +35,37 @@ /** * @brief PPC core model. */ -#define PPC_VARIANT PPC_VARIANT_e200z0 +#define PPC_VARIANT PPC_VARIANT_e200z0 /** * @brief Number of writable bits in IVPR register. */ -#define PPC_IVPR_BITS 20 +#define PPC_IVPR_BITS 20 /** * @brief IVORx registers support. */ -#define PPC_SUPPORTS_IVORS FALSE +#define PPC_SUPPORTS_IVORS FALSE /** * @brief Book E instruction set support. */ -#define PPC_SUPPORTS_BOOKE FALSE +#define PPC_SUPPORTS_BOOKE FALSE /** * @brief VLE instruction set support. */ -#define PPC_SUPPORTS_VLE TRUE +#define PPC_SUPPORTS_VLE TRUE /** * @brief Supports VLS Load/Store Multiple Volatile instructions. */ -#define PPC_SUPPORTS_VLE_MULTI TRUE +#define PPC_SUPPORTS_VLE_MULTI TRUE + +/** + * @brief Supports the decrementer timer. + */ +#define PPC_SUPPORTS_DECREMENTER FALSE #endif /* _PPCPARAMS_H_ */ diff --git a/os/ports/GCC/PPC/SPC560Pxx/ppcparams.h b/os/ports/GCC/PPC/SPC560Pxx/ppcparams.h index 8b4040bb5..7f075ee0d 100644 --- a/os/ports/GCC/PPC/SPC560Pxx/ppcparams.h +++ b/os/ports/GCC/PPC/SPC560Pxx/ppcparams.h @@ -40,27 +40,32 @@ /** * @brief Number of writable bits in IVPR register. */ -#define PPC_IVPR_BITS 16 +#define PPC_IVPR_BITS 16 /** * @brief IVORx registers support. */ -#define PPC_SUPPORTS_IVORS FALSE +#define PPC_SUPPORTS_IVORS FALSE /** * @brief Book E instruction set support. */ -#define PPC_SUPPORTS_BOOKE FALSE +#define PPC_SUPPORTS_BOOKE FALSE /** * @brief VLE instruction set support. */ -#define PPC_SUPPORTS_VLE TRUE +#define PPC_SUPPORTS_VLE TRUE /** * @brief Supports VLS Load/Store Multiple Volatile instructions. */ -#define PPC_SUPPORTS_VLE_MULTI TRUE +#define PPC_SUPPORTS_VLE_MULTI TRUE + +/** + * @brief Supports the decrementer timer. + */ +#define PPC_SUPPORTS_DECREMENTER FALSE #endif /* _PPCPARAMS_H_ */ diff --git a/os/ports/GCC/PPC/SPC563Mxx/ppcparams.h b/os/ports/GCC/PPC/SPC563Mxx/ppcparams.h index e8e843190..0b68313ce 100644 --- a/os/ports/GCC/PPC/SPC563Mxx/ppcparams.h +++ b/os/ports/GCC/PPC/SPC563Mxx/ppcparams.h @@ -35,27 +35,32 @@ /** * @brief PPC core model. */ -#define PPC_VARIANT PPC_VARIANT_e200z3 +#define PPC_VARIANT PPC_VARIANT_e200z3 /** * @brief IVORx registers support. */ -#define PPC_SUPPORTS_IVORS TRUE +#define PPC_SUPPORTS_IVORS TRUE /** * @brief Book E instruction set support. */ -#define PPC_SUPPORTS_BOOKE TRUE +#define PPC_SUPPORTS_BOOKE TRUE /** * @brief VLE instruction set support. */ -#define PPC_SUPPORTS_VLE TRUE +#define PPC_SUPPORTS_VLE TRUE /** * @brief Supports VLS Load/Store Multiple Volatile instructions. */ -#define PPC_SUPPORTS_VLE_MULTI TRUE +#define PPC_SUPPORTS_VLE_MULTI TRUE + +/** + * @brief Supports the decrementer timer. + */ +#define PPC_SUPPORTS_DECREMENTER TRUE #endif /* _PPCPARAMS_H_ */ diff --git a/os/ports/GCC/PPC/SPC56ELxx/bam.s b/os/ports/GCC/PPC/SPC56ELxx/bam.s index d4f62795e..9d20aa056 100644 --- a/os/ports/GCC/PPC/SPC56ELxx/bam.s +++ b/os/ports/GCC/PPC/SPC56ELxx/bam.s @@ -85,63 +85,39 @@ /* Special function registers clearing, required in order to avoid possible problems with lockstep mode.*/ - mtcrf 0xFF, r31 - mtspr 8, r31 /* LR */ - mtspr 9, r31 /* CTR */ - - mtspr 272, r31 /* SPRG1-7 */ - mtspr 273, r31 - mtspr 274, r31 - mtspr 275, r31 - mtspr 276, r31 - mtspr 277, r31 - mtspr 278, r31 - mtspr 279, r31 - mtspr 604, r31 /* SPRG8-9 */ - mtspr 605, r31 - mtspr 26, r31 /* SRR0-1 */ - mtspr 27, r31 - mtspr 58, r31 /* CSRR0-1 */ - mtspr 59, r31 - mtspr 61, r31 /* DEAR */ - - mtspr 22, r31 /* DEC */ - mtspr 54, r31 /* DECAR */ - mtspr 285, r31 /* TBU */ - mtspr 284, r31 /* TBL */ - - mtspr 570, r31 /* MCSRR0 */ - mtspr 571, r31 /* MCSRR1 */ - - mtspr 256, r31 /* USPRG0 */ - - mtspr 562, r31 /* DBCNT */ - - mtspr 63, r31 /* IVPR */ - mtspr 318, r31 /* DVC1-2 */ - mtspr 319, r31 - mtspr 400, r31 /* IVOR0-15 */ - mtspr 401, r31 - mtspr 402, r31 - mtspr 403, r31 - mtspr 404, r31 - mtspr 405, r31 - mtspr 406, r31 - mtspr 407, r31 - mtspr 408, r31 - mtspr 409, r31 - mtspr 410, r31 - mtspr 411, r31 - mtspr 412, r31 - mtspr 413, r31 - mtspr 414, r31 - mtspr 415, r31 - mtspr 528, r31 /* IVOR32-34 */ - mtspr 529, r31 - mtspr 530, r31 + mtcrf 0xFF, %r31 + mtspr 8, %r31 /* LR */ + mtspr 9, %r31 /* CTR */ + + mtspr 272, %r31 /* SPRG1-7 */ + mtspr 273, %r31 + mtspr 274, %r31 + mtspr 275, %r31 + mtspr 276, %r31 + mtspr 277, %r31 + mtspr 278, %r31 + mtspr 279, %r31 + mtspr 604, %r31 /* SPRG8-9 */ + mtspr 605, %r31 + mtspr 26, %r31 /* SRR0-1 */ + mtspr 27, %r31 + mtspr 58, %r31 /* CSRR0-1 */ + mtspr 59, %r31 + mtspr 61, %r31 /* DEAR */ + mtspr 22, %r31 /* DEC */ + mtspr 54, %r31 /* DECAR */ + mtspr 285, %r31 /* TBU */ + mtspr 284, %r31 /* TBL */ + mtspr 570, %r31 /* MCSRR0 */ + mtspr 571, %r31 /* MCSRR1 */ + mtspr 256, %r31 /* USPRG0 */ + mtspr 562, %r31 /* DBCNT */ + mtspr 318, %r31 /* DVC1-2 */ + mtspr 319, %r31 /* HW configuration.*/ bl _hwconf + bl _ivorinit b _boot_address diff --git a/os/ports/GCC/PPC/SPC56ELxx/hwconf.s b/os/ports/GCC/PPC/SPC56ELxx/hwconf.s index 6bb45cbfb..2211b8dbd 100644 --- a/os/ports/GCC/PPC/SPC56ELxx/hwconf.s +++ b/os/ports/GCC/PPC/SPC56ELxx/hwconf.s @@ -153,12 +153,12 @@ #if !defined(__DOXYGEN__) - .section .hwconf, "ax" + .section .coreinit, "ax" .align 2 - .globl _hwconf - .type _hwconf, @function -_hwconf: + .globl _coreinit + .type _coreinit, @function +_coreinit: /* MSR settings.*/ lis r3, MSR_DEFAULT@h ori r3, r3, MSR_DEFAULT@l diff --git a/os/ports/GCC/PPC/SPC56ELxx/ivor.s b/os/ports/GCC/PPC/SPC56ELxx/ivor.s index 24d0beef3..7d2207441 100644 --- a/os/ports/GCC/PPC/SPC56ELxx/ivor.s +++ b/os/ports/GCC/PPC/SPC56ELxx/ivor.s @@ -42,6 +42,44 @@ .section .handlers, "ax" + .align 2 + .globl _ivorinit + .type _ivorinit, @function +_ivorinit: + /* + * IVPR initialization. + */ + lis %r4, __ivpr_base__@h + ori %r4, %r4, __ivpr_base__@l + mtIVPR %r4 + + /* + * IVOR default settings. + */ + lis %r4, _unhandled_exception@h + ori %r4, %r4, _unhandled_exception@l + mtspr 400, %r4 /* IVOR0-15 */ + mtspr 401, %r4 + mtspr 402, %r4 + mtspr 403, %r4 + mtspr 404, %r4 + mtspr 405, %r4 + mtspr 406, %r4 + mtspr 407, %r4 + mtspr 408, %r4 + mtspr 409, %r4 + mtspr 410, %r4 + mtspr 411, %r4 + mtspr 412, %r4 + mtspr 413, %r4 + mtspr 414, %r4 + mtspr 415, %r4 + mtspr 528, %r4 /* IVOR32-34 */ + mtspr 529, %r4 + mtspr 530, %r4 + + blr + /* * Unhandled exceptions handler. */ @@ -78,181 +116,6 @@ _IVOR15: _unhandled_exception: b _unhandled_exception - /* - * _IVOR10 handler (Book-E decrementer). - */ - .align 4 - .globl _IVOR10 - .type _IVOR10, @function -_IVOR10: - /* Creation of the external stack frame (extctx structure).*/ - stwu %sp, -80(%sp) /* Size of the extctx structure.*/ -#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI - e_stmvsrrw 8(%sp) /* Saves PC, MSR. */ - e_stmvsprw 16(%sp) /* Saves CR, LR, CTR, XER. */ - e_stmvgprw 32(%sp) /* Saves GPR0, GPR3...GPR12. */ -#else /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */ - stw %r0, 32(%sp) /* Saves GPR0. */ - mfSRR0 %r0 - stw %r0, 8(%sp) /* Saves PC. */ - mfSRR1 %r0 - stw %r0, 12(%sp) /* Saves MSR. */ - mfCR %r0 - stw %r0, 16(%sp) /* Saves CR. */ - mfLR %r0 - stw %r0, 20(%sp) /* Saves LR. */ - mfCTR %r0 - stw %r0, 24(%sp) /* Saves CTR. */ - mfXER %r0 - stw %r0, 28(%sp) /* Saves XER. */ - stw %r3, 36(%sp) /* Saves GPR3...GPR12. */ - stw %r4, 40(%sp) - stw %r5, 44(%sp) - stw %r6, 48(%sp) - stw %r7, 52(%sp) - stw %r8, 56(%sp) - stw %r9, 60(%sp) - stw %r10, 64(%sp) - stw %r11, 68(%sp) - stw %r12, 72(%sp) -#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */ - - /* Reset DIE bit in TSR register.*/ - lis %r3, 0x0800 /* DIS bit mask. */ - mtspr 336, %r3 /* TSR register. */ - -#if CH_DBG_SYSTEM_STATE_CHECK - bl dbg_check_enter_isr - bl dbg_check_lock_from_isr -#endif - bl chSysTimerHandlerI -#if CH_DBG_SYSTEM_STATE_CHECK - bl dbg_check_unlock_from_isr - bl dbg_check_leave_isr -#endif - - /* System tick handler invocation.*/ -#if CH_DBG_SYSTEM_STATE_CHECK - bl dbg_check_lock -#endif - bl chSchIsPreemptionRequired - cmpli cr0, %r3, 0 - beq cr0, _ivor_exit - bl chSchDoReschedule - b _ivor_exit - - /* - * _IVOR4 handler (Book-E external interrupt). - */ - .align 4 - .globl _IVOR4 - .type _IVOR4, @function -_IVOR4: - /* Creation of the external stack frame (extctx structure).*/ - stwu %sp, -80(%sp) /* Size of the extctx structure.*/ -#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI - e_stmvsrrw 8(%sp) /* Saves PC, MSR. */ - e_stmvsprw 16(%sp) /* Saves CR, LR, CTR, XER. */ - e_stmvgprw 32(%sp) /* Saves GPR0, GPR3...GPR12. */ -#else /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */ - stw %r0, 32(%sp) /* Saves GPR0. */ - mfSRR0 %r0 - stw %r0, 8(%sp) /* Saves PC. */ - mfSRR1 %r0 - stw %r0, 12(%sp) /* Saves MSR. */ - mfCR %r0 - stw %r0, 16(%sp) /* Saves CR. */ - mfLR %r0 - stw %r0, 20(%sp) /* Saves LR. */ - mfCTR %r0 - stw %r0, 24(%sp) /* Saves CTR. */ - mfXER %r0 - stw %r0, 28(%sp) /* Saves XER. */ - stw %r3, 36(%sp) /* Saves GPR3...GPR12. */ - stw %r4, 40(%sp) - stw %r5, 44(%sp) - stw %r6, 48(%sp) - stw %r7, 52(%sp) - stw %r8, 56(%sp) - stw %r9, 60(%sp) - stw %r10, 64(%sp) - stw %r11, 68(%sp) - stw %r12, 72(%sp) -#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */ - - /* Software vector address from the INTC register.*/ - lis %r3, INTC_IACKR@h - ori %r3, %r3, INTC_IACKR@l /* IACKR register address. */ - lwz %r3, 0(%r3) /* IACKR register value. */ - lwz %r3, 0(%r3) - mtCTR %r3 /* Software handler address. */ - -#if PPC_USE_IRQ_PREEMPTION - /* Allows preemption while executing the software handler.*/ - wrteei 1 -#endif - - /* Exectes the software handler.*/ - bctrl - -#if PPC_USE_IRQ_PREEMPTION - /* Prevents preemption again.*/ - wrteei 0 -#endif - - /* Informs the INTC that the interrupt has been served.*/ - mbar 0 - lis %r3, INTC_EOIR@h - ori %r3, %r3, INTC_EOIR@l - stw %r3, 0(%r3) /* Writing any value should do. */ - - /* Verifies if a reschedule is required.*/ -#if CH_DBG_SYSTEM_STATE_CHECK - bl dbg_check_lock -#endif - bl chSchIsPreemptionRequired - cmpli cr0, %r3, 0 - beq cr0, _ivor_exit - bl chSchDoReschedule - - /* Context restore.*/ - .globl _ivor_exit -_ivor_exit: -#if CH_DBG_SYSTEM_STATE_CHECK - bl dbg_check_unlock -#endif -#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI - e_lmvgprw 32(%sp) /* Restores GPR0, GPR3...GPR12. */ - e_lmvsprw 16(%sp) /* Restores CR, LR, CTR, XER. */ - e_lmvsrrw 8(%sp) /* Restores PC, MSR. */ -#else /*!(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */ - lwz %r3, 36(%sp) /* Restores GPR3...GPR12. */ - lwz %r4, 40(%sp) - lwz %r5, 44(%sp) - lwz %r6, 48(%sp) - lwz %r7, 52(%sp) - lwz %r8, 56(%sp) - lwz %r9, 60(%sp) - lwz %r10, 64(%sp) - lwz %r11, 68(%sp) - lwz %r12, 72(%sp) - lwz %r0, 8(%sp) - mtSRR0 %r0 /* Restores PC. */ - lwz %r0, 12(%sp) - mtSRR1 %r0 /* Restores MSR. */ - lwz %r0, 16(%sp) - mtCR %r0 /* Restores CR. */ - lwz %r0, 20(%sp) - mtLR %r0 /* Restores LR. */ - lwz %r0, 24(%sp) - mtCTR %r0 /* Restores CTR. */ - lwz %r0, 28(%sp) - mtXER %r0 /* Restores XER. */ - lwz %r0, 32(%sp) /* Restores GPR0. */ -#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */ - addi %sp, %sp, 80 /* Back to the previous frame. */ - rfi - #endif /* !defined(__DOXYGEN__) */ /** @} */ diff --git a/os/ports/GCC/PPC/SPC56ELxx/port.mk b/os/ports/GCC/PPC/SPC56ELxx/port.mk index 8bd94f574..815d22ab4 100644 --- a/os/ports/GCC/PPC/SPC56ELxx/port.mk +++ b/os/ports/GCC/PPC/SPC56ELxx/port.mk @@ -3,9 +3,10 @@ PORTSRC = ${CHIBIOS}/os/ports/GCC/PPC/chcore.c PORTASM = ${CHIBIOS}/os/ports/GCC/PPC/SPC56ELxx/bam.s \ ${CHIBIOS}/os/ports/GCC/PPC/SPC56ELxx/hwconf.s \ - ${CHIBIOS}/os/ports/GCC/PPC/crt0.s \ ${CHIBIOS}/os/ports/GCC/PPC/SPC56ELxx/ivor.s \ - ${CHIBIOS}/os/ports/GCC/PPC/SPC56ELxx/vectors.s + ${CHIBIOS}/os/ports/GCC/PPC/SPC56ELxx/vectors.s \ + ${CHIBIOS}/os/ports/GCC/PPC/isr.s \ + ${CHIBIOS}/os/ports/GCC/PPC/crt0.s PORTINC = ${CHIBIOS}/os/ports/GCC/PPC \ ${CHIBIOS}/os/ports/GCC/PPC/SPC56ELxx diff --git a/os/ports/GCC/PPC/SPC56ELxx/ppcparams.h b/os/ports/GCC/PPC/SPC56ELxx/ppcparams.h index e8147ced4..c09b0b875 100644 --- a/os/ports/GCC/PPC/SPC56ELxx/ppcparams.h +++ b/os/ports/GCC/PPC/SPC56ELxx/ppcparams.h @@ -35,32 +35,37 @@ /** * @brief PPC core model. */ -#define PPC_VARIANT PPC_VARIANT_e200z4 +#define PPC_VARIANT PPC_VARIANT_e200z4 /** * @brief Number of writable bits in IVPR register. */ -#define PPC_IVPR_BITS 16 +#define PPC_IVPR_BITS 16 /** * @brief IVORx registers support. */ -#define PPC_SUPPORTS_IVORS TRUE +#define PPC_SUPPORTS_IVORS TRUE /** * @brief Book E instruction set support. */ -#define PPC_SUPPORTS_BOOKE TRUE +#define PPC_SUPPORTS_BOOKE TRUE /** * @brief VLE instruction set support. */ -#define PPC_SUPPORTS_VLE TRUE +#define PPC_SUPPORTS_VLE TRUE /** * @brief Supports VLS Load/Store Multiple Volatile instructions. */ -#define PPC_SUPPORTS_VLE_MULTI TRUE +#define PPC_SUPPORTS_VLE_MULTI TRUE + +/** + * @brief Supports the decrementer timer. + */ +#define PPC_SUPPORTS_DECREMENTER TRUE #endif /* _PPCPARAMS_H_ */ -- cgit v1.2.3