From 6443cb37d899f517ab165e56b450bb137e5e7ee1 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Sat, 2 Apr 2016 08:54:40 +0000 Subject: Finished STM32 renaming. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9210 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/STM32F1xx/adc_lld.c | 233 ------- os/hal/ports/STM32/STM32F1xx/adc_lld.h | 389 ----------- os/hal/ports/STM32/STM32F1xx/ext_lld_isr.c | 364 ---------- os/hal/ports/STM32/STM32F1xx/ext_lld_isr.h | 149 ----- os/hal/ports/STM32/STM32F1xx/hal_adc_lld.c | 233 +++++++ os/hal/ports/STM32/STM32F1xx/hal_adc_lld.h | 389 +++++++++++ os/hal/ports/STM32/STM32F1xx/hal_ext_lld_isr.c | 364 ++++++++++ os/hal/ports/STM32/STM32F1xx/hal_ext_lld_isr.h | 149 +++++ os/hal/ports/STM32/STM32F1xx/platform.mk | 72 +- os/hal/ports/STM32/STM32F1xx/platform_f105_f107.mk | 76 +-- os/hal/ports/STM32/STM32F37x/adc_lld.c | 735 --------------------- os/hal/ports/STM32/STM32F37x/adc_lld.h | 706 -------------------- os/hal/ports/STM32/STM32F37x/ext_lld_isr.c | 400 ----------- os/hal/ports/STM32/STM32F37x/ext_lld_isr.h | 163 ----- os/hal/ports/STM32/STM32F37x/hal_adc_lld.c | 735 +++++++++++++++++++++ os/hal/ports/STM32/STM32F37x/hal_adc_lld.h | 706 ++++++++++++++++++++ os/hal/ports/STM32/STM32F37x/hal_ext_lld_isr.c | 400 +++++++++++ os/hal/ports/STM32/STM32F37x/hal_ext_lld_isr.h | 163 +++++ os/hal/ports/STM32/STM32F37x/platform.mk | 68 +- os/hal/ports/STM32/STM32F3xx/ext_lld_isr.c | 459 ------------- os/hal/ports/STM32/STM32F3xx/ext_lld_isr.h | 177 ----- os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.c | 459 +++++++++++++ os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.h | 177 +++++ os/hal/ports/STM32/STM32F3xx/platform.mk | 68 +- os/hal/ports/STM32/STM32F4xx/ext_lld_isr.c | 407 ------------ os/hal/ports/STM32/STM32F4xx/ext_lld_isr.h | 170 ----- os/hal/ports/STM32/STM32F4xx/hal_ext_lld_isr.c | 407 ++++++++++++ os/hal/ports/STM32/STM32F4xx/hal_ext_lld_isr.h | 170 +++++ os/hal/ports/STM32/STM32F4xx/platform.mk | 80 +-- os/hal/ports/STM32/STM32F7xx/ext_lld_isr.c | 391 ----------- os/hal/ports/STM32/STM32F7xx/ext_lld_isr.h | 177 ----- os/hal/ports/STM32/STM32F7xx/hal_ext_lld_isr.c | 391 +++++++++++ os/hal/ports/STM32/STM32F7xx/hal_ext_lld_isr.h | 177 +++++ os/hal/ports/STM32/STM32F7xx/platform.mk | 80 +-- os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c | 283 -------- os/hal/ports/STM32/STM32L0xx/ext_lld_isr.h | 114 ---- os/hal/ports/STM32/STM32L0xx/hal_ext_lld_isr.c | 283 ++++++++ os/hal/ports/STM32/STM32L0xx/hal_ext_lld_isr.h | 114 ++++ os/hal/ports/STM32/STM32L0xx/platform.mk | 68 +- os/hal/ports/STM32/STM32L1xx/adc_lld.c | 291 -------- os/hal/ports/STM32/STM32L1xx/adc_lld.h | 494 -------------- os/hal/ports/STM32/STM32L1xx/ext_lld_isr.c | 396 ----------- os/hal/ports/STM32/STM32L1xx/ext_lld_isr.h | 170 ----- os/hal/ports/STM32/STM32L1xx/hal_adc_lld.c | 291 ++++++++ os/hal/ports/STM32/STM32L1xx/hal_adc_lld.h | 494 ++++++++++++++ os/hal/ports/STM32/STM32L1xx/hal_ext_lld_isr.c | 396 +++++++++++ os/hal/ports/STM32/STM32L1xx/hal_ext_lld_isr.h | 170 +++++ os/hal/ports/STM32/STM32L1xx/platform.mk | 64 +- os/hal/ports/STM32/STM32L4xx/ext_lld_isr.c | 361 ---------- os/hal/ports/STM32/STM32L4xx/ext_lld_isr.h | 156 ----- os/hal/ports/STM32/STM32L4xx/hal_ext_lld_isr.c | 361 ++++++++++ os/hal/ports/STM32/STM32L4xx/hal_ext_lld_isr.h | 156 +++++ os/hal/ports/STM32/STM32L4xx/platform.mk | 72 +- 53 files changed, 7509 insertions(+), 7509 deletions(-) delete mode 100644 os/hal/ports/STM32/STM32F1xx/adc_lld.c delete mode 100644 os/hal/ports/STM32/STM32F1xx/adc_lld.h delete mode 100644 os/hal/ports/STM32/STM32F1xx/ext_lld_isr.c delete mode 100644 os/hal/ports/STM32/STM32F1xx/ext_lld_isr.h create mode 100644 os/hal/ports/STM32/STM32F1xx/hal_adc_lld.c create mode 100644 os/hal/ports/STM32/STM32F1xx/hal_adc_lld.h create mode 100644 os/hal/ports/STM32/STM32F1xx/hal_ext_lld_isr.c create mode 100644 os/hal/ports/STM32/STM32F1xx/hal_ext_lld_isr.h delete mode 100644 os/hal/ports/STM32/STM32F37x/adc_lld.c delete mode 100644 os/hal/ports/STM32/STM32F37x/adc_lld.h delete mode 100644 os/hal/ports/STM32/STM32F37x/ext_lld_isr.c delete mode 100644 os/hal/ports/STM32/STM32F37x/ext_lld_isr.h create mode 100644 os/hal/ports/STM32/STM32F37x/hal_adc_lld.c create mode 100644 os/hal/ports/STM32/STM32F37x/hal_adc_lld.h create mode 100644 os/hal/ports/STM32/STM32F37x/hal_ext_lld_isr.c create mode 100644 os/hal/ports/STM32/STM32F37x/hal_ext_lld_isr.h delete mode 100644 os/hal/ports/STM32/STM32F3xx/ext_lld_isr.c delete mode 100644 os/hal/ports/STM32/STM32F3xx/ext_lld_isr.h create mode 100644 os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.c create mode 100644 os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.h delete mode 100644 os/hal/ports/STM32/STM32F4xx/ext_lld_isr.c delete mode 100644 os/hal/ports/STM32/STM32F4xx/ext_lld_isr.h create mode 100644 os/hal/ports/STM32/STM32F4xx/hal_ext_lld_isr.c create mode 100644 os/hal/ports/STM32/STM32F4xx/hal_ext_lld_isr.h delete mode 100644 os/hal/ports/STM32/STM32F7xx/ext_lld_isr.c delete mode 100644 os/hal/ports/STM32/STM32F7xx/ext_lld_isr.h create mode 100644 os/hal/ports/STM32/STM32F7xx/hal_ext_lld_isr.c create mode 100644 os/hal/ports/STM32/STM32F7xx/hal_ext_lld_isr.h delete mode 100644 os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c delete mode 100644 os/hal/ports/STM32/STM32L0xx/ext_lld_isr.h create mode 100644 os/hal/ports/STM32/STM32L0xx/hal_ext_lld_isr.c create mode 100644 os/hal/ports/STM32/STM32L0xx/hal_ext_lld_isr.h delete mode 100644 os/hal/ports/STM32/STM32L1xx/adc_lld.c delete mode 100644 os/hal/ports/STM32/STM32L1xx/adc_lld.h delete mode 100644 os/hal/ports/STM32/STM32L1xx/ext_lld_isr.c delete mode 100644 os/hal/ports/STM32/STM32L1xx/ext_lld_isr.h create mode 100644 os/hal/ports/STM32/STM32L1xx/hal_adc_lld.c create mode 100644 os/hal/ports/STM32/STM32L1xx/hal_adc_lld.h create mode 100644 os/hal/ports/STM32/STM32L1xx/hal_ext_lld_isr.c create mode 100644 os/hal/ports/STM32/STM32L1xx/hal_ext_lld_isr.h delete mode 100644 os/hal/ports/STM32/STM32L4xx/ext_lld_isr.c delete mode 100644 os/hal/ports/STM32/STM32L4xx/ext_lld_isr.h create mode 100644 os/hal/ports/STM32/STM32L4xx/hal_ext_lld_isr.c create mode 100644 os/hal/ports/STM32/STM32L4xx/hal_ext_lld_isr.h (limited to 'os') diff --git a/os/hal/ports/STM32/STM32F1xx/adc_lld.c b/os/hal/ports/STM32/STM32F1xx/adc_lld.c deleted file mode 100644 index fc04e2f48..000000000 --- a/os/hal/ports/STM32/STM32F1xx/adc_lld.c +++ /dev/null @@ -1,233 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F1xx/adc_lld.c - * @brief STM32F1xx ADC subsystem low level driver source. - * - * @addtogroup ADC - * @{ - */ - -#include "hal.h" - -#if HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief ADC1 driver identifier.*/ -#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) -ADCDriver ADCD1; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Shared ADC DMA ISR service routine. - * - * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { - - /* DMA errors handling.*/ - if ((flags & STM32_DMA_ISR_TEIF) != 0) { - /* DMA, this could help only if the DMA tries to access an unmapped - address space or violates alignment rules.*/ - _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); - } - else { - if ((flags & STM32_DMA_ISR_TCIF) != 0) { - /* Transfer complete processing.*/ - _adc_isr_full_code(adcp); - } - else if ((flags & STM32_DMA_ISR_HTIF) != 0) { - /* Half transfer processing.*/ - _adc_isr_half_code(adcp); - } - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level ADC driver initialization. - * - * @notapi - */ -void adc_lld_init(void) { - -#if STM32_ADC_USE_ADC1 - /* Driver initialization.*/ - adcObjectInit(&ADCD1); - ADCD1.adc = ADC1; - ADCD1.dmastp = STM32_DMA1_STREAM1; - ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | - STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | - STM32_DMA_CR_TEIE; - - /* Temporary activation.*/ - rccEnableADC1(FALSE); - ADC1->CR1 = 0; - ADC1->CR2 = ADC_CR2_ADON; - - /* Reset calibration just to be safe.*/ - ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL; - while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0) - ; - - /* Calibration.*/ - ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL; - while ((ADC1->CR2 & ADC_CR2_CAL) != 0) - ; - - /* Return the ADC in low power mode.*/ - ADC1->CR2 = 0; - rccDisableADC1(FALSE); -#endif -} - -/** - * @brief Configures and activates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_start(ADCDriver *adcp) { - - /* If in stopped state then enables the ADC and DMA clocks.*/ - if (adcp->state == ADC_STOP) { -#if STM32_ADC_USE_ADC1 - if (&ADCD1 == adcp) { - bool b; - b = dmaStreamAllocate(adcp->dmastp, - STM32_ADC_ADC1_IRQ_PRIORITY, - (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, - (void *)adcp); - osalDbgAssert(!b, "stream already allocated"); - dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); - rccEnableADC1(FALSE); - } -#endif - - /* ADC setup, the calibration procedure has already been performed - during initialization.*/ - adcp->adc->CR1 = 0; - adcp->adc->CR2 = 0; - } -} - -/** - * @brief Deactivates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_stop(ADCDriver *adcp) { - - /* If in ready state then disables the ADC clock.*/ - if (adcp->state == ADC_READY) { -#if STM32_ADC_USE_ADC1 - if (&ADCD1 == adcp) { - ADC1->CR1 = 0; - ADC1->CR2 = 0; - dmaStreamRelease(adcp->dmastp); - rccDisableADC1(FALSE); - } -#endif - } -} - -/** - * @brief Starts an ADC conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_start_conversion(ADCDriver *adcp) { - uint32_t mode, cr2; - const ADCConversionGroup *grpp = adcp->grpp; - - /* DMA setup.*/ - mode = adcp->dmamode; - if (grpp->circular) { - mode |= STM32_DMA_CR_CIRC; - if (adcp->depth > 1) { - /* If circular buffer depth > 1, then the half transfer interrupt - is enabled in order to allow streaming processing.*/ - mode |= STM32_DMA_CR_HTIE; - } - } - dmaStreamSetMemory0(adcp->dmastp, adcp->samples); - dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels * - (uint32_t)adcp->depth); - dmaStreamSetMode(adcp->dmastp, mode); - dmaStreamEnable(adcp->dmastp); - - /* ADC setup.*/ - adcp->adc->CR1 = grpp->cr1 | ADC_CR1_SCAN; - cr2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_ADON; - if ((cr2 & (ADC_CR2_EXTTRIG | ADC_CR2_JEXTTRIG)) == 0) - cr2 |= ADC_CR2_CONT; - adcp->adc->CR2 = grpp->cr2 | cr2; - adcp->adc->SMPR1 = grpp->smpr1; - adcp->adc->SMPR2 = grpp->smpr2; - adcp->adc->SQR1 = grpp->sqr1; - adcp->adc->SQR2 = grpp->sqr2; - adcp->adc->SQR3 = grpp->sqr3; - - /* ADC start by writing ADC_CR2_ADON a second time.*/ - adcp->adc->CR2 = cr2; -} - -/** - * @brief Stops an ongoing conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_stop_conversion(ADCDriver *adcp) { - - dmaStreamDisable(adcp->dmastp); - adcp->adc->CR2 = 0; -} - -#endif /* HAL_USE_ADC */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32F1xx/adc_lld.h b/os/hal/ports/STM32/STM32F1xx/adc_lld.h deleted file mode 100644 index 6e8f3c4e5..000000000 --- a/os/hal/ports/STM32/STM32F1xx/adc_lld.h +++ /dev/null @@ -1,389 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F1xx/adc_lld.h - * @brief STM32F1xx ADC subsystem low level driver header. - * - * @addtogroup ADC - * @{ - */ - -#ifndef _ADC_LLD_H_ -#define _ADC_LLD_H_ - -#if HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Triggers selection - * @{ - */ -#define ADC_CR2_EXTSEL_SRC(n) ((n) << 17) /**< @brief Trigger source. */ -#define ADC_CR2_EXTSEL_SWSTART (7 << 17) /**< @brief Software trigger. */ -/** @} */ - -/** - * @name Available analog channels - * @{ - */ -#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ -#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ -#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ -#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ -#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ -#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ -#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ -#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ -#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ -#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ -#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ -#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ -#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ -#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ -#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ -#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ -#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/ -#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */ -/** @} */ - -/** - * @name Sampling rates - * @{ - */ -#define ADC_SAMPLE_1P5 0 /**< @brief 1.5 cycles sampling time. */ -#define ADC_SAMPLE_7P5 1 /**< @brief 7.5 cycles sampling time. */ -#define ADC_SAMPLE_13P5 2 /**< @brief 13.5 cycles sampling time. */ -#define ADC_SAMPLE_28P5 3 /**< @brief 28.5 cycles sampling time. */ -#define ADC_SAMPLE_41P5 4 /**< @brief 41.5 cycles sampling time. */ -#define ADC_SAMPLE_55P5 5 /**< @brief 55.5 cycles sampling time. */ -#define ADC_SAMPLE_71P5 6 /**< @brief 71.5 cycles sampling time. */ -#define ADC_SAMPLE_239P5 7 /**< @brief 239.5 cycles sampling time. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief ADC1 driver enable switch. - * @details If set to @p TRUE the support for ADC1 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) -#define STM32_ADC_USE_ADC1 FALSE -#endif - -/** - * @brief ADC1 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#endif - -/** - * @brief ADC1 interrupt priority level setting. - */ -#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 -#error "ADC1 not present in the selected device" -#endif - -#if !STM32_ADC_USE_ADC1 -#error "ADC driver activated but no ADC peripheral assigned" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief ADC sample data type. - */ -typedef uint16_t adcsample_t; - -/** - * @brief Channels number in a conversion group. - */ -typedef uint16_t adc_channels_num_t; - -/** - * @brief Possible ADC failure causes. - * @note Error codes are architecture dependent and should not relied - * upon. - */ -typedef enum { - ADC_ERR_DMAFAILURE = 0 /**< DMA operations failure. */ -} adcerror_t; - -/** - * @brief Type of a structure representing an ADC driver. - */ -typedef struct ADCDriver ADCDriver; - -/** - * @brief ADC notification callback type. - * - * @param[in] adcp pointer to the @p ADCDriver object triggering the - * callback - * @param[in] buffer pointer to the most recent samples data - * @param[in] n number of buffer rows available starting from @p buffer - */ -typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); - -/** - * @brief ADC error callback type. - * - * @param[in] adcp pointer to the @p ADCDriver object triggering the - * callback - * @param[in] err ADC error code - */ -typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); - -/** - * @brief Conversion group configuration structure. - * @details This implementation-dependent structure describes a conversion - * operation. - * @note The use of this configuration structure requires knowledge of - * STM32 ADC cell registers interface, please refer to the STM32 - * reference manual for details. - */ -typedef struct { - /** - * @brief Enables the circular buffer mode for the group. - */ - bool circular; - /** - * @brief Number of the analog channels belonging to the conversion group. - */ - adc_channels_num_t num_channels; - /** - * @brief Callback function associated to the group or @p NULL. - */ - adccallback_t end_cb; - /** - * @brief Error callback or @p NULL. - */ - adcerrorcallback_t error_cb; - /* End of the mandatory fields.*/ - /** - * @brief ADC CR1 register initialization data. - * @note All the required bits must be defined into this field except - * @p ADC_CR1_SCAN that is enforced inside the driver. - */ - uint32_t cr1; - /** - * @brief ADC CR2 register initialization data. - * @note All the required bits must be defined into this field except - * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are - * enforced inside the driver. - */ - uint32_t cr2; - /** - * @brief ADC SMPR1 register initialization data. - * @details In this field must be specified the sample times for channels - * 10...17. - */ - uint32_t smpr1; - /** - * @brief ADC SMPR2 register initialization data. - * @details In this field must be specified the sample times for channels - * 0...9. - */ - uint32_t smpr2; - /** - * @brief ADC SQR1 register initialization data. - * @details Conversion group sequence 13...16 + sequence length. - */ - uint32_t sqr1; - /** - * @brief ADC SQR2 register initialization data. - * @details Conversion group sequence 7...12. - */ - uint32_t sqr2; - /** - * @brief ADC SQR3 register initialization data. - * @details Conversion group sequence 1...6. - */ - uint32_t sqr3; -} ADCConversionGroup; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - uint32_t dummy; -} ADCConfig; - -/** - * @brief Structure representing an ADC driver. - */ -struct ADCDriver { - /** - * @brief Driver state. - */ - adcstate_t state; - /** - * @brief Current configuration data. - */ - const ADCConfig *config; - /** - * @brief Current samples buffer pointer or @p NULL. - */ - adcsample_t *samples; - /** - * @brief Current samples buffer depth or @p 0. - */ - size_t depth; - /** - * @brief Current conversion group pointer or @p NULL. - */ - const ADCConversionGroup *grpp; -#if ADC_USE_WAIT || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - thread_reference_t thread; -#endif -#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the peripheral. - */ - mutex_t mutex; -#endif /* ADC_USE_MUTUAL_EXCLUSION */ -#if defined(ADC_DRIVER_EXT_FIELDS) - ADC_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the ADCx registers block. - */ - ADC_TypeDef *adc; - /** - * @brief Pointer to associated DMA channel. - */ - const stm32_dma_stream_t *dmastp; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Sequences building helper macros - * @{ - */ -/** - * @brief Number of channels in a conversion sequence. - */ -#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20) - -#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ -#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ -#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ -#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ -#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ -#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ - -#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ -#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ -#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ -#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ -#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ -#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ - -#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ -#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ -#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ -#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ -/** @} */ - -/** - * @name Sampling rate settings helper macros - * @{ - */ -#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ -#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ -#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ -#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ -#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ -#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ -#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ -#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ -#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ -#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ - -#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ -#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ -#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ -#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ -#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ -#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ -#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor - sampling time. */ -#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference - sampling time. */ -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) -extern ADCDriver ADCD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void adc_lld_init(void); - void adc_lld_start(ADCDriver *adcp); - void adc_lld_stop(ADCDriver *adcp); - void adc_lld_start_conversion(ADCDriver *adcp); - void adc_lld_stop_conversion(ADCDriver *adcp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_ADC */ - -#endif /* _ADC_LLD_H_ */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32F1xx/ext_lld_isr.c b/os/hal/ports/STM32/STM32F1xx/ext_lld_isr.c deleted file mode 100644 index 7dd0fbf19..000000000 --- a/os/hal/ports/STM32/STM32F1xx/ext_lld_isr.c +++ /dev/null @@ -1,364 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F1xx/ext_lld_isr.c - * @brief STM32F1xx EXT subsystem low level driver ISR code. - * - * @addtogroup EXT - * @{ - */ - -#include "hal.h" - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -#include "ext_lld_isr.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief EXTI[0] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector58) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 0); - EXTI->PR = pr; - if (pr & (1U << 0)) - EXTD1.config->channels[0].cb(&EXTD1, 0); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[1] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector5C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 1); - EXTI->PR = pr; - if (pr & (1U << 1)) - EXTD1.config->channels[1].cb(&EXTD1, 1); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[2] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector60) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 2); - EXTI->PR = pr; - if (pr & (1U << 2)) - EXTD1.config->channels[2].cb(&EXTD1, 2); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[3] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector64) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 3); - EXTI->PR = pr; - if (pr & (1U << 3)) - EXTD1.config->channels[3].cb(&EXTD1, 3); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[4] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector68) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 4); - EXTI->PR = pr; - if (pr & (1U << 4)) - EXTD1.config->channels[4].cb(&EXTD1, 4); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[5]...EXTI[9] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector9C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9)); - EXTI->PR = pr; - if (pr & (1U << 5)) - EXTD1.config->channels[5].cb(&EXTD1, 5); - if (pr & (1U << 6)) - EXTD1.config->channels[6].cb(&EXTD1, 6); - if (pr & (1U << 7)) - EXTD1.config->channels[7].cb(&EXTD1, 7); - if (pr & (1U << 8)) - EXTD1.config->channels[8].cb(&EXTD1, 8); - if (pr & (1U << 9)) - EXTD1.config->channels[9].cb(&EXTD1, 9); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[10]...EXTI[15] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorE0) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) | (1U << 14) | - (1U << 15)); - EXTI->PR = pr; - if (pr & (1U << 10)) - EXTD1.config->channels[10].cb(&EXTD1, 10); - if (pr & (1U << 11)) - EXTD1.config->channels[11].cb(&EXTD1, 11); - if (pr & (1U << 12)) - EXTD1.config->channels[12].cb(&EXTD1, 12); - if (pr & (1U << 13)) - EXTD1.config->channels[13].cb(&EXTD1, 13); - if (pr & (1U << 14)) - EXTD1.config->channels[14].cb(&EXTD1, 14); - if (pr & (1U << 15)) - EXTD1.config->channels[15].cb(&EXTD1, 15); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[16] interrupt handler (PVD). - * - * @isr - */ -OSAL_IRQ_HANDLER(Veector44) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 16); - EXTI->PR = pr; - if (pr & (1U << 16)) - EXTD1.config->channels[16].cb(&EXTD1, 16); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[17] interrupt handler (RTC). - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorE4) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 17); - EXTI->PR = pr; - if (pr & (1U << 17)) - EXTD1.config->channels[17].cb(&EXTD1, 17); - - OSAL_IRQ_EPILOGUE(); -} - -#if defined(STM32F10X_CL) -/** - * @brief EXTI[18] interrupt handler (OTG_FS_WKUP). - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorE8) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 18); - EXTI->PR = pr; - if (pr & (1U << 18)) - EXTD1.config->channels[18].cb(&EXTD1, 18); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[19] interrupt handler (ETH_WKUP). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector138) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 19); - EXTI->PR = pr; - if (pr & (1U << 19)) - EXTD1.config->channels[19].cb(&EXTD1, 19); - - OSAL_IRQ_EPILOGUE(); -} -#elif defined(STM32F10X_MD_VL) || defined(STM32F10X_HD_VL) - -#else /* Other STM32F1xx devices.*/ -/** - * @brief EXTI[18] interrupt handler (USB_FS_WKUP). - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorE8) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 18); - EXTI->PR = pr; - if (pr & (1U << 18)) - EXTD1.config->channels[18].cb(&EXTD1, 18); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Enables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_enable(void) { - - nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY); - nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY); - nvicEnableVector(EXTI2_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY); - nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY); - nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY); - nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY); - nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY); - nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY); - nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY); -#if defined(STM32F10X_CL) - /* EXTI vectors specific to STM32F1xx Connectivity Line.*/ - nvicEnableVector(OTG_FS_WKUP_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY); - nvicEnableVector(ETH_WKUP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY); -#elif defined(STM32F10X_MD_VL) || defined(STM32F10X_HD_VL) - /* EXTI vectors specific to STM32F1xx Value Line.*/ -#else - /* EXTI vectors specific to STM32F1xx except Connectivity Line.*/ - nvicEnableVector(USBWakeUp_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY); -#endif -} - -/** - * @brief Disables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_disable(void) { - - nvicDisableVector(EXTI0_IRQn); - nvicDisableVector(EXTI1_IRQn); - nvicDisableVector(EXTI2_IRQn); - nvicDisableVector(EXTI3_IRQn); - nvicDisableVector(EXTI4_IRQn); - nvicDisableVector(EXTI9_5_IRQn); - nvicDisableVector(EXTI15_10_IRQn); - nvicDisableVector(PVD_IRQn); - nvicDisableVector(RTC_Alarm_IRQn); -#if defined(STM32F10X_CL) - /* EXTI vectors specific to STM32F1xx Connectivity Line.*/ - nvicDisableVector(OTG_FS_WKUP_IRQn); - nvicDisableVector(ETH_WKUP_IRQn); -#elif defined(STM32F10X_MD_VL) || defined(STM32F10X_HD_VL) - /* EXTI vectors specific to STM32F1xx Value Line.*/ -#else - /* EXTI vectors specific to STM32F1xx except Connectivity Line.*/ - nvicDisableVector(USBWakeUp_IRQn); -#endif -} - -#endif /* HAL_USE_EXT */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32F1xx/ext_lld_isr.h b/os/hal/ports/STM32/STM32F1xx/ext_lld_isr.h deleted file mode 100644 index 839228222..000000000 --- a/os/hal/ports/STM32/STM32F1xx/ext_lld_isr.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F1xx/ext_lld_isr.h - * @brief STM32F1xx EXT subsystem low level driver ISR header. - * - * @addtogroup EXT - * @{ - */ - -#ifndef _EXT_LLD_ISR_H_ -#define _EXT_LLD_ISR_H_ - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief EXTI0 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI1 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI2 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI3 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI4 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI9..5 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI15..10 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI16 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI17 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI18 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI19 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void ext_lld_exti_irq_enable(void); - void ext_lld_exti_irq_disable(void); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EXT */ - -#endif /* _EXT_LLD_ISR_H_ */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.c b/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.c new file mode 100644 index 000000000..fc04e2f48 --- /dev/null +++ b/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.c @@ -0,0 +1,233 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F1xx/adc_lld.c + * @brief STM32F1xx ADC subsystem low level driver source. + * + * @addtogroup ADC + * @{ + */ + +#include "hal.h" + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief ADC1 driver identifier.*/ +#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) +ADCDriver ADCD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Shared ADC DMA ISR service routine. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { + + /* DMA errors handling.*/ + if ((flags & STM32_DMA_ISR_TEIF) != 0) { + /* DMA, this could help only if the DMA tries to access an unmapped + address space or violates alignment rules.*/ + _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); + } + else { + if ((flags & STM32_DMA_ISR_TCIF) != 0) { + /* Transfer complete processing.*/ + _adc_isr_full_code(adcp); + } + else if ((flags & STM32_DMA_ISR_HTIF) != 0) { + /* Half transfer processing.*/ + _adc_isr_half_code(adcp); + } + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ADC driver initialization. + * + * @notapi + */ +void adc_lld_init(void) { + +#if STM32_ADC_USE_ADC1 + /* Driver initialization.*/ + adcObjectInit(&ADCD1); + ADCD1.adc = ADC1; + ADCD1.dmastp = STM32_DMA1_STREAM1; + ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_TEIE; + + /* Temporary activation.*/ + rccEnableADC1(FALSE); + ADC1->CR1 = 0; + ADC1->CR2 = ADC_CR2_ADON; + + /* Reset calibration just to be safe.*/ + ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL; + while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0) + ; + + /* Calibration.*/ + ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL; + while ((ADC1->CR2 & ADC_CR2_CAL) != 0) + ; + + /* Return the ADC in low power mode.*/ + ADC1->CR2 = 0; + rccDisableADC1(FALSE); +#endif +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) { + + /* If in stopped state then enables the ADC and DMA clocks.*/ + if (adcp->state == ADC_STOP) { +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + bool b; + b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_ADC1_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, + (void *)adcp); + osalDbgAssert(!b, "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); + rccEnableADC1(FALSE); + } +#endif + + /* ADC setup, the calibration procedure has already been performed + during initialization.*/ + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + } +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) { + + /* If in ready state then disables the ADC clock.*/ + if (adcp->state == ADC_READY) { +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + ADC1->CR1 = 0; + ADC1->CR2 = 0; + dmaStreamRelease(adcp->dmastp); + rccDisableADC1(FALSE); + } +#endif + } +} + +/** + * @brief Starts an ADC conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) { + uint32_t mode, cr2; + const ADCConversionGroup *grpp = adcp->grpp; + + /* DMA setup.*/ + mode = adcp->dmamode; + if (grpp->circular) { + mode |= STM32_DMA_CR_CIRC; + if (adcp->depth > 1) { + /* If circular buffer depth > 1, then the half transfer interrupt + is enabled in order to allow streaming processing.*/ + mode |= STM32_DMA_CR_HTIE; + } + } + dmaStreamSetMemory0(adcp->dmastp, adcp->samples); + dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels * + (uint32_t)adcp->depth); + dmaStreamSetMode(adcp->dmastp, mode); + dmaStreamEnable(adcp->dmastp); + + /* ADC setup.*/ + adcp->adc->CR1 = grpp->cr1 | ADC_CR1_SCAN; + cr2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_ADON; + if ((cr2 & (ADC_CR2_EXTTRIG | ADC_CR2_JEXTTRIG)) == 0) + cr2 |= ADC_CR2_CONT; + adcp->adc->CR2 = grpp->cr2 | cr2; + adcp->adc->SMPR1 = grpp->smpr1; + adcp->adc->SMPR2 = grpp->smpr2; + adcp->adc->SQR1 = grpp->sqr1; + adcp->adc->SQR2 = grpp->sqr2; + adcp->adc->SQR3 = grpp->sqr3; + + /* ADC start by writing ADC_CR2_ADON a second time.*/ + adcp->adc->CR2 = cr2; +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) { + + dmaStreamDisable(adcp->dmastp); + adcp->adc->CR2 = 0; +} + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.h b/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.h new file mode 100644 index 000000000..6e8f3c4e5 --- /dev/null +++ b/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.h @@ -0,0 +1,389 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F1xx/adc_lld.h + * @brief STM32F1xx ADC subsystem low level driver header. + * + * @addtogroup ADC + * @{ + */ + +#ifndef _ADC_LLD_H_ +#define _ADC_LLD_H_ + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Triggers selection + * @{ + */ +#define ADC_CR2_EXTSEL_SRC(n) ((n) << 17) /**< @brief Trigger source. */ +#define ADC_CR2_EXTSEL_SWSTART (7 << 17) /**< @brief Software trigger. */ +/** @} */ + +/** + * @name Available analog channels + * @{ + */ +#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ +#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ +#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ +#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ +#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ +#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ +#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ +#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ +#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ +#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ +#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ +#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ +#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ +#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ +#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ +#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ +#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/ +#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */ +/** @} */ + +/** + * @name Sampling rates + * @{ + */ +#define ADC_SAMPLE_1P5 0 /**< @brief 1.5 cycles sampling time. */ +#define ADC_SAMPLE_7P5 1 /**< @brief 7.5 cycles sampling time. */ +#define ADC_SAMPLE_13P5 2 /**< @brief 13.5 cycles sampling time. */ +#define ADC_SAMPLE_28P5 3 /**< @brief 28.5 cycles sampling time. */ +#define ADC_SAMPLE_41P5 4 /**< @brief 41.5 cycles sampling time. */ +#define ADC_SAMPLE_55P5 5 /**< @brief 55.5 cycles sampling time. */ +#define ADC_SAMPLE_71P5 6 /**< @brief 71.5 cycles sampling time. */ +#define ADC_SAMPLE_239P5 7 /**< @brief 239.5 cycles sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ADC1 driver enable switch. + * @details If set to @p TRUE the support for ADC1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) +#define STM32_ADC_USE_ADC1 FALSE +#endif + +/** + * @brief ADC1 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC1 interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 +#error "ADC1 not present in the selected device" +#endif + +#if !STM32_ADC_USE_ADC1 +#error "ADC driver activated but no ADC peripheral assigned" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ADC sample data type. + */ +typedef uint16_t adcsample_t; + +/** + * @brief Channels number in a conversion group. + */ +typedef uint16_t adc_channels_num_t; + +/** + * @brief Possible ADC failure causes. + * @note Error codes are architecture dependent and should not relied + * upon. + */ +typedef enum { + ADC_ERR_DMAFAILURE = 0 /**< DMA operations failure. */ +} adcerror_t; + +/** + * @brief Type of a structure representing an ADC driver. + */ +typedef struct ADCDriver ADCDriver; + +/** + * @brief ADC notification callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] buffer pointer to the most recent samples data + * @param[in] n number of buffer rows available starting from @p buffer + */ +typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); + +/** + * @brief ADC error callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] err ADC error code + */ +typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); + +/** + * @brief Conversion group configuration structure. + * @details This implementation-dependent structure describes a conversion + * operation. + * @note The use of this configuration structure requires knowledge of + * STM32 ADC cell registers interface, please refer to the STM32 + * reference manual for details. + */ +typedef struct { + /** + * @brief Enables the circular buffer mode for the group. + */ + bool circular; + /** + * @brief Number of the analog channels belonging to the conversion group. + */ + adc_channels_num_t num_channels; + /** + * @brief Callback function associated to the group or @p NULL. + */ + adccallback_t end_cb; + /** + * @brief Error callback or @p NULL. + */ + adcerrorcallback_t error_cb; + /* End of the mandatory fields.*/ + /** + * @brief ADC CR1 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR1_SCAN that is enforced inside the driver. + */ + uint32_t cr1; + /** + * @brief ADC CR2 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are + * enforced inside the driver. + */ + uint32_t cr2; + /** + * @brief ADC SMPR1 register initialization data. + * @details In this field must be specified the sample times for channels + * 10...17. + */ + uint32_t smpr1; + /** + * @brief ADC SMPR2 register initialization data. + * @details In this field must be specified the sample times for channels + * 0...9. + */ + uint32_t smpr2; + /** + * @brief ADC SQR1 register initialization data. + * @details Conversion group sequence 13...16 + sequence length. + */ + uint32_t sqr1; + /** + * @brief ADC SQR2 register initialization data. + * @details Conversion group sequence 7...12. + */ + uint32_t sqr2; + /** + * @brief ADC SQR3 register initialization data. + * @details Conversion group sequence 1...6. + */ + uint32_t sqr3; +} ADCConversionGroup; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + uint32_t dummy; +} ADCConfig; + +/** + * @brief Structure representing an ADC driver. + */ +struct ADCDriver { + /** + * @brief Driver state. + */ + adcstate_t state; + /** + * @brief Current configuration data. + */ + const ADCConfig *config; + /** + * @brief Current samples buffer pointer or @p NULL. + */ + adcsample_t *samples; + /** + * @brief Current samples buffer depth or @p 0. + */ + size_t depth; + /** + * @brief Current conversion group pointer or @p NULL. + */ + const ADCConversionGroup *grpp; +#if ADC_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + thread_reference_t thread; +#endif +#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + mutex_t mutex; +#endif /* ADC_USE_MUTUAL_EXCLUSION */ +#if defined(ADC_DRIVER_EXT_FIELDS) + ADC_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the ADCx registers block. + */ + ADC_TypeDef *adc; + /** + * @brief Pointer to associated DMA channel. + */ + const stm32_dma_stream_t *dmastp; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Sequences building helper macros + * @{ + */ +/** + * @brief Number of channels in a conversion sequence. + */ +#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20) + +#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ +#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ +#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ +#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ +#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ +#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ + +#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ +#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ +#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ +#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ +#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ +#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ + +#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ +#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ +#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ +#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ +/** @} */ + +/** + * @name Sampling rate settings helper macros + * @{ + */ +#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ +#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ +#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ +#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ +#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ +#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ +#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ +#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ +#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ +#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ + +#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ +#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ +#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ +#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ +#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ +#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ +#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor + sampling time. */ +#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference + sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) +extern ADCDriver ADCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void adc_lld_init(void); + void adc_lld_start(ADCDriver *adcp); + void adc_lld_stop(ADCDriver *adcp); + void adc_lld_start_conversion(ADCDriver *adcp); + void adc_lld_stop_conversion(ADCDriver *adcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC */ + +#endif /* _ADC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32F1xx/hal_ext_lld_isr.c b/os/hal/ports/STM32/STM32F1xx/hal_ext_lld_isr.c new file mode 100644 index 000000000..12e360cd5 --- /dev/null +++ b/os/hal/ports/STM32/STM32F1xx/hal_ext_lld_isr.c @@ -0,0 +1,364 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F1xx/ext_lld_isr.c + * @brief STM32F1xx EXT subsystem low level driver ISR code. + * + * @addtogroup EXT + * @{ + */ + +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +#include "hal_ext_lld_isr.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief EXTI[0] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector58) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 0); + EXTI->PR = pr; + if (pr & (1U << 0)) + EXTD1.config->channels[0].cb(&EXTD1, 0); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[1] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector5C) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 1); + EXTI->PR = pr; + if (pr & (1U << 1)) + EXTD1.config->channels[1].cb(&EXTD1, 1); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[2] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector60) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 2); + EXTI->PR = pr; + if (pr & (1U << 2)) + EXTD1.config->channels[2].cb(&EXTD1, 2); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[3] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector64) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 3); + EXTI->PR = pr; + if (pr & (1U << 3)) + EXTD1.config->channels[3].cb(&EXTD1, 3); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[4] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector68) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 4); + EXTI->PR = pr; + if (pr & (1U << 4)) + EXTD1.config->channels[4].cb(&EXTD1, 4); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[5]...EXTI[9] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector9C) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9)); + EXTI->PR = pr; + if (pr & (1U << 5)) + EXTD1.config->channels[5].cb(&EXTD1, 5); + if (pr & (1U << 6)) + EXTD1.config->channels[6].cb(&EXTD1, 6); + if (pr & (1U << 7)) + EXTD1.config->channels[7].cb(&EXTD1, 7); + if (pr & (1U << 8)) + EXTD1.config->channels[8].cb(&EXTD1, 8); + if (pr & (1U << 9)) + EXTD1.config->channels[9].cb(&EXTD1, 9); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[10]...EXTI[15] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(VectorE0) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) | (1U << 14) | + (1U << 15)); + EXTI->PR = pr; + if (pr & (1U << 10)) + EXTD1.config->channels[10].cb(&EXTD1, 10); + if (pr & (1U << 11)) + EXTD1.config->channels[11].cb(&EXTD1, 11); + if (pr & (1U << 12)) + EXTD1.config->channels[12].cb(&EXTD1, 12); + if (pr & (1U << 13)) + EXTD1.config->channels[13].cb(&EXTD1, 13); + if (pr & (1U << 14)) + EXTD1.config->channels[14].cb(&EXTD1, 14); + if (pr & (1U << 15)) + EXTD1.config->channels[15].cb(&EXTD1, 15); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[16] interrupt handler (PVD). + * + * @isr + */ +OSAL_IRQ_HANDLER(Veector44) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 16); + EXTI->PR = pr; + if (pr & (1U << 16)) + EXTD1.config->channels[16].cb(&EXTD1, 16); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[17] interrupt handler (RTC). + * + * @isr + */ +OSAL_IRQ_HANDLER(VectorE4) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 17); + EXTI->PR = pr; + if (pr & (1U << 17)) + EXTD1.config->channels[17].cb(&EXTD1, 17); + + OSAL_IRQ_EPILOGUE(); +} + +#if defined(STM32F10X_CL) +/** + * @brief EXTI[18] interrupt handler (OTG_FS_WKUP). + * + * @isr + */ +OSAL_IRQ_HANDLER(VectorE8) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 18); + EXTI->PR = pr; + if (pr & (1U << 18)) + EXTD1.config->channels[18].cb(&EXTD1, 18); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[19] interrupt handler (ETH_WKUP). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector138) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 19); + EXTI->PR = pr; + if (pr & (1U << 19)) + EXTD1.config->channels[19].cb(&EXTD1, 19); + + OSAL_IRQ_EPILOGUE(); +} +#elif defined(STM32F10X_MD_VL) || defined(STM32F10X_HD_VL) + +#else /* Other STM32F1xx devices.*/ +/** + * @brief EXTI[18] interrupt handler (USB_FS_WKUP). + * + * @isr + */ +OSAL_IRQ_HANDLER(VectorE8) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 18); + EXTI->PR = pr; + if (pr & (1U << 18)) + EXTD1.config->channels[18].cb(&EXTD1, 18); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_enable(void) { + + nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY); + nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY); + nvicEnableVector(EXTI2_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY); + nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY); + nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY); + nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY); + nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY); + nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY); + nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY); +#if defined(STM32F10X_CL) + /* EXTI vectors specific to STM32F1xx Connectivity Line.*/ + nvicEnableVector(OTG_FS_WKUP_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY); + nvicEnableVector(ETH_WKUP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY); +#elif defined(STM32F10X_MD_VL) || defined(STM32F10X_HD_VL) + /* EXTI vectors specific to STM32F1xx Value Line.*/ +#else + /* EXTI vectors specific to STM32F1xx except Connectivity Line.*/ + nvicEnableVector(USBWakeUp_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY); +#endif +} + +/** + * @brief Disables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_disable(void) { + + nvicDisableVector(EXTI0_IRQn); + nvicDisableVector(EXTI1_IRQn); + nvicDisableVector(EXTI2_IRQn); + nvicDisableVector(EXTI3_IRQn); + nvicDisableVector(EXTI4_IRQn); + nvicDisableVector(EXTI9_5_IRQn); + nvicDisableVector(EXTI15_10_IRQn); + nvicDisableVector(PVD_IRQn); + nvicDisableVector(RTC_Alarm_IRQn); +#if defined(STM32F10X_CL) + /* EXTI vectors specific to STM32F1xx Connectivity Line.*/ + nvicDisableVector(OTG_FS_WKUP_IRQn); + nvicDisableVector(ETH_WKUP_IRQn); +#elif defined(STM32F10X_MD_VL) || defined(STM32F10X_HD_VL) + /* EXTI vectors specific to STM32F1xx Value Line.*/ +#else + /* EXTI vectors specific to STM32F1xx except Connectivity Line.*/ + nvicDisableVector(USBWakeUp_IRQn); +#endif +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32F1xx/hal_ext_lld_isr.h b/os/hal/ports/STM32/STM32F1xx/hal_ext_lld_isr.h new file mode 100644 index 000000000..839228222 --- /dev/null +++ b/os/hal/ports/STM32/STM32F1xx/hal_ext_lld_isr.h @@ -0,0 +1,149 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F1xx/ext_lld_isr.h + * @brief STM32F1xx EXT subsystem low level driver ISR header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_ISR_H_ +#define _EXT_LLD_ISR_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief EXTI0 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI1 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI2 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI3 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI4 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI9..5 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI15..10 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI16 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI17 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI18 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI19 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_exti_irq_enable(void); + void ext_lld_exti_irq_disable(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_ISR_H_ */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32F1xx/platform.mk b/os/hal/ports/STM32/STM32F1xx/platform.mk index f1d136fc3..ea64e57d5 100644 --- a/os/hal/ports/STM32/STM32F1xx/platform.mk +++ b/os/hal/ports/STM32/STM32F1xx/platform.mk @@ -5,78 +5,78 @@ HALCONF := $(strip $(shell cat halconf.h | egrep -e "define")) PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/hal_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/adc_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.c endif ifneq ($(findstring HAL_USE_CAN TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c endif ifneq ($(findstring HAL_USE_DAC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c endif ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/ext_lld_isr.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/hal_ext_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/hal_ext_lld_isr.c endif ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv1/pal_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c endif ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c endif ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv1/rtc_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv1/hal_rtc_lld.c endif ifneq ($(findstring HAL_USE_SDC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SDIOv1/sdc_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.c endif ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/spi_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/hal_spi_lld.c endif ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c endif ifneq ($(findstring HAL_USE_ICU TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c endif ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c endif ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/serial_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/hal_serial_lld.c endif ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/uart_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c endif ifneq ($(findstring HAL_USE_USB TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/usb_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c endif ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c endif else PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/hal_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/adc_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/ext_lld_isr.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/hal_ext_lld_isr.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv1/pal_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv1/rtc_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/SDIOv1/sdc_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/spi_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/serial_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/uart_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/usb_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.c + $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/hal_ext_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv1/hal_rtc_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/hal_spi_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/hal_serial_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c endif # Required include directories diff --git a/os/hal/ports/STM32/STM32F1xx/platform_f105_f107.mk b/os/hal/ports/STM32/STM32F1xx/platform_f105_f107.mk index 1b84d99fb..7f26f33c3 100644 --- a/os/hal/ports/STM32/STM32F1xx/platform_f105_f107.mk +++ b/os/hal/ports/STM32/STM32F1xx/platform_f105_f107.mk @@ -5,82 +5,82 @@ HALCONF := $(strip $(shell cat halconf.h | egrep -e "define")) PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/hal_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/adc_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.c endif ifneq ($(findstring HAL_USE_CAN TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c endif ifneq ($(findstring HAL_USE_DAC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c endif ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/ext_lld_isr.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/hal_ext_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/hal_ext_lld_isr.c endif ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv1/pal_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c endif ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c endif ifneq ($(findstring HAL_USE_MAC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1/mac_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1/hal_mac_lld.c endif ifneq ($(findstring HAL_USE_USB TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/usb_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c endif ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv1/rtc_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv1/hal_rtc_lld.c endif ifneq ($(findstring HAL_USE_SDC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SDIOv1/sdc_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.c endif ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/spi_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/hal_spi_lld.c endif ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c endif ifneq ($(findstring HAL_USE_ICU TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c endif ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c endif ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/serial_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/hal_serial_lld.c endif ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/uart_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c endif ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c endif else PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/hal_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/adc_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/ext_lld_isr.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/hal_adc_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/hal_ext_lld_isr.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv1/pal_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1/mac_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/usb_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv1/rtc_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/SDIOv1/sdc_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/spi_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/serial_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/uart_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.c + $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/hal_ext_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1/hal_mac_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv1/hal_rtc_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/hal_spi_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/hal_serial_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c endif # Required include directories diff --git a/os/hal/ports/STM32/STM32F37x/adc_lld.c b/os/hal/ports/STM32/STM32F37x/adc_lld.c deleted file mode 100644 index 5262c1ed8..000000000 --- a/os/hal/ports/STM32/STM32F37x/adc_lld.c +++ /dev/null @@ -1,735 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F37x/adc_lld.c - * @brief STM32F37x ADC subsystem low level driver source. - * - * @addtogroup ADC - * @{ - */ - -#include "hal.h" - -#if HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define SDADC_FORBIDDEN_CR1_FLAGS (SDADC_CR1_INIT | SDADC_CR1_RDMAEN | \ - SDADC_CR1_RSYNC | SDADC_CR1_JSYNC | \ - SDADC_CR1_ROVRIE | SDADC_CR1_REOCIE | \ - SDADC_CR1_JEOCIE | SDADC_CR1_EOCALIE) - -#define SDADC_ENFORCED_CR1_FLAGS (SDADC_CR1_JDMAEN | SDADC_CR1_JOVRIE) - -#define SDADC_FORBIDDEN_CR2_FLAGS (SDADC_CR2_RSWSTART | \ - SDADC_CR2_RCONT | \ - SDADC_CR2_RCH | \ - SDADC_CR2_JCONT | \ - SDADC_CR2_STARTCALIB | \ - SDADC_CR2_CALIBCNT) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief ADC1 driver identifier.*/ -#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) -ADCDriver ADCD1; -#endif - -/** @brief SDADC1 driver identifier.*/ -#if STM32_ADC_USE_SDADC1 || defined(__DOXYGEN__) -ADCDriver SDADCD1; -#endif - -/** @brief SDADC2 driver identifier.*/ -#if STM32_ADC_USE_SDADC2 || defined(__DOXYGEN__) -ADCDriver SDADCD2; -#endif - -/** @brief SDADC3 driver identifier.*/ -#if STM32_ADC_USE_SDADC3 || defined(__DOXYGEN__) -ADCDriver SDADCD3; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -static const ADCConfig adc_lld_default_config = { -#if STM32_ADC_USE_SDADC - 0, - { - 0, - 0, - 0 - } -#else /* !STM32_ADC_USE_SDADC */ - 0 -#endif /* !STM32_ADC_USE_SDADC */ -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Stops, reconfigures and restarts an ADC/SDADC. - * - * @param[in] adcp pointer to the @p ADCDriver object - */ -static void adc_lld_reconfig(ADCDriver *adcp) { - -#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC - if (adcp->adc != NULL) -#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ -#if STM32_ADC_USE_ADC - { - /* ADC initial setup, starting the analog part here in order to reduce - the latency when starting a conversion.*/ - uint32_t cr2 = adcp->adc->CR2 & ADC_CR2_TSVREFE; - adcp->adc->CR2 = cr2; - adcp->adc->CR1 = 0; - adcp->adc->CR2 = cr2 | ADC_CR2_ADON; - - } -#endif /* STM32_ADC_USE_ADC */ -#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC - else if (adcp->sdadc != NULL) -#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ -#if STM32_ADC_USE_SDADC - { - /* SDADC initial setup, starting the analog part here in order to reduce - the latency when starting a conversion.*/ - adcp->sdadc->CR2 = 0; - adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) & - ~SDADC_FORBIDDEN_CR1_FLAGS; - adcp->sdadc->CONF0R = (adcp->sdadc->CONF0R & SDADC_CONFR_OFFSET_MASK) | - adcp->config->confxr[0]; - adcp->sdadc->CONF1R = (adcp->sdadc->CONF1R & SDADC_CONFR_OFFSET_MASK) | - adcp->config->confxr[1]; - adcp->sdadc->CONF2R = (adcp->sdadc->CONF2R & SDADC_CONFR_OFFSET_MASK) | - adcp->config->confxr[2]; - adcp->sdadc->CR2 = SDADC_CR2_ADON; - } -#endif /* STM32_ADC_USE_SDADC */ -#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC -else { - osalDbgAssert(FALSE, "invalid state"); - } -#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ -} - -/** - * @brief ADC DMA ISR service routine. - * - * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] flags pre-shifted content of the ISR register - * - * @notapi - */ -static void adc_lld_serve_dma_interrupt(ADCDriver *adcp, uint32_t flags) { - - /* DMA errors handling.*/ - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - /* DMA, this could help only if the DMA tries to access an unmapped - address space or violates alignment rules.*/ - _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); - } - else { - /* It is possible that the conversion group has already be reset by the - ADC error handler, in this case this interrupt is spurious.*/ - if (adcp->grpp != NULL) { - if ((flags & STM32_DMA_ISR_TCIF) != 0) { - /* Transfer complete processing.*/ - _adc_isr_full_code(adcp); - } - else if ((flags & STM32_DMA_ISR_HTIF) != 0) { - /* Half transfer processing.*/ - _adc_isr_half_code(adcp); - } - } - } -} - -#if STM32_ADC_USE_ADC || defined(__DOXYGEN__) -/** - * @brief ADC ISR service routine. - * - * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] sr content of the ISR register - * - * @notapi - */ -static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t sr) { - - /* It could be a spurious interrupt caused by overflows after DMA disabling, - just ignore it in this case.*/ - if (adcp->grpp != NULL) { - if (sr & ADC_SR_AWD) { - /* Analog watchdog error.*/ - _adc_isr_error_code(adcp, ADC_ERR_AWD1); - } - } -} -#endif /* STM32_ADC_USE_ADC */ - -#if STM32_ADC_USE_SDADC || defined(__DOXYGEN__) -/** - * @brief ADC ISR service routine. - * - * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] isr content of the ISR register - * - * @notapi - */ -static void sdadc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) { - - /* It could be a spurious interrupt caused by overflows after DMA disabling, - just ignore it in this case.*/ - if (adcp->grpp != NULL) { - /* Note, an overflow may occur after the conversion ended before the driver - is able to stop the ADC, this is why the DMA channel is checked too.*/ - if ((isr & SDADC_ISR_JOVRF) && - (dmaStreamGetTransactionSize(adcp->dmastp) > 0)) { - /* ADC overflow condition, this could happen only if the DMA is unable - to read data fast enough.*/ - _adc_isr_error_code(adcp, ADC_ERR_OVERFLOW); - } - } -} -#endif /* STM32_ADC_USE_SDADC */ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) -/** - * @brief ADC1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector88) { - uint32_t sr; - - OSAL_IRQ_PROLOGUE(); - - sr = ADC1->SR; - ADC1->SR = 0; - adc_lld_serve_interrupt(&ADCD1, sr); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_ADC_USE_ADC1 */ - -#if STM32_ADC_USE_SDADC1 || defined(__DOXYGEN__) -/** - * @brief SDADC1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector134) { - uint32_t isr; - - OSAL_IRQ_PROLOGUE(); - - isr = SDADC1->ISR; - SDADC1->CLRISR = isr; - sdadc_lld_serve_interrupt(&SDADCD1, isr); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_ADC_USE_SDADC1 */ - -#if STM32_ADC_USE_SDADC2 || defined(__DOXYGEN__) -/** - * @brief SDADC2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector138) { - uint32_t isr; - - OSAL_IRQ_PROLOGUE(); - - isr = SDADC2->ISR; - SDADC2->CLRISR = isr; - sdadc_lld_serve_interrupt(&SDADCD2, isr); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_ADC_USE_SDADC2 */ - -#if STM32_ADC_USE_SDADC3 || defined(__DOXYGEN__) -/** - * @brief SDADC3 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector13C) { - uint32_t isr; - - OSAL_IRQ_PROLOGUE(); - - isr = SDADC3->ISR; - SDADC3->CLRISR = isr; - sdadc_lld_serve_interrupt(&SDADCD3, isr); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_ADC_USE_SDADC3 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level ADC driver initialization. - * - * @notapi - */ -void adc_lld_init(void) { - -#if STM32_ADC_USE_ADC1 - /* Driver initialization.*/ - adcObjectInit(&ADCD1); - ADCD1.adc = ADC1; -#if STM32_ADC_USE_SDADC - ADCD1.sdadc = NULL; -#endif - ADCD1.dmastp = STM32_DMA1_STREAM1; - ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - nvicEnableVector(ADC1_IRQn, STM32_ADC_ADC1_IRQ_PRIORITY); -#endif - -#if STM32_ADC_USE_SDADC1 - /* Driver initialization.*/ - adcObjectInit(&SDADCD1); -#if STM32_ADC_USE_ADC - SDADCD1.adc = NULL; -#endif - SDADCD1.sdadc = SDADC1; - SDADCD1.dmastp = STM32_DMA2_STREAM3; - SDADCD1.dmamode = STM32_DMA_CR_CHSEL(SDADC1_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_ADC_SDADC1_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - nvicEnableVector(SDADC1_IRQn, STM32_ADC_SDADC1_IRQ_PRIORITY); -#endif - -#if STM32_ADC_USE_SDADC2 - /* Driver initialization.*/ - adcObjectInit(&SDADCD2); -#if STM32_ADC_USE_ADC - SDADCD2.adc = NULL; -#endif - SDADCD2.sdadc = SDADC2; - SDADCD2.dmastp = STM32_DMA2_STREAM4; - SDADCD2.dmamode = STM32_DMA_CR_CHSEL(SDADC2_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_ADC_SDADC2_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - nvicEnableVector(SDADC2_IRQn, STM32_ADC_SDADC2_IRQ_PRIORITY); -#endif - -#if STM32_ADC_USE_SDADC3 - /* Driver initialization.*/ - adcObjectInit(&SDADCD3); -#if STM32_ADC_USE_ADC - SDADCD3.adc = NULL; -#endif - SDADCD3.sdadc = SDADC3; - SDADCD3.dmastp = STM32_DMA2_STREAM5; - SDADCD3.dmamode = STM32_DMA_CR_CHSEL(SDADC3_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_ADC_SDADC3_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; - nvicEnableVector(SDADC3_IRQn, STM32_ADC_SDADC3_IRQ_PRIORITY); -#endif -} - -/** - * @brief Configures and activates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_start(ADCDriver *adcp) { - - if (adcp->config == NULL) - adcp->config = &adc_lld_default_config; - - /* If in stopped state then enables the ADC and DMA clocks.*/ - if (adcp->state == ADC_STOP) { -#if STM32_ADC_USE_ADC1 - if (&ADCD1 == adcp) { - bool b = dmaStreamAllocate(adcp->dmastp, - STM32_ADC_ADC1_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, - (void *)adcp); - osalDbgAssert(!b, "stream already allocated"); - dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); - rccEnableADC1(FALSE); - } -#endif /* STM32_ADC_USE_ADC1 */ - -#if STM32_ADC_USE_SDADC1 - if (&SDADCD1 == adcp) { - bool b = dmaStreamAllocate(adcp->dmastp, - STM32_ADC_SDADC1_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, - (void *)adcp); - osalDbgAssert(!b, "stream already allocated"); - dmaStreamSetPeripheral(adcp->dmastp, &SDADC1->JDATAR); - rccEnableSDADC1(FALSE); - PWR->CR |= PWR_CR_SDADC1EN; - adcp->sdadc->CR2 = 0; - adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) & - ~SDADC_FORBIDDEN_CR1_FLAGS; - adcp->sdadc->CR2 = SDADC_CR2_ADON; - } -#endif /* STM32_ADC_USE_SDADC1 */ - -#if STM32_ADC_USE_SDADC2 - if (&SDADCD2 == adcp) { - bool b = dmaStreamAllocate(adcp->dmastp, - STM32_ADC_SDADC2_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, - (void *)adcp); - osalDbgAssert(!b, "stream already allocated"); - dmaStreamSetPeripheral(adcp->dmastp, &SDADC2->JDATAR); - rccEnableSDADC2(FALSE); - PWR->CR |= PWR_CR_SDADC2EN; - adcp->sdadc->CR2 = 0; - adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) & - ~SDADC_FORBIDDEN_CR1_FLAGS; - adcp->sdadc->CR2 = SDADC_CR2_ADON; - } -#endif /* STM32_ADC_USE_SDADC2 */ - -#if STM32_ADC_USE_SDADC3 - if (&SDADCD3 == adcp) { - bool b = dmaStreamAllocate(adcp->dmastp, - STM32_ADC_SDADC3_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, - (void *)adcp); - osalDbgAssert(!b, "stream already allocated"); - dmaStreamSetPeripheral(adcp->dmastp, &SDADC3->JDATAR); - rccEnableSDADC3(FALSE); - PWR->CR |= PWR_CR_SDADC3EN; - adcp->sdadc->CR2 = 0; - adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) & - ~SDADC_FORBIDDEN_CR1_FLAGS; - adcp->sdadc->CR2 = SDADC_CR2_ADON; - } -#endif /* STM32_ADC_USE_SDADC3 */ - } - - adc_lld_reconfig(adcp); -} - -/** - * @brief Deactivates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_stop(ADCDriver *adcp) { - - /* If in ready state then disables the ADC clock.*/ - if (adcp->state == ADC_READY) { - dmaStreamRelease(adcp->dmastp); - -#if STM32_ADC_USE_ADC1 - if (&ADCD1 == adcp) { - adcp->adc->CR1 = 0; - adcp->adc->CR2 = 0; - rccDisableADC1(FALSE); - } -#endif - -#if STM32_ADC_USE_SDADC1 - if (&SDADCD1 == adcp) { - adcp->sdadc->CR1 = 0; - adcp->sdadc->CR2 = 0; - rccDisableSDADC1(FALSE); - PWR->CR &= ~PWR_CR_SDADC1EN; - } -#endif - -#if STM32_ADC_USE_SDADC2 - if (&SDADCD2 == adcp) { - adcp->sdadc->CR1 = 0; - adcp->sdadc->CR2 = 0; - rccDisableSDADC2(FALSE); - PWR->CR &= ~PWR_CR_SDADC2EN; - } -#endif - -#if STM32_ADC_USE_SDADC3 - if (&SDADCD3 == adcp) { - adcp->sdadc->CR1 = 0; - adcp->sdadc->CR2 = 0; - rccDisableSDADC3(FALSE); - PWR->CR &= ~PWR_CR_SDADC3EN; - } -#endif - } -} - -/** - * @brief Starts an ADC conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_start_conversion(ADCDriver *adcp) { - uint32_t mode; - const ADCConversionGroup* grpp = adcp->grpp; - - /* DMA setup.*/ - mode = adcp->dmamode; - if (grpp->circular) { - mode |= STM32_DMA_CR_CIRC; - if (adcp->depth > 1) { - /* If circular buffer depth > 1, then the half transfer interrupt - is enabled in order to allow streaming processing.*/ - mode |= STM32_DMA_CR_HTIE; - } - } - dmaStreamSetMemory0(adcp->dmastp, adcp->samples); - dmaStreamSetTransactionSize(adcp->dmastp, - (uint32_t)grpp->num_channels * - (uint32_t)adcp->depth); - dmaStreamSetMode(adcp->dmastp, mode); - dmaStreamEnable(adcp->dmastp); - -#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC - if (adcp->adc != NULL) -#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ -#if STM32_ADC_USE_ADC - { - uint32_t cr2 = adcp->adc->CR2 & ADC_CR2_TSVREFE; - cr2 |= grpp->u.adc.cr2 | ADC_CR2_DMA | ADC_CR2_ADON; - if ((cr2 & ADC_CR2_SWSTART) != 0) - cr2 |= ADC_CR2_CONT; - adcp->adc->CR2 = cr2; - - /* ADC setup.*/ - adcp->adc->SR = 0; - adcp->adc->LTR = grpp->u.adc.ltr; - adcp->adc->HTR = grpp->u.adc.htr; - adcp->adc->SMPR1 = grpp->u.adc.smpr[0]; - adcp->adc->SMPR2 = grpp->u.adc.smpr[1]; - adcp->adc->SQR1 = grpp->u.adc.sqr[0] | - ADC_SQR1_NUM_CH(grpp->num_channels); - adcp->adc->SQR2 = grpp->u.adc.sqr[1]; - adcp->adc->SQR3 = grpp->u.adc.sqr[2]; - - /* ADC conversion start, the start is performed using the method - specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/ - adcp->adc->CR1 = grpp->u.adc.cr1 | ADC_CR1_AWDIE | ADC_CR1_SCAN; - adcp->adc->CR2 = adcp->adc->CR2; /* Triggers the conversion start.*/ - } -#endif /* STM32_ADC_USE_ADC */ -#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC - else if (adcp->sdadc != NULL) -#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ -#if STM32_ADC_USE_SDADC - { - uint32_t cr2 = (grpp->u.sdadc.cr2 & ~SDADC_FORBIDDEN_CR2_FLAGS) | - SDADC_CR2_ADON; - if ((grpp->u.sdadc.cr2 & SDADC_CR2_JSWSTART) != 0) - cr2 |= SDADC_CR2_JCONT; - - /* Entering initialization mode.*/ - adcp->sdadc->CR1 |= SDADC_CR1_INIT; - while ((adcp->sdadc->ISR & SDADC_ISR_INITRDY) == 0) - ; - - /* SDADC setup.*/ - adcp->sdadc->JCHGR = grpp->u.sdadc.jchgr; - adcp->sdadc->CONFCHR1 = grpp->u.sdadc.confchr[0]; - adcp->sdadc->CONFCHR2 = grpp->u.sdadc.confchr[1]; - - /* SDADC trigger modes, this write must be performed when - SDADC_CR1_INIT=1.*/ - adcp->sdadc->CR2 = cr2; - - /* Leaving initialization mode.*/ - adcp->sdadc->CR1 &= ~SDADC_CR1_INIT; - - /* Special case, if SDADC_CR2_JSWSTART is specified it has to be - written after SDADC_CR1_INIT has been set to zero. Just a write is - performed, any other bit is ingore if not in initialization mode.*/ - adcp->sdadc->CR2 = cr2; - } -#endif /* STM32_ADC_USE_SDADC */ -#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC - else { - osalDbgAssert(FALSE, "invalid state"); - } -#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ -} - -/** - * @brief Stops an ongoing conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_stop_conversion(ADCDriver *adcp) { - - /* Disabling the associated DMA stream.*/ - dmaStreamDisable(adcp->dmastp); - - /* Stopping and restarting the whole ADC, apparently the only way to stop - a conversion.*/ - adc_lld_reconfig(adcp); -} - -/** - * @brief Calibrates an ADC unit. - * @note The calibration must be performed after calling @p adcStart(). - * @note For SDADC units it is assumed that the field SDADC_CR2_CALIBCNT - * has been - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @api - */ -void adcSTM32Calibrate(ADCDriver *adcp) { - - osalDbgAssert((adcp->state == ADC_READY) || - (adcp->state == ADC_COMPLETE) || - (adcp->state == ADC_ERROR), - "not ready"); - -#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC - if (adcp->adc != NULL) -#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ -#if STM32_ADC_USE_ADC - { - /* Resetting calibration just to be safe.*/ - ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL; - while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0) - ; - - /* Calibration.*/ - ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL; - while ((ADC1->CR2 & ADC_CR2_CAL) != 0) - ; - } -#endif /* STM32_ADC_USE_ADC */ -#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC - else if (adcp->sdadc != NULL) -#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ -#if STM32_ADC_USE_SDADC - { - /* Selecting a full calibration in three steps.*/ - adcp->sdadc->CR2 = (adcp->sdadc->CR2 & ~SDADC_CR2_CALIBCNT) | - SDADC_CR2_CALIBCNT_1; - - /* Calibration.*/ - adcp->sdadc->CR2 |= SDADC_CR2_STARTCALIB; - while ((adcp->sdadc->ISR & SDADC_ISR_EOCALF) == 0) - ; - - /* Clearing the EOCALF flag.*/ - adcp->sdadc->CLRISR |= SDADC_ISR_CLREOCALF; - } -#endif /* STM32_ADC_USE_SDADC */ -#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC - else { - osalDbgAssert(FALSE, "invalid state"); - } -#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ -} - -#if STM32_ADC_USE_ADC || defined(__DOXYGEN__) -/** - * @brief Enables the TSVREFE bit. - * @details The TSVREFE bit is required in order to sample the internal - * temperature sensor and internal reference voltage. - * @note This is an STM32-only functionality. - * - * @api - */ -void adcSTM32EnableTSVREFE(void) { - - ADC1->CR2 |= ADC_CR2_TSVREFE; -} - -/** - * @brief Disables the TSVREFE bit. - * @details The TSVREFE bit is required in order to sample the internal - * temperature sensor and internal reference voltage. - * @note This is an STM32-only functionality. - * - * @api - */ -void adcSTM32DisableTSVREFE(void) { - - ADC1->CR2 &= ~ADC_CR2_TSVREFE; -} - -/** - * @brief Enables the VBATE bit. - * @details The VBATE bit is required in order to sample the VBAT channel. - * @note This is an STM32-only functionality. - * - * @api - */ -void adcSTM32EnableVBATE(void) { - - SYSCFG->CFGR1 |= SYSCFG_CFGR1_VBAT; -} - -/** - * @brief Disables the VBATE bit. - * @details The VBATE bit is required in order to sample the VBAT channel. - * @note This is an STM32-only functionality. - * - * @api - */ -void adcSTM32DisableVBATE(void) { - - SYSCFG->CFGR1 &= ~SYSCFG_CFGR1_VBAT; -} -#endif /* STM32_ADC_USE_ADC */ - -#endif /* HAL_USE_ADC */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32F37x/adc_lld.h b/os/hal/ports/STM32/STM32F37x/adc_lld.h deleted file mode 100644 index cb7281811..000000000 --- a/os/hal/ports/STM32/STM32F37x/adc_lld.h +++ /dev/null @@ -1,706 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F37x/adc_lld.h - * @brief STM32F37x ADC subsystem low level driver header. - * - * @addtogroup ADC - * @{ - */ - -#ifndef _ADC_LLD_H_ -#define _ADC_LLD_H_ - -#if HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Triggers selection - * @{ - */ -#define ADC_CR2_EXTSEL_SRC(n) ((n) << 24) /**< @brief Trigger source. */ -/** @} */ - -/** - * @name ADC clock divider settings - * @{ - */ -#define ADC_CCR_ADCPRE_DIV2 0 -#define ADC_CCR_ADCPRE_DIV4 1 -#define ADC_CCR_ADCPRE_DIV6 2 -#define ADC_CCR_ADCPRE_DIV8 3 -/** @} */ - -/** - * @name Available analog channels - * @{ - */ -#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ -#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ -#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ -#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ -#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ -#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ -#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ -#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ -#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ -#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ -#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ -#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ -#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ -#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ -#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ -#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ -#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/ -#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */ -#define ADC_CHANNEL_VBAT 18 /**< @brief VBAT. */ -/** @} */ - -/** - * @name Sampling rates - * @{ - */ -#define ADC_SAMPLE_1P5 0 /**< @brief 1.5 cycles sampling time. */ -#define ADC_SAMPLE_7P5 1 /**< @brief 7.5 cycles sampling time. */ -#define ADC_SAMPLE_13P5 2 /**< @brief 13.5 cycles sampling time. */ -#define ADC_SAMPLE_28P5 3 /**< @brief 28.5 cycles sampling time. */ -#define ADC_SAMPLE_41P5 4 /**< @brief 41.5 cycles sampling time. */ -#define ADC_SAMPLE_55P5 5 /**< @brief 55.5 cycles sampling time. */ -#define ADC_SAMPLE_71P5 6 /**< @brief 71.5 cycles sampling time. */ -#define ADC_SAMPLE_239P5 7 /**< @brief 239.5 cycles sampling time. */ -/** @} */ - -/** - * @name SDADC JCHGR bit definitions - * @{ - */ -#define SDADC_JCHG_MASK (511U << 0) -#define SDADC_JCHG(n) (1U << (n)) -/** @} */ - -/** - * @name SDADC channels definitions - * @{ - */ -#define SDADC_CHANNEL_0 SDADC_JCHG(0) -#define SDADC_CHANNEL_1 SDADC_JCHG(1) -#define SDADC_CHANNEL_2 SDADC_JCHG(2) -#define SDADC_CHANNEL_3 SDADC_JCHG(3) -#define SDADC_CHANNEL_4 SDADC_JCHG(4) -#define SDADC_CHANNEL_5 SDADC_JCHG(5) -#define SDADC_CHANNEL_6 SDADC_JCHG(6) -#define SDADC_CHANNEL_7 SDADC_JCHG(7) -#define SDADC_CHANNEL_8 SDADC_JCHG(8) -#define SDADC_CHANNEL_9 SDADC_JCHG(9) -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief ADC1 driver enable switch. - * @details If set to @p TRUE the support for ADC1 is included. - */ -#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) -#define STM32_ADC_USE_ADC1 FALSE -#endif - -/** - * @brief SDADC1 driver enable switch. - * @details If set to @p TRUE the support for SDADC1 is included. - */ -#if !defined(STM32_ADC_USE_SDADC1) || defined(__DOXYGEN__) -#define STM32_ADC_USE_SDADC1 FALSE -#endif - -/** - * @brief SDADC2 driver enable switch. - * @details If set to @p TRUE the support for SDADC2 is included. - */ -#if !defined(STM32_ADC_USE_SDADC2) || defined(__DOXYGEN__) -#define STM32_ADC_USE_SDADC2 FALSE -#endif - -/** - * @brief SDADC3 driver enable switch. - * @details If set to @p TRUE the support for SDADC3 is included. - */ -#if !defined(STM32_ADC_USE_SDADC3) || defined(__DOXYGEN__) -#define STM32_ADC_USE_SDADC3 FALSE -#endif - -/** - * @brief ADC1 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#endif - -/** - * @brief SDADC1 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_ADC_SDADC1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_SDADC1_DMA_PRIORITY 2 -#endif - -/** - * @brief SDADC2 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_ADC_SDADC2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_SDADC2_DMA_PRIORITY 2 -#endif - -/** - * @brief SDADC3 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_ADC_SDADC3_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_SDADC3_DMA_PRIORITY 2 -#endif - -/** - * @brief ADC interrupt priority level setting. - */ -#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#endif - -/** - * @brief ADC DMA interrupt priority level setting. - */ -#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 -#endif - -/** - * @brief SDADC1 interrupt priority level setting. - */ -#if !defined(STM32_ADC_SDADC1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_SDADC1_IRQ_PRIORITY 5 -#endif - -/** - * @brief SDADC2 interrupt priority level setting. - */ -#if !defined(STM32_ADC_SDADC2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_SDADC2_IRQ_PRIORITY 5 -#endif - -/** - * @brief SDADC3 interrupt priority level setting. - */ -#if !defined(STM32_ADC_SDADC3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_SDADC3_IRQ_PRIORITY 5 -#endif - -/** - * @brief SDADC1 DMA interrupt priority level setting. - */ -#if !defined(STM32_ADC_SDADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_SDADC1_DMA_IRQ_PRIORITY 5 -#endif - -/** - * @brief SDADC2 DMA interrupt priority level setting. - */ -#if !defined(STM32_ADC_SDADC2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_SDADC2_DMA_IRQ_PRIORITY 5 -#endif - -/** - * @brief SDADC3 DMA interrupt priority level setting. - */ -#if !defined(STM32_ADC_SDADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_SDADC3_DMA_IRQ_PRIORITY 5 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/** - * @brief At least an ADC unit is in use. - */ -#define STM32_ADC_USE_ADC STM32_ADC_USE_ADC1 - -/** - * @brief At least an SDADC unit is in use. - */ -#define STM32_ADC_USE_SDADC (STM32_ADC_USE_SDADC1 || \ - STM32_ADC_USE_SDADC2 || \ - STM32_ADC_USE_SDADC3) - -#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 -#error "ADC1 not present in the selected device" -#endif - -#if STM32_ADC_USE_SDADC1 && !STM32_HAS_SDADC1 -#error "SDADC1 not present in the selected device" -#endif - -#if STM32_ADC_USE_SDADC2 && !STM32_HAS_SDADC2 -#error "SDADC2 not present in the selected device" -#endif - -#if STM32_ADC_USE_SDADC3 && !STM32_HAS_SDADC3 -#error "SDADC3 not present in the selected device" -#endif - -#if !STM32_ADC_USE_ADC && !STM32_ADC_USE_SDADC -#error "ADC driver activated but no ADC/SDADC peripheral assigned" -#endif - -#if STM32_ADC_USE_ADC1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to ADC1" -#endif - -#if STM32_ADC_USE_ADC1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to ADC1 DMA" -#endif - -#if STM32_ADC_USE_ADC1 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY) -#error "Invalid DMA priority assigned to ADC1" -#endif - -#if STM32_ADC_USE_SDADC1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SDADC1" -#endif - -#if STM32_ADC_USE_SDADC1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC1_DMA_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SDADC1 DMA" -#endif - -#if STM32_ADC_USE_SDADC1 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_SDADC1_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SDADC1" -#endif - -#if STM32_ADC_USE_SDADC2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SDADC2" -#endif - -#if STM32_ADC_USE_SDADC2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC2_DMA_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SDADC2 DMA" -#endif - -#if STM32_ADC_USE_SDADC2 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_SDADC2_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SDADC2" -#endif - -#if STM32_ADC_USE_SDADC3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SDADC3" -#endif - -#if STM32_ADC_USE_SDADC3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC3_DMA_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SDADC3 DMA" -#endif - -#if STM32_ADC_USE_SDADC3 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_SDADC3_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SDADC3" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief ADC sample data type. - */ -typedef uint16_t adcsample_t; - -/** - * @brief Channels number in a conversion group. - */ -typedef uint16_t adc_channels_num_t; - -/** - * @brief Possible ADC failure causes. - * @note Error codes are architecture dependent and should not relied - * upon. - */ -typedef enum { - ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */ - ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */ - ADC_ERR_AWD1 = 2 /**< Watchdog 1 triggered. */ -} adcerror_t; - -/** - * @brief Type of a structure representing an ADC driver. - */ -typedef struct ADCDriver ADCDriver; - -/** - * @brief ADC notification callback type. - * - * @param[in] adcp pointer to the @p ADCDriver object triggering the - * callback - * @param[in] buffer pointer to the most recent samples data - * @param[in] n number of buffer rows available starting from @p buffer - */ -typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); - -/** - * @brief ADC error callback type. - * - * @param[in] adcp pointer to the @p ADCDriver object triggering the - * callback - * @param[in] err ADC error code - */ -typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); - -/** - * @brief Conversion group configuration structure. - * @details This implementation-dependent structure describes a conversion - * operation. - * @note The use of this configuration structure requires knowledge of - * STM32 ADC cell registers interface, please refer to the STM32 - * reference manual for details. - */ -typedef struct { - /** - * @brief Enables the circular buffer mode for the group. - */ - bool circular; - /** - * @brief Number of the analog channels belonging to the conversion group. - */ - adc_channels_num_t num_channels; - /** - * @brief Callback function associated to the group or @p NULL. - */ - adccallback_t end_cb; - /** - * @brief Error callback or @p NULL. - */ - adcerrorcallback_t error_cb; - /* End of the mandatory fields.*/ - - /** - * @brief Union of ADC and SDADC config parms. The decision of which struct - * union to use is determined by the ADCDriver. If the ADCDriver adc parm - * is not NULL, then use the adc struct, otherwise if the ADCDriver sdadc parm - * is not NULL, then use the sdadc struct. - */ - union { -#if STM32_ADC_USE_ADC || defined(__DOXYGEN__) - struct { - /** - * @brief ADC CR1 register initialization data. - * @note All the required bits must be defined into this field except - * @p ADC_CR1_SCAN that is enforced inside the driver. - */ - uint32_t cr1; - /** - * @brief ADC CR2 register initialization data. - * @note All the required bits must be defined into this field except - * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are - * enforced inside the driver. - */ - uint32_t cr2; - /** - * @brief ADC LTR register initialization data. - */ - uint32_t ltr; - /** - * @brief ADC HTR register initialization data. - */ - uint32_t htr; - /** - * @brief ADC SMPRx registers initialization data. - */ - uint32_t smpr[2]; - /** - * @brief ADC SQRx register initialization data. - */ - uint32_t sqr[3]; - } adc; -#endif /* STM32_ADC_USE_ADC */ -#if STM32_ADC_USE_SDADC || defined(__DOXYGEN__) - struct { - /** - * @brief SDADC CR2 register initialization data. - * @note Only the @p SDADC_CR2_JSWSTART, @p SDADC_CR2_JEXTSEL - * and @p SDADC_CR2_JEXTEN can be specified in this field. - */ - uint32_t cr2; - /** - * @brief SDADC JCHGR register initialization data. - */ - uint32_t jchgr; - /** - * @brief SDADC CONFCHxR registers initialization data. - */ - uint32_t confchr[2]; - } sdadc; -#endif /* STM32_ADC_USE_SDADC */ - } u; -} ADCConversionGroup; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { -#if STM32_ADC_USE_SDADC - /** - * @brief SDADC CR1 register initialization data. - */ - uint32_t cr1; - /** - * @brief SDADC CONFxR registers initialization data. - */ - uint32_t confxr[3]; -#else /* !STM32_ADC_USE_SDADC */ - uint32_t dummy; -#endif /* !STM32_ADC_USE_SDADC */ -} ADCConfig; - -/** - * @brief Structure representing an ADC driver. - */ -struct ADCDriver { - /** - * @brief Driver state. - */ - adcstate_t state; - /** - * @brief Current configuration data. - */ - const ADCConfig *config; - /** - * @brief Current samples buffer pointer or @p NULL. - */ - adcsample_t *samples; - /** - * @brief Current samples buffer depth or @p 0. - */ - size_t depth; - /** - * @brief Current conversion group pointer or @p NULL. - */ - const ADCConversionGroup *grpp; -#if ADC_USE_WAIT || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - thread_reference_t thread; -#endif -#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the peripheral. - */ - mutex_t mutex; -#endif /* ADC_USE_MUTUAL_EXCLUSION */ -#if defined(ADC_DRIVER_EXT_FIELDS) - ADC_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ -#if STM32_ADC_USE_ADC || defined(__DOXYGEN__) - /** - * @brief Pointer to the ADCx registers block. - */ - ADC_TypeDef *adc; -#endif -#if STM32_ADC_USE_SDADC || defined(__DOXYGEN__) - /** - * @brief Pointer to the SDADCx registers block. - */ - SDADC_TypeDef *sdadc; -#endif - /** - * @brief Pointer to associated DMA channel. - */ - const stm32_dma_stream_t *dmastp; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Sequences building helper macros for ADC - * @{ - */ -/** - * @brief Number of channels in a conversion sequence. - */ -#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20) -#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ -#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ -#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ -#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ - -#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ -#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ -#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ -#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ -#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ -#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ - -#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ -#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ -#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ -#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ -#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ -#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ -/** @} */ - -/** - * @name Sampling rate settings helper macros - * @{ - */ -#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ -#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ -#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ -#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ -#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ -#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ -#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ -#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ -#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ -#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ - -#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ -#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ -#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ -#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ -#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ -#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ -#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor - sampling time. */ -#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference - sampling time. */ -#define ADC_SMPR1_SMP_VBAT(n) ((n) << 24) /**< @brief VBAT sampling time. */ -/** @} */ - -/** - * @name Sequences building helper macros for SDADC - * @{ - */ -#define SDADC_JCHGR_CH(n) (1U << (n)) -/** @} */ - -/** - * @name Channel configuration number helper macros for SDADC - * @{ - */ -#define SDADC_CONFCHR1_CH0(n) ((n) << 0) -#define SDADC_CONFCHR1_CH1(n) ((n) << 4) -#define SDADC_CONFCHR1_CH2(n) ((n) << 8) -#define SDADC_CONFCHR1_CH3(n) ((n) << 12) -#define SDADC_CONFCHR1_CH4(n) ((n) << 16) -#define SDADC_CONFCHR1_CH5(n) ((n) << 20) -#define SDADC_CONFCHR1_CH6(n) ((n) << 24) -#define SDADC_CONFCHR1_CH7(n) ((n) << 28) -#define SDADC_CONFCHR2_CH8(n) ((n) << 0) -/** @} */ - -/** - * @name Configuration registers helper macros for SDADC - * @{ - */ -#define SDADC_CONFR_OFFSET_MASK (0xFFFU << 0) -#define SDADC_CONFR_OFFSET(n) ((n) << 0) -#define SDADC_CONFR_GAIN_MASK (7U << 20) -#define SDADC_CONFR_GAIN_1X (0U << 20) -#define SDADC_CONFR_GAIN_2X (1U << 20) -#define SDADC_CONFR_GAIN_4X (2U << 20) -#define SDADC_CONFR_GAIN_8X (3U << 20) -#define SDADC_CONFR_GAIN_16X (4U << 20) -#define SDADC_CONFR_GAIN_32X (5U << 20) -#define SDADC_CONFR_GAIN_0P5X (7U << 20) -#define SDADC_CONFR_SE_MASK (3U << 26) -#define SDADC_CONFR_SE_DIFF (0U << 26) -#define SDADC_CONFR_SE_OFFSET (1U << 26) -#define SDADC_CONFR_SE_ZERO_VOLT (3U << 26) -#define SDADC_CONFR_COMMON_MASK (3U << 30) -#define SDADC_CONFR_COMMON_VSSSD (0U << 30) -#define SDADC_CONFR_COMMON_VDDSD2 (1U << 30) -#define SDADC_CONFR_COMMON_VDDSD (2U << 30) -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) -extern ADCDriver ADCD1; -#endif - -#if STM32_ADC_USE_SDADC1 && !defined(__DOXYGEN__) -extern ADCDriver SDADCD1; -#endif - -#if STM32_ADC_USE_SDADC2 && !defined(__DOXYGEN__) -extern ADCDriver SDADCD2; -#endif - -#if STM32_ADC_USE_SDADC3 && !defined(__DOXYGEN__) -extern ADCDriver SDADCD3; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void adc_lld_init(void); - void adc_lld_start(ADCDriver *adcp); - void adc_lld_stop(ADCDriver *adcp); - void adc_lld_start_conversion(ADCDriver *adcp); - void adc_lld_stop_conversion(ADCDriver *adcp); - void adcSTM32Calibrate(ADCDriver *adcdp); -#if STM32_ADC_USE_ADC - void adcSTM32EnableTSVREFE(void); - void adcSTM32DisableTSVREFE(void); - void adcSTM32EnableVBATE(void); - void adcSTM32DisableVBATE(void); -#endif /* STM32_ADC_USE_ADC */ -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_ADC */ - -#endif /* _ADC_LLD_H_ */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32F37x/ext_lld_isr.c b/os/hal/ports/STM32/STM32F37x/ext_lld_isr.c deleted file mode 100644 index ee3770cab..000000000 --- a/os/hal/ports/STM32/STM32F37x/ext_lld_isr.c +++ /dev/null @@ -1,400 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F37x/ext_lld_isr.c - * @brief STM32F37x EXT subsystem low level driver ISR code. - * - * @addtogroup EXT - * @{ - */ - -#include "hal.h" - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -#include "ext_lld_isr.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if !defined(STM32_DISABLE_EXTI0_HANDLER) -/** - * @brief EXTI[0] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector58) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 0); - EXTI->PR = pr; - if (pr & (1U << 0)) - EXTD1.config->channels[0].cb(&EXTD1, 0); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI1_HANDLER) -/** - * @brief EXTI[1] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector5C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 1); - EXTI->PR = pr; - if (pr & (1U << 1)) - EXTD1.config->channels[1].cb(&EXTD1, 1); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI2_HANDLER) -/** - * @brief EXTI[2] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector60) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 2); - EXTI->PR = pr; - if (pr & (1U << 2)) - EXTD1.config->channels[2].cb(&EXTD1, 2); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI3_HANDLER) -/** - * @brief EXTI[3] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector64) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 3); - EXTI->PR = pr; - if (pr & (1U << 3)) - EXTD1.config->channels[3].cb(&EXTD1, 3); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI4_HANDLER) -/** - * @brief EXTI[4] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector68) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 4); - EXTI->PR = pr; - if (pr & (1U << 4)) - EXTD1.config->channels[4].cb(&EXTD1, 4); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI5_9_HANDLER) -/** - * @brief EXTI[5]...EXTI[9] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector9C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) | - (1U << 9)); - EXTI->PR = pr; - if (pr & (1U << 5)) - EXTD1.config->channels[5].cb(&EXTD1, 5); - if (pr & (1U << 6)) - EXTD1.config->channels[6].cb(&EXTD1, 6); - if (pr & (1U << 7)) - EXTD1.config->channels[7].cb(&EXTD1, 7); - if (pr & (1U << 8)) - EXTD1.config->channels[8].cb(&EXTD1, 8); - if (pr & (1U << 9)) - EXTD1.config->channels[9].cb(&EXTD1, 9); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI10_15_HANDLER) -/** - * @brief EXTI[10]...EXTI[15] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorE0) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) | - (1U << 14) | (1U << 15)); - EXTI->PR = pr; - if (pr & (1U << 10)) - EXTD1.config->channels[10].cb(&EXTD1, 10); - if (pr & (1U << 11)) - EXTD1.config->channels[11].cb(&EXTD1, 11); - if (pr & (1U << 12)) - EXTD1.config->channels[12].cb(&EXTD1, 12); - if (pr & (1U << 13)) - EXTD1.config->channels[13].cb(&EXTD1, 13); - if (pr & (1U << 14)) - EXTD1.config->channels[14].cb(&EXTD1, 14); - if (pr & (1U << 15)) - EXTD1.config->channels[15].cb(&EXTD1, 15); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI16_HANDLER) -/** - * @brief EXTI[16] interrupt handler (PVD). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector44) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 16); - EXTI->PR = pr; - if (pr & (1U << 16)) - EXTD1.config->channels[16].cb(&EXTD1, 16); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI17_HANDLER) -/** - * @brief EXTI[17] interrupt handler (RTC Alarm). - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorE4) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 17); - EXTI->PR = pr; - if (pr & (1U << 17)) - EXTD1.config->channels[17].cb(&EXTD1, 17); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if STM32_HAS_USB && !defined(STM32_DISABLE_EXTI18_HANDLER) -/** - * @brief EXTI[18] interrupt handler (USB Wakeup). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector170) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 18); - EXTI->PR = pr; - if (pr & (1U << 18)) - EXTD1.config->channels[18].cb(&EXTD1, 18); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI19_HANDLER) -/** - * @brief EXTI[19] interrupt handler (Tamper TimeStamp). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector48) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 19); - EXTI->PR = pr; - if (pr & (1U << 19)) - EXTD1.config->channels[19].cb(&EXTD1, 19); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI20_HANDLER) -/** - * @brief EXTI[20] interrupt handler (RTC Wakeup). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector4C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 20); - EXTI->PR = pr; - if (pr & (1U << 20)) - EXTD1.config->channels[20].cb(&EXTD1, 20); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI21_22_HANDLER) -/** - * @brief EXTI[21]..EXTI[22] interrupt handler (COMP1, COMP2). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector140) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & ((1U << 21) | (1U << 22)); - EXTI->PR = pr; - if (pr & (1U << 21)) - EXTD1.config->channels[21].cb(&EXTD1, 21); - if (pr & (1U << 22)) - EXTD1.config->channels[22].cb(&EXTD1, 22); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Enables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_enable(void) { - - nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY); - nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY); - nvicEnableVector(EXTI2_TSC_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY); - nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY); - nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY); - nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY); - nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY); - nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY); - nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY); -#if STM32_HAS_USB - nvicEnableVector(USBWakeUp_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY); -#endif - nvicEnableVector(TAMP_STAMP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY); - nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY); - nvicEnableVector(COMP_IRQn, STM32_EXT_EXTI21_22_IRQ_PRIORITY); -} - -/** - * @brief Disables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_disable(void) { - - nvicDisableVector(EXTI0_IRQn); - nvicDisableVector(EXTI1_IRQn); - nvicDisableVector(EXTI2_TSC_IRQn); - nvicDisableVector(EXTI3_IRQn); - nvicDisableVector(EXTI4_IRQn); - nvicDisableVector(EXTI9_5_IRQn); - nvicDisableVector(EXTI15_10_IRQn); - nvicDisableVector(PVD_IRQn); - nvicDisableVector(RTC_Alarm_IRQn); -#if STM32_HAS_USB - nvicDisableVector(USBWakeUp_IRQn); -#endif - nvicDisableVector(TAMP_STAMP_IRQn); - nvicDisableVector(RTC_WKUP_IRQn); - nvicDisableVector(COMP_IRQn); -} - -#endif /* HAL_USE_EXT */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32F37x/ext_lld_isr.h b/os/hal/ports/STM32/STM32F37x/ext_lld_isr.h deleted file mode 100644 index 7761994be..000000000 --- a/os/hal/ports/STM32/STM32F37x/ext_lld_isr.h +++ /dev/null @@ -1,163 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F37x/ext_lld_isr.h - * @brief STM32F37x EXT subsystem low level driver ISR header. - * - * @addtogroup EXT - * @{ - */ - -#ifndef _EXT_LLD_ISR_H_ -#define _EXT_LLD_ISR_H_ - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief EXTI0 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI1 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI2 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI3 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI4 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI5..9 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI10..15 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI16 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI17 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI18 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI19 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI20 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI21..22 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI21_22_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void ext_lld_exti_irq_enable(void); - void ext_lld_exti_irq_disable(void); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EXT */ - -#endif /* _EXT_LLD_ISR_H_ */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32F37x/hal_adc_lld.c b/os/hal/ports/STM32/STM32F37x/hal_adc_lld.c new file mode 100644 index 000000000..5262c1ed8 --- /dev/null +++ b/os/hal/ports/STM32/STM32F37x/hal_adc_lld.c @@ -0,0 +1,735 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F37x/adc_lld.c + * @brief STM32F37x ADC subsystem low level driver source. + * + * @addtogroup ADC + * @{ + */ + +#include "hal.h" + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define SDADC_FORBIDDEN_CR1_FLAGS (SDADC_CR1_INIT | SDADC_CR1_RDMAEN | \ + SDADC_CR1_RSYNC | SDADC_CR1_JSYNC | \ + SDADC_CR1_ROVRIE | SDADC_CR1_REOCIE | \ + SDADC_CR1_JEOCIE | SDADC_CR1_EOCALIE) + +#define SDADC_ENFORCED_CR1_FLAGS (SDADC_CR1_JDMAEN | SDADC_CR1_JOVRIE) + +#define SDADC_FORBIDDEN_CR2_FLAGS (SDADC_CR2_RSWSTART | \ + SDADC_CR2_RCONT | \ + SDADC_CR2_RCH | \ + SDADC_CR2_JCONT | \ + SDADC_CR2_STARTCALIB | \ + SDADC_CR2_CALIBCNT) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief ADC1 driver identifier.*/ +#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) +ADCDriver ADCD1; +#endif + +/** @brief SDADC1 driver identifier.*/ +#if STM32_ADC_USE_SDADC1 || defined(__DOXYGEN__) +ADCDriver SDADCD1; +#endif + +/** @brief SDADC2 driver identifier.*/ +#if STM32_ADC_USE_SDADC2 || defined(__DOXYGEN__) +ADCDriver SDADCD2; +#endif + +/** @brief SDADC3 driver identifier.*/ +#if STM32_ADC_USE_SDADC3 || defined(__DOXYGEN__) +ADCDriver SDADCD3; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +static const ADCConfig adc_lld_default_config = { +#if STM32_ADC_USE_SDADC + 0, + { + 0, + 0, + 0 + } +#else /* !STM32_ADC_USE_SDADC */ + 0 +#endif /* !STM32_ADC_USE_SDADC */ +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Stops, reconfigures and restarts an ADC/SDADC. + * + * @param[in] adcp pointer to the @p ADCDriver object + */ +static void adc_lld_reconfig(ADCDriver *adcp) { + +#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC + if (adcp->adc != NULL) +#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ +#if STM32_ADC_USE_ADC + { + /* ADC initial setup, starting the analog part here in order to reduce + the latency when starting a conversion.*/ + uint32_t cr2 = adcp->adc->CR2 & ADC_CR2_TSVREFE; + adcp->adc->CR2 = cr2; + adcp->adc->CR1 = 0; + adcp->adc->CR2 = cr2 | ADC_CR2_ADON; + + } +#endif /* STM32_ADC_USE_ADC */ +#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC + else if (adcp->sdadc != NULL) +#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ +#if STM32_ADC_USE_SDADC + { + /* SDADC initial setup, starting the analog part here in order to reduce + the latency when starting a conversion.*/ + adcp->sdadc->CR2 = 0; + adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) & + ~SDADC_FORBIDDEN_CR1_FLAGS; + adcp->sdadc->CONF0R = (adcp->sdadc->CONF0R & SDADC_CONFR_OFFSET_MASK) | + adcp->config->confxr[0]; + adcp->sdadc->CONF1R = (adcp->sdadc->CONF1R & SDADC_CONFR_OFFSET_MASK) | + adcp->config->confxr[1]; + adcp->sdadc->CONF2R = (adcp->sdadc->CONF2R & SDADC_CONFR_OFFSET_MASK) | + adcp->config->confxr[2]; + adcp->sdadc->CR2 = SDADC_CR2_ADON; + } +#endif /* STM32_ADC_USE_SDADC */ +#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC +else { + osalDbgAssert(FALSE, "invalid state"); + } +#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ +} + +/** + * @brief ADC DMA ISR service routine. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] flags pre-shifted content of the ISR register + * + * @notapi + */ +static void adc_lld_serve_dma_interrupt(ADCDriver *adcp, uint32_t flags) { + + /* DMA errors handling.*/ + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + /* DMA, this could help only if the DMA tries to access an unmapped + address space or violates alignment rules.*/ + _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); + } + else { + /* It is possible that the conversion group has already be reset by the + ADC error handler, in this case this interrupt is spurious.*/ + if (adcp->grpp != NULL) { + if ((flags & STM32_DMA_ISR_TCIF) != 0) { + /* Transfer complete processing.*/ + _adc_isr_full_code(adcp); + } + else if ((flags & STM32_DMA_ISR_HTIF) != 0) { + /* Half transfer processing.*/ + _adc_isr_half_code(adcp); + } + } + } +} + +#if STM32_ADC_USE_ADC || defined(__DOXYGEN__) +/** + * @brief ADC ISR service routine. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] sr content of the ISR register + * + * @notapi + */ +static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t sr) { + + /* It could be a spurious interrupt caused by overflows after DMA disabling, + just ignore it in this case.*/ + if (adcp->grpp != NULL) { + if (sr & ADC_SR_AWD) { + /* Analog watchdog error.*/ + _adc_isr_error_code(adcp, ADC_ERR_AWD1); + } + } +} +#endif /* STM32_ADC_USE_ADC */ + +#if STM32_ADC_USE_SDADC || defined(__DOXYGEN__) +/** + * @brief ADC ISR service routine. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] isr content of the ISR register + * + * @notapi + */ +static void sdadc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) { + + /* It could be a spurious interrupt caused by overflows after DMA disabling, + just ignore it in this case.*/ + if (adcp->grpp != NULL) { + /* Note, an overflow may occur after the conversion ended before the driver + is able to stop the ADC, this is why the DMA channel is checked too.*/ + if ((isr & SDADC_ISR_JOVRF) && + (dmaStreamGetTransactionSize(adcp->dmastp) > 0)) { + /* ADC overflow condition, this could happen only if the DMA is unable + to read data fast enough.*/ + _adc_isr_error_code(adcp, ADC_ERR_OVERFLOW); + } + } +} +#endif /* STM32_ADC_USE_SDADC */ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) +/** + * @brief ADC1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector88) { + uint32_t sr; + + OSAL_IRQ_PROLOGUE(); + + sr = ADC1->SR; + ADC1->SR = 0; + adc_lld_serve_interrupt(&ADCD1, sr); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* STM32_ADC_USE_ADC1 */ + +#if STM32_ADC_USE_SDADC1 || defined(__DOXYGEN__) +/** + * @brief SDADC1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector134) { + uint32_t isr; + + OSAL_IRQ_PROLOGUE(); + + isr = SDADC1->ISR; + SDADC1->CLRISR = isr; + sdadc_lld_serve_interrupt(&SDADCD1, isr); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* STM32_ADC_USE_SDADC1 */ + +#if STM32_ADC_USE_SDADC2 || defined(__DOXYGEN__) +/** + * @brief SDADC2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector138) { + uint32_t isr; + + OSAL_IRQ_PROLOGUE(); + + isr = SDADC2->ISR; + SDADC2->CLRISR = isr; + sdadc_lld_serve_interrupt(&SDADCD2, isr); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* STM32_ADC_USE_SDADC2 */ + +#if STM32_ADC_USE_SDADC3 || defined(__DOXYGEN__) +/** + * @brief SDADC3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector13C) { + uint32_t isr; + + OSAL_IRQ_PROLOGUE(); + + isr = SDADC3->ISR; + SDADC3->CLRISR = isr; + sdadc_lld_serve_interrupt(&SDADCD3, isr); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* STM32_ADC_USE_SDADC3 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ADC driver initialization. + * + * @notapi + */ +void adc_lld_init(void) { + +#if STM32_ADC_USE_ADC1 + /* Driver initialization.*/ + adcObjectInit(&ADCD1); + ADCD1.adc = ADC1; +#if STM32_ADC_USE_SDADC + ADCD1.sdadc = NULL; +#endif + ADCD1.dmastp = STM32_DMA1_STREAM1; + ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + nvicEnableVector(ADC1_IRQn, STM32_ADC_ADC1_IRQ_PRIORITY); +#endif + +#if STM32_ADC_USE_SDADC1 + /* Driver initialization.*/ + adcObjectInit(&SDADCD1); +#if STM32_ADC_USE_ADC + SDADCD1.adc = NULL; +#endif + SDADCD1.sdadc = SDADC1; + SDADCD1.dmastp = STM32_DMA2_STREAM3; + SDADCD1.dmamode = STM32_DMA_CR_CHSEL(SDADC1_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_ADC_SDADC1_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + nvicEnableVector(SDADC1_IRQn, STM32_ADC_SDADC1_IRQ_PRIORITY); +#endif + +#if STM32_ADC_USE_SDADC2 + /* Driver initialization.*/ + adcObjectInit(&SDADCD2); +#if STM32_ADC_USE_ADC + SDADCD2.adc = NULL; +#endif + SDADCD2.sdadc = SDADC2; + SDADCD2.dmastp = STM32_DMA2_STREAM4; + SDADCD2.dmamode = STM32_DMA_CR_CHSEL(SDADC2_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_ADC_SDADC2_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + nvicEnableVector(SDADC2_IRQn, STM32_ADC_SDADC2_IRQ_PRIORITY); +#endif + +#if STM32_ADC_USE_SDADC3 + /* Driver initialization.*/ + adcObjectInit(&SDADCD3); +#if STM32_ADC_USE_ADC + SDADCD3.adc = NULL; +#endif + SDADCD3.sdadc = SDADC3; + SDADCD3.dmastp = STM32_DMA2_STREAM5; + SDADCD3.dmamode = STM32_DMA_CR_CHSEL(SDADC3_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_ADC_SDADC3_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + nvicEnableVector(SDADC3_IRQn, STM32_ADC_SDADC3_IRQ_PRIORITY); +#endif +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) { + + if (adcp->config == NULL) + adcp->config = &adc_lld_default_config; + + /* If in stopped state then enables the ADC and DMA clocks.*/ + if (adcp->state == ADC_STOP) { +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + bool b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_ADC1_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, + (void *)adcp); + osalDbgAssert(!b, "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); + rccEnableADC1(FALSE); + } +#endif /* STM32_ADC_USE_ADC1 */ + +#if STM32_ADC_USE_SDADC1 + if (&SDADCD1 == adcp) { + bool b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_SDADC1_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, + (void *)adcp); + osalDbgAssert(!b, "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &SDADC1->JDATAR); + rccEnableSDADC1(FALSE); + PWR->CR |= PWR_CR_SDADC1EN; + adcp->sdadc->CR2 = 0; + adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) & + ~SDADC_FORBIDDEN_CR1_FLAGS; + adcp->sdadc->CR2 = SDADC_CR2_ADON; + } +#endif /* STM32_ADC_USE_SDADC1 */ + +#if STM32_ADC_USE_SDADC2 + if (&SDADCD2 == adcp) { + bool b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_SDADC2_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, + (void *)adcp); + osalDbgAssert(!b, "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &SDADC2->JDATAR); + rccEnableSDADC2(FALSE); + PWR->CR |= PWR_CR_SDADC2EN; + adcp->sdadc->CR2 = 0; + adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) & + ~SDADC_FORBIDDEN_CR1_FLAGS; + adcp->sdadc->CR2 = SDADC_CR2_ADON; + } +#endif /* STM32_ADC_USE_SDADC2 */ + +#if STM32_ADC_USE_SDADC3 + if (&SDADCD3 == adcp) { + bool b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_SDADC3_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, + (void *)adcp); + osalDbgAssert(!b, "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &SDADC3->JDATAR); + rccEnableSDADC3(FALSE); + PWR->CR |= PWR_CR_SDADC3EN; + adcp->sdadc->CR2 = 0; + adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) & + ~SDADC_FORBIDDEN_CR1_FLAGS; + adcp->sdadc->CR2 = SDADC_CR2_ADON; + } +#endif /* STM32_ADC_USE_SDADC3 */ + } + + adc_lld_reconfig(adcp); +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) { + + /* If in ready state then disables the ADC clock.*/ + if (adcp->state == ADC_READY) { + dmaStreamRelease(adcp->dmastp); + +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + rccDisableADC1(FALSE); + } +#endif + +#if STM32_ADC_USE_SDADC1 + if (&SDADCD1 == adcp) { + adcp->sdadc->CR1 = 0; + adcp->sdadc->CR2 = 0; + rccDisableSDADC1(FALSE); + PWR->CR &= ~PWR_CR_SDADC1EN; + } +#endif + +#if STM32_ADC_USE_SDADC2 + if (&SDADCD2 == adcp) { + adcp->sdadc->CR1 = 0; + adcp->sdadc->CR2 = 0; + rccDisableSDADC2(FALSE); + PWR->CR &= ~PWR_CR_SDADC2EN; + } +#endif + +#if STM32_ADC_USE_SDADC3 + if (&SDADCD3 == adcp) { + adcp->sdadc->CR1 = 0; + adcp->sdadc->CR2 = 0; + rccDisableSDADC3(FALSE); + PWR->CR &= ~PWR_CR_SDADC3EN; + } +#endif + } +} + +/** + * @brief Starts an ADC conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) { + uint32_t mode; + const ADCConversionGroup* grpp = adcp->grpp; + + /* DMA setup.*/ + mode = adcp->dmamode; + if (grpp->circular) { + mode |= STM32_DMA_CR_CIRC; + if (adcp->depth > 1) { + /* If circular buffer depth > 1, then the half transfer interrupt + is enabled in order to allow streaming processing.*/ + mode |= STM32_DMA_CR_HTIE; + } + } + dmaStreamSetMemory0(adcp->dmastp, adcp->samples); + dmaStreamSetTransactionSize(adcp->dmastp, + (uint32_t)grpp->num_channels * + (uint32_t)adcp->depth); + dmaStreamSetMode(adcp->dmastp, mode); + dmaStreamEnable(adcp->dmastp); + +#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC + if (adcp->adc != NULL) +#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ +#if STM32_ADC_USE_ADC + { + uint32_t cr2 = adcp->adc->CR2 & ADC_CR2_TSVREFE; + cr2 |= grpp->u.adc.cr2 | ADC_CR2_DMA | ADC_CR2_ADON; + if ((cr2 & ADC_CR2_SWSTART) != 0) + cr2 |= ADC_CR2_CONT; + adcp->adc->CR2 = cr2; + + /* ADC setup.*/ + adcp->adc->SR = 0; + adcp->adc->LTR = grpp->u.adc.ltr; + adcp->adc->HTR = grpp->u.adc.htr; + adcp->adc->SMPR1 = grpp->u.adc.smpr[0]; + adcp->adc->SMPR2 = grpp->u.adc.smpr[1]; + adcp->adc->SQR1 = grpp->u.adc.sqr[0] | + ADC_SQR1_NUM_CH(grpp->num_channels); + adcp->adc->SQR2 = grpp->u.adc.sqr[1]; + adcp->adc->SQR3 = grpp->u.adc.sqr[2]; + + /* ADC conversion start, the start is performed using the method + specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/ + adcp->adc->CR1 = grpp->u.adc.cr1 | ADC_CR1_AWDIE | ADC_CR1_SCAN; + adcp->adc->CR2 = adcp->adc->CR2; /* Triggers the conversion start.*/ + } +#endif /* STM32_ADC_USE_ADC */ +#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC + else if (adcp->sdadc != NULL) +#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ +#if STM32_ADC_USE_SDADC + { + uint32_t cr2 = (grpp->u.sdadc.cr2 & ~SDADC_FORBIDDEN_CR2_FLAGS) | + SDADC_CR2_ADON; + if ((grpp->u.sdadc.cr2 & SDADC_CR2_JSWSTART) != 0) + cr2 |= SDADC_CR2_JCONT; + + /* Entering initialization mode.*/ + adcp->sdadc->CR1 |= SDADC_CR1_INIT; + while ((adcp->sdadc->ISR & SDADC_ISR_INITRDY) == 0) + ; + + /* SDADC setup.*/ + adcp->sdadc->JCHGR = grpp->u.sdadc.jchgr; + adcp->sdadc->CONFCHR1 = grpp->u.sdadc.confchr[0]; + adcp->sdadc->CONFCHR2 = grpp->u.sdadc.confchr[1]; + + /* SDADC trigger modes, this write must be performed when + SDADC_CR1_INIT=1.*/ + adcp->sdadc->CR2 = cr2; + + /* Leaving initialization mode.*/ + adcp->sdadc->CR1 &= ~SDADC_CR1_INIT; + + /* Special case, if SDADC_CR2_JSWSTART is specified it has to be + written after SDADC_CR1_INIT has been set to zero. Just a write is + performed, any other bit is ingore if not in initialization mode.*/ + adcp->sdadc->CR2 = cr2; + } +#endif /* STM32_ADC_USE_SDADC */ +#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC + else { + osalDbgAssert(FALSE, "invalid state"); + } +#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) { + + /* Disabling the associated DMA stream.*/ + dmaStreamDisable(adcp->dmastp); + + /* Stopping and restarting the whole ADC, apparently the only way to stop + a conversion.*/ + adc_lld_reconfig(adcp); +} + +/** + * @brief Calibrates an ADC unit. + * @note The calibration must be performed after calling @p adcStart(). + * @note For SDADC units it is assumed that the field SDADC_CR2_CALIBCNT + * has been + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @api + */ +void adcSTM32Calibrate(ADCDriver *adcp) { + + osalDbgAssert((adcp->state == ADC_READY) || + (adcp->state == ADC_COMPLETE) || + (adcp->state == ADC_ERROR), + "not ready"); + +#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC + if (adcp->adc != NULL) +#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ +#if STM32_ADC_USE_ADC + { + /* Resetting calibration just to be safe.*/ + ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL; + while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0) + ; + + /* Calibration.*/ + ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL; + while ((ADC1->CR2 & ADC_CR2_CAL) != 0) + ; + } +#endif /* STM32_ADC_USE_ADC */ +#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC + else if (adcp->sdadc != NULL) +#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ +#if STM32_ADC_USE_SDADC + { + /* Selecting a full calibration in three steps.*/ + adcp->sdadc->CR2 = (adcp->sdadc->CR2 & ~SDADC_CR2_CALIBCNT) | + SDADC_CR2_CALIBCNT_1; + + /* Calibration.*/ + adcp->sdadc->CR2 |= SDADC_CR2_STARTCALIB; + while ((adcp->sdadc->ISR & SDADC_ISR_EOCALF) == 0) + ; + + /* Clearing the EOCALF flag.*/ + adcp->sdadc->CLRISR |= SDADC_ISR_CLREOCALF; + } +#endif /* STM32_ADC_USE_SDADC */ +#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC + else { + osalDbgAssert(FALSE, "invalid state"); + } +#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */ +} + +#if STM32_ADC_USE_ADC || defined(__DOXYGEN__) +/** + * @brief Enables the TSVREFE bit. + * @details The TSVREFE bit is required in order to sample the internal + * temperature sensor and internal reference voltage. + * @note This is an STM32-only functionality. + * + * @api + */ +void adcSTM32EnableTSVREFE(void) { + + ADC1->CR2 |= ADC_CR2_TSVREFE; +} + +/** + * @brief Disables the TSVREFE bit. + * @details The TSVREFE bit is required in order to sample the internal + * temperature sensor and internal reference voltage. + * @note This is an STM32-only functionality. + * + * @api + */ +void adcSTM32DisableTSVREFE(void) { + + ADC1->CR2 &= ~ADC_CR2_TSVREFE; +} + +/** + * @brief Enables the VBATE bit. + * @details The VBATE bit is required in order to sample the VBAT channel. + * @note This is an STM32-only functionality. + * + * @api + */ +void adcSTM32EnableVBATE(void) { + + SYSCFG->CFGR1 |= SYSCFG_CFGR1_VBAT; +} + +/** + * @brief Disables the VBATE bit. + * @details The VBATE bit is required in order to sample the VBAT channel. + * @note This is an STM32-only functionality. + * + * @api + */ +void adcSTM32DisableVBATE(void) { + + SYSCFG->CFGR1 &= ~SYSCFG_CFGR1_VBAT; +} +#endif /* STM32_ADC_USE_ADC */ + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32F37x/hal_adc_lld.h b/os/hal/ports/STM32/STM32F37x/hal_adc_lld.h new file mode 100644 index 000000000..cb7281811 --- /dev/null +++ b/os/hal/ports/STM32/STM32F37x/hal_adc_lld.h @@ -0,0 +1,706 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F37x/adc_lld.h + * @brief STM32F37x ADC subsystem low level driver header. + * + * @addtogroup ADC + * @{ + */ + +#ifndef _ADC_LLD_H_ +#define _ADC_LLD_H_ + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Triggers selection + * @{ + */ +#define ADC_CR2_EXTSEL_SRC(n) ((n) << 24) /**< @brief Trigger source. */ +/** @} */ + +/** + * @name ADC clock divider settings + * @{ + */ +#define ADC_CCR_ADCPRE_DIV2 0 +#define ADC_CCR_ADCPRE_DIV4 1 +#define ADC_CCR_ADCPRE_DIV6 2 +#define ADC_CCR_ADCPRE_DIV8 3 +/** @} */ + +/** + * @name Available analog channels + * @{ + */ +#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ +#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ +#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ +#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ +#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ +#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ +#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ +#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ +#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ +#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ +#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ +#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ +#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ +#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ +#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ +#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ +#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/ +#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */ +#define ADC_CHANNEL_VBAT 18 /**< @brief VBAT. */ +/** @} */ + +/** + * @name Sampling rates + * @{ + */ +#define ADC_SAMPLE_1P5 0 /**< @brief 1.5 cycles sampling time. */ +#define ADC_SAMPLE_7P5 1 /**< @brief 7.5 cycles sampling time. */ +#define ADC_SAMPLE_13P5 2 /**< @brief 13.5 cycles sampling time. */ +#define ADC_SAMPLE_28P5 3 /**< @brief 28.5 cycles sampling time. */ +#define ADC_SAMPLE_41P5 4 /**< @brief 41.5 cycles sampling time. */ +#define ADC_SAMPLE_55P5 5 /**< @brief 55.5 cycles sampling time. */ +#define ADC_SAMPLE_71P5 6 /**< @brief 71.5 cycles sampling time. */ +#define ADC_SAMPLE_239P5 7 /**< @brief 239.5 cycles sampling time. */ +/** @} */ + +/** + * @name SDADC JCHGR bit definitions + * @{ + */ +#define SDADC_JCHG_MASK (511U << 0) +#define SDADC_JCHG(n) (1U << (n)) +/** @} */ + +/** + * @name SDADC channels definitions + * @{ + */ +#define SDADC_CHANNEL_0 SDADC_JCHG(0) +#define SDADC_CHANNEL_1 SDADC_JCHG(1) +#define SDADC_CHANNEL_2 SDADC_JCHG(2) +#define SDADC_CHANNEL_3 SDADC_JCHG(3) +#define SDADC_CHANNEL_4 SDADC_JCHG(4) +#define SDADC_CHANNEL_5 SDADC_JCHG(5) +#define SDADC_CHANNEL_6 SDADC_JCHG(6) +#define SDADC_CHANNEL_7 SDADC_JCHG(7) +#define SDADC_CHANNEL_8 SDADC_JCHG(8) +#define SDADC_CHANNEL_9 SDADC_JCHG(9) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ADC1 driver enable switch. + * @details If set to @p TRUE the support for ADC1 is included. + */ +#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) +#define STM32_ADC_USE_ADC1 FALSE +#endif + +/** + * @brief SDADC1 driver enable switch. + * @details If set to @p TRUE the support for SDADC1 is included. + */ +#if !defined(STM32_ADC_USE_SDADC1) || defined(__DOXYGEN__) +#define STM32_ADC_USE_SDADC1 FALSE +#endif + +/** + * @brief SDADC2 driver enable switch. + * @details If set to @p TRUE the support for SDADC2 is included. + */ +#if !defined(STM32_ADC_USE_SDADC2) || defined(__DOXYGEN__) +#define STM32_ADC_USE_SDADC2 FALSE +#endif + +/** + * @brief SDADC3 driver enable switch. + * @details If set to @p TRUE the support for SDADC3 is included. + */ +#if !defined(STM32_ADC_USE_SDADC3) || defined(__DOXYGEN__) +#define STM32_ADC_USE_SDADC3 FALSE +#endif + +/** + * @brief ADC1 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#endif + +/** + * @brief SDADC1 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_SDADC1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_SDADC1_DMA_PRIORITY 2 +#endif + +/** + * @brief SDADC2 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_SDADC2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_SDADC2_DMA_PRIORITY 2 +#endif + +/** + * @brief SDADC3 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_SDADC3_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_SDADC3_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#endif + +/** + * @brief ADC DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#endif + +/** + * @brief SDADC1 interrupt priority level setting. + */ +#if !defined(STM32_ADC_SDADC1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_SDADC1_IRQ_PRIORITY 5 +#endif + +/** + * @brief SDADC2 interrupt priority level setting. + */ +#if !defined(STM32_ADC_SDADC2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_SDADC2_IRQ_PRIORITY 5 +#endif + +/** + * @brief SDADC3 interrupt priority level setting. + */ +#if !defined(STM32_ADC_SDADC3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_SDADC3_IRQ_PRIORITY 5 +#endif + +/** + * @brief SDADC1 DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_SDADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_SDADC1_DMA_IRQ_PRIORITY 5 +#endif + +/** + * @brief SDADC2 DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_SDADC2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_SDADC2_DMA_IRQ_PRIORITY 5 +#endif + +/** + * @brief SDADC3 DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_SDADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_SDADC3_DMA_IRQ_PRIORITY 5 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/** + * @brief At least an ADC unit is in use. + */ +#define STM32_ADC_USE_ADC STM32_ADC_USE_ADC1 + +/** + * @brief At least an SDADC unit is in use. + */ +#define STM32_ADC_USE_SDADC (STM32_ADC_USE_SDADC1 || \ + STM32_ADC_USE_SDADC2 || \ + STM32_ADC_USE_SDADC3) + +#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 +#error "ADC1 not present in the selected device" +#endif + +#if STM32_ADC_USE_SDADC1 && !STM32_HAS_SDADC1 +#error "SDADC1 not present in the selected device" +#endif + +#if STM32_ADC_USE_SDADC2 && !STM32_HAS_SDADC2 +#error "SDADC2 not present in the selected device" +#endif + +#if STM32_ADC_USE_SDADC3 && !STM32_HAS_SDADC3 +#error "SDADC3 not present in the selected device" +#endif + +#if !STM32_ADC_USE_ADC && !STM32_ADC_USE_SDADC +#error "ADC driver activated but no ADC/SDADC peripheral assigned" +#endif + +#if STM32_ADC_USE_ADC1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to ADC1" +#endif + +#if STM32_ADC_USE_ADC1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to ADC1 DMA" +#endif + +#if STM32_ADC_USE_ADC1 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY) +#error "Invalid DMA priority assigned to ADC1" +#endif + +#if STM32_ADC_USE_SDADC1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SDADC1" +#endif + +#if STM32_ADC_USE_SDADC1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC1_DMA_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SDADC1 DMA" +#endif + +#if STM32_ADC_USE_SDADC1 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_SDADC1_DMA_PRIORITY) +#error "Invalid DMA priority assigned to SDADC1" +#endif + +#if STM32_ADC_USE_SDADC2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SDADC2" +#endif + +#if STM32_ADC_USE_SDADC2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC2_DMA_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SDADC2 DMA" +#endif + +#if STM32_ADC_USE_SDADC2 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_SDADC2_DMA_PRIORITY) +#error "Invalid DMA priority assigned to SDADC2" +#endif + +#if STM32_ADC_USE_SDADC3 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SDADC3" +#endif + +#if STM32_ADC_USE_SDADC3 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_SDADC3_DMA_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SDADC3 DMA" +#endif + +#if STM32_ADC_USE_SDADC3 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_SDADC3_DMA_PRIORITY) +#error "Invalid DMA priority assigned to SDADC3" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ADC sample data type. + */ +typedef uint16_t adcsample_t; + +/** + * @brief Channels number in a conversion group. + */ +typedef uint16_t adc_channels_num_t; + +/** + * @brief Possible ADC failure causes. + * @note Error codes are architecture dependent and should not relied + * upon. + */ +typedef enum { + ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */ + ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */ + ADC_ERR_AWD1 = 2 /**< Watchdog 1 triggered. */ +} adcerror_t; + +/** + * @brief Type of a structure representing an ADC driver. + */ +typedef struct ADCDriver ADCDriver; + +/** + * @brief ADC notification callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] buffer pointer to the most recent samples data + * @param[in] n number of buffer rows available starting from @p buffer + */ +typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); + +/** + * @brief ADC error callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] err ADC error code + */ +typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); + +/** + * @brief Conversion group configuration structure. + * @details This implementation-dependent structure describes a conversion + * operation. + * @note The use of this configuration structure requires knowledge of + * STM32 ADC cell registers interface, please refer to the STM32 + * reference manual for details. + */ +typedef struct { + /** + * @brief Enables the circular buffer mode for the group. + */ + bool circular; + /** + * @brief Number of the analog channels belonging to the conversion group. + */ + adc_channels_num_t num_channels; + /** + * @brief Callback function associated to the group or @p NULL. + */ + adccallback_t end_cb; + /** + * @brief Error callback or @p NULL. + */ + adcerrorcallback_t error_cb; + /* End of the mandatory fields.*/ + + /** + * @brief Union of ADC and SDADC config parms. The decision of which struct + * union to use is determined by the ADCDriver. If the ADCDriver adc parm + * is not NULL, then use the adc struct, otherwise if the ADCDriver sdadc parm + * is not NULL, then use the sdadc struct. + */ + union { +#if STM32_ADC_USE_ADC || defined(__DOXYGEN__) + struct { + /** + * @brief ADC CR1 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR1_SCAN that is enforced inside the driver. + */ + uint32_t cr1; + /** + * @brief ADC CR2 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are + * enforced inside the driver. + */ + uint32_t cr2; + /** + * @brief ADC LTR register initialization data. + */ + uint32_t ltr; + /** + * @brief ADC HTR register initialization data. + */ + uint32_t htr; + /** + * @brief ADC SMPRx registers initialization data. + */ + uint32_t smpr[2]; + /** + * @brief ADC SQRx register initialization data. + */ + uint32_t sqr[3]; + } adc; +#endif /* STM32_ADC_USE_ADC */ +#if STM32_ADC_USE_SDADC || defined(__DOXYGEN__) + struct { + /** + * @brief SDADC CR2 register initialization data. + * @note Only the @p SDADC_CR2_JSWSTART, @p SDADC_CR2_JEXTSEL + * and @p SDADC_CR2_JEXTEN can be specified in this field. + */ + uint32_t cr2; + /** + * @brief SDADC JCHGR register initialization data. + */ + uint32_t jchgr; + /** + * @brief SDADC CONFCHxR registers initialization data. + */ + uint32_t confchr[2]; + } sdadc; +#endif /* STM32_ADC_USE_SDADC */ + } u; +} ADCConversionGroup; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { +#if STM32_ADC_USE_SDADC + /** + * @brief SDADC CR1 register initialization data. + */ + uint32_t cr1; + /** + * @brief SDADC CONFxR registers initialization data. + */ + uint32_t confxr[3]; +#else /* !STM32_ADC_USE_SDADC */ + uint32_t dummy; +#endif /* !STM32_ADC_USE_SDADC */ +} ADCConfig; + +/** + * @brief Structure representing an ADC driver. + */ +struct ADCDriver { + /** + * @brief Driver state. + */ + adcstate_t state; + /** + * @brief Current configuration data. + */ + const ADCConfig *config; + /** + * @brief Current samples buffer pointer or @p NULL. + */ + adcsample_t *samples; + /** + * @brief Current samples buffer depth or @p 0. + */ + size_t depth; + /** + * @brief Current conversion group pointer or @p NULL. + */ + const ADCConversionGroup *grpp; +#if ADC_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + thread_reference_t thread; +#endif +#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + mutex_t mutex; +#endif /* ADC_USE_MUTUAL_EXCLUSION */ +#if defined(ADC_DRIVER_EXT_FIELDS) + ADC_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ +#if STM32_ADC_USE_ADC || defined(__DOXYGEN__) + /** + * @brief Pointer to the ADCx registers block. + */ + ADC_TypeDef *adc; +#endif +#if STM32_ADC_USE_SDADC || defined(__DOXYGEN__) + /** + * @brief Pointer to the SDADCx registers block. + */ + SDADC_TypeDef *sdadc; +#endif + /** + * @brief Pointer to associated DMA channel. + */ + const stm32_dma_stream_t *dmastp; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Sequences building helper macros for ADC + * @{ + */ +/** + * @brief Number of channels in a conversion sequence. + */ +#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20) +#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ +#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ +#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ +#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ + +#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ +#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ +#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ +#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ +#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ +#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ + +#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ +#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ +#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ +#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ +#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ +#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ +/** @} */ + +/** + * @name Sampling rate settings helper macros + * @{ + */ +#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ +#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ +#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ +#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ +#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ +#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ +#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ +#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ +#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ +#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ + +#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ +#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ +#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ +#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ +#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ +#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ +#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor + sampling time. */ +#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference + sampling time. */ +#define ADC_SMPR1_SMP_VBAT(n) ((n) << 24) /**< @brief VBAT sampling time. */ +/** @} */ + +/** + * @name Sequences building helper macros for SDADC + * @{ + */ +#define SDADC_JCHGR_CH(n) (1U << (n)) +/** @} */ + +/** + * @name Channel configuration number helper macros for SDADC + * @{ + */ +#define SDADC_CONFCHR1_CH0(n) ((n) << 0) +#define SDADC_CONFCHR1_CH1(n) ((n) << 4) +#define SDADC_CONFCHR1_CH2(n) ((n) << 8) +#define SDADC_CONFCHR1_CH3(n) ((n) << 12) +#define SDADC_CONFCHR1_CH4(n) ((n) << 16) +#define SDADC_CONFCHR1_CH5(n) ((n) << 20) +#define SDADC_CONFCHR1_CH6(n) ((n) << 24) +#define SDADC_CONFCHR1_CH7(n) ((n) << 28) +#define SDADC_CONFCHR2_CH8(n) ((n) << 0) +/** @} */ + +/** + * @name Configuration registers helper macros for SDADC + * @{ + */ +#define SDADC_CONFR_OFFSET_MASK (0xFFFU << 0) +#define SDADC_CONFR_OFFSET(n) ((n) << 0) +#define SDADC_CONFR_GAIN_MASK (7U << 20) +#define SDADC_CONFR_GAIN_1X (0U << 20) +#define SDADC_CONFR_GAIN_2X (1U << 20) +#define SDADC_CONFR_GAIN_4X (2U << 20) +#define SDADC_CONFR_GAIN_8X (3U << 20) +#define SDADC_CONFR_GAIN_16X (4U << 20) +#define SDADC_CONFR_GAIN_32X (5U << 20) +#define SDADC_CONFR_GAIN_0P5X (7U << 20) +#define SDADC_CONFR_SE_MASK (3U << 26) +#define SDADC_CONFR_SE_DIFF (0U << 26) +#define SDADC_CONFR_SE_OFFSET (1U << 26) +#define SDADC_CONFR_SE_ZERO_VOLT (3U << 26) +#define SDADC_CONFR_COMMON_MASK (3U << 30) +#define SDADC_CONFR_COMMON_VSSSD (0U << 30) +#define SDADC_CONFR_COMMON_VDDSD2 (1U << 30) +#define SDADC_CONFR_COMMON_VDDSD (2U << 30) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) +extern ADCDriver ADCD1; +#endif + +#if STM32_ADC_USE_SDADC1 && !defined(__DOXYGEN__) +extern ADCDriver SDADCD1; +#endif + +#if STM32_ADC_USE_SDADC2 && !defined(__DOXYGEN__) +extern ADCDriver SDADCD2; +#endif + +#if STM32_ADC_USE_SDADC3 && !defined(__DOXYGEN__) +extern ADCDriver SDADCD3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void adc_lld_init(void); + void adc_lld_start(ADCDriver *adcp); + void adc_lld_stop(ADCDriver *adcp); + void adc_lld_start_conversion(ADCDriver *adcp); + void adc_lld_stop_conversion(ADCDriver *adcp); + void adcSTM32Calibrate(ADCDriver *adcdp); +#if STM32_ADC_USE_ADC + void adcSTM32EnableTSVREFE(void); + void adcSTM32DisableTSVREFE(void); + void adcSTM32EnableVBATE(void); + void adcSTM32DisableVBATE(void); +#endif /* STM32_ADC_USE_ADC */ +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC */ + +#endif /* _ADC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32F37x/hal_ext_lld_isr.c b/os/hal/ports/STM32/STM32F37x/hal_ext_lld_isr.c new file mode 100644 index 000000000..aa8c3208a --- /dev/null +++ b/os/hal/ports/STM32/STM32F37x/hal_ext_lld_isr.c @@ -0,0 +1,400 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F37x/ext_lld_isr.c + * @brief STM32F37x EXT subsystem low level driver ISR code. + * + * @addtogroup EXT + * @{ + */ + +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +#include "hal_ext_lld_isr.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if !defined(STM32_DISABLE_EXTI0_HANDLER) +/** + * @brief EXTI[0] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector58) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 0); + EXTI->PR = pr; + if (pr & (1U << 0)) + EXTD1.config->channels[0].cb(&EXTD1, 0); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI1_HANDLER) +/** + * @brief EXTI[1] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector5C) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 1); + EXTI->PR = pr; + if (pr & (1U << 1)) + EXTD1.config->channels[1].cb(&EXTD1, 1); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI2_HANDLER) +/** + * @brief EXTI[2] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector60) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 2); + EXTI->PR = pr; + if (pr & (1U << 2)) + EXTD1.config->channels[2].cb(&EXTD1, 2); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI3_HANDLER) +/** + * @brief EXTI[3] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector64) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 3); + EXTI->PR = pr; + if (pr & (1U << 3)) + EXTD1.config->channels[3].cb(&EXTD1, 3); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI4_HANDLER) +/** + * @brief EXTI[4] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector68) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 4); + EXTI->PR = pr; + if (pr & (1U << 4)) + EXTD1.config->channels[4].cb(&EXTD1, 4); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI5_9_HANDLER) +/** + * @brief EXTI[5]...EXTI[9] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector9C) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) | + (1U << 9)); + EXTI->PR = pr; + if (pr & (1U << 5)) + EXTD1.config->channels[5].cb(&EXTD1, 5); + if (pr & (1U << 6)) + EXTD1.config->channels[6].cb(&EXTD1, 6); + if (pr & (1U << 7)) + EXTD1.config->channels[7].cb(&EXTD1, 7); + if (pr & (1U << 8)) + EXTD1.config->channels[8].cb(&EXTD1, 8); + if (pr & (1U << 9)) + EXTD1.config->channels[9].cb(&EXTD1, 9); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI10_15_HANDLER) +/** + * @brief EXTI[10]...EXTI[15] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(VectorE0) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) | + (1U << 14) | (1U << 15)); + EXTI->PR = pr; + if (pr & (1U << 10)) + EXTD1.config->channels[10].cb(&EXTD1, 10); + if (pr & (1U << 11)) + EXTD1.config->channels[11].cb(&EXTD1, 11); + if (pr & (1U << 12)) + EXTD1.config->channels[12].cb(&EXTD1, 12); + if (pr & (1U << 13)) + EXTD1.config->channels[13].cb(&EXTD1, 13); + if (pr & (1U << 14)) + EXTD1.config->channels[14].cb(&EXTD1, 14); + if (pr & (1U << 15)) + EXTD1.config->channels[15].cb(&EXTD1, 15); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI16_HANDLER) +/** + * @brief EXTI[16] interrupt handler (PVD). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector44) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 16); + EXTI->PR = pr; + if (pr & (1U << 16)) + EXTD1.config->channels[16].cb(&EXTD1, 16); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI17_HANDLER) +/** + * @brief EXTI[17] interrupt handler (RTC Alarm). + * + * @isr + */ +OSAL_IRQ_HANDLER(VectorE4) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 17); + EXTI->PR = pr; + if (pr & (1U << 17)) + EXTD1.config->channels[17].cb(&EXTD1, 17); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if STM32_HAS_USB && !defined(STM32_DISABLE_EXTI18_HANDLER) +/** + * @brief EXTI[18] interrupt handler (USB Wakeup). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector170) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 18); + EXTI->PR = pr; + if (pr & (1U << 18)) + EXTD1.config->channels[18].cb(&EXTD1, 18); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI19_HANDLER) +/** + * @brief EXTI[19] interrupt handler (Tamper TimeStamp). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector48) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 19); + EXTI->PR = pr; + if (pr & (1U << 19)) + EXTD1.config->channels[19].cb(&EXTD1, 19); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI20_HANDLER) +/** + * @brief EXTI[20] interrupt handler (RTC Wakeup). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector4C) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 20); + EXTI->PR = pr; + if (pr & (1U << 20)) + EXTD1.config->channels[20].cb(&EXTD1, 20); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI21_22_HANDLER) +/** + * @brief EXTI[21]..EXTI[22] interrupt handler (COMP1, COMP2). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector140) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & ((1U << 21) | (1U << 22)); + EXTI->PR = pr; + if (pr & (1U << 21)) + EXTD1.config->channels[21].cb(&EXTD1, 21); + if (pr & (1U << 22)) + EXTD1.config->channels[22].cb(&EXTD1, 22); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_enable(void) { + + nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY); + nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY); + nvicEnableVector(EXTI2_TSC_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY); + nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY); + nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY); + nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY); + nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY); + nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY); + nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY); +#if STM32_HAS_USB + nvicEnableVector(USBWakeUp_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY); +#endif + nvicEnableVector(TAMP_STAMP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY); + nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY); + nvicEnableVector(COMP_IRQn, STM32_EXT_EXTI21_22_IRQ_PRIORITY); +} + +/** + * @brief Disables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_disable(void) { + + nvicDisableVector(EXTI0_IRQn); + nvicDisableVector(EXTI1_IRQn); + nvicDisableVector(EXTI2_TSC_IRQn); + nvicDisableVector(EXTI3_IRQn); + nvicDisableVector(EXTI4_IRQn); + nvicDisableVector(EXTI9_5_IRQn); + nvicDisableVector(EXTI15_10_IRQn); + nvicDisableVector(PVD_IRQn); + nvicDisableVector(RTC_Alarm_IRQn); +#if STM32_HAS_USB + nvicDisableVector(USBWakeUp_IRQn); +#endif + nvicDisableVector(TAMP_STAMP_IRQn); + nvicDisableVector(RTC_WKUP_IRQn); + nvicDisableVector(COMP_IRQn); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32F37x/hal_ext_lld_isr.h b/os/hal/ports/STM32/STM32F37x/hal_ext_lld_isr.h new file mode 100644 index 000000000..7761994be --- /dev/null +++ b/os/hal/ports/STM32/STM32F37x/hal_ext_lld_isr.h @@ -0,0 +1,163 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F37x/ext_lld_isr.h + * @brief STM32F37x EXT subsystem low level driver ISR header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_ISR_H_ +#define _EXT_LLD_ISR_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief EXTI0 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI1 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI2 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI3 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI4 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI5..9 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI10..15 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI16 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI17 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI18 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI19 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI20 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI21..22 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI21_22_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_exti_irq_enable(void); + void ext_lld_exti_irq_disable(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_ISR_H_ */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32F37x/platform.mk b/os/hal/ports/STM32/STM32F37x/platform.mk index 54317b687..507295b71 100644 --- a/os/hal/ports/STM32/STM32F37x/platform.mk +++ b/os/hal/ports/STM32/STM32F37x/platform.mk @@ -5,74 +5,74 @@ HALCONF := $(strip $(shell cat halconf.h | egrep -e "define")) PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/hal_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/adc_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/hal_adc_lld.c endif ifneq ($(findstring HAL_USE_CAN TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c endif ifneq ($(findstring HAL_USE_DAC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c endif ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/ext_lld_isr.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/hal_ext_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/hal_ext_lld_isr.c endif ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c endif ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.c endif ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c endif ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.c endif ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c endif ifneq ($(findstring HAL_USE_ICU TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c endif ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c endif ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c endif ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/uart_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c endif ifneq ($(findstring HAL_USE_USB TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/usb_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c endif ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c endif else PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/hal_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/adc_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/ext_lld_isr.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/hal_adc_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/hal_ext_lld_isr.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/uart_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/usb_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.c + $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/hal_ext_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c endif # Required include directories diff --git a/os/hal/ports/STM32/STM32F3xx/ext_lld_isr.c b/os/hal/ports/STM32/STM32F3xx/ext_lld_isr.c deleted file mode 100644 index 262cb4942..000000000 --- a/os/hal/ports/STM32/STM32F3xx/ext_lld_isr.c +++ /dev/null @@ -1,459 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F3xx/ext_lld_isr.c - * @brief STM32F3xx EXT subsystem low level driver ISR code. - * - * @addtogroup EXT - * @{ - */ - -#include "hal.h" - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -#include "ext_lld_isr.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if !defined(STM32_DISABLE_EXTI0_HANDLER) -/** - * @brief EXTI[0] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector58) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 0); - EXTI->PR = pr; - if (pr & (1U << 0)) - EXTD1.config->channels[0].cb(&EXTD1, 0); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI1_HANDLER) -/** - * @brief EXTI[1] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector5C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 1); - EXTI->PR = pr; - if (pr & (1U << 1)) - EXTD1.config->channels[1].cb(&EXTD1, 1); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI2_HANDLER) -/** - * @brief EXTI[2] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector60) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 2); - EXTI->PR = pr; - if (pr & (1U << 2)) - EXTD1.config->channels[2].cb(&EXTD1, 2); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI3_HANDLER) -/** - * @brief EXTI[3] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector64) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 3); - EXTI->PR = pr; - if (pr & (1U << 3)) - EXTD1.config->channels[3].cb(&EXTD1, 3); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI4_HANDLER) -/** - * @brief EXTI[4] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector68) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 4); - EXTI->PR = pr; - if (pr & (1U << 4)) - EXTD1.config->channels[4].cb(&EXTD1, 4); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI5_9_HANDLER) -/** - * @brief EXTI[5]...EXTI[9] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector9C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) | - (1U << 9)); - EXTI->PR = pr; - if (pr & (1U << 5)) - EXTD1.config->channels[5].cb(&EXTD1, 5); - if (pr & (1U << 6)) - EXTD1.config->channels[6].cb(&EXTD1, 6); - if (pr & (1U << 7)) - EXTD1.config->channels[7].cb(&EXTD1, 7); - if (pr & (1U << 8)) - EXTD1.config->channels[8].cb(&EXTD1, 8); - if (pr & (1U << 9)) - EXTD1.config->channels[9].cb(&EXTD1, 9); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI10_15_HANDLER) -/** - * @brief EXTI[10]...EXTI[15] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorE0) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) | - (1U << 14) | (1U << 15)); - EXTI->PR = pr; - if (pr & (1U << 10)) - EXTD1.config->channels[10].cb(&EXTD1, 10); - if (pr & (1U << 11)) - EXTD1.config->channels[11].cb(&EXTD1, 11); - if (pr & (1U << 12)) - EXTD1.config->channels[12].cb(&EXTD1, 12); - if (pr & (1U << 13)) - EXTD1.config->channels[13].cb(&EXTD1, 13); - if (pr & (1U << 14)) - EXTD1.config->channels[14].cb(&EXTD1, 14); - if (pr & (1U << 15)) - EXTD1.config->channels[15].cb(&EXTD1, 15); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI16_HANDLER) -/** - * @brief EXTI[16] interrupt handler (PVD). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector44) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 16); - EXTI->PR = pr; - if (pr & (1U << 16)) - EXTD1.config->channels[16].cb(&EXTD1, 16); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI17_HANDLER) -/** - * @brief EXTI[17] interrupt handler (RTC Alarm). - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorE4) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 17); - EXTI->PR = pr; - if (pr & (1U << 17)) - EXTD1.config->channels[17].cb(&EXTD1, 17); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI18_HANDLER) && STM32_HAS_USB -/** - * @brief EXTI[18] interrupt handler (USB Wakeup). - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorE8) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 18); - EXTI->PR = pr; - if (pr & (1U << 18)) - EXTD1.config->channels[18].cb(&EXTD1, 18); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI19_HANDLER) -/** - * @brief EXTI[19] interrupt handler (Tamper TimeStamp). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector48) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 19); - EXTI->PR = pr; - if (pr & (1U << 19)) - EXTD1.config->channels[19].cb(&EXTD1, 19); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI20_HANDLER) -/** - * @brief EXTI[20] interrupt handler (RTC Wakeup). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector4C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 20); - EXTI->PR = pr; - if (pr & (1U << 20)) - EXTD1.config->channels[20].cb(&EXTD1, 20); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI21_22_29_HANDLER) -/** - * @brief EXTI[21],EXTI[22],EXTI[29] interrupt handler (COMP1, COMP2, COMP3). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector140) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & ((1U << 21) | (1U << 22) | (1U << 29)); - EXTI->PR = pr; - if (pr & (1U << 21)) - EXTD1.config->channels[21].cb(&EXTD1, 21); - if (pr & (1U << 22)) - EXTD1.config->channels[22].cb(&EXTD1, 22); - if (pr & (1U << 29)) - EXTD1.config->channels[29].cb(&EXTD1, 29); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI30_32_HANDLER) -/** - * @brief EXTI[30]...EXTI[32] interrupt handler (COMP4, COMP5, COMP6). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector144) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & ((1U << 30) | (1U << 31)); - EXTI->PR = pr; - if (pr & (1U << 30)) - EXTD1.config->channels[30].cb(&EXTD1, 30); - if (pr & (1U << 31)) - EXTD1.config->channels[31].cb(&EXTD1, 31); - - pr = EXTI->PR2 & EXTI->IMR2 & (1U << 0); - EXTI->PR2 = pr; - if (pr & (1U << 0)) - EXTD1.config->channels[32].cb(&EXTD1, 32); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI33_HANDLER) -/** - * @brief EXTI[33] interrupt handler (COMP7). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector148) { - uint32_t pr2; - - OSAL_IRQ_PROLOGUE(); - - pr2 = EXTI->PR2; - pr2 = EXTI->IMR & (1U << 1); - EXTI->PR2 = pr2; - if (pr2 & (1U << 1)) - EXTD1.config->channels[33].cb(&EXTD1, 33); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Enables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_enable(void) { - - nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY); - nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY); - nvicEnableVector(EXTI2_TSC_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY); - nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY); - nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY); - nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY); - nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY); - nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY); - nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY); -#if STM32_HAS_USB - nvicEnableVector(USBWakeUp_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY); -#endif - nvicEnableVector(TAMP_STAMP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY); - nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY); - nvicEnableVector(COMP1_2_3_IRQn, STM32_EXT_EXTI21_22_29_IRQ_PRIORITY); - nvicEnableVector(COMP4_5_6_IRQn, STM32_EXT_EXTI30_32_IRQ_PRIORITY); -#if STM32_EXTI_NUM_LINES >= 34 - nvicEnableVector(COMP7_IRQn, STM32_EXT_EXTI33_IRQ_PRIORITY); -#endif -} - -/** - * @brief Disables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_disable(void) { - - nvicDisableVector(EXTI0_IRQn); - nvicDisableVector(EXTI1_IRQn); - nvicDisableVector(EXTI2_TSC_IRQn); - nvicDisableVector(EXTI3_IRQn); - nvicDisableVector(EXTI4_IRQn); - nvicDisableVector(EXTI9_5_IRQn); - nvicDisableVector(EXTI15_10_IRQn); - nvicDisableVector(PVD_IRQn); - nvicDisableVector(RTC_Alarm_IRQn); -#if STM32_HAS_USB - nvicDisableVector(USBWakeUp_IRQn); -#endif - nvicDisableVector(TAMP_STAMP_IRQn); - nvicDisableVector(RTC_WKUP_IRQn); - nvicDisableVector(COMP1_2_3_IRQn); - nvicDisableVector(COMP4_5_6_IRQn); -#if STM32_EXTI_NUM_LINES >= 34 - nvicDisableVector(COMP7_IRQn); -#endif -} - -#endif /* HAL_USE_EXT */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32F3xx/ext_lld_isr.h b/os/hal/ports/STM32/STM32F3xx/ext_lld_isr.h deleted file mode 100644 index d667f9c30..000000000 --- a/os/hal/ports/STM32/STM32F3xx/ext_lld_isr.h +++ /dev/null @@ -1,177 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F3xx/ext_lld_isr.h - * @brief STM32F3xx EXT subsystem low level driver ISR header. - * - * @addtogroup EXT - * @{ - */ - -#ifndef _EXT_LLD_ISR_H_ -#define _EXT_LLD_ISR_H_ - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief EXTI0 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI1 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI2 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI3 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI4 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI5..9 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI10..15 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI16 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI17 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI18 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI19 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI20 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI21,22,29 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI21_22_29_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI21_22_29_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI30..32 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI30_32_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI33 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI33_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void ext_lld_exti_irq_enable(void); - void ext_lld_exti_irq_disable(void); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EXT */ - -#endif /* _EXT_LLD_ISR_H_ */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.c b/os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.c new file mode 100644 index 000000000..52e5041c4 --- /dev/null +++ b/os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.c @@ -0,0 +1,459 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F3xx/ext_lld_isr.c + * @brief STM32F3xx EXT subsystem low level driver ISR code. + * + * @addtogroup EXT + * @{ + */ + +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +#include "hal_ext_lld_isr.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if !defined(STM32_DISABLE_EXTI0_HANDLER) +/** + * @brief EXTI[0] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector58) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 0); + EXTI->PR = pr; + if (pr & (1U << 0)) + EXTD1.config->channels[0].cb(&EXTD1, 0); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI1_HANDLER) +/** + * @brief EXTI[1] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector5C) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 1); + EXTI->PR = pr; + if (pr & (1U << 1)) + EXTD1.config->channels[1].cb(&EXTD1, 1); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI2_HANDLER) +/** + * @brief EXTI[2] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector60) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 2); + EXTI->PR = pr; + if (pr & (1U << 2)) + EXTD1.config->channels[2].cb(&EXTD1, 2); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI3_HANDLER) +/** + * @brief EXTI[3] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector64) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 3); + EXTI->PR = pr; + if (pr & (1U << 3)) + EXTD1.config->channels[3].cb(&EXTD1, 3); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI4_HANDLER) +/** + * @brief EXTI[4] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector68) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 4); + EXTI->PR = pr; + if (pr & (1U << 4)) + EXTD1.config->channels[4].cb(&EXTD1, 4); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI5_9_HANDLER) +/** + * @brief EXTI[5]...EXTI[9] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector9C) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) | + (1U << 9)); + EXTI->PR = pr; + if (pr & (1U << 5)) + EXTD1.config->channels[5].cb(&EXTD1, 5); + if (pr & (1U << 6)) + EXTD1.config->channels[6].cb(&EXTD1, 6); + if (pr & (1U << 7)) + EXTD1.config->channels[7].cb(&EXTD1, 7); + if (pr & (1U << 8)) + EXTD1.config->channels[8].cb(&EXTD1, 8); + if (pr & (1U << 9)) + EXTD1.config->channels[9].cb(&EXTD1, 9); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI10_15_HANDLER) +/** + * @brief EXTI[10]...EXTI[15] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(VectorE0) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) | + (1U << 14) | (1U << 15)); + EXTI->PR = pr; + if (pr & (1U << 10)) + EXTD1.config->channels[10].cb(&EXTD1, 10); + if (pr & (1U << 11)) + EXTD1.config->channels[11].cb(&EXTD1, 11); + if (pr & (1U << 12)) + EXTD1.config->channels[12].cb(&EXTD1, 12); + if (pr & (1U << 13)) + EXTD1.config->channels[13].cb(&EXTD1, 13); + if (pr & (1U << 14)) + EXTD1.config->channels[14].cb(&EXTD1, 14); + if (pr & (1U << 15)) + EXTD1.config->channels[15].cb(&EXTD1, 15); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI16_HANDLER) +/** + * @brief EXTI[16] interrupt handler (PVD). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector44) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 16); + EXTI->PR = pr; + if (pr & (1U << 16)) + EXTD1.config->channels[16].cb(&EXTD1, 16); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI17_HANDLER) +/** + * @brief EXTI[17] interrupt handler (RTC Alarm). + * + * @isr + */ +OSAL_IRQ_HANDLER(VectorE4) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 17); + EXTI->PR = pr; + if (pr & (1U << 17)) + EXTD1.config->channels[17].cb(&EXTD1, 17); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI18_HANDLER) && STM32_HAS_USB +/** + * @brief EXTI[18] interrupt handler (USB Wakeup). + * + * @isr + */ +OSAL_IRQ_HANDLER(VectorE8) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 18); + EXTI->PR = pr; + if (pr & (1U << 18)) + EXTD1.config->channels[18].cb(&EXTD1, 18); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI19_HANDLER) +/** + * @brief EXTI[19] interrupt handler (Tamper TimeStamp). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector48) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 19); + EXTI->PR = pr; + if (pr & (1U << 19)) + EXTD1.config->channels[19].cb(&EXTD1, 19); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI20_HANDLER) +/** + * @brief EXTI[20] interrupt handler (RTC Wakeup). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector4C) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 20); + EXTI->PR = pr; + if (pr & (1U << 20)) + EXTD1.config->channels[20].cb(&EXTD1, 20); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI21_22_29_HANDLER) +/** + * @brief EXTI[21],EXTI[22],EXTI[29] interrupt handler (COMP1, COMP2, COMP3). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector140) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & ((1U << 21) | (1U << 22) | (1U << 29)); + EXTI->PR = pr; + if (pr & (1U << 21)) + EXTD1.config->channels[21].cb(&EXTD1, 21); + if (pr & (1U << 22)) + EXTD1.config->channels[22].cb(&EXTD1, 22); + if (pr & (1U << 29)) + EXTD1.config->channels[29].cb(&EXTD1, 29); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI30_32_HANDLER) +/** + * @brief EXTI[30]...EXTI[32] interrupt handler (COMP4, COMP5, COMP6). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector144) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & ((1U << 30) | (1U << 31)); + EXTI->PR = pr; + if (pr & (1U << 30)) + EXTD1.config->channels[30].cb(&EXTD1, 30); + if (pr & (1U << 31)) + EXTD1.config->channels[31].cb(&EXTD1, 31); + + pr = EXTI->PR2 & EXTI->IMR2 & (1U << 0); + EXTI->PR2 = pr; + if (pr & (1U << 0)) + EXTD1.config->channels[32].cb(&EXTD1, 32); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI33_HANDLER) +/** + * @brief EXTI[33] interrupt handler (COMP7). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector148) { + uint32_t pr2; + + OSAL_IRQ_PROLOGUE(); + + pr2 = EXTI->PR2; + pr2 = EXTI->IMR & (1U << 1); + EXTI->PR2 = pr2; + if (pr2 & (1U << 1)) + EXTD1.config->channels[33].cb(&EXTD1, 33); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_enable(void) { + + nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY); + nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY); + nvicEnableVector(EXTI2_TSC_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY); + nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY); + nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY); + nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY); + nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY); + nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY); + nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY); +#if STM32_HAS_USB + nvicEnableVector(USBWakeUp_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY); +#endif + nvicEnableVector(TAMP_STAMP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY); + nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY); + nvicEnableVector(COMP1_2_3_IRQn, STM32_EXT_EXTI21_22_29_IRQ_PRIORITY); + nvicEnableVector(COMP4_5_6_IRQn, STM32_EXT_EXTI30_32_IRQ_PRIORITY); +#if STM32_EXTI_NUM_LINES >= 34 + nvicEnableVector(COMP7_IRQn, STM32_EXT_EXTI33_IRQ_PRIORITY); +#endif +} + +/** + * @brief Disables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_disable(void) { + + nvicDisableVector(EXTI0_IRQn); + nvicDisableVector(EXTI1_IRQn); + nvicDisableVector(EXTI2_TSC_IRQn); + nvicDisableVector(EXTI3_IRQn); + nvicDisableVector(EXTI4_IRQn); + nvicDisableVector(EXTI9_5_IRQn); + nvicDisableVector(EXTI15_10_IRQn); + nvicDisableVector(PVD_IRQn); + nvicDisableVector(RTC_Alarm_IRQn); +#if STM32_HAS_USB + nvicDisableVector(USBWakeUp_IRQn); +#endif + nvicDisableVector(TAMP_STAMP_IRQn); + nvicDisableVector(RTC_WKUP_IRQn); + nvicDisableVector(COMP1_2_3_IRQn); + nvicDisableVector(COMP4_5_6_IRQn); +#if STM32_EXTI_NUM_LINES >= 34 + nvicDisableVector(COMP7_IRQn); +#endif +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.h b/os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.h new file mode 100644 index 000000000..d667f9c30 --- /dev/null +++ b/os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.h @@ -0,0 +1,177 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F3xx/ext_lld_isr.h + * @brief STM32F3xx EXT subsystem low level driver ISR header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_ISR_H_ +#define _EXT_LLD_ISR_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief EXTI0 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI1 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI2 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI3 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI4 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI5..9 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI10..15 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI16 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI17 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI18 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI19 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI20 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI21,22,29 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI21_22_29_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI21_22_29_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI30..32 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI30_32_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI33 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI33_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_exti_irq_enable(void); + void ext_lld_exti_irq_disable(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_ISR_H_ */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32F3xx/platform.mk b/os/hal/ports/STM32/STM32F3xx/platform.mk index 07d633b10..741a9549e 100644 --- a/os/hal/ports/STM32/STM32F3xx/platform.mk +++ b/os/hal/ports/STM32/STM32F3xx/platform.mk @@ -5,74 +5,74 @@ HALCONF := $(strip $(shell cat halconf.h | egrep -e "define")) PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/hal_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/adc_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c endif ifneq ($(findstring HAL_USE_CAN TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c endif ifneq ($(findstring HAL_USE_DAC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c endif ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/ext_lld_isr.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/hal_ext_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.c endif ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c endif ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.c endif ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c endif ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.c endif ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c endif ifneq ($(findstring HAL_USE_ICU TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c endif ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c endif ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c endif ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/uart_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c endif ifneq ($(findstring HAL_USE_USB TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/usb_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c endif ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c endif else PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/hal_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/ext_lld_isr.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/adc_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/uart_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/usb_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.c + $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/hal_ext_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c endif # Required include directories diff --git a/os/hal/ports/STM32/STM32F4xx/ext_lld_isr.c b/os/hal/ports/STM32/STM32F4xx/ext_lld_isr.c deleted file mode 100644 index bd69d0b13..000000000 --- a/os/hal/ports/STM32/STM32F4xx/ext_lld_isr.c +++ /dev/null @@ -1,407 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F4xx/ext_lld_isr.c - * @brief STM32F4xx/STM32F2xx EXT subsystem low level driver ISR code. - * - * @addtogroup EXT - * @{ - */ - -#include "hal.h" - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -#include "ext_lld_isr.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief EXTI[0] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector58) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 0); - EXTI->PR = pr; - if (pr & (1U << 0)) - EXTD1.config->channels[0].cb(&EXTD1, 0); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[1] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector5C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 1); - EXTI->PR = pr; - if (pr & (1U << 1)) - EXTD1.config->channels[1].cb(&EXTD1, 1); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[2] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector60) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 2); - EXTI->PR = pr; - if (pr & (1U << 2)) - EXTD1.config->channels[2].cb(&EXTD1, 2); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[3] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector64) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 3); - EXTI->PR = pr; - if (pr & (1U << 3)) - EXTD1.config->channels[3].cb(&EXTD1, 3); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[4] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector68) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 4); - EXTI->PR = pr; - if (pr & (1U << 4)) - EXTD1.config->channels[4].cb(&EXTD1, 4); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[5]...EXTI[9] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector9C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) | - (1U << 9)); - EXTI->PR = pr; - if (pr & (1U << 5)) - EXTD1.config->channels[5].cb(&EXTD1, 5); - if (pr & (1U << 6)) - EXTD1.config->channels[6].cb(&EXTD1, 6); - if (pr & (1U << 7)) - EXTD1.config->channels[7].cb(&EXTD1, 7); - if (pr & (1U << 8)) - EXTD1.config->channels[8].cb(&EXTD1, 8); - if (pr & (1U << 9)) - EXTD1.config->channels[9].cb(&EXTD1, 9); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[10]...EXTI[15] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorE0) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) | - (1U << 14) | (1U << 15)); - EXTI->PR = pr; - if (pr & (1U << 10)) - EXTD1.config->channels[10].cb(&EXTD1, 10); - if (pr & (1U << 11)) - EXTD1.config->channels[11].cb(&EXTD1, 11); - if (pr & (1U << 12)) - EXTD1.config->channels[12].cb(&EXTD1, 12); - if (pr & (1U << 13)) - EXTD1.config->channels[13].cb(&EXTD1, 13); - if (pr & (1U << 14)) - EXTD1.config->channels[14].cb(&EXTD1, 14); - if (pr & (1U << 15)) - EXTD1.config->channels[15].cb(&EXTD1, 15); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[16] interrupt handler (PVD). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector44) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr = EXTI->IMR & (1U << 16); - EXTI->PR = pr; - if (pr & (1U << 16)) - EXTD1.config->channels[16].cb(&EXTD1, 16); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[17] interrupt handler (RTC_ALARM). - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorE4) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr = EXTI->IMR & (1U << 17); - EXTI->PR = pr; - if (pr & (1U << 17)) - EXTD1.config->channels[17].cb(&EXTD1, 17); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[18] interrupt handler (OTG_FS_WKUP). - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorE8) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 18); - EXTI->PR = pr; - if (pr & (1U << 18)) - EXTD1.config->channels[18].cb(&EXTD1, 18); - - OSAL_IRQ_EPILOGUE(); -} - -#if STM32_HAS_ETH || defined(__DOXYGEN__) -/** - * @brief EXTI[19] interrupt handler (ETH_WKUP). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector138) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 19); - EXTI->PR = pr; - if (pr & (1U << 19)) - EXTD1.config->channels[19].cb(&EXTD1, 19); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_HAS_ETH */ - -#if STM32_HAS_OTG2 || defined(__DOXYGEN__) -/** - * @brief EXTI[20] interrupt handler (OTG_HS_WKUP). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector170) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 20); - EXTI->PR = pr; - if (pr & (1U << 20)) - EXTD1.config->channels[20].cb(&EXTD1, 20); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* STM32_HAS_OTG2 */ - -#if !defined(STM32F401xx) -/** - * @brief EXTI[21] interrupt handler (TAMPER_STAMP). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector48) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 21); - EXTI->PR = pr; - if (pr & (1U << 21)) - EXTD1.config->channels[21].cb(&EXTD1, 21); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* !defined(STM32F401xx) */ - -/** - * @brief EXTI[22] interrupt handler (RTC_WKUP). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector4C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 22); - EXTI->PR = pr; - if (pr & (1U << 22)) - EXTD1.config->channels[22].cb(&EXTD1, 22); - - OSAL_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Enables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_enable(void) { - - nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY); - nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY); - nvicEnableVector(EXTI2_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY); - nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY); - nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY); - nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY); - nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY); - nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY); - nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY); - nvicEnableVector(OTG_FS_WKUP_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY); -#if STM32_HAS_ETH - nvicEnableVector(ETH_WKUP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY); -#endif -#if STM32_HAS_OTG2 - nvicEnableVector(OTG_HS_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY); -#endif -#if !defined(STM32F401xx) - nvicEnableVector(TAMP_STAMP_IRQn, STM32_EXT_EXTI21_IRQ_PRIORITY); -#endif /* !defined(STM32F401xx) */ - nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI22_IRQ_PRIORITY); -} - -/** - * @brief Disables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_disable(void) { - - nvicDisableVector(EXTI0_IRQn); - nvicDisableVector(EXTI1_IRQn); - nvicDisableVector(EXTI2_IRQn); - nvicDisableVector(EXTI3_IRQn); - nvicDisableVector(EXTI4_IRQn); - nvicDisableVector(EXTI9_5_IRQn); - nvicDisableVector(EXTI15_10_IRQn); - nvicDisableVector(PVD_IRQn); - nvicDisableVector(RTC_Alarm_IRQn); - nvicDisableVector(OTG_FS_WKUP_IRQn); -#if STM32_HAS_ETH - nvicDisableVector(ETH_WKUP_IRQn); -#endif -#if STM32_HAS_OTG2 - nvicDisableVector(OTG_HS_WKUP_IRQn); -#endif -#if !defined(STM32F401xx) - nvicDisableVector(TAMP_STAMP_IRQn); -#endif /* !defined(STM32F401xx) */ - nvicDisableVector(RTC_WKUP_IRQn); -} - -#endif /* HAL_USE_EXT */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32F4xx/ext_lld_isr.h b/os/hal/ports/STM32/STM32F4xx/ext_lld_isr.h deleted file mode 100644 index 6f4a0b73c..000000000 --- a/os/hal/ports/STM32/STM32F4xx/ext_lld_isr.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F4xx/ext_lld_isr.h - * @brief STM32F4xx/STM32F2xx EXT subsystem low level driver ISR header. - * - * @addtogroup EXT - * @{ - */ - -#ifndef _EXT_LLD_ISR_H_ -#define _EXT_LLD_ISR_H_ - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief EXTI0 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI1 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI2 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI3 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI4 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI9..5 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI15..10 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI16 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI17 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI18 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI19 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI20 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI21 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI21_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI21_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI22 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI22_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI22_IRQ_PRIORITY 6 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void ext_lld_exti_irq_enable(void); - void ext_lld_exti_irq_disable(void); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EXT */ - -#endif /* _EXT_LLD_ISR_H_ */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32F4xx/hal_ext_lld_isr.c b/os/hal/ports/STM32/STM32F4xx/hal_ext_lld_isr.c new file mode 100644 index 000000000..fca11ac6e --- /dev/null +++ b/os/hal/ports/STM32/STM32F4xx/hal_ext_lld_isr.c @@ -0,0 +1,407 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F4xx/ext_lld_isr.c + * @brief STM32F4xx/STM32F2xx EXT subsystem low level driver ISR code. + * + * @addtogroup EXT + * @{ + */ + +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +#include "hal_ext_lld_isr.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief EXTI[0] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector58) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 0); + EXTI->PR = pr; + if (pr & (1U << 0)) + EXTD1.config->channels[0].cb(&EXTD1, 0); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[1] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector5C) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 1); + EXTI->PR = pr; + if (pr & (1U << 1)) + EXTD1.config->channels[1].cb(&EXTD1, 1); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[2] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector60) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 2); + EXTI->PR = pr; + if (pr & (1U << 2)) + EXTD1.config->channels[2].cb(&EXTD1, 2); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[3] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector64) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 3); + EXTI->PR = pr; + if (pr & (1U << 3)) + EXTD1.config->channels[3].cb(&EXTD1, 3); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[4] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector68) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 4); + EXTI->PR = pr; + if (pr & (1U << 4)) + EXTD1.config->channels[4].cb(&EXTD1, 4); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[5]...EXTI[9] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector9C) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) | + (1U << 9)); + EXTI->PR = pr; + if (pr & (1U << 5)) + EXTD1.config->channels[5].cb(&EXTD1, 5); + if (pr & (1U << 6)) + EXTD1.config->channels[6].cb(&EXTD1, 6); + if (pr & (1U << 7)) + EXTD1.config->channels[7].cb(&EXTD1, 7); + if (pr & (1U << 8)) + EXTD1.config->channels[8].cb(&EXTD1, 8); + if (pr & (1U << 9)) + EXTD1.config->channels[9].cb(&EXTD1, 9); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[10]...EXTI[15] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(VectorE0) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) | + (1U << 14) | (1U << 15)); + EXTI->PR = pr; + if (pr & (1U << 10)) + EXTD1.config->channels[10].cb(&EXTD1, 10); + if (pr & (1U << 11)) + EXTD1.config->channels[11].cb(&EXTD1, 11); + if (pr & (1U << 12)) + EXTD1.config->channels[12].cb(&EXTD1, 12); + if (pr & (1U << 13)) + EXTD1.config->channels[13].cb(&EXTD1, 13); + if (pr & (1U << 14)) + EXTD1.config->channels[14].cb(&EXTD1, 14); + if (pr & (1U << 15)) + EXTD1.config->channels[15].cb(&EXTD1, 15); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[16] interrupt handler (PVD). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector44) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr = EXTI->IMR & (1U << 16); + EXTI->PR = pr; + if (pr & (1U << 16)) + EXTD1.config->channels[16].cb(&EXTD1, 16); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[17] interrupt handler (RTC_ALARM). + * + * @isr + */ +OSAL_IRQ_HANDLER(VectorE4) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr = EXTI->IMR & (1U << 17); + EXTI->PR = pr; + if (pr & (1U << 17)) + EXTD1.config->channels[17].cb(&EXTD1, 17); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[18] interrupt handler (OTG_FS_WKUP). + * + * @isr + */ +OSAL_IRQ_HANDLER(VectorE8) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 18); + EXTI->PR = pr; + if (pr & (1U << 18)) + EXTD1.config->channels[18].cb(&EXTD1, 18); + + OSAL_IRQ_EPILOGUE(); +} + +#if STM32_HAS_ETH || defined(__DOXYGEN__) +/** + * @brief EXTI[19] interrupt handler (ETH_WKUP). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector138) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 19); + EXTI->PR = pr; + if (pr & (1U << 19)) + EXTD1.config->channels[19].cb(&EXTD1, 19); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* STM32_HAS_ETH */ + +#if STM32_HAS_OTG2 || defined(__DOXYGEN__) +/** + * @brief EXTI[20] interrupt handler (OTG_HS_WKUP). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector170) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 20); + EXTI->PR = pr; + if (pr & (1U << 20)) + EXTD1.config->channels[20].cb(&EXTD1, 20); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* STM32_HAS_OTG2 */ + +#if !defined(STM32F401xx) +/** + * @brief EXTI[21] interrupt handler (TAMPER_STAMP). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector48) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 21); + EXTI->PR = pr; + if (pr & (1U << 21)) + EXTD1.config->channels[21].cb(&EXTD1, 21); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* !defined(STM32F401xx) */ + +/** + * @brief EXTI[22] interrupt handler (RTC_WKUP). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector4C) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 22); + EXTI->PR = pr; + if (pr & (1U << 22)) + EXTD1.config->channels[22].cb(&EXTD1, 22); + + OSAL_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_enable(void) { + + nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY); + nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY); + nvicEnableVector(EXTI2_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY); + nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY); + nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY); + nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY); + nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY); + nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY); + nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY); + nvicEnableVector(OTG_FS_WKUP_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY); +#if STM32_HAS_ETH + nvicEnableVector(ETH_WKUP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY); +#endif +#if STM32_HAS_OTG2 + nvicEnableVector(OTG_HS_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY); +#endif +#if !defined(STM32F401xx) + nvicEnableVector(TAMP_STAMP_IRQn, STM32_EXT_EXTI21_IRQ_PRIORITY); +#endif /* !defined(STM32F401xx) */ + nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI22_IRQ_PRIORITY); +} + +/** + * @brief Disables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_disable(void) { + + nvicDisableVector(EXTI0_IRQn); + nvicDisableVector(EXTI1_IRQn); + nvicDisableVector(EXTI2_IRQn); + nvicDisableVector(EXTI3_IRQn); + nvicDisableVector(EXTI4_IRQn); + nvicDisableVector(EXTI9_5_IRQn); + nvicDisableVector(EXTI15_10_IRQn); + nvicDisableVector(PVD_IRQn); + nvicDisableVector(RTC_Alarm_IRQn); + nvicDisableVector(OTG_FS_WKUP_IRQn); +#if STM32_HAS_ETH + nvicDisableVector(ETH_WKUP_IRQn); +#endif +#if STM32_HAS_OTG2 + nvicDisableVector(OTG_HS_WKUP_IRQn); +#endif +#if !defined(STM32F401xx) + nvicDisableVector(TAMP_STAMP_IRQn); +#endif /* !defined(STM32F401xx) */ + nvicDisableVector(RTC_WKUP_IRQn); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32F4xx/hal_ext_lld_isr.h b/os/hal/ports/STM32/STM32F4xx/hal_ext_lld_isr.h new file mode 100644 index 000000000..6f4a0b73c --- /dev/null +++ b/os/hal/ports/STM32/STM32F4xx/hal_ext_lld_isr.h @@ -0,0 +1,170 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F4xx/ext_lld_isr.h + * @brief STM32F4xx/STM32F2xx EXT subsystem low level driver ISR header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_ISR_H_ +#define _EXT_LLD_ISR_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief EXTI0 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI1 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI2 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI3 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI4 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI9..5 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI15..10 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI16 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI17 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI18 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI19 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI20 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI21 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI21_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI21_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI22 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI22_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI22_IRQ_PRIORITY 6 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_exti_irq_enable(void); + void ext_lld_exti_irq_disable(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_ISR_H_ */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32F4xx/platform.mk b/os/hal/ports/STM32/STM32F4xx/platform.mk index ee04c8c00..77008189c 100644 --- a/os/hal/ports/STM32/STM32F4xx/platform.mk +++ b/os/hal/ports/STM32/STM32F4xx/platform.mk @@ -5,86 +5,86 @@ HALCONF := $(strip $(shell cat halconf.h | egrep -e "define")) PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/hal_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv2/adc_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv2/hal_adc_lld.c endif ifneq ($(findstring HAL_USE_CAN TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c endif ifneq ($(findstring HAL_USE_DAC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c endif ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/ext_lld_isr.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/hal_ext_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/hal_ext_lld_isr.c endif ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c endif ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c endif ifneq ($(findstring HAL_USE_MAC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1/mac_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1/hal_mac_lld.c endif ifneq ($(findstring HAL_USE_USB TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/usb_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c endif ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c endif ifneq ($(findstring HAL_USE_I2S TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/i2s_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/hal_i2s_lld.c endif ifneq ($(findstring HAL_USE_SDC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SDIOv1/sdc_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.c endif ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/spi_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/hal_spi_lld.c endif ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c endif ifneq ($(findstring HAL_USE_ICU TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c endif ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c endif ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/serial_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/hal_serial_lld.c endif ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/uart_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c endif ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c endif else PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/hal_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/ext_lld_isr.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv2/adc_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/hal_ext_lld_isr.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv2/hal_adc_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/hal_ext_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1/mac_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/usb_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/SDIOv1/sdc_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/i2s_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/spi_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/serial_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/uart_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.c + $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1/hal_mac_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/hal_i2s_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/hal_spi_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/hal_serial_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c endif # Required include directories diff --git a/os/hal/ports/STM32/STM32F7xx/ext_lld_isr.c b/os/hal/ports/STM32/STM32F7xx/ext_lld_isr.c deleted file mode 100644 index 8fba798a8..000000000 --- a/os/hal/ports/STM32/STM32F7xx/ext_lld_isr.c +++ /dev/null @@ -1,391 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F7xx/ext_lld_isr.c - * @brief STM32F7xx EXT subsystem low level driver ISR code. - * - * @addtogroup EXT - * @{ - */ - -#include "hal.h" - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -#include "ext_lld_isr.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief EXTI[0] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector58) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 0); - EXTI->PR = pr; - if (pr & (1U << 0)) - EXTD1.config->channels[0].cb(&EXTD1, 0); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[1] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector5C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 1); - EXTI->PR = pr; - if (pr & (1U << 1)) - EXTD1.config->channels[1].cb(&EXTD1, 1); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[2] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector60) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 2); - EXTI->PR = pr; - if (pr & (1U << 2)) - EXTD1.config->channels[2].cb(&EXTD1, 2); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[3] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector64) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 3); - EXTI->PR = pr; - if (pr & (1U << 3)) - EXTD1.config->channels[3].cb(&EXTD1, 3); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[4] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector68) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 4); - EXTI->PR = pr; - if (pr & (1U << 4)) - EXTD1.config->channels[4].cb(&EXTD1, 4); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[5]...EXTI[9] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector9C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) | - (1U << 9)); - EXTI->PR = pr; - if (pr & (1U << 5)) - EXTD1.config->channels[5].cb(&EXTD1, 5); - if (pr & (1U << 6)) - EXTD1.config->channels[6].cb(&EXTD1, 6); - if (pr & (1U << 7)) - EXTD1.config->channels[7].cb(&EXTD1, 7); - if (pr & (1U << 8)) - EXTD1.config->channels[8].cb(&EXTD1, 8); - if (pr & (1U << 9)) - EXTD1.config->channels[9].cb(&EXTD1, 9); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[10]...EXTI[15] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorE0) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) | - (1U << 14) | (1U << 15)); - EXTI->PR = pr; - if (pr & (1U << 10)) - EXTD1.config->channels[10].cb(&EXTD1, 10); - if (pr & (1U << 11)) - EXTD1.config->channels[11].cb(&EXTD1, 11); - if (pr & (1U << 12)) - EXTD1.config->channels[12].cb(&EXTD1, 12); - if (pr & (1U << 13)) - EXTD1.config->channels[13].cb(&EXTD1, 13); - if (pr & (1U << 14)) - EXTD1.config->channels[14].cb(&EXTD1, 14); - if (pr & (1U << 15)) - EXTD1.config->channels[15].cb(&EXTD1, 15); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[16] interrupt handler (PVD). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector44) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 16); - EXTI->PR = pr; - if (pr & (1U << 16)) - EXTD1.config->channels[16].cb(&EXTD1, 16); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[17] interrupt handler (RTC_ALARM). - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorE4) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 17); - EXTI->PR = pr; - if (pr & (1U << 17)) - EXTD1.config->channels[17].cb(&EXTD1, 17); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[18] interrupt handler (OTG_FS_WKUP). - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorE8) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 18); - EXTI->PR = pr; - if (pr & (1U << 18)) - EXTD1.config->channels[18].cb(&EXTD1, 18); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[19] interrupt handler (ETH_WKUP). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector138) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 19); - EXTI->PR = pr; - if (pr & (1U << 19)) - EXTD1.config->channels[19].cb(&EXTD1, 19); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[20] interrupt handler (OTG_HS_WKUP). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector170) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 20); - EXTI->PR = pr; - if (pr & (1U << 20)) - EXTD1.config->channels[20].cb(&EXTD1, 20); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[21] interrupt handler (TAMPER_STAMP). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector48) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 21); - EXTI->PR = pr; - if (pr & (1U << 21)) - EXTD1.config->channels[21].cb(&EXTD1, 21); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[22] interrupt handler (RTC_WKUP). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector4C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 22); - EXTI->PR = pr; - if (pr & (1U << 22)) - EXTD1.config->channels[22].cb(&EXTD1, 22); - - OSAL_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Enables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_enable(void) { - - nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY); - nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY); - nvicEnableVector(EXTI2_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY); - nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY); - nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY); - nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY); - nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY); - nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY); - nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY); - nvicEnableVector(OTG_FS_WKUP_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY); - nvicEnableVector(ETH_WKUP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY); - nvicEnableVector(OTG_HS_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY); - nvicEnableVector(TAMP_STAMP_IRQn, STM32_EXT_EXTI21_IRQ_PRIORITY); - nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI22_IRQ_PRIORITY); - nvicEnableVector(LPTIM1_IRQn, STM32_EXT_EXTI23_IRQ_PRIORITY); -} - -/** - * @brief Disables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_disable(void) { - - nvicDisableVector(EXTI0_IRQn); - nvicDisableVector(EXTI1_IRQn); - nvicDisableVector(EXTI2_IRQn); - nvicDisableVector(EXTI3_IRQn); - nvicDisableVector(EXTI4_IRQn); - nvicDisableVector(EXTI9_5_IRQn); - nvicDisableVector(EXTI15_10_IRQn); - nvicDisableVector(PVD_IRQn); - nvicDisableVector(RTC_Alarm_IRQn); - nvicDisableVector(OTG_FS_WKUP_IRQn); - nvicDisableVector(ETH_WKUP_IRQn); - nvicDisableVector(OTG_HS_WKUP_IRQn); - nvicDisableVector(TAMP_STAMP_IRQn); - nvicDisableVector(RTC_WKUP_IRQn); - nvicDisableVector(LPTIM1_IRQn); -} - -#endif /* HAL_USE_EXT */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32F7xx/ext_lld_isr.h b/os/hal/ports/STM32/STM32F7xx/ext_lld_isr.h deleted file mode 100644 index b754b2fc8..000000000 --- a/os/hal/ports/STM32/STM32F7xx/ext_lld_isr.h +++ /dev/null @@ -1,177 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F7xx/ext_lld_isr.h - * @brief STM32F7xx EXT subsystem low level driver ISR header. - * - * @addtogroup EXT - * @{ - */ - -#ifndef _EXT_LLD_ISR_H_ -#define _EXT_LLD_ISR_H_ - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief EXTI0 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI1 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI2 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI3 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI4 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI9..5 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI15..10 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI16 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI17 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI18 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI19 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI20 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI21 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI21_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI21_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI22 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI22_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI22_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI23 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI23_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI23_IRQ_PRIORITY 6 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void ext_lld_exti_irq_enable(void); - void ext_lld_exti_irq_disable(void); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EXT */ - -#endif /* _EXT_LLD_ISR_H_ */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32F7xx/hal_ext_lld_isr.c b/os/hal/ports/STM32/STM32F7xx/hal_ext_lld_isr.c new file mode 100644 index 000000000..e2d947473 --- /dev/null +++ b/os/hal/ports/STM32/STM32F7xx/hal_ext_lld_isr.c @@ -0,0 +1,391 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F7xx/ext_lld_isr.c + * @brief STM32F7xx EXT subsystem low level driver ISR code. + * + * @addtogroup EXT + * @{ + */ + +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +#include "hal_ext_lld_isr.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief EXTI[0] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector58) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 0); + EXTI->PR = pr; + if (pr & (1U << 0)) + EXTD1.config->channels[0].cb(&EXTD1, 0); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[1] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector5C) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 1); + EXTI->PR = pr; + if (pr & (1U << 1)) + EXTD1.config->channels[1].cb(&EXTD1, 1); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[2] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector60) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 2); + EXTI->PR = pr; + if (pr & (1U << 2)) + EXTD1.config->channels[2].cb(&EXTD1, 2); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[3] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector64) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 3); + EXTI->PR = pr; + if (pr & (1U << 3)) + EXTD1.config->channels[3].cb(&EXTD1, 3); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[4] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector68) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 4); + EXTI->PR = pr; + if (pr & (1U << 4)) + EXTD1.config->channels[4].cb(&EXTD1, 4); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[5]...EXTI[9] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector9C) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) | + (1U << 9)); + EXTI->PR = pr; + if (pr & (1U << 5)) + EXTD1.config->channels[5].cb(&EXTD1, 5); + if (pr & (1U << 6)) + EXTD1.config->channels[6].cb(&EXTD1, 6); + if (pr & (1U << 7)) + EXTD1.config->channels[7].cb(&EXTD1, 7); + if (pr & (1U << 8)) + EXTD1.config->channels[8].cb(&EXTD1, 8); + if (pr & (1U << 9)) + EXTD1.config->channels[9].cb(&EXTD1, 9); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[10]...EXTI[15] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(VectorE0) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) | + (1U << 14) | (1U << 15)); + EXTI->PR = pr; + if (pr & (1U << 10)) + EXTD1.config->channels[10].cb(&EXTD1, 10); + if (pr & (1U << 11)) + EXTD1.config->channels[11].cb(&EXTD1, 11); + if (pr & (1U << 12)) + EXTD1.config->channels[12].cb(&EXTD1, 12); + if (pr & (1U << 13)) + EXTD1.config->channels[13].cb(&EXTD1, 13); + if (pr & (1U << 14)) + EXTD1.config->channels[14].cb(&EXTD1, 14); + if (pr & (1U << 15)) + EXTD1.config->channels[15].cb(&EXTD1, 15); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[16] interrupt handler (PVD). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector44) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 16); + EXTI->PR = pr; + if (pr & (1U << 16)) + EXTD1.config->channels[16].cb(&EXTD1, 16); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[17] interrupt handler (RTC_ALARM). + * + * @isr + */ +OSAL_IRQ_HANDLER(VectorE4) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 17); + EXTI->PR = pr; + if (pr & (1U << 17)) + EXTD1.config->channels[17].cb(&EXTD1, 17); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[18] interrupt handler (OTG_FS_WKUP). + * + * @isr + */ +OSAL_IRQ_HANDLER(VectorE8) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 18); + EXTI->PR = pr; + if (pr & (1U << 18)) + EXTD1.config->channels[18].cb(&EXTD1, 18); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[19] interrupt handler (ETH_WKUP). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector138) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 19); + EXTI->PR = pr; + if (pr & (1U << 19)) + EXTD1.config->channels[19].cb(&EXTD1, 19); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[20] interrupt handler (OTG_HS_WKUP). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector170) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 20); + EXTI->PR = pr; + if (pr & (1U << 20)) + EXTD1.config->channels[20].cb(&EXTD1, 20); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[21] interrupt handler (TAMPER_STAMP). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector48) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 21); + EXTI->PR = pr; + if (pr & (1U << 21)) + EXTD1.config->channels[21].cb(&EXTD1, 21); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[22] interrupt handler (RTC_WKUP). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector4C) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 22); + EXTI->PR = pr; + if (pr & (1U << 22)) + EXTD1.config->channels[22].cb(&EXTD1, 22); + + OSAL_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_enable(void) { + + nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY); + nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY); + nvicEnableVector(EXTI2_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY); + nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY); + nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY); + nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY); + nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY); + nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY); + nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY); + nvicEnableVector(OTG_FS_WKUP_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY); + nvicEnableVector(ETH_WKUP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY); + nvicEnableVector(OTG_HS_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY); + nvicEnableVector(TAMP_STAMP_IRQn, STM32_EXT_EXTI21_IRQ_PRIORITY); + nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI22_IRQ_PRIORITY); + nvicEnableVector(LPTIM1_IRQn, STM32_EXT_EXTI23_IRQ_PRIORITY); +} + +/** + * @brief Disables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_disable(void) { + + nvicDisableVector(EXTI0_IRQn); + nvicDisableVector(EXTI1_IRQn); + nvicDisableVector(EXTI2_IRQn); + nvicDisableVector(EXTI3_IRQn); + nvicDisableVector(EXTI4_IRQn); + nvicDisableVector(EXTI9_5_IRQn); + nvicDisableVector(EXTI15_10_IRQn); + nvicDisableVector(PVD_IRQn); + nvicDisableVector(RTC_Alarm_IRQn); + nvicDisableVector(OTG_FS_WKUP_IRQn); + nvicDisableVector(ETH_WKUP_IRQn); + nvicDisableVector(OTG_HS_WKUP_IRQn); + nvicDisableVector(TAMP_STAMP_IRQn); + nvicDisableVector(RTC_WKUP_IRQn); + nvicDisableVector(LPTIM1_IRQn); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32F7xx/hal_ext_lld_isr.h b/os/hal/ports/STM32/STM32F7xx/hal_ext_lld_isr.h new file mode 100644 index 000000000..b754b2fc8 --- /dev/null +++ b/os/hal/ports/STM32/STM32F7xx/hal_ext_lld_isr.h @@ -0,0 +1,177 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F7xx/ext_lld_isr.h + * @brief STM32F7xx EXT subsystem low level driver ISR header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_ISR_H_ +#define _EXT_LLD_ISR_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief EXTI0 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI1 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI2 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI3 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI4 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI9..5 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI15..10 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI16 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI17 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI18 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI19 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI20 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI21 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI21_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI21_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI22 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI22_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI22_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI23 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI23_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI23_IRQ_PRIORITY 6 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_exti_irq_enable(void); + void ext_lld_exti_irq_disable(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_ISR_H_ */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32F7xx/platform.mk b/os/hal/ports/STM32/STM32F7xx/platform.mk index 4bba31e79..4d2384d28 100644 --- a/os/hal/ports/STM32/STM32F7xx/platform.mk +++ b/os/hal/ports/STM32/STM32F7xx/platform.mk @@ -5,86 +5,86 @@ HALCONF := $(strip $(shell cat halconf.h | egrep -e "define")) PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx/hal_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv2/adc_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv2/hal_adc_lld.c endif ifneq ($(findstring HAL_USE_CAN TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c endif ifneq ($(findstring HAL_USE_DAC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c endif ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx/ext_lld_isr.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/hal_ext_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx/hal_ext_lld_isr.c endif ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c endif ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.c endif ifneq ($(findstring HAL_USE_MAC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1/mac_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1/hal_mac_lld.c endif ifneq ($(findstring HAL_USE_USB TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/usb_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c endif ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c endif ifneq ($(findstring HAL_USE_I2S TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/i2s_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/hal_i2s_lld.c endif ifneq ($(findstring HAL_USE_SDC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1/sdc_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c endif ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.c endif ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c endif ifneq ($(findstring HAL_USE_ICU TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c endif ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c endif ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c endif ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/uart_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c endif ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c endif else PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx/hal_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx/ext_lld_isr.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv2/adc_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx/hal_ext_lld_isr.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv2/hal_adc_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/hal_ext_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1/mac_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/usb_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1/sdc_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/i2s_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/uart_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.c + $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1/hal_mac_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/hal_i2s_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c endif # Required include directories diff --git a/os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c b/os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c deleted file mode 100644 index c010f42e1..000000000 --- a/os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c +++ /dev/null @@ -1,283 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32L0xx/ext_lld_isr.c - * @brief STM32L0xx EXT subsystem low level driver ISR code. - * - * @addtogroup EXT - * @{ - */ - -#include "hal.h" - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -#include "ext_lld_isr.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if !defined(STM32_DISABLE_EXTI01_HANDLER) -/** - * @brief EXTI[0]...EXTI[1] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_EXTI_LINE01_HANDLER) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & ((1U << 0) | (1U << 1)); - EXTI->PR = pr; - if (pr & (1U << 0)) - EXTD1.config->channels[0].cb(&EXTD1, 0); - if (pr & (1U << 1)) - EXTD1.config->channels[1].cb(&EXTD1, 1); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI23_HANDLER) -/** - * @brief EXTI[2]...EXTI[3] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_EXTI_LINE23_HANDLER) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & ((1U << 2) | (1U << 3)); - EXTI->PR = pr; - if (pr & (1U << 2)) - EXTD1.config->channels[2].cb(&EXTD1, 2); - if (pr & (1U << 3)) - EXTD1.config->channels[3].cb(&EXTD1, 3); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI4_15_HANDLER) -/** - * @brief EXTI[4]...EXTI[15] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_EXTI_LINE4_15_HANDLER) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & ((1U << 4) | (1U << 5) | (1U << 6) | (1U << 7) | - (1U << 8) | (1U << 9) | (1U << 10) | (1U << 11) | - (1U << 12) | (1U << 13) | (1U << 14) | (1U << 15)); - EXTI->PR = pr; - if (pr & (1U << 4)) - EXTD1.config->channels[4].cb(&EXTD1, 4); - if (pr & (1U << 5)) - EXTD1.config->channels[5].cb(&EXTD1, 5); - if (pr & (1U << 6)) - EXTD1.config->channels[6].cb(&EXTD1, 6); - if (pr & (1U << 7)) - EXTD1.config->channels[7].cb(&EXTD1, 7); - if (pr & (1U << 8)) - EXTD1.config->channels[8].cb(&EXTD1, 8); - if (pr & (1U << 9)) - EXTD1.config->channels[9].cb(&EXTD1, 9); - if (pr & (1U << 10)) - EXTD1.config->channels[10].cb(&EXTD1, 10); - if (pr & (1U << 11)) - EXTD1.config->channels[11].cb(&EXTD1, 11); - if (pr & (1U << 12)) - EXTD1.config->channels[12].cb(&EXTD1, 12); - if (pr & (1U << 13)) - EXTD1.config->channels[13].cb(&EXTD1, 13); - if (pr & (1U << 14)) - EXTD1.config->channels[14].cb(&EXTD1, 14); - if (pr & (1U << 15)) - EXTD1.config->channels[15].cb(&EXTD1, 15); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI16_HANDLER) -/** - * @brief EXTI[16] interrupt handler (PVD). - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_EXTI_LINE16_HANDLER) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 16); - EXTI->PR = pr; - if (pr & (1U << 16)) - EXTD1.config->channels[16].cb(&EXTD1, 16); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI171920_HANDLER) -/** - * @brief EXTI[17],EXTI[19],EXTI[20] interrupt handler (RTC, CSS). - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_EXTI_LINE171920_HANDLER) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & ((1U << 17) | (1U << 19) | (1U << 20)); - EXTI->PR = pr; - if (pr & (1U << 17)) - EXTD1.config->channels[17].cb(&EXTD1, 17); - if (pr & (1U << 19)) - EXTD1.config->channels[19].cb(&EXTD1, 19); - if (pr & (1U << 20)) - EXTD1.config->channels[20].cb(&EXTD1, 20); - - OSAL_IRQ_EPILOGUE(); -} -#endif -#endif /* HAL_USE_EXT */ - -#if (HAL_USE_EXT || HAL_USE_ADC) || defined(__DOXYGEN__) -#if !defined(STM32_DISABLE_EXTI2122_HANDLER) -/** - * @brief EXTI[21],EXTI[22] interrupt handler (ADC, COMP). - * @note This handler is shared with the ADC so it is handled - * a bit differently. - * - * @isr - */ -OSAL_IRQ_HANDLER(STM32_EXTI_LINE2122_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - -#if HAL_USE_EXT - { - uint32_t pr; - - pr = EXTI->PR; - pr &= EXTI->IMR & ((1U << 21) | (1U << 22)); - EXTI->PR = pr; - if (pr & (1U << 21)) - EXTD1.config->channels[21].cb(&EXTD1, 21); - if (pr & (1U << 22)) - EXTD1.config->channels[21].cb(&EXTD1, 22); - } -#endif -#if HAL_USE_ADC - adc_lld_serve_interrupt(&ADCD1); -#endif - - OSAL_IRQ_EPILOGUE(); -} -#endif -#endif /* HAL_USE_EXT || HAL_USE_ADC */ - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Enables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_enable(void) { - - nvicEnableVector(STM32_EXTI_LINE01_NUMBER, - STM32_EXT_EXTI0_1_IRQ_PRIORITY); - nvicEnableVector(STM32_EXTI_LINE23_NUMBER, - STM32_EXT_EXTI2_3_IRQ_PRIORITY); - nvicEnableVector(STM32_EXTI_LINE4_15_NUMBER, - STM32_EXT_EXTI4_15_IRQ_PRIORITY); - nvicEnableVector(STM32_EXTI_LINE16_NUMBER, - STM32_EXT_EXTI16_IRQ_PRIORITY); - nvicEnableVector(STM32_EXTI_LINE171920_NUMBER, - STM32_EXT_EXTI17_20_IRQ_PRIORITY); -#if HAL_USE_ADC - /* If the ADC is not working then the vector can be enabled.*/ - if (ADCD1.state == ADC_STOP) { - nvicEnableVector(STM32_EXTI_LINE2122_NUMBER, - STM32_EXT_EXTI21_22_IRQ_PRIORITY); - } -#else - nvicEnableVector(STM32_EXTI_LINE2122_NUMBER, - STM32_EXT_EXTI21_22_IRQ_PRIORITY); -#endif -} - -/** - * @brief Disables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_disable(void) { - - nvicDisableVector(STM32_EXTI_LINE01_NUMBER); - nvicDisableVector(STM32_EXTI_LINE23_NUMBER); - nvicDisableVector(STM32_EXTI_LINE4_15_NUMBER); - nvicDisableVector(STM32_EXTI_LINE16_NUMBER); - nvicDisableVector(STM32_EXTI_LINE2122_NUMBER); -#if HAL_USE_ADC - /* If the ADC is not working then the vector can be disabled.*/ - if (ADCD1.state == ADC_STOP) { - nvicDisableVector(STM32_EXTI_LINE171920_NUMBER); - } -#else - nvicDisableVector(STM32_EXTI_LINE171920_NUMBER); -#endif -} - -#endif /* HAL_USE_EXT */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32L0xx/ext_lld_isr.h b/os/hal/ports/STM32/STM32L0xx/ext_lld_isr.h deleted file mode 100644 index 947520d44..000000000 --- a/os/hal/ports/STM32/STM32L0xx/ext_lld_isr.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32L0xx/ext_lld_isr.h - * @brief STM32L0xx EXT subsystem low level driver ISR header. - * - * @addtogroup EXT - * @{ - */ - -#ifndef _EXT_LLD_ISR_H_ -#define _EXT_LLD_ISR_H_ - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief EXTI0..1 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI0_1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3 -#endif - -/** - * @brief EXTI2..3 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI2_3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3 -#endif - -/** - * @brief EXTI4..15 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI4_15_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3 -#endif - -/** - * @brief EXTI16 (PVD) interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI16_IRQ_PRIORITY 3 -#endif - -/** - * @brief EXTI17,19,20 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI17_20_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI17_20_IRQ_PRIORITY 3 -#endif - -/** - * @brief EXTI21,22 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI21_22_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 3 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void ext_lld_exti_irq_enable(void); - void ext_lld_exti_irq_disable(void); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EXT */ - -#endif /* _EXT_LLD_ISR_H_ */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32L0xx/hal_ext_lld_isr.c b/os/hal/ports/STM32/STM32L0xx/hal_ext_lld_isr.c new file mode 100644 index 000000000..8717260bc --- /dev/null +++ b/os/hal/ports/STM32/STM32L0xx/hal_ext_lld_isr.c @@ -0,0 +1,283 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32L0xx/ext_lld_isr.c + * @brief STM32L0xx EXT subsystem low level driver ISR code. + * + * @addtogroup EXT + * @{ + */ + +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +#include "hal_ext_lld_isr.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if !defined(STM32_DISABLE_EXTI01_HANDLER) +/** + * @brief EXTI[0]...EXTI[1] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_EXTI_LINE01_HANDLER) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & ((1U << 0) | (1U << 1)); + EXTI->PR = pr; + if (pr & (1U << 0)) + EXTD1.config->channels[0].cb(&EXTD1, 0); + if (pr & (1U << 1)) + EXTD1.config->channels[1].cb(&EXTD1, 1); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI23_HANDLER) +/** + * @brief EXTI[2]...EXTI[3] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_EXTI_LINE23_HANDLER) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & ((1U << 2) | (1U << 3)); + EXTI->PR = pr; + if (pr & (1U << 2)) + EXTD1.config->channels[2].cb(&EXTD1, 2); + if (pr & (1U << 3)) + EXTD1.config->channels[3].cb(&EXTD1, 3); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI4_15_HANDLER) +/** + * @brief EXTI[4]...EXTI[15] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_EXTI_LINE4_15_HANDLER) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & ((1U << 4) | (1U << 5) | (1U << 6) | (1U << 7) | + (1U << 8) | (1U << 9) | (1U << 10) | (1U << 11) | + (1U << 12) | (1U << 13) | (1U << 14) | (1U << 15)); + EXTI->PR = pr; + if (pr & (1U << 4)) + EXTD1.config->channels[4].cb(&EXTD1, 4); + if (pr & (1U << 5)) + EXTD1.config->channels[5].cb(&EXTD1, 5); + if (pr & (1U << 6)) + EXTD1.config->channels[6].cb(&EXTD1, 6); + if (pr & (1U << 7)) + EXTD1.config->channels[7].cb(&EXTD1, 7); + if (pr & (1U << 8)) + EXTD1.config->channels[8].cb(&EXTD1, 8); + if (pr & (1U << 9)) + EXTD1.config->channels[9].cb(&EXTD1, 9); + if (pr & (1U << 10)) + EXTD1.config->channels[10].cb(&EXTD1, 10); + if (pr & (1U << 11)) + EXTD1.config->channels[11].cb(&EXTD1, 11); + if (pr & (1U << 12)) + EXTD1.config->channels[12].cb(&EXTD1, 12); + if (pr & (1U << 13)) + EXTD1.config->channels[13].cb(&EXTD1, 13); + if (pr & (1U << 14)) + EXTD1.config->channels[14].cb(&EXTD1, 14); + if (pr & (1U << 15)) + EXTD1.config->channels[15].cb(&EXTD1, 15); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI16_HANDLER) +/** + * @brief EXTI[16] interrupt handler (PVD). + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_EXTI_LINE16_HANDLER) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 16); + EXTI->PR = pr; + if (pr & (1U << 16)) + EXTD1.config->channels[16].cb(&EXTD1, 16); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI171920_HANDLER) +/** + * @brief EXTI[17],EXTI[19],EXTI[20] interrupt handler (RTC, CSS). + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_EXTI_LINE171920_HANDLER) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & ((1U << 17) | (1U << 19) | (1U << 20)); + EXTI->PR = pr; + if (pr & (1U << 17)) + EXTD1.config->channels[17].cb(&EXTD1, 17); + if (pr & (1U << 19)) + EXTD1.config->channels[19].cb(&EXTD1, 19); + if (pr & (1U << 20)) + EXTD1.config->channels[20].cb(&EXTD1, 20); + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif /* HAL_USE_EXT */ + +#if (HAL_USE_EXT || HAL_USE_ADC) || defined(__DOXYGEN__) +#if !defined(STM32_DISABLE_EXTI2122_HANDLER) +/** + * @brief EXTI[21],EXTI[22] interrupt handler (ADC, COMP). + * @note This handler is shared with the ADC so it is handled + * a bit differently. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_EXTI_LINE2122_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + +#if HAL_USE_EXT + { + uint32_t pr; + + pr = EXTI->PR; + pr &= EXTI->IMR & ((1U << 21) | (1U << 22)); + EXTI->PR = pr; + if (pr & (1U << 21)) + EXTD1.config->channels[21].cb(&EXTD1, 21); + if (pr & (1U << 22)) + EXTD1.config->channels[21].cb(&EXTD1, 22); + } +#endif +#if HAL_USE_ADC + adc_lld_serve_interrupt(&ADCD1); +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif /* HAL_USE_EXT || HAL_USE_ADC */ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_enable(void) { + + nvicEnableVector(STM32_EXTI_LINE01_NUMBER, + STM32_EXT_EXTI0_1_IRQ_PRIORITY); + nvicEnableVector(STM32_EXTI_LINE23_NUMBER, + STM32_EXT_EXTI2_3_IRQ_PRIORITY); + nvicEnableVector(STM32_EXTI_LINE4_15_NUMBER, + STM32_EXT_EXTI4_15_IRQ_PRIORITY); + nvicEnableVector(STM32_EXTI_LINE16_NUMBER, + STM32_EXT_EXTI16_IRQ_PRIORITY); + nvicEnableVector(STM32_EXTI_LINE171920_NUMBER, + STM32_EXT_EXTI17_20_IRQ_PRIORITY); +#if HAL_USE_ADC + /* If the ADC is not working then the vector can be enabled.*/ + if (ADCD1.state == ADC_STOP) { + nvicEnableVector(STM32_EXTI_LINE2122_NUMBER, + STM32_EXT_EXTI21_22_IRQ_PRIORITY); + } +#else + nvicEnableVector(STM32_EXTI_LINE2122_NUMBER, + STM32_EXT_EXTI21_22_IRQ_PRIORITY); +#endif +} + +/** + * @brief Disables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_disable(void) { + + nvicDisableVector(STM32_EXTI_LINE01_NUMBER); + nvicDisableVector(STM32_EXTI_LINE23_NUMBER); + nvicDisableVector(STM32_EXTI_LINE4_15_NUMBER); + nvicDisableVector(STM32_EXTI_LINE16_NUMBER); + nvicDisableVector(STM32_EXTI_LINE2122_NUMBER); +#if HAL_USE_ADC + /* If the ADC is not working then the vector can be disabled.*/ + if (ADCD1.state == ADC_STOP) { + nvicDisableVector(STM32_EXTI_LINE171920_NUMBER); + } +#else + nvicDisableVector(STM32_EXTI_LINE171920_NUMBER); +#endif +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32L0xx/hal_ext_lld_isr.h b/os/hal/ports/STM32/STM32L0xx/hal_ext_lld_isr.h new file mode 100644 index 000000000..947520d44 --- /dev/null +++ b/os/hal/ports/STM32/STM32L0xx/hal_ext_lld_isr.h @@ -0,0 +1,114 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32L0xx/ext_lld_isr.h + * @brief STM32L0xx EXT subsystem low level driver ISR header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_ISR_H_ +#define _EXT_LLD_ISR_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief EXTI0..1 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI0_1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI2..3 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI2_3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI4..15 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI4_15_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI16 (PVD) interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI16_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI17,19,20 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI17_20_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI17_20_IRQ_PRIORITY 3 +#endif + +/** + * @brief EXTI21,22 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI21_22_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 3 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_exti_irq_enable(void); + void ext_lld_exti_irq_disable(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_ISR_H_ */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32L0xx/platform.mk b/os/hal/ports/STM32/STM32L0xx/platform.mk index 43a6b092c..402a3e4d7 100644 --- a/os/hal/ports/STM32/STM32L0xx/platform.mk +++ b/os/hal/ports/STM32/STM32L0xx/platform.mk @@ -5,74 +5,74 @@ HALCONF := $(strip $(shell cat halconf.h | egrep -e "define")) PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/hal_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c + $(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/hal_ext_lld_isr.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv1/adc_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.c endif ifneq ($(findstring HAL_USE_CAN TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c endif ifneq ($(findstring HAL_USE_DAC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c endif ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/hal_ext_lld.c endif ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c endif ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.c endif ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c endif ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/spi_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/hal_spi_lld.c endif ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c endif ifneq ($(findstring HAL_USE_ICU TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c endif ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c endif ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c endif ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/uart_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c endif ifneq ($(findstring HAL_USE_USB TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/usb_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c endif ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c endif else PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/hal_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv1/adc_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/hal_ext_lld_isr.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/spi_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/uart_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/usb_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.c + $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/hal_ext_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/hal_spi_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c endif # Required include directories diff --git a/os/hal/ports/STM32/STM32L1xx/adc_lld.c b/os/hal/ports/STM32/STM32L1xx/adc_lld.c deleted file mode 100644 index 34d84632d..000000000 --- a/os/hal/ports/STM32/STM32L1xx/adc_lld.c +++ /dev/null @@ -1,291 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32L1xx/adc_lld.c - * @brief STM32L1xx ADC subsystem low level driver source. - * - * @addtogroup ADC - * @{ - */ - -#include "hal.h" - -#if HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief ADC1 driver identifier.*/ -#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) -ADCDriver ADCD1; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief ADC DMA ISR service routine. - * - * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { - - /* DMA errors handling.*/ - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - /* DMA, this could help only if the DMA tries to access an unmapped - address space or violates alignment rules.*/ - _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); - } - else { - /* It is possible that the conversion group has already be reset by the - ADC error handler, in this case this interrupt is spurious.*/ - if (adcp->grpp != NULL) { - if ((flags & STM32_DMA_ISR_TCIF) != 0) { - /* Transfer complete processing.*/ - _adc_isr_full_code(adcp); - } - else if ((flags & STM32_DMA_ISR_HTIF) != 0) { - /* Half transfer processing.*/ - _adc_isr_half_code(adcp); - } - } - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) -/** - * @brief ADC interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector88) { - uint32_t sr; - - OSAL_IRQ_PROLOGUE(); - - sr = ADC1->SR; - ADC1->SR = 0; - /* Note, an overflow may occur after the conversion ended before the driver - is able to stop the ADC, this is why the DMA channel is checked too.*/ - if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) { - /* ADC overflow condition, this could happen only if the DMA is unable - to read data fast enough.*/ - if (ADCD1.grpp != NULL) - _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW); - } - /* TODO: Add here analog watchdog handling.*/ - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level ADC driver initialization. - * - * @notapi - */ -void adc_lld_init(void) { - -#if STM32_ADC_USE_ADC1 - /* Driver initialization.*/ - adcObjectInit(&ADCD1); - ADCD1.adc = ADC1; - ADCD1.dmastp = STM32_DMA1_STREAM1; - ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | - STM32_DMA_CR_DIR_P2M | - STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | - STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | - STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; -#endif - - /* The shared vector is initialized on driver initialization and never - disabled.*/ - nvicEnableVector(ADC1_IRQn, STM32_ADC_IRQ_PRIORITY); -} - -/** - * @brief Configures and activates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_start(ADCDriver *adcp) { - - /* If in stopped state then enables the ADC and DMA clocks.*/ - if (adcp->state == ADC_STOP) { -#if STM32_ADC_USE_ADC1 - if (&ADCD1 == adcp) { - bool b = dmaStreamAllocate(adcp->dmastp, - STM32_ADC_ADC1_DMA_IRQ_PRIORITY, - (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, - (void *)adcp); - osalDbgAssert(!b, "stream already allocated"); - dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); - rccEnableADC1(FALSE); - } -#endif /* STM32_ADC_USE_ADC1 */ - - ADC->CCR = (ADC->CCR & ADC_CCR_TSVREFE) | (STM32_ADC_ADCPRE << 16); - - /* ADC initial setup, starting the analog part here in order to reduce - the latency when starting a conversion.*/ - adcp->adc->CR1 = 0; - adcp->adc->CR2 = 0; - adcp->adc->CR2 = ADC_CR2_ADON; - } -} - -/** - * @brief Deactivates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_stop(ADCDriver *adcp) { - - /* If in ready state then disables the ADC clock and analog part.*/ - if (adcp->state == ADC_READY) { - dmaStreamRelease(adcp->dmastp); - adcp->adc->CR1 = 0; - adcp->adc->CR2 = 0; - -#if STM32_ADC_USE_ADC1 - if (&ADCD1 == adcp) - rccDisableADC1(FALSE); -#endif - } -} - -/** - * @brief Starts an ADC conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_start_conversion(ADCDriver *adcp) { - uint32_t mode; - uint32_t cr2; - const ADCConversionGroup *grpp = adcp->grpp; - - /* DMA setup.*/ - mode = adcp->dmamode; - if (grpp->circular) { - mode |= STM32_DMA_CR_CIRC; - if (adcp->depth > 1) { - /* If circular buffer depth > 1, then the half transfer interrupt - is enabled in order to allow streaming processing.*/ - mode |= STM32_DMA_CR_HTIE; - } - } - dmaStreamSetMemory0(adcp->dmastp, adcp->samples); - dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels * - (uint32_t)adcp->depth); - dmaStreamSetMode(adcp->dmastp, mode); - dmaStreamEnable(adcp->dmastp); - - /* ADC setup.*/ - adcp->adc->SR = 0; - adcp->adc->SMPR1 = grpp->smpr1; - adcp->adc->SMPR2 = grpp->smpr2; - adcp->adc->SMPR3 = grpp->smpr3; - adcp->adc->SQR1 = grpp->sqr1; - adcp->adc->SQR2 = grpp->sqr2; - adcp->adc->SQR3 = grpp->sqr3; - adcp->adc->SQR4 = grpp->sqr4; - adcp->adc->SQR5 = grpp->sqr5; - - /* ADC configuration and start.*/ - adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN; - - /* Enforcing the mandatory bits in CR2.*/ - cr2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_DDS | ADC_CR2_ADON; - - /* The start method is different dependign if HW or SW triggered, the - start is performed using the method specified in the CR2 configuration.*/ - if ((cr2 & ADC_CR2_SWSTART) != 0) { - /* Initializing CR2 while keeping ADC_CR2_SWSTART at zero.*/ - adcp->adc->CR2 = (cr2 | ADC_CR2_CONT) & ~ADC_CR2_SWSTART; - - /* Finally enabling ADC_CR2_SWSTART.*/ - adcp->adc->CR2 = (cr2 | ADC_CR2_CONT); - } - else - adcp->adc->CR2 = cr2; -} - -/** - * @brief Stops an ongoing conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_stop_conversion(ADCDriver *adcp) { - - dmaStreamDisable(adcp->dmastp); - adcp->adc->CR1 = 0; - adcp->adc->CR2 = 0; - adcp->adc->CR2 = ADC_CR2_ADON; -} - -/** - * @brief Enables the TSVREFE bit. - * @details The TSVREFE bit is required in order to sample the internal - * temperature sensor and internal reference voltage. - * @note This is an STM32-only functionality. - */ -void adcSTM32EnableTSVREFE(void) { - - ADC->CCR |= ADC_CCR_TSVREFE; -} - -/** - * @brief Disables the TSVREFE bit. - * @details The TSVREFE bit is required in order to sample the internal - * temperature sensor and internal reference voltage. - * @note This is an STM32-only functionality. - */ -void adcSTM32DisableTSVREFE(void) { - - ADC->CCR &= ~ADC_CCR_TSVREFE; -} - -#endif /* HAL_USE_ADC */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32L1xx/adc_lld.h b/os/hal/ports/STM32/STM32L1xx/adc_lld.h deleted file mode 100644 index 551275994..000000000 --- a/os/hal/ports/STM32/STM32L1xx/adc_lld.h +++ /dev/null @@ -1,494 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32L1xx/adc_lld.h - * @brief STM32L1xx ADC subsystem low level driver header. - * - * @addtogroup ADC - * @{ - */ - -#ifndef _ADC_LLD_H_ -#define _ADC_LLD_H_ - -#if HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Triggers selection - * @{ - */ -#define ADC_CR2_EXTSEL_SRC(n) ((n) << 24) /**< @brief Trigger source. */ -/** @} */ - -/** - * @name ADC clock divider settings - * @{ - */ -#define ADC_CCR_ADCPRE_DIV1 0 -#define ADC_CCR_ADCPRE_DIV2 1 -#define ADC_CCR_ADCPRE_DIV4 2 -/** @} */ - -/** - * @name Available analog channels - * @{ - */ -#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ -#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ -#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ -#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ -#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ -#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ -#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ -#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ -#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ -#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ -#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ -#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ -#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ -#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ -#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ -#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ -#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/ -#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */ -#define ADC_CHANNEL_IN18 18 /**< @brief External analog input 18. */ -#define ADC_CHANNEL_IN19 19 /**< @brief External analog input 19. */ -#define ADC_CHANNEL_IN20 20 /**< @brief External analog input 20. */ -#define ADC_CHANNEL_IN21 21 /**< @brief External analog input 21. */ -#define ADC_CHANNEL_IN22 22 /**< @brief External analog input 22. */ -#define ADC_CHANNEL_IN23 23 /**< @brief External analog input 23. */ -#define ADC_CHANNEL_IN24 24 /**< @brief External analog input 24. */ -#define ADC_CHANNEL_IN25 25 /**< @brief External analog input 25. */ -/** @} */ - -/** - * @name Sampling rates - * @{ - */ -#define ADC_SAMPLE_4 0 /**< @brief 4 cycles sampling time. */ -#define ADC_SAMPLE_9 1 /**< @brief 9 cycles sampling time. */ -#define ADC_SAMPLE_16 2 /**< @brief 16 cycles sampling time. */ -#define ADC_SAMPLE_24 3 /**< @brief 24 cycles sampling time. */ -#define ADC_SAMPLE_48 4 /**< @brief 48 cycles sampling time. */ -#define ADC_SAMPLE_96 5 /**< @brief 96 cycles sampling time. */ -#define ADC_SAMPLE_192 6 /**< @brief 192 cycles sampling time. */ -#define ADC_SAMPLE_384 7 /**< @brief 384 cycles sampling time. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief ADC1 driver enable switch. - * @details If set to @p TRUE the support for ADC1 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) -#define STM32_ADC_USE_ADC1 FALSE -#endif - -/** - * @brief ADC common clock divider. - * @note This setting is influenced by the VDDA voltage and other - * external conditions, please refer to the STM32L15x datasheet - * for more info.
- * See section 6.3.15 "12-bit ADC characteristics". - */ -#if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__) -#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV1 -#endif - -/** - * @brief ADC1 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#endif - -/** - * @brief ADC interrupt priority level setting. - */ -#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_IRQ_PRIORITY 5 -#endif - -/** - * @brief ADC1 DMA interrupt priority level setting. - */ -#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 -#error "ADC1 not present in the selected device" -#endif - -#if !STM32_ADC_USE_ADC1 -#error "ADC driver activated but no ADC peripheral assigned" -#endif - -#if STM32_ADC_USE_ADC1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to ADC1" -#endif - -#if STM32_ADC_USE_ADC1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to ADC1 DMA" -#endif - -#if STM32_ADC_USE_ADC1 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY) -#error "Invalid DMA priority assigned to ADC1" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/** - * * @brief ADC frequency. - * */ -/* ADC clock related settings and checks.*/ -#if STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV1 -#define STM32_ADCCLK STM32_HSICLK -#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV2 -#define STM32_ADCCLK (STM32_HSICLK / 2) -#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV4 -#define STM32_ADCCLK (STM32_HSICLK / 4) -#else -#error "invalid STM32_ADC_ADCPRE value specified" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief ADC sample data type. - */ -typedef uint16_t adcsample_t; - -/** - * @brief Channels number in a conversion group. - */ -typedef uint16_t adc_channels_num_t; - -/** - * @brief Possible ADC failure causes. - * @note Error codes are architecture dependent and should not relied - * upon. - */ -typedef enum { - ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */ - ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */ -} adcerror_t; - -/** - * @brief Type of a structure representing an ADC driver. - */ -typedef struct ADCDriver ADCDriver; - -/** - * @brief ADC notification callback type. - * - * @param[in] adcp pointer to the @p ADCDriver object triggering the - * callback - * @param[in] buffer pointer to the most recent samples data - * @param[in] n number of buffer rows available starting from @p buffer - */ -typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); - -/** - * @brief ADC error callback type. - * - * @param[in] adcp pointer to the @p ADCDriver object triggering the - * callback - * @param[in] err ADC error code - */ -typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); - -/** - * @brief Conversion group configuration structure. - * @details This implementation-dependent structure describes a conversion - * operation. - * @note The use of this configuration structure requires knowledge of - * STM32 ADC cell registers interface, please refer to the STM32 - * reference manual for details. - */ -typedef struct { - /** - * @brief Enables the circular buffer mode for the group. - */ - bool circular; - /** - * @brief Number of the analog channels belonging to the conversion group. - */ - adc_channels_num_t num_channels; - /** - * @brief Callback function associated to the group or @p NULL. - */ - adccallback_t end_cb; - /** - * @brief Error callback or @p NULL. - */ - adcerrorcallback_t error_cb; - /* End of the mandatory fields.*/ - /** - * @brief ADC CR1 register initialization data. - * @note All the required bits must be defined into this field except - * @p ADC_CR1_SCAN that is enforced inside the driver. - */ - uint32_t cr1; - /** - * @brief ADC CR2 register initialization data. - * @note All the required bits must be defined into this field except - * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are - * enforced inside the driver. - */ - uint32_t cr2; - /** - * @brief ADC SMPR1 register initialization data. - * @details In this field must be specified the sample times for channels - * 20...25. - */ - uint32_t smpr1; - /** - * @brief ADC SMPR2 register initialization data. - * @details In this field must be specified the sample times for channels - * 10...19. - */ - uint32_t smpr2; - /** - * @brief ADC SMPR3 register initialization data. - * @details In this field must be specified the sample times for channels - * 0...9. - */ - uint32_t smpr3; - /** - * @brief ADC SQR1 register initialization data. - * @details Conversion group sequence 25...27 + sequence length. - */ - uint32_t sqr1; - /** - * @brief ADC SQR2 register initialization data. - * @details Conversion group sequence 19...24. - */ - uint32_t sqr2; - /** - * @brief ADC SQR3 register initialization data. - * @details Conversion group sequence 13...18. - */ - uint32_t sqr3; - /** - * @brief ADC SQR3 register initialization data. - * @details Conversion group sequence 7...12. - */ - uint32_t sqr4; - /** - * @brief ADC SQR3 register initialization data. - * @details Conversion group sequence 1...6. - */ - uint32_t sqr5; -} ADCConversionGroup; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - uint32_t dummy; -} ADCConfig; - -/** - * @brief Structure representing an ADC driver. - */ -struct ADCDriver { - /** - * @brief Driver state. - */ - adcstate_t state; - /** - * @brief Current configuration data. - */ - const ADCConfig *config; - /** - * @brief Current samples buffer pointer or @p NULL. - */ - adcsample_t *samples; - /** - * @brief Current samples buffer depth or @p 0. - */ - size_t depth; - /** - * @brief Current conversion group pointer or @p NULL. - */ - const ADCConversionGroup *grpp; -#if ADC_USE_WAIT || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - thread_reference_t thread; -#endif -#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the peripheral. - */ - mutex_t mutex; -#endif /* ADC_USE_MUTUAL_EXCLUSION */ -#if defined(ADC_DRIVER_EXT_FIELDS) - ADC_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the ADCx registers block. - */ - ADC_TypeDef *adc; - /** - * @brief Pointer to associated DMA channel. - */ - const stm32_dma_stream_t *dmastp; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @name Sequences building helper macros - * @{ - */ -/** - * @brief Number of channels in a conversion sequence. - */ -#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20) - -#define ADC_SQR5_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ -#define ADC_SQR5_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ -#define ADC_SQR5_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ -#define ADC_SQR5_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ -#define ADC_SQR5_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ -#define ADC_SQR5_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ - -#define ADC_SQR4_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ -#define ADC_SQR4_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ -#define ADC_SQR4_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ -#define ADC_SQR4_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ -#define ADC_SQR4_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ -#define ADC_SQR4_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ - -#define ADC_SQR3_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ -#define ADC_SQR3_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ -#define ADC_SQR3_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ -#define ADC_SQR3_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ -#define ADC_SQR3_SQ17_N(n) ((n) << 20) /**< @brief 17th channel in seq.*/ -#define ADC_SQR3_SQ18_N(n) ((n) << 25) /**< @brief 18th channel in seq.*/ - -#define ADC_SQR2_SQ19_N(n) ((n) << 0) /**< @brief 19th channel in seq.*/ -#define ADC_SQR2_SQ20_N(n) ((n) << 5) /**< @brief 20th channel in seq.*/ -#define ADC_SQR2_SQ21_N(n) ((n) << 10) /**< @brief 21th channel in seq.*/ -#define ADC_SQR2_SQ22_N(n) ((n) << 15) /**< @brief 22th channel in seq.*/ -#define ADC_SQR2_SQ23_N(n) ((n) << 20) /**< @brief 23th channel in seq.*/ -#define ADC_SQR2_SQ24_N(n) ((n) << 25) /**< @brief 24th channel in seq.*/ - -#define ADC_SQR1_SQ25_N(n) ((n) << 0) /**< @brief 25th channel in seq.*/ -#define ADC_SQR1_SQ26_N(n) ((n) << 5) /**< @brief 26th channel in seq.*/ -#define ADC_SQR1_SQ27_N(n) ((n) << 10) /**< @brief 27th channel in seq.*/ -/** @} */ - -/** - * @name Sampling rate settings helper macros - * @{ - */ -#define ADC_SMPR3_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ -#define ADC_SMPR3_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ -#define ADC_SMPR3_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ -#define ADC_SMPR3_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ -#define ADC_SMPR3_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ -#define ADC_SMPR3_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ -#define ADC_SMPR3_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ -#define ADC_SMPR3_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ -#define ADC_SMPR3_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ -#define ADC_SMPR3_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ - -#define ADC_SMPR2_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ -#define ADC_SMPR2_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ -#define ADC_SMPR2_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ -#define ADC_SMPR2_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ -#define ADC_SMPR2_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ -#define ADC_SMPR2_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ -#define ADC_SMPR2_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor - sampling time. */ -#define ADC_SMPR2_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference - sampling time. */ -#define ADC_SMPR2_SMP_AN18(n) ((n) << 24) /**< @brief AN18 sampling time. */ -#define ADC_SMPR2_SMP_AN19(n) ((n) << 27) /**< @brief AN19 sampling time. */ - -#define ADC_SMPR1_SMP_AN20(n) ((n) << 0) /**< @brief AN20 sampling time. */ -#define ADC_SMPR1_SMP_AN21(n) ((n) << 3) /**< @brief AN21 sampling time. */ -#define ADC_SMPR1_SMP_AN22(n) ((n) << 6) /**< @brief AN22 sampling time. */ -#define ADC_SMPR1_SMP_AN23(n) ((n) << 9) /**< @brief AN23 sampling time. */ -#define ADC_SMPR1_SMP_AN24(n) ((n) << 12) /**< @brief AN24 sampling time. */ -#define ADC_SMPR1_SMP_AN25(n) ((n) << 15) /**< @brief AN25 sampling time. */ -/** @} */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) -extern ADCDriver ADCD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void adc_lld_init(void); - void adc_lld_start(ADCDriver *adcp); - void adc_lld_stop(ADCDriver *adcp); - void adc_lld_start_conversion(ADCDriver *adcp); - void adc_lld_stop_conversion(ADCDriver *adcp); - void adcSTM32EnableTSVREFE(void); - void adcSTM32DisableTSVREFE(void); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_ADC */ - -#endif /* _ADC_LLD_H_ */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.c b/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.c deleted file mode 100644 index e49f304b2..000000000 --- a/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.c +++ /dev/null @@ -1,396 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32L1xx/ext_lld_isr.c - * @brief STM32L1xx EXT subsystem low level driver ISR code. - * - * @addtogroup EXT - * @{ - */ - -#include "hal.h" - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -#include "ext_lld_isr.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief EXTI[0] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector58) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 0); - EXTI->PR = pr; - if (pr & (1U << 0)) - EXTD1.config->channels[0].cb(&EXTD1, 0); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[1] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector5C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 1); - EXTI->PR = pr; - if (pr & (1U << 1)) - EXTD1.config->channels[1].cb(&EXTD1, 1); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[2] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector60) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 2); - EXTI->PR = pr; - if (pr & (1U << 2)) - EXTD1.config->channels[2].cb(&EXTD1, 2); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[3] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector64) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 3); - EXTI->PR = pr; - if (pr & (1U << 3)) - EXTD1.config->channels[3].cb(&EXTD1, 3); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[4] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector68) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 4); - EXTI->PR = pr; - if (pr & (1U << 4)) - EXTD1.config->channels[4].cb(&EXTD1, 4); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[5]...EXTI[9] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector9C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) | - (1U << 9)); - EXTI->PR = pr; - if (pr & (1U << 5)) - EXTD1.config->channels[5].cb(&EXTD1, 5); - if (pr & (1U << 6)) - EXTD1.config->channels[6].cb(&EXTD1, 6); - if (pr & (1U << 7)) - EXTD1.config->channels[7].cb(&EXTD1, 7); - if (pr & (1U << 8)) - EXTD1.config->channels[8].cb(&EXTD1, 8); - if (pr & (1U << 9)) - EXTD1.config->channels[9].cb(&EXTD1, 9); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[10]...EXTI[15] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorE0) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) | - (1U << 14) | (1U << 15)); - EXTI->PR = pr; - if (pr & (1U << 10)) - EXTD1.config->channels[10].cb(&EXTD1, 10); - if (pr & (1U << 11)) - EXTD1.config->channels[11].cb(&EXTD1, 11); - if (pr & (1U << 12)) - EXTD1.config->channels[12].cb(&EXTD1, 12); - if (pr & (1U << 13)) - EXTD1.config->channels[13].cb(&EXTD1, 13); - if (pr & (1U << 14)) - EXTD1.config->channels[14].cb(&EXTD1, 14); - if (pr & (1U << 15)) - EXTD1.config->channels[15].cb(&EXTD1, 15); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[16] interrupt handler (PVD). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector44) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 16); - EXTI->PR = pr; - if (pr & (1U << 16)) - EXTD1.config->channels[16].cb(&EXTD1, 16); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[17] interrupt handler (RTC). - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorE4) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 17); - EXTI->PR = pr; - if (pr & (1U << 17)) - EXTD1.config->channels[17].cb(&EXTD1, 17); - - OSAL_IRQ_EPILOGUE(); -} -/** - * @brief EXTI[18] interrupt handler (USB_FS_WKUP). - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorE8) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 18); - EXTI->PR = pr; - if (pr & (1U << 18)) - EXTD1.config->channels[18].cb(&EXTD1, 18); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[19] interrupt handler (TAMPER_STAMP). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector48) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 19); - EXTI->PR = pr; - if (pr & (1U << 19)) - EXTD1.config->channels[19].cb(&EXTD1, 19); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[20] interrupt handler (RTC_WKUP). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector4C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 20); - EXTI->PR = pr; - if (pr & (1U << 20)) - EXTD1.config->channels[20].cb(&EXTD1, 20); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[21]...EXTI[22] interrupt handler (COMP). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector98) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & ((1U << 21) | (1U << 22)); - EXTI->PR = pr; - if (pr & (1U << 21)) - EXTD1.config->channels[21].cb(&EXTD1, 21); - if (pr & (1U << 22)) - EXTD1.config->channels[22].cb(&EXTD1, 22); - - OSAL_IRQ_EPILOGUE(); -} - -#if (STM32_EXTI_NUM_LINES > 23) || defined(__DOXYGEN__) -/** - * @brief EXTI[23] interrupt handler (Channel Acquisition). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector120) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 23); - EXTI->PR = pr; - if (pr & (1U << 23)) - EXTD1.config->channels[23].cb(&EXTD1, 23); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Enables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_enable(void) { - - nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY); - nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY); - nvicEnableVector(EXTI2_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY); - nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY); - nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY); - nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY); - nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY); - nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY); - nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY); - nvicEnableVector(USB_FS_WKUP_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY); - nvicEnableVector(TAMPER_STAMP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY); - nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY); - nvicEnableVector(COMP_IRQn, STM32_EXT_EXTI21_22_IRQ_PRIORITY); -#if STM32_EXTI_NUM_LINES > 23 - nvicEnableVector(COMP_ACQ_IRQn, STM32_EXT_EXTI23_IRQ_PRIORITY); -#endif -} - -/** - * @brief Disables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_disable(void) { - - nvicDisableVector(EXTI0_IRQn); - nvicDisableVector(EXTI1_IRQn); - nvicDisableVector(EXTI2_IRQn); - nvicDisableVector(EXTI3_IRQn); - nvicDisableVector(EXTI4_IRQn); - nvicDisableVector(EXTI9_5_IRQn); - nvicDisableVector(EXTI15_10_IRQn); - nvicDisableVector(PVD_IRQn); - nvicDisableVector(RTC_Alarm_IRQn); - nvicDisableVector(USB_FS_WKUP_IRQn); - nvicDisableVector(TAMPER_STAMP_IRQn); - nvicDisableVector(RTC_WKUP_IRQn); - nvicDisableVector(COMP_IRQn); -#if STM32_EXTI_NUM_LINES > 23 - nvicDisableVector(COMP_ACQ_IRQn); -#endif -} - -#endif /* HAL_USE_EXT */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.h b/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.h deleted file mode 100644 index 9ee76fe1e..000000000 --- a/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32L1xx/ext_lld_isr.h - * @brief STM32L1xx EXT subsystem low level driver ISR header. - * - * @addtogroup EXT - * @{ - */ - -#ifndef _EXT_LLD_ISR_H_ -#define _EXT_LLD_ISR_H_ - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief EXTI0 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI1 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI2 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI3 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI4 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI9..5 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI15..10 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI16 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI17 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI18 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI19 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI20 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI21..22 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI21_22_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI23 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI23_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI23_IRQ_PRIORITY 6 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void ext_lld_exti_irq_enable(void); - void ext_lld_exti_irq_disable(void); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EXT */ - -#endif /* _EXT_LLD_ISR_H_ */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.c b/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.c new file mode 100644 index 000000000..34d84632d --- /dev/null +++ b/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.c @@ -0,0 +1,291 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32L1xx/adc_lld.c + * @brief STM32L1xx ADC subsystem low level driver source. + * + * @addtogroup ADC + * @{ + */ + +#include "hal.h" + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief ADC1 driver identifier.*/ +#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) +ADCDriver ADCD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief ADC DMA ISR service routine. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { + + /* DMA errors handling.*/ + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + /* DMA, this could help only if the DMA tries to access an unmapped + address space or violates alignment rules.*/ + _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); + } + else { + /* It is possible that the conversion group has already be reset by the + ADC error handler, in this case this interrupt is spurious.*/ + if (adcp->grpp != NULL) { + if ((flags & STM32_DMA_ISR_TCIF) != 0) { + /* Transfer complete processing.*/ + _adc_isr_full_code(adcp); + } + else if ((flags & STM32_DMA_ISR_HTIF) != 0) { + /* Half transfer processing.*/ + _adc_isr_half_code(adcp); + } + } + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) +/** + * @brief ADC interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector88) { + uint32_t sr; + + OSAL_IRQ_PROLOGUE(); + + sr = ADC1->SR; + ADC1->SR = 0; + /* Note, an overflow may occur after the conversion ended before the driver + is able to stop the ADC, this is why the DMA channel is checked too.*/ + if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) { + /* ADC overflow condition, this could happen only if the DMA is unable + to read data fast enough.*/ + if (ADCD1.grpp != NULL) + _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW); + } + /* TODO: Add here analog watchdog handling.*/ + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ADC driver initialization. + * + * @notapi + */ +void adc_lld_init(void) { + +#if STM32_ADC_USE_ADC1 + /* Driver initialization.*/ + adcObjectInit(&ADCD1); + ADCD1.adc = ADC1; + ADCD1.dmastp = STM32_DMA1_STREAM1; + ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; +#endif + + /* The shared vector is initialized on driver initialization and never + disabled.*/ + nvicEnableVector(ADC1_IRQn, STM32_ADC_IRQ_PRIORITY); +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) { + + /* If in stopped state then enables the ADC and DMA clocks.*/ + if (adcp->state == ADC_STOP) { +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + bool b = dmaStreamAllocate(adcp->dmastp, + STM32_ADC_ADC1_DMA_IRQ_PRIORITY, + (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, + (void *)adcp); + osalDbgAssert(!b, "stream already allocated"); + dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); + rccEnableADC1(FALSE); + } +#endif /* STM32_ADC_USE_ADC1 */ + + ADC->CCR = (ADC->CCR & ADC_CCR_TSVREFE) | (STM32_ADC_ADCPRE << 16); + + /* ADC initial setup, starting the analog part here in order to reduce + the latency when starting a conversion.*/ + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + adcp->adc->CR2 = ADC_CR2_ADON; + } +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) { + + /* If in ready state then disables the ADC clock and analog part.*/ + if (adcp->state == ADC_READY) { + dmaStreamRelease(adcp->dmastp); + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) + rccDisableADC1(FALSE); +#endif + } +} + +/** + * @brief Starts an ADC conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) { + uint32_t mode; + uint32_t cr2; + const ADCConversionGroup *grpp = adcp->grpp; + + /* DMA setup.*/ + mode = adcp->dmamode; + if (grpp->circular) { + mode |= STM32_DMA_CR_CIRC; + if (adcp->depth > 1) { + /* If circular buffer depth > 1, then the half transfer interrupt + is enabled in order to allow streaming processing.*/ + mode |= STM32_DMA_CR_HTIE; + } + } + dmaStreamSetMemory0(adcp->dmastp, adcp->samples); + dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels * + (uint32_t)adcp->depth); + dmaStreamSetMode(adcp->dmastp, mode); + dmaStreamEnable(adcp->dmastp); + + /* ADC setup.*/ + adcp->adc->SR = 0; + adcp->adc->SMPR1 = grpp->smpr1; + adcp->adc->SMPR2 = grpp->smpr2; + adcp->adc->SMPR3 = grpp->smpr3; + adcp->adc->SQR1 = grpp->sqr1; + adcp->adc->SQR2 = grpp->sqr2; + adcp->adc->SQR3 = grpp->sqr3; + adcp->adc->SQR4 = grpp->sqr4; + adcp->adc->SQR5 = grpp->sqr5; + + /* ADC configuration and start.*/ + adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN; + + /* Enforcing the mandatory bits in CR2.*/ + cr2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_DDS | ADC_CR2_ADON; + + /* The start method is different dependign if HW or SW triggered, the + start is performed using the method specified in the CR2 configuration.*/ + if ((cr2 & ADC_CR2_SWSTART) != 0) { + /* Initializing CR2 while keeping ADC_CR2_SWSTART at zero.*/ + adcp->adc->CR2 = (cr2 | ADC_CR2_CONT) & ~ADC_CR2_SWSTART; + + /* Finally enabling ADC_CR2_SWSTART.*/ + adcp->adc->CR2 = (cr2 | ADC_CR2_CONT); + } + else + adcp->adc->CR2 = cr2; +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) { + + dmaStreamDisable(adcp->dmastp); + adcp->adc->CR1 = 0; + adcp->adc->CR2 = 0; + adcp->adc->CR2 = ADC_CR2_ADON; +} + +/** + * @brief Enables the TSVREFE bit. + * @details The TSVREFE bit is required in order to sample the internal + * temperature sensor and internal reference voltage. + * @note This is an STM32-only functionality. + */ +void adcSTM32EnableTSVREFE(void) { + + ADC->CCR |= ADC_CCR_TSVREFE; +} + +/** + * @brief Disables the TSVREFE bit. + * @details The TSVREFE bit is required in order to sample the internal + * temperature sensor and internal reference voltage. + * @note This is an STM32-only functionality. + */ +void adcSTM32DisableTSVREFE(void) { + + ADC->CCR &= ~ADC_CCR_TSVREFE; +} + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.h b/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.h new file mode 100644 index 000000000..551275994 --- /dev/null +++ b/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.h @@ -0,0 +1,494 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32L1xx/adc_lld.h + * @brief STM32L1xx ADC subsystem low level driver header. + * + * @addtogroup ADC + * @{ + */ + +#ifndef _ADC_LLD_H_ +#define _ADC_LLD_H_ + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Triggers selection + * @{ + */ +#define ADC_CR2_EXTSEL_SRC(n) ((n) << 24) /**< @brief Trigger source. */ +/** @} */ + +/** + * @name ADC clock divider settings + * @{ + */ +#define ADC_CCR_ADCPRE_DIV1 0 +#define ADC_CCR_ADCPRE_DIV2 1 +#define ADC_CCR_ADCPRE_DIV4 2 +/** @} */ + +/** + * @name Available analog channels + * @{ + */ +#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ +#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ +#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ +#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ +#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ +#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ +#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ +#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ +#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ +#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ +#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ +#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ +#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ +#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ +#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ +#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ +#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/ +#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */ +#define ADC_CHANNEL_IN18 18 /**< @brief External analog input 18. */ +#define ADC_CHANNEL_IN19 19 /**< @brief External analog input 19. */ +#define ADC_CHANNEL_IN20 20 /**< @brief External analog input 20. */ +#define ADC_CHANNEL_IN21 21 /**< @brief External analog input 21. */ +#define ADC_CHANNEL_IN22 22 /**< @brief External analog input 22. */ +#define ADC_CHANNEL_IN23 23 /**< @brief External analog input 23. */ +#define ADC_CHANNEL_IN24 24 /**< @brief External analog input 24. */ +#define ADC_CHANNEL_IN25 25 /**< @brief External analog input 25. */ +/** @} */ + +/** + * @name Sampling rates + * @{ + */ +#define ADC_SAMPLE_4 0 /**< @brief 4 cycles sampling time. */ +#define ADC_SAMPLE_9 1 /**< @brief 9 cycles sampling time. */ +#define ADC_SAMPLE_16 2 /**< @brief 16 cycles sampling time. */ +#define ADC_SAMPLE_24 3 /**< @brief 24 cycles sampling time. */ +#define ADC_SAMPLE_48 4 /**< @brief 48 cycles sampling time. */ +#define ADC_SAMPLE_96 5 /**< @brief 96 cycles sampling time. */ +#define ADC_SAMPLE_192 6 /**< @brief 192 cycles sampling time. */ +#define ADC_SAMPLE_384 7 /**< @brief 384 cycles sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief ADC1 driver enable switch. + * @details If set to @p TRUE the support for ADC1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) +#define STM32_ADC_USE_ADC1 FALSE +#endif + +/** + * @brief ADC common clock divider. + * @note This setting is influenced by the VDDA voltage and other + * external conditions, please refer to the STM32L15x datasheet + * for more info.
+ * See section 6.3.15 "12-bit ADC characteristics". + */ +#if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__) +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV1 +#endif + +/** + * @brief ADC1 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC interrupt priority level setting. + */ +#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_IRQ_PRIORITY 5 +#endif + +/** + * @brief ADC1 DMA interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 +#error "ADC1 not present in the selected device" +#endif + +#if !STM32_ADC_USE_ADC1 +#error "ADC driver activated but no ADC peripheral assigned" +#endif + +#if STM32_ADC_USE_ADC1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to ADC1" +#endif + +#if STM32_ADC_USE_ADC1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to ADC1 DMA" +#endif + +#if STM32_ADC_USE_ADC1 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY) +#error "Invalid DMA priority assigned to ADC1" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/** + * * @brief ADC frequency. + * */ +/* ADC clock related settings and checks.*/ +#if STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV1 +#define STM32_ADCCLK STM32_HSICLK +#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV2 +#define STM32_ADCCLK (STM32_HSICLK / 2) +#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV4 +#define STM32_ADCCLK (STM32_HSICLK / 4) +#else +#error "invalid STM32_ADC_ADCPRE value specified" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ADC sample data type. + */ +typedef uint16_t adcsample_t; + +/** + * @brief Channels number in a conversion group. + */ +typedef uint16_t adc_channels_num_t; + +/** + * @brief Possible ADC failure causes. + * @note Error codes are architecture dependent and should not relied + * upon. + */ +typedef enum { + ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */ + ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */ +} adcerror_t; + +/** + * @brief Type of a structure representing an ADC driver. + */ +typedef struct ADCDriver ADCDriver; + +/** + * @brief ADC notification callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] buffer pointer to the most recent samples data + * @param[in] n number of buffer rows available starting from @p buffer + */ +typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); + +/** + * @brief ADC error callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] err ADC error code + */ +typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); + +/** + * @brief Conversion group configuration structure. + * @details This implementation-dependent structure describes a conversion + * operation. + * @note The use of this configuration structure requires knowledge of + * STM32 ADC cell registers interface, please refer to the STM32 + * reference manual for details. + */ +typedef struct { + /** + * @brief Enables the circular buffer mode for the group. + */ + bool circular; + /** + * @brief Number of the analog channels belonging to the conversion group. + */ + adc_channels_num_t num_channels; + /** + * @brief Callback function associated to the group or @p NULL. + */ + adccallback_t end_cb; + /** + * @brief Error callback or @p NULL. + */ + adcerrorcallback_t error_cb; + /* End of the mandatory fields.*/ + /** + * @brief ADC CR1 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR1_SCAN that is enforced inside the driver. + */ + uint32_t cr1; + /** + * @brief ADC CR2 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are + * enforced inside the driver. + */ + uint32_t cr2; + /** + * @brief ADC SMPR1 register initialization data. + * @details In this field must be specified the sample times for channels + * 20...25. + */ + uint32_t smpr1; + /** + * @brief ADC SMPR2 register initialization data. + * @details In this field must be specified the sample times for channels + * 10...19. + */ + uint32_t smpr2; + /** + * @brief ADC SMPR3 register initialization data. + * @details In this field must be specified the sample times for channels + * 0...9. + */ + uint32_t smpr3; + /** + * @brief ADC SQR1 register initialization data. + * @details Conversion group sequence 25...27 + sequence length. + */ + uint32_t sqr1; + /** + * @brief ADC SQR2 register initialization data. + * @details Conversion group sequence 19...24. + */ + uint32_t sqr2; + /** + * @brief ADC SQR3 register initialization data. + * @details Conversion group sequence 13...18. + */ + uint32_t sqr3; + /** + * @brief ADC SQR3 register initialization data. + * @details Conversion group sequence 7...12. + */ + uint32_t sqr4; + /** + * @brief ADC SQR3 register initialization data. + * @details Conversion group sequence 1...6. + */ + uint32_t sqr5; +} ADCConversionGroup; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + uint32_t dummy; +} ADCConfig; + +/** + * @brief Structure representing an ADC driver. + */ +struct ADCDriver { + /** + * @brief Driver state. + */ + adcstate_t state; + /** + * @brief Current configuration data. + */ + const ADCConfig *config; + /** + * @brief Current samples buffer pointer or @p NULL. + */ + adcsample_t *samples; + /** + * @brief Current samples buffer depth or @p 0. + */ + size_t depth; + /** + * @brief Current conversion group pointer or @p NULL. + */ + const ADCConversionGroup *grpp; +#if ADC_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + thread_reference_t thread; +#endif +#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + mutex_t mutex; +#endif /* ADC_USE_MUTUAL_EXCLUSION */ +#if defined(ADC_DRIVER_EXT_FIELDS) + ADC_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the ADCx registers block. + */ + ADC_TypeDef *adc; + /** + * @brief Pointer to associated DMA channel. + */ + const stm32_dma_stream_t *dmastp; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Sequences building helper macros + * @{ + */ +/** + * @brief Number of channels in a conversion sequence. + */ +#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20) + +#define ADC_SQR5_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ +#define ADC_SQR5_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ +#define ADC_SQR5_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ +#define ADC_SQR5_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ +#define ADC_SQR5_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ +#define ADC_SQR5_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ + +#define ADC_SQR4_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ +#define ADC_SQR4_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ +#define ADC_SQR4_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ +#define ADC_SQR4_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ +#define ADC_SQR4_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ +#define ADC_SQR4_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ + +#define ADC_SQR3_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ +#define ADC_SQR3_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ +#define ADC_SQR3_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ +#define ADC_SQR3_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ +#define ADC_SQR3_SQ17_N(n) ((n) << 20) /**< @brief 17th channel in seq.*/ +#define ADC_SQR3_SQ18_N(n) ((n) << 25) /**< @brief 18th channel in seq.*/ + +#define ADC_SQR2_SQ19_N(n) ((n) << 0) /**< @brief 19th channel in seq.*/ +#define ADC_SQR2_SQ20_N(n) ((n) << 5) /**< @brief 20th channel in seq.*/ +#define ADC_SQR2_SQ21_N(n) ((n) << 10) /**< @brief 21th channel in seq.*/ +#define ADC_SQR2_SQ22_N(n) ((n) << 15) /**< @brief 22th channel in seq.*/ +#define ADC_SQR2_SQ23_N(n) ((n) << 20) /**< @brief 23th channel in seq.*/ +#define ADC_SQR2_SQ24_N(n) ((n) << 25) /**< @brief 24th channel in seq.*/ + +#define ADC_SQR1_SQ25_N(n) ((n) << 0) /**< @brief 25th channel in seq.*/ +#define ADC_SQR1_SQ26_N(n) ((n) << 5) /**< @brief 26th channel in seq.*/ +#define ADC_SQR1_SQ27_N(n) ((n) << 10) /**< @brief 27th channel in seq.*/ +/** @} */ + +/** + * @name Sampling rate settings helper macros + * @{ + */ +#define ADC_SMPR3_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ +#define ADC_SMPR3_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ +#define ADC_SMPR3_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ +#define ADC_SMPR3_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ +#define ADC_SMPR3_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ +#define ADC_SMPR3_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ +#define ADC_SMPR3_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ +#define ADC_SMPR3_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ +#define ADC_SMPR3_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ +#define ADC_SMPR3_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ + +#define ADC_SMPR2_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ +#define ADC_SMPR2_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ +#define ADC_SMPR2_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ +#define ADC_SMPR2_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ +#define ADC_SMPR2_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ +#define ADC_SMPR2_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ +#define ADC_SMPR2_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor + sampling time. */ +#define ADC_SMPR2_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference + sampling time. */ +#define ADC_SMPR2_SMP_AN18(n) ((n) << 24) /**< @brief AN18 sampling time. */ +#define ADC_SMPR2_SMP_AN19(n) ((n) << 27) /**< @brief AN19 sampling time. */ + +#define ADC_SMPR1_SMP_AN20(n) ((n) << 0) /**< @brief AN20 sampling time. */ +#define ADC_SMPR1_SMP_AN21(n) ((n) << 3) /**< @brief AN21 sampling time. */ +#define ADC_SMPR1_SMP_AN22(n) ((n) << 6) /**< @brief AN22 sampling time. */ +#define ADC_SMPR1_SMP_AN23(n) ((n) << 9) /**< @brief AN23 sampling time. */ +#define ADC_SMPR1_SMP_AN24(n) ((n) << 12) /**< @brief AN24 sampling time. */ +#define ADC_SMPR1_SMP_AN25(n) ((n) << 15) /**< @brief AN25 sampling time. */ +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) +extern ADCDriver ADCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void adc_lld_init(void); + void adc_lld_start(ADCDriver *adcp); + void adc_lld_stop(ADCDriver *adcp); + void adc_lld_start_conversion(ADCDriver *adcp); + void adc_lld_stop_conversion(ADCDriver *adcp); + void adcSTM32EnableTSVREFE(void); + void adcSTM32DisableTSVREFE(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC */ + +#endif /* _ADC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32L1xx/hal_ext_lld_isr.c b/os/hal/ports/STM32/STM32L1xx/hal_ext_lld_isr.c new file mode 100644 index 000000000..9287461e2 --- /dev/null +++ b/os/hal/ports/STM32/STM32L1xx/hal_ext_lld_isr.c @@ -0,0 +1,396 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32L1xx/ext_lld_isr.c + * @brief STM32L1xx EXT subsystem low level driver ISR code. + * + * @addtogroup EXT + * @{ + */ + +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +#include "hal_ext_lld_isr.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief EXTI[0] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector58) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 0); + EXTI->PR = pr; + if (pr & (1U << 0)) + EXTD1.config->channels[0].cb(&EXTD1, 0); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[1] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector5C) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 1); + EXTI->PR = pr; + if (pr & (1U << 1)) + EXTD1.config->channels[1].cb(&EXTD1, 1); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[2] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector60) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 2); + EXTI->PR = pr; + if (pr & (1U << 2)) + EXTD1.config->channels[2].cb(&EXTD1, 2); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[3] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector64) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 3); + EXTI->PR = pr; + if (pr & (1U << 3)) + EXTD1.config->channels[3].cb(&EXTD1, 3); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[4] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector68) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 4); + EXTI->PR = pr; + if (pr & (1U << 4)) + EXTD1.config->channels[4].cb(&EXTD1, 4); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[5]...EXTI[9] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector9C) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) | + (1U << 9)); + EXTI->PR = pr; + if (pr & (1U << 5)) + EXTD1.config->channels[5].cb(&EXTD1, 5); + if (pr & (1U << 6)) + EXTD1.config->channels[6].cb(&EXTD1, 6); + if (pr & (1U << 7)) + EXTD1.config->channels[7].cb(&EXTD1, 7); + if (pr & (1U << 8)) + EXTD1.config->channels[8].cb(&EXTD1, 8); + if (pr & (1U << 9)) + EXTD1.config->channels[9].cb(&EXTD1, 9); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[10]...EXTI[15] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(VectorE0) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) | + (1U << 14) | (1U << 15)); + EXTI->PR = pr; + if (pr & (1U << 10)) + EXTD1.config->channels[10].cb(&EXTD1, 10); + if (pr & (1U << 11)) + EXTD1.config->channels[11].cb(&EXTD1, 11); + if (pr & (1U << 12)) + EXTD1.config->channels[12].cb(&EXTD1, 12); + if (pr & (1U << 13)) + EXTD1.config->channels[13].cb(&EXTD1, 13); + if (pr & (1U << 14)) + EXTD1.config->channels[14].cb(&EXTD1, 14); + if (pr & (1U << 15)) + EXTD1.config->channels[15].cb(&EXTD1, 15); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[16] interrupt handler (PVD). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector44) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 16); + EXTI->PR = pr; + if (pr & (1U << 16)) + EXTD1.config->channels[16].cb(&EXTD1, 16); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[17] interrupt handler (RTC). + * + * @isr + */ +OSAL_IRQ_HANDLER(VectorE4) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 17); + EXTI->PR = pr; + if (pr & (1U << 17)) + EXTD1.config->channels[17].cb(&EXTD1, 17); + + OSAL_IRQ_EPILOGUE(); +} +/** + * @brief EXTI[18] interrupt handler (USB_FS_WKUP). + * + * @isr + */ +OSAL_IRQ_HANDLER(VectorE8) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 18); + EXTI->PR = pr; + if (pr & (1U << 18)) + EXTD1.config->channels[18].cb(&EXTD1, 18); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[19] interrupt handler (TAMPER_STAMP). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector48) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 19); + EXTI->PR = pr; + if (pr & (1U << 19)) + EXTD1.config->channels[19].cb(&EXTD1, 19); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[20] interrupt handler (RTC_WKUP). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector4C) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 20); + EXTI->PR = pr; + if (pr & (1U << 20)) + EXTD1.config->channels[20].cb(&EXTD1, 20); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[21]...EXTI[22] interrupt handler (COMP). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector98) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & ((1U << 21) | (1U << 22)); + EXTI->PR = pr; + if (pr & (1U << 21)) + EXTD1.config->channels[21].cb(&EXTD1, 21); + if (pr & (1U << 22)) + EXTD1.config->channels[22].cb(&EXTD1, 22); + + OSAL_IRQ_EPILOGUE(); +} + +#if (STM32_EXTI_NUM_LINES > 23) || defined(__DOXYGEN__) +/** + * @brief EXTI[23] interrupt handler (Channel Acquisition). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector120) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 23); + EXTI->PR = pr; + if (pr & (1U << 23)) + EXTD1.config->channels[23].cb(&EXTD1, 23); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_enable(void) { + + nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY); + nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY); + nvicEnableVector(EXTI2_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY); + nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY); + nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY); + nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY); + nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY); + nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY); + nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY); + nvicEnableVector(USB_FS_WKUP_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY); + nvicEnableVector(TAMPER_STAMP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY); + nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY); + nvicEnableVector(COMP_IRQn, STM32_EXT_EXTI21_22_IRQ_PRIORITY); +#if STM32_EXTI_NUM_LINES > 23 + nvicEnableVector(COMP_ACQ_IRQn, STM32_EXT_EXTI23_IRQ_PRIORITY); +#endif +} + +/** + * @brief Disables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_disable(void) { + + nvicDisableVector(EXTI0_IRQn); + nvicDisableVector(EXTI1_IRQn); + nvicDisableVector(EXTI2_IRQn); + nvicDisableVector(EXTI3_IRQn); + nvicDisableVector(EXTI4_IRQn); + nvicDisableVector(EXTI9_5_IRQn); + nvicDisableVector(EXTI15_10_IRQn); + nvicDisableVector(PVD_IRQn); + nvicDisableVector(RTC_Alarm_IRQn); + nvicDisableVector(USB_FS_WKUP_IRQn); + nvicDisableVector(TAMPER_STAMP_IRQn); + nvicDisableVector(RTC_WKUP_IRQn); + nvicDisableVector(COMP_IRQn); +#if STM32_EXTI_NUM_LINES > 23 + nvicDisableVector(COMP_ACQ_IRQn); +#endif +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32L1xx/hal_ext_lld_isr.h b/os/hal/ports/STM32/STM32L1xx/hal_ext_lld_isr.h new file mode 100644 index 000000000..9ee76fe1e --- /dev/null +++ b/os/hal/ports/STM32/STM32L1xx/hal_ext_lld_isr.h @@ -0,0 +1,170 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32L1xx/ext_lld_isr.h + * @brief STM32L1xx EXT subsystem low level driver ISR header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_ISR_H_ +#define _EXT_LLD_ISR_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief EXTI0 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI1 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI2 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI3 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI4 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI9..5 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI15..10 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI16 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI17 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI18 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI19 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI20 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI21..22 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI21_22_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI23 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI23_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI23_IRQ_PRIORITY 6 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_exti_irq_enable(void); + void ext_lld_exti_irq_disable(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_ISR_H_ */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32L1xx/platform.mk b/os/hal/ports/STM32/STM32L1xx/platform.mk index 4ed3c8da1..e4486c731 100644 --- a/os/hal/ports/STM32/STM32L1xx/platform.mk +++ b/os/hal/ports/STM32/STM32L1xx/platform.mk @@ -5,70 +5,70 @@ HALCONF := $(strip $(shell cat halconf.h | egrep -e "define")) PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx/hal_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx/adc_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.c endif ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/hal_ext_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx/hal_ext_lld_isr.c endif ifneq ($(findstring HAL_USE_DAC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c endif ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c endif ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c endif ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c endif ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/spi_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/hal_spi_lld.c endif ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c endif ifneq ($(findstring HAL_USE_ICU TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c endif ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c endif ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/serial_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/hal_serial_lld.c endif ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/uart_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c endif ifneq ($(findstring HAL_USE_USB TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/usb_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c endif ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c endif else PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx/hal_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx/adc_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx/hal_adc_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32L1xx/hal_ext_lld_isr.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/hal_ext_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/spi_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/serial_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/uart_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/usb_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.c + $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/hal_i2c_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/hal_spi_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/hal_serial_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c endif # Required include directories diff --git a/os/hal/ports/STM32/STM32L4xx/ext_lld_isr.c b/os/hal/ports/STM32/STM32L4xx/ext_lld_isr.c deleted file mode 100644 index 235079165..000000000 --- a/os/hal/ports/STM32/STM32L4xx/ext_lld_isr.c +++ /dev/null @@ -1,361 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32L4xx/ext_lld_isr.c - * @brief STM32L4xx EXT subsystem low level driver ISR code. - * - * @addtogroup EXT - * @{ - */ - -#include "hal.h" - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -#include "ext_lld_isr.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief EXTI[0] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector58) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR1; - pr &= EXTI->IMR1 & (1U << 0); - EXTI->PR1 = pr; - if (pr & (1U << 0)) - EXTD1.config->channels[0].cb(&EXTD1, 0); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[1] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector5C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR1; - pr &= EXTI->IMR1 & (1U << 1); - EXTI->PR1 = pr; - if (pr & (1U << 1)) - EXTD1.config->channels[1].cb(&EXTD1, 1); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[2] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector60) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR1; - pr &= EXTI->IMR1 & (1U << 2); - EXTI->PR1 = pr; - if (pr & (1U << 2)) - EXTD1.config->channels[2].cb(&EXTD1, 2); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[3] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector64) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR1; - pr &= EXTI->IMR1 & (1U << 3); - EXTI->PR1 = pr; - if (pr & (1U << 3)) - EXTD1.config->channels[3].cb(&EXTD1, 3); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[4] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector68) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR1; - pr &= EXTI->IMR1 & (1U << 4); - EXTI->PR1 = pr; - if (pr & (1U << 4)) - EXTD1.config->channels[4].cb(&EXTD1, 4); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[5]...EXTI[9] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector9C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR1; - pr &= EXTI->IMR1 & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) | - (1U << 9)); - EXTI->PR1 = pr; - if (pr & (1U << 5)) - EXTD1.config->channels[5].cb(&EXTD1, 5); - if (pr & (1U << 6)) - EXTD1.config->channels[6].cb(&EXTD1, 6); - if (pr & (1U << 7)) - EXTD1.config->channels[7].cb(&EXTD1, 7); - if (pr & (1U << 8)) - EXTD1.config->channels[8].cb(&EXTD1, 8); - if (pr & (1U << 9)) - EXTD1.config->channels[9].cb(&EXTD1, 9); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[10]...EXTI[15] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorE0) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR1; - pr &= EXTI->IMR1 & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) | - (1U << 14) | (1U << 15)); - EXTI->PR1 = pr; - if (pr & (1U << 10)) - EXTD1.config->channels[10].cb(&EXTD1, 10); - if (pr & (1U << 11)) - EXTD1.config->channels[11].cb(&EXTD1, 11); - if (pr & (1U << 12)) - EXTD1.config->channels[12].cb(&EXTD1, 12); - if (pr & (1U << 13)) - EXTD1.config->channels[13].cb(&EXTD1, 13); - if (pr & (1U << 14)) - EXTD1.config->channels[14].cb(&EXTD1, 14); - if (pr & (1U << 15)) - EXTD1.config->channels[15].cb(&EXTD1, 15); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[16/35/36/37/38] interrupt handler (PVD/PVM1/PVM2/PVM3/PVM4) - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector44) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR1; - pr &= EXTI->IMR1 & (1U << 16); - EXTI->PR1 = pr; - if (pr & (1U << 16)) - EXTD1.config->channels[16].cb(&EXTD1, 16); - - pr = EXTI->PR2 & EXTI->IMR2 & ( (1U << (35-32)) | (1U << (36-32)) | - (1U << (37-32)) | (1U << (38-32)) ); - EXTI->PR2 = pr; - if (pr & (1U << (35-32))) - EXTD1.config->channels[35].cb(&EXTD1, 35); - if (pr & (1U << (36-32))) - EXTD1.config->channels[36].cb(&EXTD1, 36); - if (pr & (1U << (37-32))) - EXTD1.config->channels[37].cb(&EXTD1, 37); - if (pr & (1U << (38-32))) - EXTD1.config->channels[38].cb(&EXTD1, 38); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[18] interrupt handler (RTC_ALARM). - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorE4) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR1; - pr &= EXTI->IMR1 & (1U << 18); - EXTI->PR1 = pr; - if (pr & (1U << 18)) - EXTD1.config->channels[18].cb(&EXTD1, 18); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[19] interrupt handler (RTC_TAMP_STAMP). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector48) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR1; - pr &= EXTI->IMR1 & (1U << 19); - EXTI->PR1 = pr; - if (pr & (1U << 19)) - EXTD1.config->channels[19].cb(&EXTD1, 19); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[20] interrupt handler (RTC_WKUP). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector4C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR1; - pr &= EXTI->IMR1 & (1U << 20); - EXTI->PR1 = pr; - if (pr & (1U << 20)) - EXTD1.config->channels[20].cb(&EXTD1, 20); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief EXTI[21/22] interrupt handler (COMP1,COMP2). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector140) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR1; - pr &= EXTI->IMR1 & ( (1U << 21) | ( 1U << 22 ) ); - EXTI->PR1 = pr; - if (pr & (1U << 21)) - EXTD1.config->channels[21].cb(&EXTD1, 21); - if (pr & (1U << 22)) - EXTD1.config->channels[22].cb(&EXTD1, 22); - - OSAL_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Enables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_enable(void) { - - nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY); - nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY); - nvicEnableVector(EXTI2_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY); - nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY); - nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY); - nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY); - nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY); - nvicEnableVector(PVD_PVM_IRQn, STM32_EXT_EXTI1635_38_IRQ_PRIORITY); - nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY); - nvicEnableVector(TAMP_STAMP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY); - nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY); - nvicEnableVector(COMP_IRQn, STM32_EXT_EXTI21_22_IRQ_PRIORITY); -} - -/** - * @brief Disables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_disable(void) { - - nvicDisableVector(EXTI0_IRQn); - nvicDisableVector(EXTI1_IRQn); - nvicDisableVector(EXTI2_IRQn); - nvicDisableVector(EXTI3_IRQn); - nvicDisableVector(EXTI4_IRQn); - nvicDisableVector(EXTI9_5_IRQn); - nvicDisableVector(EXTI15_10_IRQn); - nvicDisableVector(PVD_PVM_IRQn); - nvicDisableVector(RTC_Alarm_IRQn); - nvicDisableVector(TAMP_STAMP_IRQn); - nvicDisableVector(RTC_WKUP_IRQn); - nvicDisableVector(COMP_IRQn); -} - -#endif /* HAL_USE_EXT */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32L4xx/ext_lld_isr.h b/os/hal/ports/STM32/STM32L4xx/ext_lld_isr.h deleted file mode 100644 index 168bd0633..000000000 --- a/os/hal/ports/STM32/STM32L4xx/ext_lld_isr.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32L4xx/ext_lld_isr.h - * @brief STM32L4xx EXT subsystem low level driver ISR header. - * - * @addtogroup EXT - * @{ - */ - -#ifndef _EXT_LLD_ISR_H_ -#define _EXT_LLD_ISR_H_ - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief EXTI0 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI1 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI2 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI3 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI4 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI9..5 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI15..10 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI16-EXTI35..38 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI1635_38_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI1635_38_IRQ_PRIORIT 6 -#endif - -/** - * @brief EXTI18 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI19 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI20 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI21..22 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI21_22_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void ext_lld_exti_irq_enable(void); - void ext_lld_exti_irq_disable(void); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EXT */ - -#endif /* _EXT_LLD_ISR_H_ */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32L4xx/hal_ext_lld_isr.c b/os/hal/ports/STM32/STM32L4xx/hal_ext_lld_isr.c new file mode 100644 index 000000000..45237090d --- /dev/null +++ b/os/hal/ports/STM32/STM32L4xx/hal_ext_lld_isr.c @@ -0,0 +1,361 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32L4xx/ext_lld_isr.c + * @brief STM32L4xx EXT subsystem low level driver ISR code. + * + * @addtogroup EXT + * @{ + */ + +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +#include "hal_ext_lld_isr.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief EXTI[0] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector58) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR1; + pr &= EXTI->IMR1 & (1U << 0); + EXTI->PR1 = pr; + if (pr & (1U << 0)) + EXTD1.config->channels[0].cb(&EXTD1, 0); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[1] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector5C) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR1; + pr &= EXTI->IMR1 & (1U << 1); + EXTI->PR1 = pr; + if (pr & (1U << 1)) + EXTD1.config->channels[1].cb(&EXTD1, 1); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[2] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector60) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR1; + pr &= EXTI->IMR1 & (1U << 2); + EXTI->PR1 = pr; + if (pr & (1U << 2)) + EXTD1.config->channels[2].cb(&EXTD1, 2); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[3] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector64) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR1; + pr &= EXTI->IMR1 & (1U << 3); + EXTI->PR1 = pr; + if (pr & (1U << 3)) + EXTD1.config->channels[3].cb(&EXTD1, 3); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[4] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector68) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR1; + pr &= EXTI->IMR1 & (1U << 4); + EXTI->PR1 = pr; + if (pr & (1U << 4)) + EXTD1.config->channels[4].cb(&EXTD1, 4); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[5]...EXTI[9] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector9C) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR1; + pr &= EXTI->IMR1 & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) | + (1U << 9)); + EXTI->PR1 = pr; + if (pr & (1U << 5)) + EXTD1.config->channels[5].cb(&EXTD1, 5); + if (pr & (1U << 6)) + EXTD1.config->channels[6].cb(&EXTD1, 6); + if (pr & (1U << 7)) + EXTD1.config->channels[7].cb(&EXTD1, 7); + if (pr & (1U << 8)) + EXTD1.config->channels[8].cb(&EXTD1, 8); + if (pr & (1U << 9)) + EXTD1.config->channels[9].cb(&EXTD1, 9); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[10]...EXTI[15] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(VectorE0) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR1; + pr &= EXTI->IMR1 & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) | + (1U << 14) | (1U << 15)); + EXTI->PR1 = pr; + if (pr & (1U << 10)) + EXTD1.config->channels[10].cb(&EXTD1, 10); + if (pr & (1U << 11)) + EXTD1.config->channels[11].cb(&EXTD1, 11); + if (pr & (1U << 12)) + EXTD1.config->channels[12].cb(&EXTD1, 12); + if (pr & (1U << 13)) + EXTD1.config->channels[13].cb(&EXTD1, 13); + if (pr & (1U << 14)) + EXTD1.config->channels[14].cb(&EXTD1, 14); + if (pr & (1U << 15)) + EXTD1.config->channels[15].cb(&EXTD1, 15); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[16/35/36/37/38] interrupt handler (PVD/PVM1/PVM2/PVM3/PVM4) + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector44) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR1; + pr &= EXTI->IMR1 & (1U << 16); + EXTI->PR1 = pr; + if (pr & (1U << 16)) + EXTD1.config->channels[16].cb(&EXTD1, 16); + + pr = EXTI->PR2 & EXTI->IMR2 & ( (1U << (35-32)) | (1U << (36-32)) | + (1U << (37-32)) | (1U << (38-32)) ); + EXTI->PR2 = pr; + if (pr & (1U << (35-32))) + EXTD1.config->channels[35].cb(&EXTD1, 35); + if (pr & (1U << (36-32))) + EXTD1.config->channels[36].cb(&EXTD1, 36); + if (pr & (1U << (37-32))) + EXTD1.config->channels[37].cb(&EXTD1, 37); + if (pr & (1U << (38-32))) + EXTD1.config->channels[38].cb(&EXTD1, 38); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[18] interrupt handler (RTC_ALARM). + * + * @isr + */ +OSAL_IRQ_HANDLER(VectorE4) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR1; + pr &= EXTI->IMR1 & (1U << 18); + EXTI->PR1 = pr; + if (pr & (1U << 18)) + EXTD1.config->channels[18].cb(&EXTD1, 18); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[19] interrupt handler (RTC_TAMP_STAMP). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector48) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR1; + pr &= EXTI->IMR1 & (1U << 19); + EXTI->PR1 = pr; + if (pr & (1U << 19)) + EXTD1.config->channels[19].cb(&EXTD1, 19); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[20] interrupt handler (RTC_WKUP). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector4C) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR1; + pr &= EXTI->IMR1 & (1U << 20); + EXTI->PR1 = pr; + if (pr & (1U << 20)) + EXTD1.config->channels[20].cb(&EXTD1, 20); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[21/22] interrupt handler (COMP1,COMP2). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector140) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR1; + pr &= EXTI->IMR1 & ( (1U << 21) | ( 1U << 22 ) ); + EXTI->PR1 = pr; + if (pr & (1U << 21)) + EXTD1.config->channels[21].cb(&EXTD1, 21); + if (pr & (1U << 22)) + EXTD1.config->channels[22].cb(&EXTD1, 22); + + OSAL_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_enable(void) { + + nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY); + nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY); + nvicEnableVector(EXTI2_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY); + nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY); + nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY); + nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY); + nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY); + nvicEnableVector(PVD_PVM_IRQn, STM32_EXT_EXTI1635_38_IRQ_PRIORITY); + nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY); + nvicEnableVector(TAMP_STAMP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY); + nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY); + nvicEnableVector(COMP_IRQn, STM32_EXT_EXTI21_22_IRQ_PRIORITY); +} + +/** + * @brief Disables EXTI IRQ sources. + * + * @notapi + */ +void ext_lld_exti_irq_disable(void) { + + nvicDisableVector(EXTI0_IRQn); + nvicDisableVector(EXTI1_IRQn); + nvicDisableVector(EXTI2_IRQn); + nvicDisableVector(EXTI3_IRQn); + nvicDisableVector(EXTI4_IRQn); + nvicDisableVector(EXTI9_5_IRQn); + nvicDisableVector(EXTI15_10_IRQn); + nvicDisableVector(PVD_PVM_IRQn); + nvicDisableVector(RTC_Alarm_IRQn); + nvicDisableVector(TAMP_STAMP_IRQn); + nvicDisableVector(RTC_WKUP_IRQn); + nvicDisableVector(COMP_IRQn); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32L4xx/hal_ext_lld_isr.h b/os/hal/ports/STM32/STM32L4xx/hal_ext_lld_isr.h new file mode 100644 index 000000000..168bd0633 --- /dev/null +++ b/os/hal/ports/STM32/STM32L4xx/hal_ext_lld_isr.h @@ -0,0 +1,156 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32L4xx/ext_lld_isr.h + * @brief STM32L4xx EXT subsystem low level driver ISR header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef _EXT_LLD_ISR_H_ +#define _EXT_LLD_ISR_H_ + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief EXTI0 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI1 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI2 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI3 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI4 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI9..5 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI15..10 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI16-EXTI35..38 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI1635_38_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI1635_38_IRQ_PRIORIT 6 +#endif + +/** + * @brief EXTI18 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI19 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI20 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#endif + +/** + * @brief EXTI21..22 interrupt priority level setting. + */ +#if !defined(STM32_EXT_EXTI21_22_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_exti_irq_enable(void); + void ext_lld_exti_irq_disable(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* _EXT_LLD_ISR_H_ */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32L4xx/platform.mk b/os/hal/ports/STM32/STM32L4xx/platform.mk index 1028cc5e5..e6ea2706b 100644 --- a/os/hal/ports/STM32/STM32L4xx/platform.mk +++ b/os/hal/ports/STM32/STM32L4xx/platform.mk @@ -5,78 +5,78 @@ HALCONF := $(strip $(shell cat halconf.h | egrep -e "define")) PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/hal_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/adc_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c endif ifneq ($(findstring HAL_USE_CAN TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c endif ifneq ($(findstring HAL_USE_DAC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c endif ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/ext_lld_isr.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/hal_ext_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/hal_ext_lld_isr.c endif ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv3/pal_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.c endif ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.c endif ifneq ($(findstring HAL_USE_USB TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/usb_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c endif ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c endif ifneq ($(findstring HAL_USE_SDC TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1/sdc_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c endif ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.c endif ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c endif ifneq ($(findstring HAL_USE_ICU TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c endif ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c endif ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c endif ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/uart_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c endif ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.c +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c endif else PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/hal_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/ext_lld_isr.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/adc_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/hal_ext_lld_isr.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/hal_can_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv3/pal_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/usb_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1/sdc_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/uart_lld.c \ - $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/wdg_lld.c + $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/hal_ext_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_icu_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c endif # Required include directories -- cgit v1.2.3