From 56f18ed54da774cf8c7527545812be6a7cdb28fa Mon Sep 17 00:00:00 2001 From: lbednarz Date: Wed, 2 Apr 2014 18:26:14 +0000 Subject: merged RX stuff git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6831 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/include/usb.h | 9 + os/hal/platforms/Rx62n/hal_lld.c | 75 + os/hal/platforms/Rx62n/hal_lld.h | 361 ++ os/hal/platforms/Rx62n/iodefine_gcc62n.h | 7317 ++++++++++++++++++++++++++ os/hal/platforms/Rx62n/mac_lld.c | 667 +++ os/hal/platforms/Rx62n/mac_lld.h | 340 ++ os/hal/platforms/Rx62n/pal_lld.c | 310 ++ os/hal/platforms/Rx62n/pal_lld.h | 452 ++ os/hal/platforms/Rx62n/rx62n_mii.c | 259 + os/hal/platforms/Rx62n/rx62n_mii.h | 87 + os/hal/platforms/Rx62n/serial_lld.c | 306 ++ os/hal/platforms/Rx62n/serial_lld.h | 142 + os/hal/platforms/Rx62n/usb_lld.c | 983 ++++ os/hal/platforms/Rx62n/usb_lld.h | 534 ++ os/hal/src/usb.c | 26 +- os/ports/GCC/RX/RX62N/ld/R5F562N8xxxx_ram.ld | 167 + os/ports/GCC/RX/RX62N/rxparams.h | 59 + os/ports/GCC/RX/RX62N/vectors.c | 519 ++ os/ports/GCC/RX/chcore.c | 150 + os/ports/GCC/RX/chcore.h | 356 ++ os/ports/GCC/RX/chtypes.h | 87 + os/ports/GCC/RX/crt0.c | 302 ++ 22 files changed, 13507 insertions(+), 1 deletion(-) create mode 100644 os/hal/platforms/Rx62n/hal_lld.c create mode 100644 os/hal/platforms/Rx62n/hal_lld.h create mode 100644 os/hal/platforms/Rx62n/iodefine_gcc62n.h create mode 100644 os/hal/platforms/Rx62n/mac_lld.c create mode 100644 os/hal/platforms/Rx62n/mac_lld.h create mode 100644 os/hal/platforms/Rx62n/pal_lld.c create mode 100644 os/hal/platforms/Rx62n/pal_lld.h create mode 100644 os/hal/platforms/Rx62n/rx62n_mii.c create mode 100644 os/hal/platforms/Rx62n/rx62n_mii.h create mode 100644 os/hal/platforms/Rx62n/serial_lld.c create mode 100644 os/hal/platforms/Rx62n/serial_lld.h create mode 100644 os/hal/platforms/Rx62n/usb_lld.c create mode 100644 os/hal/platforms/Rx62n/usb_lld.h create mode 100644 os/ports/GCC/RX/RX62N/ld/R5F562N8xxxx_ram.ld create mode 100644 os/ports/GCC/RX/RX62N/rxparams.h create mode 100644 os/ports/GCC/RX/RX62N/vectors.c create mode 100644 os/ports/GCC/RX/chcore.c create mode 100644 os/ports/GCC/RX/chcore.h create mode 100644 os/ports/GCC/RX/chtypes.h create mode 100644 os/ports/GCC/RX/crt0.c (limited to 'os') diff --git a/os/hal/include/usb.h b/os/hal/include/usb.h index 4a948a84f..9cfc0fb00 100644 --- a/os/hal/include/usb.h +++ b/os/hal/include/usb.h @@ -78,6 +78,12 @@ #define USB_EARLY_SET_ADDRESS 0 #define USB_LATE_SET_ADDRESS 1 +#define USB_EP0_STATUS_STAGE_SW 0 +#define USB_EP0_STATUS_STAGE_HW 1 + +#define USB_SET_ADDRESS_ACK_SW 0 +#define USB_SET_ADDRESS_ACK_HW 1 + /** * @name Helper macros for USB descriptors * @{ @@ -445,6 +451,9 @@ typedef const USBDescriptor * (*usbgetdescriptor_t)(USBDriver *usbp, (usbp)->ep0endcb = (endcb); \ } +#define usbSetupEnd(usbp, ep) \ + usb_lld_end_transaction(usbp, ep) + /** * @brief Reads a setup packet from the dedicated packet buffer. * @details This function must be invoked in the context of the @p setup_cb diff --git a/os/hal/platforms/Rx62n/hal_lld.c b/os/hal/platforms/Rx62n/hal_lld.c new file mode 100644 index 000000000..61048dd47 --- /dev/null +++ b/os/hal/platforms/Rx62n/hal_lld.c @@ -0,0 +1,75 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RX62N/hal_lld.c + * @brief RX62N HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + +} + +/** + * @brief RX62N clocks initialization. + * @note This function must be invoked only after the system reset. + * + * @special + */ +void rx62n_clock_init(void) { + + SYSTEM.SCKCR.LONG = RX62N_SCKCR_ICK | RX62N_SCKCR_PCK | RX62N_SCKCR_BCK +#if RX62N_SDCLK_OUTPUT_ENABLED == FALSE + | (1 << 22) +#endif +#if RX62N_BCLK_OUTPUT_ENABLED == FALSE + | (1 << 23) +#endif + ; +} + +/** @} */ diff --git a/os/hal/platforms/Rx62n/hal_lld.h b/os/hal/platforms/Rx62n/hal_lld.h new file mode 100644 index 000000000..db3dcc40f --- /dev/null +++ b/os/hal/platforms/Rx62n/hal_lld.h @@ -0,0 +1,361 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RX62N/hal_lld.h + * @brief HAL subsystem low level driver header template. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "iodefine_gcc62n.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +#define IWDTCLK 125000 /**< Watchdog internal clock */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief System PLL multiplier. + * @note The value is hardware fixed at 8. + */ +#if defined(__DOXYGEN__) +#define RX62N_SYSPLL_MUL 8 +#endif + +/** + * @brief System PLL divider. + * @note The value must be chosen between (1, 2, 4, 8). + */ +/* +#if defined(__DOXYGEN__) +#define RX62N_SYSPLL_DIV 1 +#endif +*/ + +/** + * @brief Enables or disables the SDCLK clock output. + */ +#if !defined(RX62N_SDCLK_OUTPUT_ENABLED) || defined(__DOXYGEN__) +#define RX62N_SDCLK_OUTPUT_ENABLED FALSE +#endif + +/** + * @brief Enables or disables the BCLK clock output. + */ +#if !defined(RX62N_BCLK_OUTPUT_ENABLED) || defined(__DOXYGEN__) +#define RX62N_BCLK_OUTPUT_ENABLED FALSE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/** + * @brief ICK mask in SCKCR register. + */ +#if (RX62N_ICLK_MUL == 1) || defined(__DOXYGEN__) +#define RX62N_SCKCR_ICK (3 << 24) +#elif RX62N_ICLK_MUL == 2 +#define RX62N_SCKCR_ICK (2 << 24) +#elif RX62N_ICLK_MUL == 4 +#define RX62N_SCKCR_ICK (1 << 24) +#elif RX62N_ICLK_MUL == 8 +#define RX62N_SCKCR_ICK (0 << 24) +#else +#error "invalid RX62N_ICLK_MUL value (1,2,4,8), check mcuconf.h" +#endif + +/** + * @brief BCK mask in SCKCR register. + */ +#if (RX62N_BCLK_MUL == 1) || defined(__DOXYGEN__) +#define RX62N_SCKCR_BCK (3 << 16) +#elif RX62N_BCLK_MUL == 2 +#define RX62N_SCKCR_BCK (2 << 16) +#elif RX62N_BCLK_MUL == 4 +#define RX62N_SCKCR_BCK (1 << 16) +#elif RX62N_BCLK_MUL == 8 +#define RX62N_SCKCR_BCK (0 << 16) +#else +#error "invalid RX62N_BCLK_MUL value (1,2,4,8), check mcuconf.h" +#endif + +/** + * @brief PCK mask in SCKCR register. + */ +#if (RX62N_PCLK_MUL == 1) || defined(__DOXYGEN__) +#define RX62N_SCKCR_PCK (3 << 8) +#elif RX62N_PCLK_MUL == 2 +#define RX62N_SCKCR_PCK (2 << 8) +#elif RX62N_PCLK_MUL == 4 +#define RX62N_SCKCR_PCK (1 << 8) +#elif RX62N_PCLK_MUL == 8 +#define RX62N_SCKCR_PCK (0 << 8) +#else +#error "invalid RX62N_PCLK_MUL value (1,2,4,8), check mcuconf.h" +#endif + +/** + * @brief System clock. + */ +#define RX62N_SYSCLK (EXTALCLK * RX62N_ICLK_MUL) +#if (RX62N_SYSCLK < 8000000) || (RX62N_SYSCLK > 100000000) +#error "System clock frequency out of the acceptable range (8..100MHz max)" +#endif + +/** + * @brief Peripheral clock. + */ +#define RX62N_PERCLK (EXTALCLK * RX62N_PCLK_MUL) +#if (RX62N_PERCLK < 8000000) || (RX62N_PERCLK > 100000000) +#error "Peripheral clock frequency out of the acceptable range (8..50MHz max)" +#endif + +#if (RX62N_PERCLK > RX62N_SYSCLK) +#error "Peripheral clock frequency higher than system clock frequency" +#endif + +#if (EXTALCLK < 8000000) || (EXTALCLK > 14000000) +#error "External crystal frequency out of the acceptable range (8..14MHz max)" +#endif + +/* + * TODO: check SYSCLK (ICLK) when ethernet controller is used (SYSCLK > 12.5MHz) + * TODO: check UCLK when USB is used + * TODO: oscilation stop detection + */ + +/* +Clock frequencies (from manual): +ICLK: 8..100MHz +PCLK: 8..50MHz +BCLK: 8..50MHz or 8..100MHz +BCLK_OUT: 8..25MHz or 8..50MHz +SDCLK: 8..50MHz +UCLK: 48MHz (only when EXTAL = 12MHz) +SUBCLK: 32768Hz +IWDTCLK: 125kHz +ICLK >= PCLK +ICLK >= BCLK +*/ + +#if defined(__DOXYGEN__) +/** + * @name Platform identification + * @{ + */ +#define PLATFORM_NAME "RX62N" +/** @} */ + +#elif defined(RX62NXADBG) || defined(RX62NXBDBG) || \ + defined(RX62NXADLE) || defined(RX62NXBDLE) || \ + defined(RX62NXADFB) || defined(RX62NXBDFB) || \ + defined(RX62NXADFP) || defined(RX62NXBDFP) || \ + defined(RX62NXADLD) || defined(RX62NXBDLD) || \ + defined(__DOXYGEN__) + +#else +#error "unspecified, unsupported or invalid RX62N platform" +#endif + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +#if defined(RX62NXADBG) || defined (RX62NXBDBG) || defined(__DOXYGEN__) +/** + * @name RX62NXXDBG capabilities (LFBGA176) + * @{ + */ + +#error "unsupported RX62N platform" + +/** @} */ +#endif /* defined(RX62NXADBG) || defined(RX62NXBDBG) */ + +#if defined(RX62NXADLE) || defined (RX62NXBDLE) || defined(__DOXYGEN__) +/** + * @name RX62NXXDLE capabilities (TFLGA145) + * @{ + */ + +#error "unsupported RX62N platform" + +/** @} */ +#endif /* defined(RX62NXADLE) || defined(RX62NXBDLE) */ + +#if defined(RX62NXADFB) || defined (RX62NXBDFB) || defined(__DOXYGEN__) +/** + * @name RX62NXXDLE capabilities (LQFP144) + * @{ + */ + +#error "unsupported RX62N platform" + +/** @} */ +#endif /* defined(RX62NXADFB) || defined(RX62NXBDFB) */ + +#if defined(RX62NXADFP) || defined (RX62NXBDFP) || defined(__DOXYGEN__) +/** + * @name RX62NXXDFP capabilities (LQFP100) + * @{ + */ +/* ADC attributes.*/ +#define RX62N_HAS_ADC1 TRUE + +/* CAN attributes.*/ +#if defined (RX62NXADFP) +#define RX62N_HAS_CAN FALSE +#else +#define RX62N_HAS_CAN TRUE +#endif + +/* DAC attributes.*/ +#define RX62N_HAS_DAC TRUE + +/* DMA attributes.*/ + +/* ETH attributes.*/ +#define RX62N_HAS_ETH TRUE + +/* EXTI attributes.*/ +//#define RX62N_EXTI_NUM_CHANNELS 18 + +/* GPIO attributes.*/ +#define RX62N_HAS_PORT0 TRUE +#define RX62N_HAS_PORT0_OD TRUE /* Open Drain */ +#define RX62N_HAS_PORT1 TRUE +#define RX62N_HAS_PORT1_OD TRUE /* Open Drain */ +#define RX62N_HAS_PORT2 TRUE +#define RX62N_HAS_PORT2_OD TRUE /* Open Drain */ +#define RX62N_HAS_PORT3 TRUE +#define RX62N_HAS_PORT3_OD TRUE /* Open Drain (P30 to P34) */ +#define RX62N_HAS_PORT4 TRUE +#define RX62N_HAS_PORT5 TRUE +#define RX62N_HAS_PORT6 FALSE +#undef PORT6 +#define RX62N_HAS_PORT7 FALSE +#undef PORT7 +#define RX62N_HAS_PORT8 FALSE +#undef PORT8 +#define RX62N_HAS_PORT9 FALSE +#undef PORT9 +#define RX62N_HAS_PORTA TRUE +#define RX62N_HAS_PORTA_PU TRUE /* pull-up */ +#define RX62N_HAS_PORTB TRUE +#define RX62N_HAS_PORTB_PU TRUE /* pull-up */ +#define RX62N_HAS_PORTC TRUE +#define RX62N_HAS_PORTC_OD TRUE /* Open Drain */ +#define RX62N_HAS_PORTC_PU TRUE /* Pull-up */ +#define RX62N_HAS_PORTD TRUE +#define RX62N_HAS_PORTD_PU TRUE /* pull-up */ +#define RX62N_HAS_PORTE TRUE +#define RX62N_HAS_PORTE_PU TRUE /* pull-up */ +#define RX62N_HAS_PORTF FALSE +#undef PORTF +#define RX62N_HAS_PORTG FALSE +#undef PORTG + +/* I2C attributes.*/ +#define RX62N_HAS_I2C1 TRUE +#define RX62N_HAS_I2C2 TRUE + +/* SDIO attributes.*/ +//#define RX62N_HAS_SDIO FALSE + +/* SPI attributes.*/ +#define RX62N_HAS_SPI1 TRUE +#define RX62N_HAS_SPI2 TRUE + +/* TIM attributes.*/ +#define RX62N_HAS_TIM1 TRUE +#define RX62N_HAS_TIM2 TRUE +#define RX62N_HAS_TIM3 TRUE +#define RX62N_HAS_TIM4 TRUE +#define RX62N_HAS_TIM5 TRUE +#define RX62N_HAS_TIM6 TRUE +#define RX62N_HAS_TIM7 TRUE +#define RX62N_HAS_TIM8 TRUE +#define RX62N_HAS_TIM9 TRUE +#define RX62N_HAS_TIM10 TRUE +#define RX62N_HAS_TIM11 TRUE +#define RX62N_HAS_TIM12 TRUE + +/* USART attributes.*/ +#define RX62N_HAS_USART1 TRUE +#define RX62N_HAS_USART2 TRUE +#define RX62N_HAS_USART3 TRUE +#define RX62N_HAS_USART4 TRUE +#define RX62N_HAS_USART6 TRUE +#define RX62N_HAS_USART7 TRUE + +/* USB attributes.*/ +/*#define RX62N_HAS_USB TRUE*/ +/*#define RX62N_HAS_OTG1 TRUE*/ + +/** @} */ +#endif /* defined(RX62NXADFP) || defined(RX62NXBDFP) */ + +#if defined(RX62NXADLD) || defined (RX62NXBDLD) || defined(__DOXYGEN__) +/** + * @name RX62NXXDLD capabilities (TFLGA85) + * @{ + */ + +#error "unsupported RX62N platform" + +/** @} */ +#endif /* defined(RX62NXADLD) || defined(RX62NXBDLD) */ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void rx62n_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/Rx62n/iodefine_gcc62n.h b/os/hal/platforms/Rx62n/iodefine_gcc62n.h new file mode 100644 index 000000000..26067fa0c --- /dev/null +++ b/os/hal/platforms/Rx62n/iodefine_gcc62n.h @@ -0,0 +1,7317 @@ +/***********************************************************************/ +/* */ +/* FILE :iodefine.h */ +/* DATE :Sun, Apr 17, 2011 */ +/* DESCRIPTION :Definition of I/O Register */ +/* CPU TYPE :RX62N */ +/* */ +/* This file is Written by Atsu from Tokushu Denshi Kairo Inc. */ +/* NOTE:THIS IS A TYPICAL EXAMPLE. */ +/* */ +/***********************************************************************/ +/************************************************************************ +* +* Device : RX/RX600/RX62N +* +* File Name : ioedfine.h +* +* Abstract : Definition of I/O Register. +* +* History : 1.00 (2010-02-18) [Hardware Manual Revision : 0.5] +* : 1.01 (2010-04-21) [Hardware Manual Revision : 0.5] +* : 2.00 (2010-08-21) [Hardware Manual Revision : 1.0] +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright (C) 2010 Renesas Electronics Corporation and +* Renesas Solutions Corp. All rights reserved. +* +************************************************************************/ +/********************************************************************************/ +/* */ +/* DESCRIPTION : Definition of ICU Register */ +/* CPU TYPE : RX62N */ +/* */ +/* Usage : IR,DTCER,IER,IPR of ICU Register */ +/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */ +/* The bit access operation is "Bit_Name(interrupt source,name)". */ +/* A part of the name can be omitted. */ +/* for example : */ +/* IR(MTU0,TGIA0) = 0; expands to : */ +/* ICU.IR[114].BIT.IR = 0; */ +/* */ +/* DTCE(ICU,IRQ0) = 1; expands to : */ +/* ICU.DTCER[64].BIT.DTCE = 1; */ +/* */ +/* IEN(CMT0,CMI0) = 1; expands to : */ +/* ICU.IER[0x03].BIT.IEN4 = 1; */ +/* */ +/* IPR(MTU1,TGIA1) = 2; expands to : */ +/* IPR(MTU1,TGI ) = 2; // TGIA1,TGIB1 share IPR level. */ +/* ICU.IPR[0x53].BIT.IPR = 2; */ +/* */ +/* IPR(SCI0,ERI0) = 3; expands to : */ +/* IPR(SCI0, ) = 3; // SCI0 uses single IPR for all sources. */ +/* ICU.IPR[0x80].BIT.IPR = 3; */ +/* */ +/* Usage : #pragma interrupt Function_Identifier(vect=**) */ +/* The number of vector is "(interrupt source, name)". */ +/* for example : */ +/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */ +/* #pragma interrupt INT_IRQ0(vect=64) */ +/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */ +/* #pragma interrupt INT_CMT0_CMI0(vect=28) */ +/* #pragma interrupt INT_MTU0_TGIA0(vect=VECT(MTU0,TGIA0)) expands to : */ +/* #pragma interrupt INT_MTU0_TGIA0(vect=114) */ +/* */ +/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */ +/* The bit access operation is "MSTP(name)". */ +/* The name that can be used is a macro name defined with "iodefine.h". */ +/* for example : */ +/* MSTP(TMR2) = 0; // TMR2,TMR3,TMR23 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; */ +/* MSTP(SCI0) = 0; // SCI0,SMCI0 expands to : */ +/* SYSTEM.MSTPCRB.BIT.MSTPB31 = 0; */ +/* MSTP(MTU4) = 0; // MTUA,MTU0,MTU1,MTU2,MTU3,MTU4,MTU5 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */ +/* MSTP(CMT3) = 0; // CMT2,CMT3 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA14 = 0; */ +/* */ +/* */ +/********************************************************************************/ +#ifndef __RX62NIODEFINE_HEADER__ +#define __RX62NIODEFINE_HEADER__ +// for gcc +struct st_ad { + unsigned short ADDRA; + unsigned short ADDRB; + unsigned short ADDRC; + unsigned short ADDRD; + char wk0[8]; + union { + unsigned char BYTE; + struct { + unsigned char CH:4; + unsigned char :1; + unsigned char ADST:1; + unsigned char ADIE:1; + unsigned char :1; + } BIT; + } ADCSR; + union { + unsigned char BYTE; + struct { + unsigned char MODE:2; + unsigned char CKS:2; + unsigned char :1; + unsigned char TRGS:3; + } BIT; + } ADCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DPSEL:1; + } BIT; + } ADDPR; + unsigned char ADSSTR; + char wk1[11]; + union { + unsigned char BYTE; + struct { + unsigned char DIAG:2; + unsigned char :6; + } BIT; + } ADDIAGR; +}; + +struct st_bsc { + union { + unsigned char BYTE; + struct { + unsigned char STSCLR:1; + unsigned char :7; + } BIT; + } BERCLR; + char wk0[3]; + union { + unsigned char BYTE; + struct { + unsigned char IGAEN:1; + unsigned char TOEN:1; + unsigned char :6; + + + } BIT; + } BEREN; + char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char IA:1; + unsigned char TO:1; + unsigned char :2; + unsigned char MST:3; + unsigned char :1; + } BIT; + } BERSR1; + char wk2[1]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short ADDR:13; + } BIT; + } BERSR2; + char wk3[7414]; + union { + unsigned short WORD; + struct { + unsigned short WRMOD:1; + unsigned short :2; + unsigned short EWENB:1; + unsigned short :4; + unsigned short PRENB:1; + unsigned short PWENB:1; + unsigned short :5; + unsigned short PRMOD:1; + } BIT; + } CS0MOD; + union { + unsigned long LONG; + struct { + unsigned long CSPWWAIT:3; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSWWAIT:5; + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + } BIT; + } CS0WCR1; + union { + unsigned long LONG; + struct { + unsigned long CSROFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :5; + unsigned long RDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + } BIT; + } CS0WCR2; + char wk4[6]; + union { + unsigned short WORD; + struct { + unsigned short WRMOD:1; + unsigned short :2; + unsigned short EWENB:1; + unsigned short :4; + unsigned short PRENB:1; + unsigned short PWENB:1; + unsigned short :5; + unsigned short PRMOD:1; + } BIT; + } CS1MOD; + union { + unsigned long LONG; + struct { + unsigned long CSPWWAIT:3; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSWWAIT:5; + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + } BIT; + } CS1WCR1; + union { + unsigned long LONG; + struct { + unsigned long CSROFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :5; + unsigned long RDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + } BIT; + } CS1WCR2; + char wk5[6]; + union { + unsigned short WORD; + struct { + unsigned short WRMOD:1; + unsigned short :2; + unsigned short EWENB:1; + unsigned short :4; + unsigned short PRENB:1; + unsigned short PWENB:1; + unsigned short :5; + unsigned short PRMOD:1; + } BIT; + } CS2MOD; + union { + unsigned long LONG; + struct { + unsigned long CSPWWAIT:3; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSWWAIT:5; + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + } BIT; + } CS2WCR1; + union { + unsigned long LONG; + struct { + unsigned long CSROFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :5; + unsigned long RDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + } BIT; + } CS2WCR2; + char wk6[6]; + union { + unsigned short WORD; + struct { + unsigned short WRMOD:1; + unsigned short :2; + unsigned short EWENB:1; + unsigned short :4; + unsigned short PRENB:1; + unsigned short PWENB:1; + unsigned short :5; + unsigned short PRMOD:1; + } BIT; + } CS3MOD; + union { + unsigned long LONG; + struct { + unsigned long CSPWWAIT:3; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSWWAIT:5; + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + } BIT; + } CS3WCR1; + union { + unsigned long LONG; + struct { + unsigned long CSROFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :5; + unsigned long RDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + } BIT; + } CS3WCR2; + char wk7[6]; + union { + unsigned short WORD; + struct { + unsigned short WRMOD:1; + unsigned short :2; + unsigned short EWENB:1; + unsigned short :4; + unsigned short PRENB:1; + unsigned short PWENB:1; + unsigned short :5; + unsigned short PRMOD:1; + } BIT; + } CS4MOD; + union { + unsigned long LONG; + struct { + unsigned long CSPWWAIT:3; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSWWAIT:5; + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + } BIT; + } CS4WCR1; + union { + unsigned long LONG; + struct { + unsigned long CSROFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :5; + unsigned long RDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + } BIT; + } CS4WCR2; + char wk8[6]; + union { + unsigned short WORD; + struct { + unsigned short WRMOD:1; + unsigned short :2; + unsigned short EWENB:1; + unsigned short :4; + unsigned short PRENB:1; + unsigned short PWENB:1; + unsigned short :5; + unsigned short PRMOD:1; + } BIT; + } CS5MOD; + union { + unsigned long LONG; + struct { + unsigned long CSPWWAIT:3; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSWWAIT:5; + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + } BIT; + } CS5WCR1; + union { + unsigned long LONG; + struct { + unsigned long CSROFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :5; + unsigned long RDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + } BIT; + } CS5WCR2; + char wk9[6]; + union { + unsigned short WORD; + struct { + unsigned short WRMOD:1; + unsigned short :2; + unsigned short EWENB:1; + unsigned short :4; + unsigned short PRENB:1; + unsigned short PWENB:1; + unsigned short :5; + unsigned short PRMOD:1; + } BIT; + } CS6MOD; + union { + unsigned long LONG; + struct { + unsigned long CSPWWAIT:3; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSWWAIT:5; + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + } BIT; + } CS6WCR1; + union { + unsigned long LONG; + struct { + unsigned long CSROFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :5; + unsigned long RDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + } BIT; + } CS6WCR2; + char wk10[6]; + union { + unsigned short WORD; + struct { + unsigned short WRMOD:1; + unsigned short :2; + unsigned short EWENB:1; + unsigned short :4; + unsigned short PRENB:1; + unsigned short PWENB:1; + unsigned short :5; + unsigned short PRMOD:1; + } BIT; + } CS7MOD; + union { + unsigned long LONG; + struct { + unsigned long CSPWWAIT:3; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSWWAIT:5; + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + } BIT; + } CS7WCR1; + union { + unsigned long LONG; + struct { + unsigned long CSROFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :5; + unsigned long RDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + } BIT; + } CS7WCR2; + char wk11[1926]; + union { + unsigned short WORD; + struct { + unsigned short EXENB:1; + unsigned short :3; + unsigned short BSIZE:2; + unsigned short :2; + unsigned short EMODE:1; + unsigned short :7; + } BIT; + } CS0CR; + char wk12[6]; + union { + unsigned short WORD; + struct { + unsigned short RRCV:4; + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + } BIT; + } CS0REC; + char wk13[6]; + union { + unsigned short WORD; + struct { + unsigned short EXENB:1; + unsigned short :3; + unsigned short BSIZE:2; + unsigned short :2; + unsigned short EMODE:1; + unsigned short :7; + } BIT; + } CS1CR; + char wk14[6]; + union { + unsigned short WORD; + struct { + unsigned short RRCV:4; + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + } BIT; + } CS1REC; + char wk15[6]; + union { + unsigned short WORD; + struct { + unsigned short EXENB:1; + unsigned short :3; + unsigned short BSIZE:2; + unsigned short :2; + unsigned short EMODE:1; + unsigned short :7; + } BIT; + } CS2CR; + char wk16[6]; + union { + unsigned short WORD; + struct { + unsigned short RRCV:4; + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + } BIT; + } CS2REC; + char wk17[6]; + union { + unsigned short WORD; + struct { + unsigned short EXENB:1; + unsigned short :3; + unsigned short BSIZE:2; + unsigned short :2; + unsigned short EMODE:1; + unsigned short :7; + } BIT; + } CS3CR; + char wk18[6]; + union { + unsigned short WORD; + struct { + unsigned short RRCV:4; + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + } BIT; + } CS3REC; + char wk19[6]; + union { + unsigned short WORD; + struct { + unsigned short EXENB:1; + unsigned short :3; + unsigned short BSIZE:2; + unsigned short :2; + unsigned short EMODE:1; + unsigned short :7; + } BIT; + } CS4CR; + char wk20[6]; + union { + unsigned short WORD; + struct { + unsigned short RRCV:4; + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + } BIT; + } CS4REC; + char wk21[6]; + union { + unsigned short WORD; + struct { + unsigned short EXENB:1; + unsigned short :3; + unsigned short BSIZE:2; + unsigned short :2; + unsigned short EMODE:1; + unsigned short :7; + } BIT; + } CS5CR; + char wk22[6]; + union { + unsigned short WORD; + struct { + unsigned short RRCV:4; + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + } BIT; + } CS5REC; + char wk23[6]; + union { + unsigned short WORD; + struct { + unsigned short EXENB:1; + unsigned short :3; + unsigned short BSIZE:2; + unsigned short :2; + unsigned short EMODE:1; + unsigned short :7; + } BIT; + } CS6CR; + char wk24[6]; + union { + unsigned short WORD; + struct { + unsigned short RRCV:4; + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + } BIT; + } CS6REC; + char wk25[6]; + union { + unsigned short WORD; + struct { + unsigned short EXENB:1; + unsigned short :3; + unsigned short BSIZE:2; + unsigned short :2; + unsigned short EMODE:1; + unsigned short :7; + } BIT; + } CS7CR; + char wk26[6]; + union { + unsigned short WORD; + struct { + unsigned short RRCV:4; + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + } BIT; + } CS7REC; + char wk27[900]; + union { + unsigned char BYTE; + struct { + unsigned char EXENB:1; + unsigned char :3; + unsigned char BSIZE:2; + unsigned char :2; + } BIT; + } SDCCR; + union { + unsigned char BYTE; + struct { + unsigned char EMODE:1; + unsigned char :7; + } BIT; + } SDCMOD; + union { + unsigned char BYTE; + struct { + unsigned char BE:1; + unsigned char :7; + } BIT; + } SDAMOD; + char wk28[13]; + union { + unsigned char BYTE; + struct { + unsigned char SFEN:1; + unsigned char :7; + } BIT; + } SDSELF; + char wk29[3]; + union { + unsigned short WORD; + struct { + unsigned short RFC:12; + unsigned short REFW:4; + } BIT; + } SDRFCR; + union { + unsigned char BYTE; + struct { + unsigned char RFEN:1; + unsigned char :7; + } BIT; + } SDRFEN; + char wk30[9]; + union { + unsigned char BYTE; + struct { + unsigned char INIRQ:1; + unsigned char :7; + } BIT; + } SDICR; + char wk31[3]; + union { + unsigned short WORD; + struct { + unsigned short ARFI:4; + unsigned short ARFC:4; + unsigned short PRC:3; + unsigned short :5; + } BIT; + } SDIR; + char wk32[26]; + union { + unsigned char BYTE; + struct { + unsigned char MXC:2; + unsigned char :6; + } BIT; + } SDADR; + char wk33[3]; + union { + unsigned long LONG; + struct { + unsigned long CL:3; + unsigned long :5; + unsigned long WR:1; + unsigned long RP:3; + unsigned long RCD:2; + unsigned long :2; + unsigned long RAS:3; + unsigned long :13; + } BIT; + } SDTR; + union { + unsigned short WORD; + struct { + unsigned short MR:15; + unsigned short :1; + } BIT; + } SDMOD; + char wk34[6]; + union { + unsigned char BYTE; + struct { + unsigned char MRSST:1; + unsigned char :2; + unsigned char INIST:1; + unsigned char SRFST:1; + unsigned char :3; + } BIT; + } SDSR; +}; + +struct st_can { + struct { + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + unsigned long EID:18; + unsigned long SID:11; + unsigned long :1; + unsigned long RTR:1; + unsigned long IDE:1; + } BIT; + } ID; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; +/* -- oops! + struct { + unsigned char DLC:4; + unsigned char :4; + unsigned char :8; + + } BIT; +*/ + } DLC; + unsigned char DATA[8]; + union { + unsigned short WORD; + struct { + unsigned char TSL; + unsigned char TSH; + } BYTE; + } TS; + } MB[32]; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + unsigned long EID:18; + unsigned long SID:11; + unsigned long :3; + } BIT; + } MKR[8]; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + unsigned long EID:18; + unsigned long SID:11; + unsigned long :1; + unsigned long RTR:1; + unsigned long IDE:1; + } BIT; + } FIDCR0; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + unsigned long EID:18; + unsigned long SID:11; + unsigned long :1; + unsigned long RTR:1; + unsigned long IDE:1; + } BIT; + } FIDCR1; + unsigned long MKIVLR; + unsigned long MIER; + char wk0[1008]; + union { + unsigned char BYTE; + union { + struct { + unsigned char SENTDATA:1; + unsigned char TRMACTIVE:1; + unsigned char TRMABT:1; + unsigned char :1; + unsigned char ONESHOT:1; + unsigned char :1; + unsigned char RECREQ:1; + unsigned char TRMREQ:1; + } TX; + struct { + unsigned char NEWDATA:1; + unsigned char INVALDATA:1; + unsigned char MSGLOST:1; + unsigned char :5; + } RX; + } BIT; + } MCTL[32]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + struct { + unsigned char MBM:1; + unsigned char IDFM:2; + unsigned char MLM:1; + unsigned char TPM:1; + unsigned char TSRC:1; + unsigned char TSPS:2; + unsigned char CANM:2; + unsigned char SLPM:1; + unsigned char BOM:2; + unsigned char RBOC:1; + unsigned char :2; + } BIT; + } CTLR; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + struct { + unsigned char NDST:1; + unsigned char SDST:1; + unsigned char RFST:1; + unsigned char TFST:1; + unsigned char NMLST:1; + unsigned char FMLST:1; + unsigned char TABST:1; + unsigned char EST:1; + unsigned char RSTST:1; + unsigned char HLTST:1; + unsigned char SLPST:1; + unsigned char EPST:1; + unsigned char BOST:1; + unsigned char TRMST:1; + unsigned char RECST:1; + unsigned char :1; + } BIT; + } STR; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + struct { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct { + unsigned long :8; + unsigned long TSEG2:3; + unsigned long :1; + unsigned long SJW:2; + unsigned long :2; + unsigned long BRP:10; + unsigned long :2; + unsigned long TSEG1:4; + } BIT; + + } BCR; + union { + unsigned char BYTE; + struct { + unsigned char RFE:1; + unsigned char RFUST:3; + unsigned char RFMLF:1; + unsigned char RFFST:1; + unsigned char RFWST:1; + unsigned char RFEST:1; + } BIT; + } RFCR; + unsigned char RFPCR; + union { + unsigned char BYTE; + struct { + unsigned char TFE:1; + unsigned char TFUST:3; + unsigned char :2; + unsigned char TFFST:1; + unsigned char TFEST:1; + } BIT; + } TFCR; + unsigned char TFPCR; + union { + unsigned char BYTE; + struct { + unsigned char BEIE:1; + unsigned char EWIE:1; + unsigned char EPIE:1; + unsigned char BOEIE:1; + unsigned char BORIE:1; + unsigned char ORIE:1; + unsigned char OLIE:1; + unsigned char BLIE:1; + } BIT; + } EIER; + union { + unsigned char BYTE; + struct { + unsigned char BEIF:1; + unsigned char EWIF:1; + unsigned char EPIF:1; + unsigned char BOEIF:1; + unsigned char BORIF:1; + unsigned char ORIF:1; + unsigned char OLIF:1; + unsigned char BLIF:1; + } BIT; + } EIFR; + unsigned char RECR; + unsigned char TECR; + union { + unsigned char BYTE; + struct { + unsigned char SEF:1; + unsigned char FEF:1; + unsigned char AEF:1; + unsigned char CEF:1; + unsigned char BE1F:1; + unsigned char BE0F:1; + unsigned char ADEF:1; + unsigned char EDPM:1; + } BIT; + } ECSR; + unsigned char CSSR; + union { + unsigned char BYTE; + struct { + unsigned char MBNST:5; + unsigned char :2; + unsigned char SEST:1; + } BIT; + } MSSR; + union { + unsigned char BYTE; + struct { + unsigned char MBSM:2; + unsigned char :6; + } BIT; + } MSMR; + unsigned short TSR; + unsigned short AFSR; + union { + unsigned char BYTE; + struct { + unsigned char TSTE:1; + unsigned char TSTM:2; + unsigned char :5; + } BIT; + } TCR; +}; + +struct st_cmt { + union { + unsigned short WORD; + struct { + unsigned short STR0:1; + unsigned short STR1:1; + unsigned short :14; + } BIT; + } CMSTR0; + char wk0[14]; + union { + unsigned short WORD; + struct { + unsigned short STR2:1; + unsigned short STR3:1; + unsigned short :14; + } BIT; + } CMSTR1; +}; + +struct st_cmt0 { + union { + unsigned short WORD; + struct { + unsigned short CKS:2; + unsigned short :4; + unsigned short CMIE:1; + unsigned short :9; + } BIT; + } CMCR; + unsigned short CMCNT; + unsigned short CMCOR; +}; + +struct st_crc { + union { + unsigned char BYTE; + struct { + unsigned char GPS:2; + unsigned char LMS:1; + unsigned char :4; + unsigned char DORCLR:1; + } BIT; + } CRCCR; + unsigned char CRCDIR; + unsigned short CRCDOR; +}; + +struct st_da { + unsigned short DADR0; + unsigned short DADR1; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char DAE:1; + unsigned char DAOE0:1; + unsigned char DAOE1:1; + } BIT; + } DACR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DPSEL:1; + } BIT; + } DADPR; +}; + +struct st_dmac { + union { + unsigned char BYTE; + struct { + unsigned char DMST:1; + unsigned char :7; + } BIT; + } DMAST; +}; + +struct st_dmac0 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short DCTG:2; + unsigned short :6; + unsigned short SZ:2; + unsigned short :2; + unsigned short DTS:2; + unsigned short MD:2; + } BIT; + } DMTMD; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char DARIE:1; + unsigned char SARIE:1; + unsigned char RPTIE:1; + unsigned char ESIE:1; + unsigned char DTIE:1; + unsigned char :3; + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + unsigned short DARA:5; + unsigned short :1; + unsigned short DM:2; + unsigned short SARA:5; + unsigned short :1; + unsigned short SM:2; + } BIT; + } DMAMD; + char wk2[2]; + unsigned long DMOFR; + union { + unsigned char BYTE; + struct { + unsigned char DTE:1; + unsigned char :7; + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + unsigned char SWREQ:1; + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ESIF:1; + unsigned char :3; + unsigned char DTIF:1; + unsigned char :2; + unsigned char ACT:1; + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + unsigned char DISEL:1; + unsigned char :7; + } BIT; + } DMCSL; +}; + +struct st_dmac1 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short DCTG:2; + unsigned short :6; + unsigned short SZ:2; + unsigned short :2; + unsigned short DTS:2; + unsigned short MD:2; + } BIT; + } DMTMD; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char DARIE:1; + unsigned char SARIE:1; + unsigned char RPTIE:1; + unsigned char ESIE:1; + unsigned char DTIE:1; + unsigned char :3; + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + unsigned short DARA:5; + unsigned short :1; + unsigned short DM:2; + unsigned short SARA:5; + unsigned short :1; + unsigned short SM:2; + } BIT; + } DMAMD; + char wk2[6]; + union { + unsigned char BYTE; + struct { + unsigned char DTE:1; + unsigned char :7; + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + unsigned char SWREQ:1; + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ESIF:1; + unsigned char :3; + unsigned char DTIF:1; + unsigned char :2; + unsigned char ACT:1; + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + unsigned char DISEL:1; + unsigned char :7; + } BIT; + } DMCSL; +}; + +struct st_dtc { + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char RRS:1; + unsigned char :3; + } BIT; + } DTCCR; + char wk0[3]; + void *DTCVBR; + union { + unsigned char BYTE; + struct { + unsigned char SHORT:1; + unsigned char DTCADMOD:7; + } BIT; + } DTCADMOD; + char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char DTCST:1; + unsigned char DTCADMOD:7; + } BIT; + } DTCST; + char wk2[1]; + union { + unsigned short WORD; +/* -- oops! + struct { + unsigned short VECN:8; + unsigned short :7; + unsigned short ACT:1; + } BIT; +*/ + } DTCSTS; +}; + +struct st_edmac { + union { + unsigned long LONG; + struct { + unsigned long SWR:1; + unsigned long :3; + unsigned long DL:2; + unsigned long DE:1; + unsigned long :25; + } BIT; + } EDMR; + char wk0[4]; + union { + unsigned long LONG; + struct { + unsigned long TR:1; + unsigned long :31; + } BIT; + } EDTRR; + char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long RR:1; + unsigned long :31; + } BIT; + } EDRRR; + char wk2[4]; + void *TDLAR; + char wk3[4]; + void *RDLAR; + char wk4[4]; + union { + unsigned long LONG; + struct { + unsigned long CERF:1; + unsigned long PRE:1; + unsigned long RTSF:1; + unsigned long RTLF:1; + unsigned long RRF:1; + unsigned long :2; + unsigned long RMAF:1; + unsigned long TRO:1; + unsigned long CD:1; + unsigned long DLC:1; + unsigned long CND:1; + unsigned long :4; + unsigned long RFOF:1; + unsigned long RDE:1; + unsigned long FR:1; + unsigned long TFUF:1; + unsigned long TDE:1; + unsigned long TC:1; + unsigned long ECI:1; + unsigned long ADE:1; + unsigned long RFCOF:1; + unsigned long RABT:1; + unsigned long TABT:1; + unsigned long :3; + unsigned long TWB:1; + unsigned long :1; + } BIT; + } EESR; + char wk5[4]; + union { + unsigned long LONG; + struct { + unsigned long CERFIP:1; + unsigned long PREIP:1; + unsigned long RTSFIP:1; + unsigned long RTLFIP:1; + unsigned long RRFIP:1; + unsigned long :2; + unsigned long RMAFIP:1; + unsigned long TROIP:1; + unsigned long CDIP:1; + unsigned long DLCIP:1; + unsigned long CNDIP:1; + unsigned long :4; + unsigned long RFOFIP:1; + unsigned long RDEIP:1; + unsigned long FRIP:1; + unsigned long TFUFIP:1; + unsigned long TDEIP:1; + unsigned long TCIP:1; + unsigned long ECIIP:1; + unsigned long ADEIP:1; + unsigned long RFCOFIP:1; + unsigned long RABTIP:1; + unsigned long TABTIP:1; + unsigned long :3; + unsigned long TWBIP:1; + unsigned long :1; + } BIT; + } EESIPR; + char wk6[4]; + union { + unsigned long LONG; + struct { + unsigned long CERFCE:1; + unsigned long PRECE:1; + unsigned long RTSFCE:1; + unsigned long RTLFCE:1; + unsigned long RRFCE:1; + unsigned long :2; + unsigned long RMAFCE:1; + unsigned long TROCE:1; + unsigned long CDCE:1; + unsigned long DLCCE:1; + unsigned long CNDCE:1; + unsigned long :20; + } BIT; + } TRSCER; + char wk7[4]; + union { + unsigned long LONG; +/* -- oops! + struct { + unsigned long MFC:16; + unsigned long :16; + } BIT; +*/ + } RMFCR; + char wk8[4]; + union { + unsigned long LONG; + struct { + unsigned long TFT:11; + unsigned long :21; + } BIT; + } TFTR; + char wk9[4]; + union { + unsigned long LONG; + struct { + unsigned long RFD:5; + unsigned long :3; + unsigned long TFD:5; + unsigned long :19; + } BIT; + } FDR; + char wk10[4]; + union { + unsigned long LONG; + struct { + unsigned long RNR:1; + unsigned long RNC:1; + unsigned long :30; + } BIT; + } RMCR; + char wk11[8]; + union { + unsigned long LONG; +/* -- oops! + struct { + unsigned long UNDER:16; + unsigned long :16; + } BIT; +*/ + } TFUCR; + union { + unsigned long LONG; +/* -- oops! + struct { + unsigned long OVER:16; + unsigned long :16; + } BIT; +*/ + } RFOCR; + union { + unsigned long LONG; + struct { + unsigned long ELB:1; + unsigned long :31; + } BIT; + } IOSR; + union { + unsigned long LONG; + struct { + unsigned long RFDO:3; + unsigned long :13; + unsigned long RFFO:3; + unsigned long :13; + } BIT; + } FCFTR; + char wk12[4]; + union { + unsigned long LONG; + struct { + unsigned long PADR:6; + unsigned long :10; + unsigned long PADS:2; + unsigned long :14; + } BIT; + } RPADIR; + union { + unsigned long LONG; + struct { + unsigned long TIS:1; + unsigned long :3; + unsigned long TIM:1; + unsigned long :27; + } BIT; + } TRIMD; + char wk13[72]; + void *RBWAR; + void *RDFAR; + char wk14[4]; + void *TBRAR; + void *TDFAR; +}; + +struct st_etherc { + union { + unsigned long LONG; + struct { + unsigned long PRM:1; + unsigned long DM:1; + unsigned long RTM:1; + unsigned long ILB:1; + unsigned long :1; + unsigned long TE:1; + unsigned long RE:1; + unsigned long :2; + unsigned long MPDE:1; + unsigned long :2; + unsigned long PRCEF:1; + unsigned long :3; + unsigned long TXF:1; + unsigned long RXF:1; + unsigned long PFR:1; + unsigned long ZPE:1; + unsigned long TPC:1; + unsigned long :11; + } BIT; + } ECMR; + char wk0[4]; + union { + unsigned long LONG; + struct { + unsigned long RFL:12; + unsigned long :20; + } BIT; + } RFLR; + char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long ICD:1; + unsigned long MPD:1; + unsigned long LCHNG:1; + unsigned long :1; + unsigned long PSRTO:1; + unsigned long BFR:1; + unsigned long :26; + } BIT; + } ECSR; + char wk2[4]; + union { + unsigned long LONG; + struct { + unsigned long ICDIP:1; + unsigned long MPDIP:1; + unsigned long LCHNGIP:1; + unsigned long :1; + unsigned long PSRTOIP:1; + unsigned long BFSIPR:1; + unsigned long :26; + } BIT; + } ECSIPR; + char wk3[4]; + union { + unsigned long LONG; + struct { + unsigned long MDC:1; + unsigned long MMD:1; + unsigned long MDO:1; + unsigned long MDI:1; + unsigned long :28; + } BIT; + } PIR; + char wk4[4]; + union { + unsigned long LONG; + struct { + unsigned long LMON:1; + unsigned long :31; + } BIT; + } PSR; + char wk5[20]; + union { + unsigned long LONG; + struct { + unsigned long RMD:20; + unsigned long :12; + } BIT; + } RDMLR; + char wk6[12]; + union { + unsigned long LONG; + struct { + unsigned long IPG:5; + unsigned long :27; + } BIT; + } IPGR; + union { + unsigned long LONG; +/* -- oops! + struct { + unsigned long AP:16; + unsigned long :16; + } BIT; +*/ + } APR; + union { + unsigned long LONG; +/* -- oops! + struct { + unsigned long MP:16; + unsigned long :16; + } BIT; +*/ + } MPR; + char wk7[4]; + union { + unsigned long LONG; +/* -- oops! + struct { + unsigned long RPAUSE:8; + unsigned long :24; + } BIT; +*/ + } RFCF; + union { + unsigned long LONG; +/* -- oops! + struct { + unsigned long TPAUSE:16; + unsigned long :16; + } BIT; +*/ + } TPAUSER; + union { + unsigned long LONG; +/* -- oops! + struct { + unsigned long TXP:8; + unsigned long :24; + } BIT; +*/ + } TPAUSECR; + union { + unsigned long LONG; +/* -- oops! + struct { + unsigned long BCF:16; + unsigned long :16; + } BIT; +*/ + } BCFRR; + char wk8[80]; + unsigned long MAHR; + char wk9[4]; + union { + unsigned long LONG; +/* -- oops! + struct { + unsigned long MA:16; + unsigned long :16; + } BIT; +*/ + } MALR; + char wk10[4]; + unsigned long TROCR; + unsigned long CDCR; + unsigned long LCCR; + unsigned long CNDCR; + char wk11[4]; + unsigned long CEFCR; + unsigned long FRECR; + unsigned long TSFRCR; + unsigned long TLFRCR; + unsigned long RFCR; + unsigned long MAFCR; +}; + +struct st_exdmac { + union { + unsigned char BYTE; + struct { + unsigned char DMST:1; + unsigned char :7; + } BIT; + } EDMAST; + char wk0[479]; + unsigned long CLSBR0; + unsigned long CLSBR1; + unsigned long CLSBR2; + unsigned long CLSBR3; + unsigned long CLSBR4; + unsigned long CLSBR5; + unsigned long CLSBR6; + unsigned long CLSBR7; +}; + +struct st_exdmac0 { + void *EDMSAR; + void *EDMDAR; + unsigned long EDMCRA; + unsigned short EDMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short DCTG:2; + unsigned short :6; + unsigned short SZ:2; + unsigned short :2; + unsigned short DTS:2; + unsigned short MD:2; + } BIT; + } EDMTMD; + union { + unsigned char BYTE; + struct { + unsigned char DACKSEL:1; // ”²‚¯ + unsigned char DACKW:1; + unsigned char DACKE:1; + unsigned char DACKS:1; + unsigned char :4; + } BIT; + } EDMOMD; + union { + unsigned char BYTE; + struct { + unsigned char DARIE:1; + unsigned char SARIE:1; + unsigned char RPTIE:1; + unsigned char ESIE:1; + unsigned char DTIE:1; + unsigned char :3; + } BIT; + } EDMINT; + union { + unsigned long LONG; + struct { + unsigned long DARA:5; + unsigned long :1; + unsigned long DM:2; + unsigned long SARA:5; + unsigned long :1; + unsigned long SM:2; + unsigned long DIR:1; + unsigned long AMS:1; + unsigned long :14; + } BIT; + } EDMAMD; + unsigned long EDMOFR; + union { + unsigned char BYTE; + struct { + unsigned char DTE:1; + unsigned char :7; + } BIT; + } EDMCNT; + union { + unsigned char BYTE; + struct { + unsigned char SWREQ:1; + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + } BIT; + } EDMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ESIF:1; + unsigned char :3; + unsigned char DTIF:1; + unsigned char :2; + unsigned char ACT:1; + } BIT; + } EDMSTS; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char DREQS:2; + unsigned char :6; + } BIT; + } EDMRMD; + union { + unsigned char BYTE; + struct { + unsigned char EREQ:1; + unsigned char :7; + } BIT; + } EDMERF; + union { + unsigned char BYTE; + struct { + unsigned char PREQ:1; + unsigned char :7; + } BIT; + } EDMPRF; +}; + +struct st_exdmac1 { + void *EDMSAR; + void *EDMDAR; + unsigned long EDMCRA; + unsigned short EDMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short DCTG:2; + unsigned short :6; + unsigned short SZ:2; + unsigned short :2; + unsigned short DTS:2; + unsigned short MD:2; + } BIT; + } EDMTMD; + union { + unsigned char BYTE; + struct { + unsigned char DACKSEL:1; // ”²‚¯ + unsigned char DACKW:1; + unsigned char DACKE:1; + unsigned char DACKS:1; + unsigned char :4; + } BIT; + } EDMOMD; + union { + unsigned char BYTE; + struct { + unsigned char DARIE:1; + unsigned char SARIE:1; + unsigned char RPTIE:1; + unsigned char ESIE:1; + unsigned char DTIE:1; + unsigned char :3; + } BIT; + } EDMINT; + union { + unsigned long LONG; + struct { + unsigned long DARA:5; + unsigned long :1; + unsigned long DM:2; + unsigned long SARA:5; + unsigned long :1; + unsigned long SM:2; + unsigned long DIR:1; + unsigned long AMS:1; + unsigned long :14; + } BIT; + } EDMAMD; + char wk1[4]; + union { + unsigned char BYTE; + struct { + unsigned char DTE:1; + unsigned char :7; + } BIT; + } EDMCNT; + union { + unsigned char BYTE; + struct { + unsigned char SWREQ:1; + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + } BIT; + } EDMREQ; + union { + unsigned char BYTE; + struct { + + unsigned char ESIF:1; + unsigned char :3; + unsigned char DTIF:1; + unsigned char :2; + unsigned char ACT:1; + } BIT; + } EDMSTS; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char DREQS:2; + unsigned char :6; + } BIT; + } EDMRMD; + union { + unsigned char BYTE; + struct { + unsigned char EREQ:1; + unsigned char :7; + } BIT; + } EDMERF; + union { + unsigned char BYTE; + struct { + unsigned char PREQ:1; + unsigned char :7; + } BIT; + } EDMPRF; +}; + +struct st_flash { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char FLWE:2; + unsigned char :6; + } BIT; + } FWEPROR; + char wk1[7799160]; + union { + unsigned char BYTE; + struct { + unsigned char FRDMD:1; + unsigned char :3; + } BIT; + } FMODR; + char wk2[13]; + union { + unsigned char BYTE; + struct { + unsigned char DFLWPE:1; + unsigned char DFLRPE:1; + unsigned char :1; + unsigned char DFLAE:1; + unsigned char CMDLK:1; + unsigned char :2; + unsigned char ROMAE:1; + } BIT; + } FASTAT; + union { + unsigned char BYTE; + struct { + unsigned char DFLWPEIE:1; + unsigned char DFLRPEIE:1; + unsigned char :1; + unsigned char DFLAEIE:1; + unsigned char CMDLKIE:1; + unsigned char :2; + unsigned char ROMAEIE:1; + } BIT; + } FAEINT; + union { + unsigned char BYTE; + struct { + unsigned char FRDYIE:1; + unsigned char :7; + } BIT; + } FRDYIE; + char wk3[45]; + union { + unsigned short WORD; +/* -- oops! + struct { + unsigned short DBRE00:1; + unsigned short DBRE01:1; + unsigned short DBRE02:1; + unsigned short DBRE03:1; + unsigned short DBRE04:1; + unsigned short DBRE05:1; + unsigned short DBRE06:1; + unsigned short DBRE07:1; + unsigned short KEY:8; + } BIT; +*/ + } DFLRE0; + union { + unsigned short WORD; +/* -- oops! + struct { + unsigned short DBRE08:1; + unsigned short DBRE09:1; + unsigned short DBRE10:1; + unsigned short DBRE11:1; + unsigned short DBRE12:1; + unsigned short DBRE13:1; + unsigned short DBRE14:1; + unsigned short DBRE15:1; + unsigned short KEY:8; + } BIT; +*/ + } DFLRE1; + char wk4[12]; + union { + unsigned short WORD; +/* -- oops! + struct { + unsigned short DBWE00:1; + unsigned short DBWE01:1; + unsigned short DBWE02:1; + unsigned short DBWE03:1; + unsigned short DBWE04:1; + unsigned short DBWE05:1; + unsigned short DBWE06:1; + unsigned short DBWE07:1; + unsigned short KEY:8; + } BIT; +*/ + } DFLWE0; + union { + unsigned short WORD; +/* -- oops! + struct { + unsigned short DBWE08:1; + unsigned short DBWE09:1; + unsigned short DBWE10:1; + unsigned short DBWE11:1; + unsigned short DBWE12:1; + unsigned short DBWE13:1; + unsigned short DBWE14:1; + unsigned short DBWE15:1; + unsigned short KEY:8; + } BIT; +*/ + } DFLWE1; + union { + unsigned short WORD; +/* -- oops! + struct { + unsigned short FCRME:1; + unsigned short :7; + unsigned short KEY:8; + + } BIT; +*/ + } FCURAME; + char wk5[15194]; + union { + unsigned char BYTE; + struct { + unsigned char PRGSPD:1; + unsigned char ERSSPD:1; + unsigned char :1; + unsigned char SUSRDY:1; + unsigned char PRGERR:1; + unsigned char ERSERR:1; + unsigned char ILGLERR:1; + unsigned char FRDY:1; + } BIT; + } FSTATR0; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char FLOCKST:1; + unsigned char :2; + unsigned char FCUERR:1; + } BIT; + } FSTATR1; + union { + unsigned short WORD; +/* -- oops! + struct { + unsigned short FENTRY0:1; + unsigned short :6; + unsigned short FENTRYD:1; + unsigned short FEKEY:8; + } BIT; +*/ + } FENTRYR; + union { + unsigned short WORD; +/* -- oops! + struct { + unsigned short FPROTCN:1; + unsigned short :7; + unsigned short FPKEY:8; + } BIT; +*/ + } FPROTR; + union { + unsigned short WORD; +/* -- oops! + struct { + unsigned short FRESET:1; + unsigned short :7; + unsigned short FPKEY:8; + } BIT; +*/ + } FRESETR; + char wk6[2]; + union { + unsigned short WORD; +/* -- oops! + struct { + unsigned short PCMDR:8; + unsigned short CMDR:8; + } BIT; +*/ + } FCMDR; + char wk7[12]; + union { + unsigned short WORD; + struct { + unsigned short ESUSPMD:1; + unsigned short :15; + } BIT; + } FCPSR; + union { + unsigned short WORD; +/* -- oops! + struct { + unsigned short BCSIZE:1; + unsigned short :2; + unsigned short BCADR:8; + unsigned short :5; + } BIT; +*/ + } DFLBCCNT; + union { + unsigned short WORD; +/* -- oops! + struct { + unsigned short PEERRST:8; + unsigned short :8; + } BIT; +*/ + } FPESTAT; + union { + unsigned short WORD; + struct { + unsigned short BCST:1; + unsigned short :15; + } BIT; + } DFLBCSTAT; + char wk8[24]; + union { + unsigned short WORD; +/* -- oops! + struct { + unsigned short PCKA:8; + unsigned short :8; + } BIT; +*/ + } PCKAR; +}; + +struct st_icu { + union { + unsigned char BYTE; + struct { + unsigned char IR:1; + unsigned char :7; + } BIT; + } IR[255]; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char DTCE:1; + unsigned char :7; + } BIT; + } DTCER[255]; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char IEN0:1; + unsigned char IEN1:1; + unsigned char IEN2:1; + unsigned char IEN3:1; + unsigned char IEN4:1; + unsigned char IEN5:1; + unsigned char IEN6:1; + unsigned char IEN7:1; + } BIT; + } IER[32]; + char wk2[192]; + union { + unsigned char BYTE; + struct { + unsigned char SWINT:1; + unsigned char :7; + } BIT; + } SWINTR; + char wk3[15]; + union { + unsigned short WORD; +/* -- oops! + struct { + unsigned short FVCT:8; + unsigned short :7; + unsigned short FIEN:1; + } BIT; +*/ + } FIR; + char wk4[14]; + union { + unsigned char BYTE; + struct { + unsigned char IPR:4; + unsigned char :4; + } BIT; + } IPR[144]; + char wk5[112]; + unsigned char DMRSR0; + char wk6[3]; + unsigned char DMRSR1; + char wk7[3]; + unsigned char DMRSR2; + char wk8[3]; + unsigned char DMRSR3; + char wk9[243]; + union { + unsigned char BYTE; + struct { + unsigned char IRQMD:2; + unsigned char :4; + } BIT; + } IRQCR[16]; + char wk10[112]; + union { + unsigned char BYTE; + struct { + unsigned char NMIST:1; + unsigned char LVDST:1; + unsigned char OSTST:1; + unsigned char :5; + } BIT; + } NMISR; + union { + unsigned char BYTE; + struct { + unsigned char NMIEN:1; + unsigned char LVDEN:1; + unsigned char OSTEN:1; + unsigned char :5; + } BIT; + } NMIER; + union { + unsigned char BYTE; + struct { + unsigned char NMICLR:1; + unsigned char :1; + unsigned char OSTCLR:1; + unsigned char :5; + } BIT; + } NMICLR; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char NMIMD:1; + unsigned char :4; + } BIT; + } NMICR; +}; + +struct st_ioport { + union { + unsigned char BYTE; + struct { + unsigned char CS0E:1; + unsigned char CS1E:1; + unsigned char CS2E:1; + unsigned char CS3E:1; + unsigned char CS4E:1; + unsigned char CS5E:1; + unsigned char CS6E:1; + unsigned char CS7E:1; + } BIT; + } PF0CSE; + union { + unsigned char BYTE; + struct { + unsigned char CS4S:2; + unsigned char CS5S:2; + unsigned char CS6S:2; + unsigned char CS7S:2; + } BIT; + } PF1CSS; + union { + unsigned char BYTE; + struct { + unsigned char CS0S:1; + unsigned char :1; + unsigned char CS1S:2; + unsigned char CS2S:2; + unsigned char CS3S:2; + } BIT; + } PF2CSS; + union { + unsigned char BYTE; + struct { + unsigned char A16E:1; + unsigned char A17E:1; + unsigned char A18E:1; + unsigned char A19E:1; + unsigned char A20E:1; + unsigned char A21E:1; + unsigned char A22E:1; + unsigned char A23E:1; + } BIT; + } PF3BUS; + union { + unsigned char BYTE; + struct { + unsigned char ADRLE:2; + unsigned char A10E:1; + unsigned char A11E:1; + unsigned char A12E:1; + unsigned char A13E:1; + unsigned char A14E:1; + unsigned char A15E:1; + } BIT; + } PF4BUS; + union { + unsigned char BYTE; + struct { + unsigned char ADRHMS:1; + unsigned char :2; + unsigned char DHE:1; + unsigned char DH32E:1; + unsigned char WR1BC1E:1; + unsigned char WR32BC32E:1; + } BIT; + } PF5BUS; + union { + unsigned char BYTE; + struct { + unsigned char WAITS:2; + unsigned char :2; + unsigned char MDSDE:1; + unsigned char :1; + unsigned char DQM1E:1; + unsigned char SDCLKE:1; + } BIT; + } PF6BUS; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char EDMA0S:2; + unsigned char EDMA1S:2; + } BIT; + } PF7DMA; + union { + unsigned char BYTE; + struct { + unsigned char ITS8:1; + unsigned char ITS9:1; + unsigned char ITS10:1; + unsigned char ITS11:1; + unsigned char :1; + unsigned char ITS13:1; + unsigned char :1; + unsigned char ITS15:1; + } BIT; + } PF8IRQ; + union { + unsigned char BYTE; + struct { + unsigned char ITS0:1; + unsigned char ITS1:1; + unsigned char ITS2:1; + unsigned char ITS3:1; + unsigned char ITS4:1; + unsigned char ITS5:1; + unsigned char ITS6:1; + unsigned char ITS7:1; + } BIT; + } PF9IRQ; + union { + unsigned char BYTE; + struct { + unsigned char ADTRG0S:1; + unsigned char :7; + } BIT; + } PFAADC; + union { + unsigned char BYTE; + struct { + unsigned char TMR0S:1; + unsigned char TMR1S:1; + unsigned char TMR2S:1; + unsigned char TMR3S:1; + unsigned char :4; + } BIT; + } PFBTMR; + union { + unsigned char BYTE; + struct { + unsigned char MTUS0:1; + unsigned char MTUS1:1; + unsigned char MTUS2:1; + unsigned char MTUS3:1; + unsigned char MTUS4:1; + unsigned char MTUS5:1; + unsigned char MTUS6:1; + unsigned char TCLKS:1; + } BIT; + } PFCMTU; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TCLKS:1; + unsigned char MTUS6:1; + } BIT; + } PFDMTU; + union { + unsigned char BYTE; + struct { + unsigned char ENETE0:1; + unsigned char ENETE1:1; + unsigned char ENETE2:1; + unsigned char ENETE3:1; + unsigned char PHYMODE:1; + unsigned char :2; + unsigned char EE:1; + } BIT; + } PFENET; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SCI1S:1; + unsigned char SCI2S:1; + unsigned char SCI3S:1; + unsigned char :2; + unsigned char SCI6S:1; + unsigned char :1; + } BIT; + } PFFSCI; + union { + unsigned char BYTE; + struct { + unsigned char RSPIS:1; + unsigned char RSPCKE:1; + unsigned char MOSIE:1; + unsigned char MISOE:1; + unsigned char SSL0E:1; + unsigned char SSL1E:1; + unsigned char SSL2E:1; + unsigned char SSL3E:1; + } BIT; + } PFGSPI; + union { + unsigned char BYTE; + struct { + unsigned char RSPIS:1; + unsigned char RSPCKE:1; + unsigned char MOSIE:1; + unsigned char MISOE:1; + unsigned char SSL0E:1; + unsigned char SSL1E:1; + unsigned char SSL2E:1; + unsigned char SSL3E:1; + } BIT; + } PFHSPI; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char CAN0E:1; + unsigned char :7; + } BIT; + } PFJCAN; + union { + unsigned char BYTE; + struct { + unsigned char USBMD:2; + unsigned char PUPHZS:1; + unsigned char PDHZS:1; + unsigned char USBE:1; + unsigned char :3; + } BIT; + } PFKUSB; + union { + unsigned char BYTE; + struct { + unsigned char USBMD:2; + unsigned char PUPHZS:1; + unsigned char PDHZS:1; + unsigned char USBE:1; + unsigned char :3; + } BIT; + } PFLUSB; + union { + unsigned char BYTE; + struct { + unsigned char POE0E:1; + unsigned char POE1E:1; + unsigned char POE2E:1; + unsigned char POE3E:1; + unsigned char POE4E:1; + unsigned char POE5E:1; + unsigned char POE6E:1; + unsigned char POE7E:1; + } BIT; + } PFMPOE; + union { + unsigned char BYTE; + struct { + unsigned char POE8E:1; + unsigned char POE9E:1; + unsigned char :6; + } BIT; + } PFNPOE; +}; + +struct st_iwdt { + unsigned char IWDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + unsigned short TOPS:2; + unsigned short :2; + unsigned short CKS:4; + unsigned short :8; + } BIT; + } IWDTCR; + union { + unsigned short WORD; + struct { + unsigned short CNTVAL:14; + unsigned short UNDFF:1; + unsigned short :1; + } BIT; + } IWDTSR; +}; + +struct st_mtu0 { + union { + unsigned char BYTE; + struct { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char MD:4; + unsigned char BFA:1; + unsigned char BFB:1; + unsigned char BFE:1; + unsigned char :1; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOC:4; + unsigned char IOD:4; + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char TGIEC:1; + unsigned char TGIED:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TTGE:1; + } BIT; + } TIER; + unsigned char TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; + char wk0[16]; + unsigned short TGRE; + unsigned short TGRF; + union { + unsigned char BYTE; + struct { + unsigned char TGIEE:1; + unsigned char TGIEF:1; + unsigned char :6; + } BIT; + } TIER2; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTSA:1; + unsigned char TTSB:1; + unsigned char TTSE:1; + unsigned char :5; + } BIT; + } TBTM; +}; + +struct st_mtu1 { + union { + unsigned char BYTE; + struct { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:2; + unsigned char :1; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char MD:4; + unsigned char :4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIOR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TCIEU:1; + unsigned char :1; + unsigned char TTGE:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TCFD:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + char wk1[4]; + union { + unsigned char BYTE; + struct { + unsigned char I1AE:1; + unsigned char I1BE:1; + unsigned char I2AE:1; + unsigned char I2BE:1; + unsigned char :4; + } BIT; + } TICCR; +}; + +struct st_mtu2 { + union { + unsigned char BYTE; + struct { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:2; + unsigned char :1; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char MD:4; + unsigned char :4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIOR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TCIEU:1; + unsigned char :1; + unsigned char TTGE:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TCFD:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_mtu3 { + union { + unsigned char BYTE; + struct { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char MD:4; + unsigned char BFA:1; + unsigned char BFB:1; + unsigned char :2; + } BIT; + } TMDR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOC:4; + unsigned char IOD:4; + } BIT; + } TIORL; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char TGIEC:1; + unsigned char TGIED:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TTGE:1; + } BIT; + } TIER; + char wk3[7]; + unsigned short TCNT; + char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk6[4]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TCFD:1; + } BIT; + } TSR; + char wk7[11]; + union { + unsigned char BYTE; + struct { + unsigned char TTSA:1; + unsigned char TTSB:1; + unsigned char :6; + } BIT; + } TBTM; +}; + +struct st_mtu4 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char MD:4; + unsigned char BFA:1; + unsigned char BFB:1; + unsigned char :2; + } BIT; + } TMDR; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOC:4; + unsigned char IOD:4; + } BIT; + } TIORL; + char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char TGIEC:1; + unsigned char TGIED:1; + unsigned char TCIEV:1; + unsigned char :1; + unsigned char TTGE2:1; + unsigned char TTGE:1; + } BIT; + } TIER; + char wk4[8]; + unsigned short TCNT; + char wk5[8]; + unsigned short TGRA; + unsigned short TGRB; + char wk6[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk7[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TCFD:1; + } BIT; + } TSR; + char wk8[11]; + union { + unsigned char BYTE; + struct { + unsigned char TTSA:1; + unsigned char TTSB:1; + unsigned char :6; + } BIT; + } TBTM; + char wk9[6]; + union { + unsigned short WORD; + struct { + unsigned short ITB4VE:1; + unsigned short ITB3AE:1; + unsigned short ITA4VE:1; + unsigned short ITA3AE:1; + unsigned short DT4BE:1; + unsigned short UT4BE:1; + unsigned short DT4AE:1; + unsigned short UT4AE:1; + unsigned short :6; + unsigned short BF:2; + } BIT; + } TADCR; + char wk10[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; +}; + +struct st_mtu5 { + unsigned short TCNTU; + unsigned short TGRU; + union { + unsigned char BYTE; + struct { + unsigned char TPSC:2; + unsigned char :6; + } BIT; + } TCRU; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char IOC:5; + unsigned char :3; + } BIT; + } TIORU; + char wk1[9]; + unsigned short TCNTV; + unsigned short TGRV; + union { + unsigned char BYTE; + struct { + unsigned char TPSC:2; + unsigned char :6; + } BIT; + } TCRV; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char IOC:5; + unsigned char :3; + } BIT; + } TIORV; + char wk3[9]; + unsigned short TCNTW; + unsigned short TGRW; + union { + unsigned char BYTE; + struct { + unsigned char TPSC:2; + unsigned char :6; + } BIT; + } TCRW; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char IOC:5; + unsigned char :3; + } BIT; + } TIORW; + char wk5[11]; + union { + unsigned char BYTE; + struct { + unsigned char TGIE5W:1; + unsigned char TGIE5V:1; + unsigned char TGIE5U:1; + unsigned char :5; + } BIT; + } TIER; + char wk6[1]; + union { + unsigned char BYTE; + struct { + unsigned char CSTW5:1; + unsigned char CSTV5:1; + unsigned char CSTU5:1; + unsigned char :5; + } BIT; + } TSTR; + char wk7[1]; + union { + unsigned char BYTE; + struct { + unsigned char CMPCLR5W:1; + unsigned char CMPCLR5V:1; + unsigned char CMPCLR5U:1; + unsigned char :5; + } BIT; + } TCNTCMPCLR; +}; + +struct st_mtua { + union { + unsigned char BYTE; + struct { + unsigned char OE3B:1; + unsigned char OE4A:1; + unsigned char OE4B:1; + unsigned char OE3D:1; + unsigned char OE4C:1; + unsigned char OE4D:1; + unsigned char :2; + } BIT; + } TOER; + char wk0[2]; + union { + unsigned char BYTE; + struct { + unsigned char UF:1; + unsigned char VF:1; + unsigned char WF:1; + unsigned char FB:1; + unsigned char P:1; + unsigned char N:1; + unsigned char BDC:1; + unsigned char :1; + } BIT; + } TGCR; + union { + unsigned char BYTE; + struct { + unsigned char OLSP:1; + unsigned char OLSN:1; + unsigned char TOCS:1; + unsigned char TOCL:1; + unsigned char :2; + unsigned char PSYE:1; + unsigned char :1; + } BIT; + } TOCR1; + union { + unsigned char BYTE; + struct { + unsigned char OLS1P:1; + unsigned char OLS1N:1; + unsigned char OLS2P:1; + unsigned char OLS2N:1; + unsigned char OLS3N:1; + unsigned char OLS3P:1; + unsigned char BF:2; + } BIT; + } TOCR2; + char wk1[4]; + unsigned short TCDR; + unsigned short TDDR; + char wk2[8]; + unsigned short TCNTS; + unsigned short TCBR; + char wk3[12]; + union { + unsigned char BYTE; + struct { + unsigned char T4VCOR:3; + unsigned char T4VEN:1; + unsigned char T3ACOR:3; + unsigned char T3AEN:1; + } BIT; + } TITCR; + union { + unsigned char BYTE; + struct { + unsigned char T4VCNT:3; + unsigned char :1; + unsigned char T3ACNT:3; + unsigned char :1; + } BIT; + } TITCNT; + union { + unsigned char BYTE; + struct { + unsigned char BTE:2; + unsigned char :6; + } BIT; + } TBTER; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char TDER:1; + unsigned char :7; + } BIT; + } TDER; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char OLS1P:1; + unsigned char OLS1N:1; + unsigned char OLS2P:1; + unsigned char OLS2N:1; + unsigned char OLS3P:1; + unsigned char OLS3N:1; + unsigned char :2; + } BIT; + } TOLBR; + char wk6[41]; + union { + unsigned char BYTE; + struct { + unsigned char WRE:1; + unsigned char :6; + unsigned char CCE:1; + } BIT; + } TWCR; + char wk7[31]; + union { + unsigned char BYTE; + struct { + unsigned char CST0:1; + unsigned char CST1:1; + unsigned char CST2:1; + unsigned char :3; + unsigned char CST3:1; + unsigned char CST4:1; + } BIT; + } TSTR; + union { + unsigned char BYTE; + struct { + unsigned char SYNC0:1; + unsigned char SYNC1:1; + unsigned char SYNC2:1; + unsigned char :3; + unsigned char SYNC3:1; + unsigned char SYNC4:1; + } BIT; + } TSYR; + char wk8[2]; + union { + unsigned char BYTE; + struct { + unsigned char RWE:1; + unsigned char :7; + } BIT; + } TRWER; +}; + +struct st_poe { + union { + unsigned short WORD; + struct { + unsigned short POE0M:2; + unsigned short POE1M:2; + unsigned short POE2M:2; + unsigned short POE3M:2; + unsigned short PIE1:1; + unsigned short :3; + unsigned short POE0F:1; + unsigned short POE1F:1; + unsigned short POE2F:1; + unsigned short POE3F:1; + } BIT; + } ICSR1; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short OIE1:1; + unsigned short OCE1:1; + unsigned short :5; + unsigned short :5; + unsigned short OSF1:1; + } BIT; + } OCSR1; + union { + unsigned short WORD; + struct { + unsigned short POE4M:2; + unsigned short POE5M:2; + unsigned short POE6M:2; + unsigned short POE7M:2; + unsigned short PIE2:1; + unsigned short :3; + unsigned short POE4F:1; + unsigned short POE5F:1; + unsigned short POE6F:1; + unsigned short POE7F:1; + } BIT; + } ICSR2; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short OIE2:1; + unsigned short OCE2:1; + unsigned short :5; + unsigned short OSF2:1; + } BIT; + } OCSR2; + union { + unsigned short WORD; + struct { + unsigned short POE8M:2; + unsigned short :6; + unsigned short PIE3:1; + unsigned short POE8E:1; + unsigned short :2; + unsigned short POE8F:1; + unsigned short :3; + } BIT; + } ICSR3; + union { + unsigned char BYTE; + struct { + unsigned char CH34HIZ:1; + unsigned char CH0HIZ:1; + unsigned char CH910HIZ:1; + unsigned char CH6HIZ:1; + unsigned char :4; + } BIT; + } SPOER; + union { + unsigned char BYTE; + struct { + unsigned char PE0ZE:1; + unsigned char PE1ZE:1; + unsigned char PE2ZE:1; + unsigned char PE3ZE:1; + unsigned char PE4ZE:1; + unsigned char PE5ZE:1; + unsigned char PE6ZE:1; + unsigned char PE7ZE:1; + } BIT; + } POECR1; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short P6CZE:1; + unsigned short P5CZE:1; + unsigned short P4CZE:1; + unsigned short :1; + unsigned short P3CZEB:1; + unsigned short P2CZEB:1; + unsigned short P1CZEB:1; + unsigned short :1; + unsigned short P3CZEA:1; + unsigned short P2CZEA:1; + unsigned short P1CZEA:1; + unsigned short :1; + + } BIT; + } POECR2; + union { + unsigned short WORD; + struct { + unsigned short POE9M:2; + unsigned short :6; + unsigned short PIE4:1; + unsigned short POE9E:1; + unsigned short :2; + unsigned short POE9F:1; + unsigned short :3; + } BIT; + } ICSR4; +}; + +struct st_port0 { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B7:1; + } BIT; + } DDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B7:1; + } BIT; + } DR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B7:1; + } BIT; + } PORT; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B7:1; + } BIT; + } ICR; + char wk3[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } ODR; +}; + +struct st_port1 { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PORT; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ICR; + char wk3[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ODR; +}; + +struct st_port2 { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PORT; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ICR; + char wk3[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ODR; +}; + +struct st_port3 { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char :3; + } BIT; + } DDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char :3; + } BIT; + } DR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char :2; + } BIT; + } PORT; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char :3; + } BIT; + } ICR; + char wk3[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char :3; + } BIT; + } ODR; +}; + +struct st_port4 { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PORT; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ICR; +}; + +struct st_port5 { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PORT; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ICR; +}; + +struct st_port6 { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PORT; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ICR; +}; + +struct st_port7 { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PORT; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ICR; +}; + +struct st_port8 { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char :2; + } BIT; + } DDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char :2; + } BIT; + } DR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char :2; + } BIT; + } PORT; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char :2; + } BIT; + } ICR; +}; + +struct st_port9 { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PORT; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ICR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PCR; +}; + +struct st_porta { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PORT; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ICR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PCR; +}; + +struct st_portb { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PORT; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ICR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PCR; +}; + +struct st_portc { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PORT; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ICR; + char wk3[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ODR; + char wk4[63]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PCR; +}; + +struct st_portd { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PORT; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ICR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PCR; +}; + +struct st_porte { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PORT; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ICR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PCR; +}; + +struct st_portf { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char :3; + } BIT; + } DDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char :3; + } BIT; + } DR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char :3; + } BIT; + } PORT; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char :3; + } BIT; + } ICR; +}; + +struct st_portg { + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } DR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PORT; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } ICR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PCR; +}; + +struct st_ppg0 { + union { + unsigned char BYTE; + struct { + unsigned char G0CMS:2; + unsigned char G1CMS:2; + unsigned char G2CMS:2; + unsigned char G3CMS:2; + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + unsigned char G0NOV:1; + unsigned char G1NOV:1; + unsigned char G2NOV:1; + unsigned char G3NOV:1; + unsigned char G0INV:1; + unsigned char G1INV:1; + unsigned char G2INV:1; + unsigned char G3INV:1; + } BIT; + } PMR; + union { + unsigned char BYTE; + struct { + unsigned char NDER8:1; + unsigned char NDER9:1; + unsigned char NDER10:1; + unsigned char NDER11:1; + unsigned char NDER12:1; + unsigned char NDER13:1; + unsigned char NDER14:1; + unsigned char NDER15:1; + } BIT; + } NDERH; + union { + unsigned char BYTE; + struct { + unsigned char NDER0:1; + unsigned char NDER1:1; + unsigned char NDER2:1; + unsigned char NDER3:1; + unsigned char NDER4:1; + unsigned char NDER5:1; + unsigned char NDER6:1; + unsigned char NDER7:1; + } BIT; + } NDERL; + union { + unsigned char BYTE; + struct { + unsigned char POD8:1; + unsigned char POD9:1; + unsigned char POD10:1; + unsigned char POD11:1; + unsigned char POD12:1; + unsigned char POD13:1; + unsigned char POD14:1; + unsigned char POD15:1; + } BIT; + } PODRH; + union { + unsigned char BYTE; + struct { + unsigned char POD0:1; + unsigned char POD1:1; + unsigned char POD2:1; + unsigned char POD3:1; + unsigned char POD4:1; + unsigned char POD5:1; + unsigned char POD6:1; + unsigned char POD7:1; + } BIT; + } PODRL; + union { + unsigned char BYTE; + struct { + unsigned char NDR8:1; + unsigned char NDR9:1; + unsigned char NDR10:1; + unsigned char NDR11:1; + unsigned char NDR12:1; + unsigned char NDR13:1; + unsigned char NDR14:1; + unsigned char NDR15:1; + } BIT; + } NDRH; + union { + unsigned char BYTE; + struct { + unsigned char NDR0:1; + unsigned char NDR1:1; + unsigned char NDR2:1; + unsigned char NDR3:1; + unsigned char NDR4:1; + unsigned char NDR5:1; + unsigned char NDR6:1; + unsigned char NDR7:1; + } BIT; + } NDRL; + union { + unsigned char BYTE; + struct { + unsigned char NDR8:1; + unsigned char NDR9:1; + unsigned char NDR10:1; + unsigned char NDR11:1; + unsigned char :4; + } BIT; + } NDRH2; + union { + unsigned char BYTE; + struct { + unsigned char NDR0:1; + unsigned char NDR1:1; + unsigned char NDR2:1; + unsigned char NDR3:1; + unsigned char :4; + } BIT; + } NDRL2; +}; + +struct st_ppg1 { + union { + unsigned char BYTE; + struct { + unsigned char PTRSL:1; + unsigned char :7; + } BIT; + } PTRSLR; + char wk0[5]; + union { + unsigned char BYTE; + struct { + unsigned char G0CMS:2; + unsigned char G1CMS:2; + unsigned char G2CMS:2; + unsigned char G3CMS:2; + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + unsigned char G0NOV:1; + unsigned char G1NOV:1; + unsigned char G2NOV:1; + unsigned char G3NOV:1; + unsigned char G0INV:1; + unsigned char G1INV:1; + unsigned char G2INV:1; + unsigned char G3INV:1; + } BIT; + } PMR; + union { + unsigned char BYTE; + struct { + unsigned char NDER24:1; + unsigned char NDER25:1; + unsigned char NDER26:1; + unsigned char NDER27:1; + unsigned char NDER28:1; + unsigned char NDER29:1; + unsigned char NDER30:1; + unsigned char NDER31:1; + } BIT; + } NDERH; + union { + unsigned char BYTE; + struct { + unsigned char NDER16:1; + unsigned char NDER17:1; + unsigned char NDER18:1; + unsigned char NDER19:1; + unsigned char NDER20:1; + unsigned char NDER21:1; + unsigned char NDER22:1; + unsigned char NDER23:1; + } BIT; + } NDERL; + union { + unsigned char BYTE; + struct { + unsigned char POD24:1; + unsigned char POD25:1; + unsigned char POD26:1; + unsigned char POD27:1; + unsigned char POD28:1; + unsigned char POD29:1; + unsigned char POD30:1; + unsigned char POD31:1; + } BIT; + } PODRH; + union { + unsigned char BYTE; + struct { + unsigned char POD16:1; + unsigned char POD17:1; + unsigned char POD18:1; + unsigned char POD19:1; + unsigned char POD20:1; + unsigned char POD21:1; + unsigned char POD22:1; + unsigned char POD23:1; + } BIT; + } PODRL; + union { + unsigned char BYTE; + struct { + unsigned char NDR24:1; + unsigned char NDR25:1; + unsigned char NDR26:1; + unsigned char NDR27:1; + unsigned char NDR28:1; + unsigned char NDR29:1; + unsigned char NDR30:1; + unsigned char NDR31:1; + } BIT; + } NDRH; + union { + unsigned char BYTE; + struct { + unsigned char NDR16:1; + unsigned char NDR17:1; + unsigned char NDR18:1; + unsigned char NDR19:1; + unsigned char NDR20:1; + unsigned char NDR21:1; + unsigned char NDR22:1; + unsigned char NDR23:1; + } BIT; + } NDRL; + union { + unsigned char BYTE; + struct { + unsigned char NDR24:1; + unsigned char NDR25:1; + unsigned char NDR26:1; + unsigned char NDR27:1; + unsigned char :4; + } BIT; + } NDRH2; + union { + unsigned char BYTE; + struct { + unsigned char NDR16:1; + unsigned char NDR17:1; + unsigned char NDR18:1; + unsigned char NDR19:1; + unsigned char :4; + } BIT; + } NDRL2; +}; + +struct st_riic { + union { + unsigned char BYTE; + struct { + unsigned char SDAI:1; + unsigned char SCLI:1; + unsigned char SDAO:1; + unsigned char SCLO:1; + unsigned char SOWP:1; + unsigned char CLO:1; + unsigned char IICRST:1; + unsigned char ICE:1; + } BIT; + } ICCR1; + union { + unsigned char BYTE; + struct { + unsigned char ST:1; + unsigned char RS:1; + unsigned char SP:1; + unsigned char :1; + unsigned char TRS:1; + unsigned char MST:1; + unsigned char BBSY:1; + } BIT; + } ICCR2; + union { + unsigned char BYTE; + struct { + unsigned char BC:3; + unsigned char BCWP:1; + unsigned char CKS:3; + unsigned char MTWP:1; + } BIT; + } ICMR1; + union { + unsigned char BYTE; + struct { + unsigned char TMOS:1; + unsigned char TMOL:1; + unsigned char TMOH:1; + unsigned char :1; + unsigned char SDDL:3; + unsigned char DLCS:1; + } BIT; + } ICMR2; + union { + unsigned char BYTE; + struct { + unsigned char NF:2; + unsigned char ACKBR:1; + unsigned char ACKBT:1; + unsigned char ACKWP:1; + unsigned char RDRFS:1; + unsigned char WAIT:1; + unsigned char SMBS:1; + } BIT; + } ICMR3; + union { + unsigned char BYTE; + struct { + unsigned char TMOE:1; + unsigned char MALE:1; + unsigned char NALE:1; + unsigned char SALE:1; + unsigned char NACKE:1; + unsigned char NFE:1; + unsigned char SCLE:1; + unsigned char FMPE:1; + } BIT; + } ICFER; + union { + unsigned char BYTE; + struct { + unsigned char SAR0E:1; + unsigned char SAR1E:1; + unsigned char SAR2E:1; + unsigned char GCAE:1; + unsigned char :1; + unsigned char DIDE:1; + unsigned char :1; + unsigned char HOAE:1; + } BIT; + } ICSER; + union { + unsigned char BYTE; + struct { + unsigned char TMOIE:1; + unsigned char ALIE:1; + unsigned char STIE:1; + unsigned char SPIE:1; + unsigned char NAKIE:1; + unsigned char RIE:1; + unsigned char TEIE:1; + unsigned char TIE:1; + } BIT; + } ICIER; + union { + unsigned char BYTE; + struct { + unsigned char AAS0:1; + unsigned char AAS1:1; + unsigned char AAS2:1; + unsigned char GCA:1; + unsigned char :1; + unsigned char DID:1; + unsigned char :1; + unsigned char HOA:1; + } BIT; + } ICSR1; + union { + unsigned char BYTE; + struct { + unsigned char TMOF:1; + unsigned char AL:1; + unsigned char START:1; + unsigned char STOP:1; + unsigned char NACKF:1; + unsigned char RDRF:1; + unsigned char TEND:1; + unsigned char TDRE:1; + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + unsigned char SVA0:1; + unsigned char SVA:7; + } BIT; + } SARL0; + union { + unsigned char BYTE; + struct { + unsigned char FS:1; + unsigned char SVA:2; + unsigned char :5; + } BIT; + } SARU0; + union { + unsigned char BYTE; + struct { + unsigned char SVA0:1; + unsigned char SVA:7; + } BIT; + } SARL1; + union { + unsigned char BYTE; + struct { + unsigned char FS:1; + unsigned char SVA:2; + unsigned char :5; + } BIT; + } SARU1; + union { + unsigned char BYTE; + struct { + unsigned char SVA0:1; + unsigned char SVA:7; + } BIT; + } SARL2; + union { + unsigned char BYTE; + struct { + unsigned char FS:1; + unsigned char SVA:2; + unsigned char :5; + } BIT; + } SARU2; + union { + unsigned char BYTE; + struct { + unsigned char BRL:5; + unsigned char :3; + } BIT; + } ICBRL; + union { + unsigned char BYTE; + struct { + unsigned char BRH:5; + unsigned char :3; + } BIT; + } ICBRH; + unsigned char ICDRT; + unsigned char ICDRR; +}; + +struct st_rspi { + union { + unsigned char BYTE; + struct { + unsigned char SPMS:1; + unsigned char TXMD:1; + unsigned char MODFEN:1; + unsigned char MSTR:1; + unsigned char SPEIE:1; + unsigned char SPTIE:1; + unsigned char SPE:1; + unsigned char SPRIE:1; + } BIT; + } SPCR; + union { + unsigned char BYTE; + struct { + unsigned char SSLP0:1; + unsigned char SSLP1:1; + unsigned char SSLP2:1; + unsigned char SSLP3:1; + unsigned char :4; + } BIT; + } SSLP; + union { + unsigned char BYTE; + struct { + unsigned char SPLP:1; + unsigned char SPLP2:1; + unsigned char SPOM:1; + unsigned char :1; + unsigned char MOIFV:1; + unsigned char MOIFE:1; + unsigned char :2; + } BIT; + } SPPCR; + union { + unsigned char BYTE; + struct { + unsigned char OVRF:1; + unsigned char IDLNF:1; + unsigned char MODF:1; + unsigned char PERF:1; + unsigned char :1; + unsigned char SPTEF:1; + unsigned char :1; + unsigned char SPRF:1; + } BIT; + } SPSR; + union { + unsigned long LONG; + struct { + unsigned short L; + unsigned short H; + } WORD; + } SPDR; + union { + unsigned char BYTE; + struct { + unsigned char SPSLN:3; + unsigned char :5; + } BIT; + } SPSCR; + union { + unsigned char BYTE; + struct { + unsigned char SPCP:3; + unsigned char :1; + unsigned char SPECM:3; + unsigned char :1; + } BIT; + } SPSSR; + union { + unsigned char BYTE; + struct { + unsigned char SPR0:1; + unsigned char SPR1:1; + unsigned char SPR2:1; + unsigned char SPR3:1; + unsigned char SPR4:1; + unsigned char SPR5:1; + unsigned char SPR6:1; + unsigned char SPR7:1; + } BIT; + } SPBR; + union { + unsigned char BYTE; + struct { + unsigned char SPFC:2; + unsigned char SLSEL:2; + unsigned char SPRDTD:1; + unsigned char SPLW:1; + unsigned char :2; + } BIT; + } SPDCR; + union { + unsigned char BYTE; + struct { + unsigned char SCKDL:3; + unsigned char :5; + } BIT; + } SPCKD; + union { + unsigned char BYTE; + struct { + unsigned char SLNDL:3; + unsigned char :5; + } BIT; + } SSLND; + union { + unsigned char BYTE; + struct { + unsigned char SPNDL:3; + unsigned char :5; + } BIT; + } SPND; + union { + unsigned char BYTE; + struct { + unsigned char SPPE:1; + unsigned char SPOE:1; + unsigned char SPIIE:1; + unsigned char PTE:1; + unsigned char :4; + } BIT; + } SPCR2; + union { + unsigned short WORD; + struct { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV:2; + unsigned short SSLA:3; + unsigned short SSLKP:1; + unsigned short SPB:4; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD0; + union { + unsigned short WORD; + struct { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV:2; + unsigned short SSLA:3; + unsigned short SSLKP:1; + unsigned short SPB:4; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD1; + union { + unsigned short WORD; + struct { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV:2; + unsigned short SSLA:3; + unsigned short SSLKP:1; + unsigned short SPB:4; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD2; + union { + unsigned short WORD; + struct { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV:2; + unsigned short SSLA:3; + unsigned short SSLKP:1; + unsigned short SPB:4; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD3; + union { + unsigned short WORD; + struct { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV:2; + unsigned short SSLA:3; + unsigned short SSLKP:1; + unsigned short SPB:4; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD4; + union { + unsigned short WORD; + struct { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV:2; + unsigned short SSLA:3; + unsigned short SSLKP:1; + unsigned short SPB:4; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD5; + union { + unsigned short WORD; + struct { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV:2; + unsigned short SSLA:3; + unsigned short SSLKP:1; + unsigned short SPB:4; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD6; + union { + unsigned short WORD; + struct { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV:2; + unsigned short SSLA:3; + unsigned short SSLKP:1; + unsigned short SPB:4; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD7; +}; + +struct st_rtc { + union { + unsigned char BYTE; + struct { + unsigned char F1HZ:1; + unsigned char F2HZ:1; + unsigned char F4HZ:1; + unsigned char F8HZ:1; + unsigned char F16HZ:1; + unsigned char F32HZ:1; + unsigned char F64HZ:1; + } BIT; + } R64CNT; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char SEC1:4; + unsigned char SEC10:3; + unsigned char :1; + } BIT; + } RSECCNT; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char MIN1:4; + unsigned char MIN10:3; + unsigned char :1; + } BIT; + } RMINCNT; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char HOUR1:4; + unsigned char HOUR10:2; + unsigned char :2; + } BIT; + } RHRCNT; + char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char DAY:3; + unsigned char :5; + } BIT; + } RWKCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char DAY1:4; + unsigned char DAY10:2; + unsigned char :2; + } BIT; + } RDAYCNT; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char MON1:4; + unsigned char MON10:1; + unsigned char :3; + } BIT; + } RMONCNT; + char wk6[1]; + union { + unsigned short WORD; + struct { + unsigned short YEAR1:4; + unsigned short YEAR10:4; + unsigned short YEAR100:4; + unsigned short YEAR1000:4; + } BIT; + } RYRCNT; + union { + unsigned char BYTE; + struct { + unsigned char SEC1:4; + unsigned char SEC10:3; + unsigned char ENB:1; + } BIT; + } RSECAR; + char wk7[1]; + union { + unsigned char BYTE; + struct { + unsigned char MIN1:4; + unsigned char MIN10:3; + unsigned char ENB:1; + } BIT; + } RMINAR; + char wk8[1]; + union { + unsigned char BYTE; + struct { + unsigned char HOUR1:4; + unsigned char HOUR10:2; + unsigned char :1; + unsigned char ENB:1; + } BIT; + } RHRAR; + char wk9[1]; + union { + unsigned char BYTE; + struct { + unsigned char DAY:3; + unsigned char :4; + unsigned char ENB:1; + } BIT; + } RWKAR; + char wk10[1]; + union { + unsigned char BYTE; + struct { + unsigned char DAY1:4; + unsigned char DAY10:2; + unsigned char :1; + unsigned char ENB:1; + } BIT; + } RDAYAR; + char wk11[1]; + union { + unsigned char BYTE; + struct { + unsigned char MON1:4; + unsigned char MON10:1; + unsigned char :2; + unsigned char ENB:1; + } BIT; + } RMONAR; + char wk12[1]; + union { + unsigned short WORD; + struct { + unsigned short YEAR1:4; + unsigned short YEAR10:4; + unsigned short YEAR100:4; + unsigned short YEAR1000:4; + } BIT; + } RYRAR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ENB:1; + } BIT; + } RYRAREN; + char wk13[3]; + union { + unsigned char BYTE; + struct { + unsigned char AIE:1; + unsigned char CIE:1; + unsigned char PIE:1; + unsigned char :1; + unsigned char PES:3; + unsigned char :1; + } BIT; + } RCR1; + char wk14[1]; + union { + unsigned char BYTE; + struct { + unsigned char START:1; + unsigned char RESET:1; + unsigned char ADJ:1; + unsigned char RTCOE:1; + unsigned char :4; + } BIT; + } RCR2; +}; + +struct st_s12ad { + union { + unsigned char BYTE; + struct { + unsigned char EXTRG:1; + unsigned char TRGE:1; + unsigned char CKS:2; + unsigned char ADIE:1; + unsigned char :1; + unsigned char ADCS:1; + unsigned char ADST:1; + } BIT; + } ADCSR; + char wk0[3]; + union { + unsigned short WORD; +/* -- oops! + struct { + unsigned short ANS:8; + unsigned short :8; + } BIT; +*/ + } ADANS; + char wk1[2]; + union { + unsigned short WORD; +/* -- oops! + struct { + unsigned short ADS:8; + unsigned short :8; + } BIT; +*/ + } ADADS; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char ADC:2; + unsigned char :6; + } BIT; + } ADADC; + char wk3[1]; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short ACE:1; + unsigned short :9; + unsigned short ADRFMT:1; + } BIT; + } ADCER; + union { + unsigned char BYTE; + struct { + unsigned char ADSTRS:4; + unsigned char :4; + } BIT; + } ADSTRGR; + char wk4[15]; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + unsigned short ADDR4; + unsigned short ADDR5; + unsigned short ADDR6; + unsigned short ADDR7; +}; + +struct st_sci { + union { + unsigned char BYTE; + struct { + unsigned char CKS:2; + unsigned char MP:1; + unsigned char STOP:1; + unsigned char PM:1; + unsigned char PE:1; + unsigned char CHR:1; + unsigned char CM:1; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char CKE:2; + unsigned char TEIE:1; + unsigned char MPIE:1; + unsigned char RE:1; + unsigned char TE:1; + unsigned char RIE:1; + unsigned char TIE:1; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char MPBT:1; + unsigned char MPB:1; + unsigned char TEND:1; + unsigned char PER:1; + unsigned char FER:1; + unsigned char ORER:1; + unsigned char RDRF:1; + unsigned char TDRE:1; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char SMIF:1; + unsigned char :1; + unsigned char SINV:1; + unsigned char SDIR:1; + unsigned char :4; + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + unsigned char ACS0:1; + unsigned char :3; + unsigned char ABCS:1; + unsigned char :3; + } BIT; + } SEMR; +}; + +struct st_smci { + union { + unsigned char BYTE; + struct { + unsigned char CKS:2; + unsigned char BCP:2; + unsigned char PM:1; + unsigned char PE:1; + unsigned char BLK:1; + unsigned char GM:1; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char CKE:2; + unsigned char TEIE:1; + unsigned char :1; + unsigned char RE:1; + unsigned char TE:1; + unsigned char RIE:1; + unsigned char TIE:1; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char TEND:1; + unsigned char PER:1; + unsigned char ERS:1; + unsigned char ORER:1; + unsigned char RDRF:1; + unsigned char TDRE:1; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char SMIF:1; + unsigned char :1; + unsigned char SINV:1; + unsigned char SDIR:1; + unsigned char :3; + unsigned char BCP2:1; + } BIT; + } SCMR; +}; + +struct st_system { + union { + unsigned short WORD; +/* -- oops! + struct { + unsigned short MD0:1; + unsigned short MD1:1; + unsigned short :5; + unsigned short MDE:1; + unsigned short :8; + } BIT; +*/ + } MDMONR; + union { + unsigned short WORD; + struct { + unsigned short IROM:1; + unsigned short EXB:1; + unsigned short BSW:2; + unsigned short BOTS:1; + unsigned short :1; + unsigned short UBTS:1; + unsigned short :9; + } BIT; + } MDSR; + char wk0[2]; + union { + unsigned short WORD; +/* -- oops! + struct { + unsigned short ROME:1; + unsigned short EXBE:1; + unsigned short :6; + unsigned short KEY:8; + } BIT; +*/ + } SYSCR0; + union { + unsigned short WORD; + struct { + + unsigned short RAME:1; + unsigned short :15; + } BIT; + } SYSCR1; + char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short STS:5; + unsigned short :1; + unsigned short OPE:1; + unsigned short SSBY:1; + } BIT; + } SBYCR; + char wk2[2]; + union { + unsigned long LONG; + struct { + unsigned long :4; + unsigned long MSTPA4:1; + unsigned long MSTPA5:1; + unsigned long :2; + unsigned long MSTPA8:1; + unsigned long MSTPA9:1; + unsigned long MSTPA10:1; + unsigned long MSTPA11:1; + unsigned long :2; + unsigned long MSTPA14:1; + unsigned long MSTPA15:1; + unsigned long :1; + unsigned long MSTPA17:1; + unsigned long :1; + unsigned long MSTPA19:1; + unsigned long :2; + unsigned long MSTPA22:1; + unsigned long MSTPA23:1; + unsigned long :4; + unsigned long MSTPA28:1; + unsigned long MSTPA29:1; + unsigned long :1; + unsigned long ACSE:1; + } BIT; + } MSTPCRA; + union { + unsigned long LONG; + struct { + unsigned long MSTPB0:1; + unsigned long :14; + unsigned long MSTPB15:1; + unsigned long MSTPB16:1; + unsigned long MSTPB17:1; + unsigned long MSTPB18:1; + unsigned long MSTPB19:1; + unsigned long MSTPB20:1; + unsigned long MSTPB21:1; + unsigned long :1; + unsigned long MSTPB23:1; + unsigned long :1; + unsigned long MSTPB25:1; + unsigned long MSTPB26:1; + unsigned long :1; + unsigned long MSTPB28:1; + unsigned long MSTPB29:1; + unsigned long MSTPB30:1; + unsigned long MSTPB31:1; + } BIT; + } MSTPCRB; + union { + unsigned long LONG; + struct { + unsigned long MSTPC0:1; + unsigned long MSTPC1:1; + unsigned long :30; + } BIT; + } MSTPCRC; + char wk3[4]; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long PCK:4; + unsigned long :4; + unsigned long BCK:4; + unsigned long :2; + unsigned long PSTOP0:1; + unsigned long PSTOP1:1; + unsigned long ICK:4; + unsigned long :4; + } BIT; + } SCKCR; + char wk4[12]; + union { + unsigned char BYTE; + struct { + unsigned char BCLKDIV:1; + unsigned char :7; + } BIT; + } BCKCR; + char wk5[15]; + union { + unsigned short WORD; +/* -- oops! + struct { + unsigned short :6; + unsigned short OSTDF:1; + unsigned short OSTDE:1; + unsigned short KEY:8; + } BIT; +*/ + } OSTDCR; + char wk6[49726]; + union { + unsigned char BYTE; + struct { + unsigned char RAMCUT0:1; + unsigned char :3; + unsigned char RAMCUT1:1; + unsigned char RAMCUT2:1; + unsigned char IOKEEP:1; + unsigned char DPSBY:1; + } BIT; + } DPSBYCR; + union { + unsigned char BYTE; + struct { + unsigned char WTSTS:6; + unsigned char :2; + } BIT; + } DPSWCR; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ0E:1; + unsigned char DIRQ1E:1; + unsigned char DIRQ2E:1; + unsigned char DIRQ3E:1; + unsigned char DLVDE:1; + unsigned char DRTCE:1; + unsigned char DUSBE:1; + unsigned char DNMIE:1; + } BIT; + } DPSIER; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ0F:1; + unsigned char DIRQ1F:1; + unsigned char DIRQ2F:1; + unsigned char DIRQ3F:1; + unsigned char DLVDF:1; + unsigned char DRTCFF:1; + unsigned char DUSBF:1; + unsigned char DNMIF:1; + } BIT; + } DPSIFR; + union { + unsigned char BYTE; + struct { + unsigned char DIRQ0EG:1; + unsigned char DIRQ1EG:1; + unsigned char DIRQ2EG:1; + unsigned char DIRQ3EG:1; + unsigned char DPSIER:3; + unsigned char DNMIEG:1; + } BIT; + } DPSIEGR; + union { + unsigned char BYTE; + struct { + unsigned char PORF:1; + unsigned char LVD1F:1; + unsigned char LVD2F:1; + unsigned char DPSIER:4; + unsigned char DPSRSTF:1; + } BIT; + } RSTSR; + char wk7[4]; + union { + unsigned char BYTE; + struct { + unsigned char SUBSTOP:1; + unsigned char DPSIER:7; + } BIT; + } SUBOSCCR; + char wk8[1]; + unsigned char LVDKEYR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char LVD1RI:1; + unsigned char LVD1E:1; + unsigned char :2; + unsigned char LVD2RI:1; + unsigned char LVD2E:1; + } BIT; + } LVDCR; + char wk9[2]; + unsigned char DPSBKR[32]; +}; + +struct st_tmr0 { + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CCLR:2; + unsigned char OVIE:1; + unsigned char CMIEA:1; + unsigned char CMIEB:1; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char OSA:2; + unsigned char OSB:2; + unsigned char ADTE:1; + unsigned char :3; + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char CKS:3; + unsigned char CSS:2; + unsigned char :2; + unsigned char TMRIS:1; + } BIT; + } TCCR; +}; + +struct st_tmr1 { + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CCLR:2; + unsigned char OVIE:1; + unsigned char CMIEA:1; + unsigned char CMIEB:1; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char OSA:2; + unsigned char OSB:2; + unsigned char :4; + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char CKS:3; + unsigned char CSS:2; + unsigned char :2; + unsigned char TMRIS:1; + } BIT; + } TCCR; +}; + +struct st_tmr01 { + unsigned short TCORA; + unsigned short TCORB; + unsigned short TCNT; + unsigned short TCCR; +}; + +struct st_usb { + union { + unsigned long LONG; + struct { + unsigned long SRPC0:1; + unsigned long :3; + unsigned long FIXPHY0:1; + unsigned long :3; + unsigned long SRPC1:1; + unsigned long :3; + unsigned long FIXPHY1:1; + unsigned long :3; + unsigned long DP0:1; + unsigned long DM0:1; + unsigned long :2; + unsigned long DOVCA0:1; + unsigned long DOVCB0:1; + unsigned long :1; + unsigned long DVBSTS0:1; + unsigned long DP1:1; + unsigned long DM1:1; + unsigned long :2; + unsigned long DOVCA1:1; + unsigned long DOVCB1:1; + unsigned long :1; + unsigned long DVSTS1:1; + } BIT; + } DPUSR0R; + union { + unsigned long LONG; + struct { + + unsigned long DPINTE0:1; + unsigned long DMINTE0:1; + unsigned long :2; + unsigned long DOVRCRAE0:1; + unsigned long DOVRCRBE0:1; + unsigned long :1; + unsigned long DVBSE0:1; + unsigned long DPINTE1:1; + unsigned long DMINTE1:1; + unsigned long :2; + unsigned long DOVRCRAE1:1; + unsigned long DOVRCRBE1:1; + unsigned long :1; + unsigned long DVBSE1:1; + unsigned long DPINT0:1; + unsigned long DMINT0:1; + unsigned long :2; + unsigned long DOVRCRA0:1; + unsigned long DOVRCRB0:1; + unsigned long :1; + unsigned long DVBINT0:1; + unsigned long DPINT1:1; + unsigned long DMINT1:1; + unsigned long :2; + unsigned long DOVRCRA1:1; + unsigned long DOVRCRB1:1; + unsigned long :1; + unsigned long DVBINT1:1; + } BIT; + } DPUSR1R; +}; + +struct st_usb0 { + union { + unsigned short WORD; + struct { + unsigned short USBE:1; + unsigned short :3; + unsigned short DPRPU:1; + unsigned short DRPD:1; + unsigned short DCFM:1; + unsigned short :3; + unsigned short SCKE:1; + unsigned short :5; + } BIT; + } SYSCFG; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short LNST:2; + unsigned short IDMON:1; + unsigned short :3; + unsigned short HTACT:1; + unsigned short :7; + unsigned short OVCMON:2; + } BIT; + } SYSSTS0; + char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short RHST:3; + unsigned short :1; + unsigned short UACT:1; + unsigned short RESUME:1; + unsigned short USBRST:1; + unsigned short RWUPE:1; + unsigned short WKUP:1; + unsigned short VBUSEN:1; + unsigned short EXICEN:1; + unsigned short HNPBTOA:1; + unsigned short :4; + } BIT; + } DVSTCTR0; + char wk2[10]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } CFIFO; + char wk3[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D0FIFO; + char wk4[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D1FIFO; + char wk5[2]; + union { + unsigned short WORD; + struct { + unsigned short CURPIPE:4; + unsigned short :1; + unsigned short ISEL:1; + unsigned short :2; + unsigned short BIGEND:1; + unsigned short :1; + unsigned short MBW:1; + unsigned short :3; + unsigned short REW:1; + unsigned short RCNT:1; + } BIT; + } CFIFOSEL; + union { + unsigned short WORD; + struct { + unsigned short DTLN:9; + unsigned short :4; + unsigned short FRDY:1; + unsigned short BCLR:1; + unsigned short BVAL:1; + } BIT; + } CFIFOCTR; + char wk6[4]; + union { + unsigned short WORD; + struct { + unsigned short CURPIPE:4; + unsigned short :4; + unsigned short BIGEND:1; + unsigned short :1; + unsigned short MBW:1; + unsigned short :1; + unsigned short DREQE:1; + unsigned short DCLRM:1; + unsigned short REW:1; + unsigned short RCNT:1; + } BIT; + } D0FIFOSEL; + union { + unsigned short WORD; + struct { + unsigned short DTLN:9; + unsigned short :4; + unsigned short FRDY:1; + unsigned short BCLR:1; + unsigned short BVAL:1; + } BIT; + } D0FIFOCTR; + union { + unsigned short WORD; + struct { + unsigned short CURPIPE:4; + unsigned short :4; + unsigned short BIGEND:1; + unsigned short :1; + unsigned short MBW:1; + unsigned short :1; + unsigned short DREQE:1; + unsigned short DCLRM:1; + unsigned short REW:1; + unsigned short RCNT:1; + } BIT; + } D1FIFOSEL; + union { + unsigned short WORD; + struct { + unsigned short DTLN:9; + unsigned short :4; + unsigned short FRDY:1; + unsigned short BCLR:1; + unsigned short BVAL:1; + } BIT; + } D1FIFOCTR; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short BRDYE:1; + unsigned short NRDYE:1; + unsigned short BEMPE:1; + unsigned short CTRE:1; + unsigned short DVSE:1; + unsigned short SOFE:1; + unsigned short RSME:1; + unsigned short VBSE:1; + } BIT; + } INTENB0; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short SACKE:1; + unsigned short SIGNE:1; + unsigned short EOFERRE:1; + unsigned short :4; + unsigned short ATTCHE:1; + unsigned short DTCHE:1; + unsigned short :1; + unsigned short BCHGE:1; + unsigned short OVRCRE:1; + } BIT; + } INTENB1; + char wk7[2]; + union { + unsigned short WORD; + struct { + unsigned short PIPE0BRDYE:1; + unsigned short PIPE1BRDYE:1; + unsigned short PIPE2BRDYE:1; + unsigned short PIPE3BRDYE:1; + unsigned short PIPE4BRDYE:1; + unsigned short PIPE5BRDYE:1; + unsigned short PIPE6BRDYE:1; + unsigned short PIPE7BRDYE:1; + unsigned short PIPE8BRDYE:1; + unsigned short PIPE9BRDYE:1; + unsigned short :6; + } BIT; + } BRDYENB; + union { + unsigned short WORD; + struct { + unsigned short PIPE0BRDYE:1; + unsigned short PIPE1BRDYE:1; + unsigned short PIPE2BRDYE:1; + unsigned short PIPE3BRDYE:1; + unsigned short PIPE4BRDYE:1; + unsigned short PIPE5BRDYE:1; + unsigned short PIPE6BRDYE:1; + unsigned short PIPE7BRDYE:1; + unsigned short PIPE8BRDYE:1; + unsigned short PIPE9BRDYE:1; + unsigned short :6; + } BIT; + } NRDYENB; + union { + unsigned short WORD; + struct { + unsigned short PIPE0BEMPE:1; + unsigned short PIPE1BEMPE:1; + unsigned short PIPE2BEMPE:1; + unsigned short PIPE3BEMPE:1; + unsigned short PIPE4BEMPE:1; + unsigned short PIPE5BEMPE:1; + unsigned short PIPE6BEMPE:1; + unsigned short PIPE7BEMPE:1; + unsigned short PIPE8BEMPE:1; + unsigned short PIPE9BEMPE:1; + unsigned short :6; + } BIT; + } BEMPENB; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short EDGESTS:1; + unsigned short :1; + unsigned short BRDYM:1; + unsigned short :1; + unsigned short TRNENSEL:1; + unsigned short :7; + + } BIT; + } SOFCFG; + char wk8[2]; + union { + unsigned short WORD; + struct { + unsigned short CTSQ:3; + unsigned short VALID:1; + unsigned short DVSQ:3; + unsigned short VBSTS:1; + unsigned short BRDY:1; + unsigned short NRDY:1; + unsigned short BEMP:1; + unsigned short CTRT:1; + unsigned short DVST:1; + unsigned short SOFR:1; + unsigned short RESM:1; + unsigned short VBINT:1; + } BIT; + } INTSTS0; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short SACK:1; + unsigned short SIGN:1; + unsigned short EOFERR:1; + unsigned short :4; + unsigned short ATTCH:1; + unsigned short DTCH:1; + unsigned short :1; + unsigned short BCHG:1; + unsigned short OVRCR:1; + } BIT; + } INTSTS1; + char wk9[2]; + union { + unsigned short WORD; + struct { + unsigned short PIPE0BRDY:1; + unsigned short PIPE1BRDY:1; + unsigned short PIPE2BRDY:1; + unsigned short PIPE3BRDY:1; + unsigned short PIPE4BRDY:1; + unsigned short PIPE5BRDY:1; + unsigned short PIPE6BRDY:1; + unsigned short PIPE7BRDY:1; + unsigned short PIPE8BRDY:1; + unsigned short PIPE9BRDY:1; + unsigned short :6; + } BIT; + } BRDYSTS; + union { + unsigned short WORD; + struct { + unsigned short PIPE0BRDY:1; + unsigned short PIPE1BRDY:1; + unsigned short PIPE2BRDY:1; + unsigned short PIPE3BRDY:1; + unsigned short PIPE4BRDY:1; + unsigned short PIPE5BRDY:1; + unsigned short PIPE6BRDY:1; + unsigned short PIPE7BRDY:1; + unsigned short PIPE8BRDY:1; + unsigned short PIPE9BRDY:1; + unsigned short :6; + } BIT; + } NRDYSTS; + union { + unsigned short WORD; + struct { + unsigned short PIPE0BENP:1; + unsigned short PIPE1BENP:1; + unsigned short PIPE2BENP:1; + unsigned short PIPE3BENP:1; + unsigned short PIPE4BENP:1; + unsigned short PIPE5BENP:1; + unsigned short PIPE6BENP:1; + unsigned short PIPE7BENP:1; + unsigned short PIPE8BENP:1; + unsigned short PIPE9BENP:1; + unsigned short :6; + } BIT; + } BEMPSTS; + union { + unsigned short WORD; + struct { + unsigned short FRNM:11; + unsigned short :3; + unsigned short CRCE:1; + unsigned short OVRN:1; + } BIT; + } FRMNUM; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short DVCHG:1; + } BIT; + } DVCHGR; + union { + unsigned short WORD; + struct { + unsigned short USBADDR:7; + unsigned short :1; + unsigned short STSRECOV:4; + unsigned short :4; + } BIT; + } USBADDR; + char wk10[2]; + union { + unsigned short WORD; +/* -- oops! + struct { + unsigned short BMREQUESTTYPE:8; + unsigned short BREQUEST:8; + } BIT; +*/ + } USBREQ; + unsigned short USBVAL; + unsigned short USBINDX; + unsigned short USBLENG; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short DIR:1; + unsigned short :2; + unsigned short SHTNAK:1; + unsigned short :8; + } BIT; + } DCPCFG; + union { + unsigned short WORD; + struct { + unsigned short MXPS:7; + unsigned short :5; + unsigned short DEVSEL:4; + } BIT; + } DCPMAXP; + union { + unsigned short WORD; + struct { + unsigned short PID:2; + unsigned short CCPL:1; + unsigned short :2; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short :2; + unsigned short SUREQCLR:1; + unsigned short :2; + unsigned short SUREQ:1; + unsigned short BSTS:1; + } BIT; + } DCPCTR; + char wk11[2]; + union { + unsigned short WORD; + struct { + unsigned short PIPESEL:4; + unsigned short :12; + } BIT; + } PIPESEL; + char wk12[2]; + union { + unsigned short WORD; + struct { + unsigned short EPNUM:4; + unsigned short DIR:1; + unsigned short :2; + unsigned short SHTNAK:1; + unsigned short :1; + unsigned short DBLB:1; + unsigned short BFRE:1; + unsigned short :3; + unsigned short TYPE:2; + } BIT; + } PIPECFG; + char wk13[2]; + union { + unsigned short WORD; + struct { + unsigned short MXPS:9; + unsigned short :3; + unsigned short DEVSEL:4; + } BIT; + } PIPEMAXP; + union { + unsigned short WORD; + struct { + unsigned short IITV:3; + unsigned short :9; + unsigned short IFIS:1; + unsigned short :3; + } BIT; + } PIPEPERI; + union { + unsigned short WORD; + struct { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPE1CTR; + union { + unsigned short WORD; + struct { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPE2CTR; + union { + unsigned short WORD; + struct { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPE3CTR; + union { + unsigned short WORD; + struct { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPE4CTR; + union { + unsigned short WORD; + struct { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPE5CTR; + union { + unsigned short WORD; + struct { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short :5; + unsigned short BSTS:1; + } BIT; + } PIPE6CTR; + union { + unsigned short WORD; + struct { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short :5; + unsigned short BSTS:1; + } BIT; + } PIPE7CTR; + union { + unsigned short WORD; + struct { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short :5; + unsigned short BSTS:1; + } BIT; + } PIPE8CTR; + union { + unsigned short WORD; + struct { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short :5; + unsigned short BSTS:1; + } BIT; + } PIPE9CTR; + char wk14[14]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPE1TRE; + unsigned short PIPE1TRN; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPE2TRE; + unsigned short PIPE2TRN; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPE3TRE; + unsigned short PIPE3TRN; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPE4TRE; + unsigned short PIPE4TRN; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPE5TRE; + unsigned short PIPE5TRN; + char wk15[44]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short USBSPD:2; + unsigned short :8; + } BIT; + } DEVADD0; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short USBSPD:2; + unsigned short :8; + } BIT; + } DEVADD1; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short USBSPD:2; + unsigned short :8; + } BIT; + } DEVADD2; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short USBSPD:2; + unsigned short :8; + } BIT; + } DEVADD3; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short USBSPD:2; + unsigned short :8; + } BIT; + } DEVADD4; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short USBSPD:2; + unsigned short :8; + } BIT; + } DEVADD5; +}; + +union un_wdt { + struct { + union { + unsigned char BYTE; + struct { + unsigned char CKS:3; + unsigned char :2; + unsigned char TME:1; + unsigned char TMS:1; + unsigned char :1; + } BIT; + } TCSR; + unsigned char TCNT; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char RSTE:1; + unsigned char WOVF:1; + } BIT; + } RSTCSR; + } READ; + struct { + unsigned short WINA; + unsigned short WINB; + } WRITE; +}; + +enum enum_ir { +IR_BSC_BUSERR=16,IR_FCU_FIFERR=21,IR_FCU_FRDYI=23, +IR_ICU_SWINT=27, +IR_CMT0_CMI0, +IR_CMT1_CMI1, +IR_CMT2_CMI2, +IR_CMT3_CMI3, +IR_ETHER_EINT, +IR_USB0_D0FIFO0=36,IR_USB0_D1FIFO0,IR_USB0_USBI0, +IR_USB1_D0FIFO1=40,IR_USB1_D1FIFO1,IR_USB1_USBI1, +IR_RSPI0_SPEI0=44,IR_RSPI0_SPRI0,IR_RSPI0_SPTI0,IR_RSPI0_SPII0, +IR_RSPI1_SPEI1,IR_RSPI1_SPRI1,IR_RSPI1_SPTI1,IR_RSPI1_SPII1, +IR_CAN0_ERS0=56,IR_CAN0_RXF0,IR_CAN0_TXF0,IR_CAN0_RXM0,IR_CAN0_TXM0, +IR_RTC_PRD=62,IR_RTC_CUP, +IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7,IR_ICU_IRQ8,IR_ICU_IRQ9,IR_ICU_IRQ10,IR_ICU_IRQ11,IR_ICU_IRQ12,IR_ICU_IRQ13,IR_ICU_IRQ14,IR_ICU_IRQ15, +IR_USB_USBR0=90,IR_USB_USBR1, +IR_RTC_ALM, +IR_WDT_WOVI=96, +IR_AD0_ADI0=98, +IR_AD1_ADI1, +IR_S12AD_ADI=102, +IR_MTU0_TGIA0=114,IR_MTU0_TGIB0,IR_MTU0_TGIC0,IR_MTU0_TGID0,IR_MTU0_TCIV0,IR_MTU0_TGIE0,IR_MTU0_TGIF0, +IR_MTU1_TGIA1,IR_MTU1_TGIB1,IR_MTU1_TCIV1,IR_MTU1_TCIU1, +IR_MTU2_TGIA2,IR_MTU2_TGIB2,IR_MTU2_TCIV2,IR_MTU2_TCIU2, +IR_MTU3_TGIA3,IR_MTU3_TGIB3,IR_MTU3_TGIC3,IR_MTU3_TGID3,IR_MTU3_TCIV3, +IR_MTU4_TGIA4,IR_MTU4_TGIB4,IR_MTU4_TGIC4,IR_MTU4_TGID4,IR_MTU4_TCIV4, +IR_MTU5_TGIU5,IR_MTU5_TGIV5,IR_MTU5_TGIW5, +IR_MTU6_TGIA6,IR_MTU6_TGIB6,IR_MTU6_TGIC6,IR_MTU6_TGID6,IR_MTU6_TCIV6,IR_MTU6_TGIE6,IR_MTU6_TGIF6, +IR_MTU7_TGIA7,IR_MTU7_TGIB7,IR_MTU7_TCIV7,IR_MTU7_TCIU7, +IR_MTU8_TGIA8,IR_MTU8_TGIB8,IR_MTU8_TCIV8,IR_MTU8_TCIU8, +IR_MTU9_TGIA9,IR_MTU9_TGIB9,IR_MTU9_TGIC9,IR_MTU9_TGID9,IR_MTU9_TCIV9, +IR_MTU10_TGIA10,IR_MTU10_TGIB10,IR_MTU10_TGIC10,IR_MTU10_TGID10,IR_MTU10_TCIV10, +IR_MTU11_TGIU11,IR_MTU11_TGIV11,IR_MTU11_TGIW11, +IR_POE_OEI1,IR_POE_OEI2,IR_POE_OEI3,IR_POE_OEI4, +IR_TMR0_CMIA0,IR_TMR0_CMIB0,IR_TMR0_OVI0, +IR_TMR1_CMIA1,IR_TMR1_CMIB1,IR_TMR1_OVI1, +IR_TMR2_CMIA2,IR_TMR2_CMIB2,IR_TMR2_OVI2, +IR_TMR3_CMIA3,IR_TMR3_CMIB3,IR_TMR3_OVI3, +IR_DMAC_DMAC0I=198,IR_DMAC_DMAC1I,IR_DMAC_DMAC2I,IR_DMAC_DMAC3I, +IR_EXDMAC_EXDMAC0I,IR_EXDMAC_EXDMAC1I, +IR_SCI0_ERI0=214,IR_SCI0_RXI0,IR_SCI0_TXI0,IR_SCI0_TEI0, +IR_SCI1_ERI1,IR_SCI1_RXI1,IR_SCI1_TXI1,IR_SCI1_TEI1, +IR_SCI2_ERI2,IR_SCI2_RXI2,IR_SCI2_TXI2,IR_SCI2_TEI2, +IR_SCI3_ERI3,IR_SCI3_RXI3,IR_SCI3_TXI3,IR_SCI3_TEI3, +IR_SCI5_ERI5=234,IR_SCI5_RXI5,IR_SCI5_TXI5,IR_SCI5_TEI5, +IR_SCI6_ERI6,IR_SCI6_RXI6,IR_SCI6_TXI6,IR_SCI6_TEI6, +IR_RIIC0_ICEEI0=246,IR_RIIC0_ICRXI0,IR_RIIC0_ICTXI0,IR_RIIC0_ICTEI0, +IR_RIIC1_ICEEI1,IR_RIIC1_ICRXI1,IR_RIIC1_ICTXI1,IR_RIIC1_ICTEI1 +}; + +enum enum_dtce { +DTCE_ICU_SWINT=27, +DTCE_CMT0_CMI0, +DTCE_CMT1_CMI1, +DTCE_CMT2_CMI2, +DTCE_CMT3_CMI3, +DTCE_USB0_D0FIFO0=36,DTCE_USB0_D1FIFO0, +DTCE_USB1_D0FIFO1=40,DTCE_USB1_D1FIFO1, +DTCE_RSPI0_SPRI0=45,DTCE_RSPI0_SPTI0, +DTCE_RSPI1_SPRI1=49,DTCE_RSPI1_SPTI1, +DTCE_ICU_IRQ0=64,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7,DTCE_ICU_IRQ8,DTCE_ICU_IRQ9,DTCE_ICU_IRQ10,DTCE_ICU_IRQ11,DTCE_ICU_IRQ12,DTCE_ICU_IRQ13,DTCE_ICU_IRQ14,DTCE_ICU_IRQ15, +DTCE_AD0_ADI0=98, +DTCE_AD1_ADI1, +DTCE_S12AD_ADI=102, +DTCE_MTU0_TGIA0=114,DTCE_MTU0_TGIB0,DTCE_MTU0_TGIC0,DTCE_MTU0_TGID0, +DTCE_MTU1_TGIA1=121,DTCE_MTU1_TGIB1, +DTCE_MTU2_TGIA2=125,DTCE_MTU2_TGIB2, +DTCE_MTU3_TGIA3=129,DTCE_MTU3_TGIB3,DTCE_MTU3_TGIC3,DTCE_MTU3_TGID3, +DTCE_MTU4_TGIA4=134,DTCE_MTU4_TGIB4,DTCE_MTU4_TGIC4,DTCE_MTU4_TGID4,DTCE_MTU4_TCIV4, +DTCE_MTU5_TGIU5,DTCE_MTU5_TGIV5,DTCE_MTU5_TGIW5, +DTCE_MTU6_TGIA6,DTCE_MTU6_TGIB6,DTCE_MTU6_TGIC6,DTCE_MTU6_TGID6, +DTCE_MTU7_TGIA7=149,DTCE_MTU7_TGIB7, +DTCE_MTU8_TGIA8=153,DTCE_MTU8_TGIB8, +DTCE_MTU9_TGIA9=157,DTCE_MTU9_TGIB9,DTCE_MTU9_TGIC9,DTCE_MTU9_TGID9, +DTCE_MTU10_TGIA10=162,DTCE_MTU10_TGIB10,DTCE_MTU10_TGIC10,DTCE_MTU10_TGID10,DTCE_MTU10_TCIV10, +DTCE_MTU11_TGIU11,DTCE_MTU11_TGIV11,DTCE_MTU11_TGIW11, +DTCE_TMR0_CMIA0=174,DTCE_TMR0_CMIB0, +DTCE_TMR1_CMIA1=177,DTCE_TMR1_CMIB1, +DTCE_TMR2_CMIA2=180,DTCE_TMR2_CMIB2, +DTCE_TMR3_CMIA3=183,DTCE_TMR3_CMIB3, +DTCE_DMAC_DMAC0I=198,DTCE_DMAC_DMAC1I,DTCE_DMAC_DMAC2I,DTCE_DMAC_DMAC3I, +DTCE_EXDMAC_EXDMAC0I,DTCE_EXDMAC_EXDMAC1I, +DTCE_SCI0_RXI0=215,DTCE_SCI0_TXI0, +DTCE_SCI1_RXI1=219,DTCE_SCI1_TXI1, +DTCE_SCI2_RXI2=223,DTCE_SCI2_TXI2, +DTCE_SCI3_RXI3=227,DTCE_SCI3_TXI3, +DTCE_SCI5_RXI5=235,DTCE_SCI5_TXI5, +DTCE_SCI6_RXI6=239,DTCE_SCI6_TXI6, +DTCE_RIIC0_ICRXI0=247,DTCE_RIIC0_ICTXI0, +DTCE_RIIC1_ICRXI1=251,DTCE_RIIC1_ICTXI1 +}; + +enum enum_ier { +IER_BSC_BUSERR=0x02, +IER_FCU_FIFERR=0x02,IER_FCU_FRDYI=0x02, +IER_ICU_SWINT=0x03, +IER_CMT0_CMI0=0x03, +IER_CMT1_CMI1=0x03, +IER_CMT2_CMI2=0x03, +IER_CMT3_CMI3=0x03, +IER_ETHER_EINT=0x04, +IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04,IER_USB0_USBI0=0x04, +IER_USB1_D0FIFO1=0x05,IER_USB1_D1FIFO1=0x05,IER_USB1_USBI1=0x05, +IER_RSPI0_SPEI0=0x05,IER_RSPI0_SPRI0=0x05,IER_RSPI0_SPTI0=0x05,IER_RSPI0_SPII0=0x05, +IER_RSPI1_SPEI1=0x06,IER_RSPI1_SPRI1=0x06,IER_RSPI1_SPTI1=0x06,IER_RSPI1_SPII1=0x06, +IER_CAN0_ERS0=0x07,IER_CAN0_RXF0=0x07,IER_CAN0_TXF0=0x07,IER_CAN0_RXM0=0x07,IER_CAN0_TXM0=0x07, +IER_RTC_PRD=0x07,IER_RTC_CUP=0x07, +IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08,IER_ICU_IRQ8=0x09,IER_ICU_IRQ9=0x09,IER_ICU_IRQ10=0x09,IER_ICU_IRQ11=0x09,IER_ICU_IRQ12=0x09,IER_ICU_IRQ13=0x09,IER_ICU_IRQ14=0x09,IER_ICU_IRQ15=0x09, +IER_USB_USBR0=0x0B,IER_USB_USBR1=0x0B, +IER_RTC_ALM=0x0B, +IER_WDT_WOVI=0x0C, +IER_AD0_ADI0=0x0C, +IER_AD1_ADI1=0x0C, +IER_S12AD_ADI=0x0C, +IER_MTU0_TGIA0=0x0E,IER_MTU0_TGIB0=0x0E,IER_MTU0_TGIC0=0x0E,IER_MTU0_TGID0=0x0E,IER_MTU0_TCIV0=0x0E,IER_MTU0_TGIE0=0x0E,IER_MTU0_TGIF0=0x0F, +IER_MTU1_TGIA1=0x0F,IER_MTU1_TGIB1=0x0F,IER_MTU1_TCIV1=0x0F,IER_MTU1_TCIU1=0x0F, +IER_MTU2_TGIA2=0x0F,IER_MTU2_TGIB2=0x0F,IER_MTU2_TCIV2=0x0F,IER_MTU2_TCIU2=0x10, +IER_MTU3_TGIA3=0x10,IER_MTU3_TGIB3=0x10,IER_MTU3_TGIC3=0x10,IER_MTU3_TGID3=0x10,IER_MTU3_TCIV3=0x10, +IER_MTU4_TGIA4=0x10,IER_MTU4_TGIB4=0x10,IER_MTU4_TGIC4=0x11,IER_MTU4_TGID4=0x11,IER_MTU4_TCIV4=0x11, +IER_MTU5_TGIU5=0x11,IER_MTU5_TGIV5=0x11,IER_MTU5_TGIW5=0x10, +IER_MTU6_TGIA6=0x11,IER_MTU6_TGIB6=0x11,IER_MTU6_TGIC6=0x12,IER_MTU6_TGID6=0x12,IER_MTU6_TCIV6=0x12,IER_MTU6_TGIE6=0x12,IER_MTU6_TGIF6=0x12, +IER_MTU7_TGIA7=0x12,IER_MTU7_TGIB7=0x12,IER_MTU7_TCIV7=0x12,IER_MTU7_TCIU7=0x13, +IER_MTU8_TGIA8=0x13,IER_MTU8_TGIB8=0x13,IER_MTU8_TCIV8=0x13,IER_MTU8_TCIU8=0x13, +IER_MTU9_TGIA9=0x13,IER_MTU9_TGIB9=0x13,IER_MTU9_TGIC9=0x13,IER_MTU9_TGID9=0x14,IER_MTU9_TCIV9=0x14, +IER_MTU10_TGIA10=0x14,IER_MTU10_TGIB10=0x14,IER_MTU10_TGIC10=0x14,IER_MTU10_TGID10=0x14,IER_MTU10_TCIV10=0x14, +IER_MTU11_TGIU11=0x14,IER_MTU11_TGIV11=0x15,IER_MTU11_TGIW11=0x15, +IER_POE_OEI1=0x15,IER_POE_OEI2=0x15,IER_POE_OEI3=0x15,IER_POE_OEI4=0x15, +IER_TMR0_CMIA0=0x15,IER_TMR0_CMIB0=0x15,IER_TMR0_OVI0=0x16, +IER_TMR1_CMIA1=0x16,IER_TMR1_CMIB1=0x16,IER_TMR1_OVI1=0x16, +IER_TMR2_CMIA2=0x16,IER_TMR2_CMIB2=0x16,IER_TMR2_OVI2=0x16, +IER_TMR3_CMIA3=0x16,IER_TMR3_CMIB3=0x17,IER_TMR3_OVI3=0x17, +IER_DMAC_DMAC0I=0x18,IER_DMAC_DMAC1I=0x18,IER_DMAC_DMAC2I=0x19,IER_DMAC_DMAC3I=0x19, +IER_EXDMAC_EXDMAC0I=0x19,IER_EXDMAC_EXDMAC1I=0x19, +IER_SCI0_ERI0=0x1A,IER_SCI0_RXI0=0x1A,IER_SCI0_TXI0=0x1B,IER_SCI0_TEI0=0x1B, +IER_SCI1_ERI1=0x1B,IER_SCI1_RXI1=0x1B,IER_SCI1_TXI1=0x1B,IER_SCI1_TEI1=0x1B, +IER_SCI2_ERI2=0x1B,IER_SCI2_RXI2=0x1B,IER_SCI2_TXI2=0x1C,IER_SCI2_TEI2=0x1C, +IER_SCI3_ERI3=0x1C,IER_SCI3_RXI3=0x1C,IER_SCI3_TXI3=0x1C,IER_SCI3_TEI3=0x1C, +IER_SCI5_ERI5=0x1D,IER_SCI5_RXI5=0x1D,IER_SCI5_TXI5=0x1D,IER_SCI5_TEI5=0x1D, +IER_SCI6_ERI6=0x1D,IER_SCI6_RXI6=0x1D,IER_SCI6_TXI6=0x1E,IER_SCI6_TEI6=0x1E, +IER_RIIC0_ICEEI0=0x1E,IER_RIIC0_ICRXI0=0x1E,IER_RIIC0_ICTXI0=0x1F,IER_RIIC0_ICTEI0=0x1F, +IER_RIIC1_ICEEI1=0x1F,IER_RIIC1_ICRXI1=0x1F,IER_RIIC1_ICTXI1=0x1F,IER_RIIC1_ICTEI1=0x1F +}; + +enum enum_ipr { +IPR_BSC_BUSERR=0x00, +IPR_FCU_FIFERR=0x01,IPR_FCU_FRDYI=0x02, +IPR_ICU_SWINT=0x03, +IPR_CMT0_CMI0=0x04, +IPR_CMT1_CMI1=0x05, +IPR_CMT2_CMI2=0x06, +IPR_CMT3_CMI3=0x07, +IPR_ETHER_EINT=0x08, +IPR_USB0_D0FIFO0=0x0C,IPR_USB0_D1FIFO0=0x0D,IPR_USB0_USBI0=0x0E, +IPR_USB1_D0FIFO1=0x10,IPR_USB1_D1FIFO1=0x11,IPR_USB1_USBI1=0x12, +IPR_RSPI0_SPEI0=0x14,IPR_RSPI0_SPRI0=0x14,IPR_RSPI0_SPTI0=0x14,IPR_RSPI0_SPII0=0x14, +IPR_RSPI1_SPEI1=0x15,IPR_RSPI1_SPRI1=0x15,IPR_RSPI1_SPTI1=0x15,IPR_RSPI1_SPII1=0x15, +IPR_CAN0_ERS0=0x18,IPR_CAN0_RXF0=0x18,IPR_CAN0_TXF0=0x18,IPR_CAN0_RXM0=0x18,IPR_CAN0_TXM0=0x18, +IPR_RTC_PRD=0x1E,IPR_RTC_CUP=0x1F, +IPR_ICU_IRQ0=0x20,IPR_ICU_IRQ1=0x21,IPR_ICU_IRQ2=0x22,IPR_ICU_IRQ3=0x23,IPR_ICU_IRQ4=0x24,IPR_ICU_IRQ5=0x25,IPR_ICU_IRQ6=0x26,IPR_ICU_IRQ7=0x27,IPR_ICU_IRQ8=0x28,IPR_ICU_IRQ9=0x29,IPR_ICU_IRQ10=0x2A,IPR_ICU_IRQ11=0x2B,IPR_ICU_IRQ12=0x2C,IPR_ICU_IRQ13=0x2D,IPR_ICU_IRQ14=0x2E,IPR_ICU_IRQ15=0x2F, +IPR_USB_USBR0=0x3A,IPR_USB_USBR1=0x3B, +IPR_RTC_ALM=0x3C, +IPR_WDT_WOVI=0x40, +IPR_AD0_ADI0=0x44, +IPR_AD1_ADI1=0x45, +IPR_S12AD_ADI=0x48, +IPR_MTU0_TGIA0=0x51,IPR_MTU0_TGIB0=0x51,IPR_MTU0_TGIC0=0x51,IPR_MTU0_TGID0=0x51,IPR_MTU0_TCIV0=0x52,IPR_MTU0_TGIE0=0x52,IPR_MTU0_TGIF0=0x52, +IPR_MTU1_TGIA1=0x53,IPR_MTU1_TGIB1=0x53,IPR_MTU1_TCIV1=0x54,IPR_MTU1_TCIU1=0x54, +IPR_MTU2_TGIA2=0x55,IPR_MTU2_TGIB2=0x55,IPR_MTU2_TCIV2=0x56,IPR_MTU2_TCIU2=0x56, +IPR_MTU3_TGIA3=0x57,IPR_MTU3_TGIB3=0x57,IPR_MTU3_TGIC3=0x57,IPR_MTU3_TGID3=0x57,IPR_MTU3_TCIV3=0x58, +IPR_MTU4_TGIA4=0x59,IPR_MTU4_TGIB4=0x59,IPR_MTU4_TGIC4=0x59,IPR_MTU4_TGID4=0x59,IPR_MTU4_TCIV4=0x5A, +IPR_MTU5_TGIU5=0x5B,IPR_MTU5_TGIV5=0x5B,IPR_MTU5_TGIW5=0x5B, +IPR_MTU6_TGIA6=0x5C,IPR_MTU6_TGIB6=0x5C,IPR_MTU6_TGIC6=0x5C,IPR_MTU6_TGID6=0x5C,IPR_MTU6_TCIV6=0x5D,IPR_MTU6_TGIE6=0x5D,IPR_MTU6_TGIF6=0x5D, +IPR_MTU7_TGIA7=0x5E,IPR_MTU7_TGIB7=0x5E,IPR_MTU7_TCIV7=0x5F,IPR_MTU7_TCIU7=0x5F, +IPR_MTU8_TGIA8=0x60,IPR_MTU8_TGIB8=0x60,IPR_MTU8_TCIV8=0x61,IPR_MTU8_TCIU8=0x61, +IPR_MTU9_TGIA9=0x62,IPR_MTU9_TGIB9=0x62,IPR_MTU9_TGIC9=0x62,IPR_MTU9_TGID9=0x62,IPR_MTU9_TCIV9=0x63, +IPR_MTU10_TGIA10=0x64,IPR_MTU10_TGIB10=0x64,IPR_MTU10_TGIC10=0x64,IPR_MTU10_TGID10=0x64,IPR_MTU10_TCIV10=0x65, +IPR_MTU11_TGIU11=0x66,IPR_MTU11_TGIV11=0x66,IPR_MTU11_TGIW11=0x66, +IPR_POE_OEI1=0x67,IPR_POE_OEI2=0x67,IPR_POE_OEI3=0x67,IPR_POE_OEI4=0x67, +IPR_TMR0_CMIA0=0x68,IPR_TMR0_CMIB0=0x68,IPR_TMR0_OVI0=0x68, +IPR_TMR1_CMIA1=0x69,IPR_TMR1_CMIB1=0x69,IPR_TMR1_OVI1=0x69, +IPR_TMR2_CMIA2=0x6A,IPR_TMR2_CMIB2=0x6A,IPR_TMR2_OVI2=0x6A, +IPR_TMR3_CMIA3=0x6B,IPR_TMR3_CMIB3=0x6B,IPR_TMR3_OVI3=0x6B, +IPR_DMAC_DMAC0I=0x70,IPR_DMAC_DMAC1I=0x71,IPR_DMAC_DMAC2I=0x72,IPR_DMAC_DMAC3I=0x73, +IPR_EXDMAC_EXDMAC0I=0x74,IPR_EXDMAC_EXDMAC1I=0x75, +IPR_SCI0_ERI0=0x80,IPR_SCI0_RXI0=0x80,IPR_SCI0_TXI0=0x80,IPR_SCI0_TEI0=0x80, +IPR_SCI1_ERI1=0x81,IPR_SCI1_RXI1=0x81,IPR_SCI1_TXI1=0x81,IPR_SCI1_TEI1=0x81, +IPR_SCI2_ERI2=0x82,IPR_SCI2_RXI2=0x82,IPR_SCI2_TXI2=0x82,IPR_SCI2_TEI2=0x82, +IPR_SCI3_ERI3=0x83,IPR_SCI3_RXI3=0x83,IPR_SCI3_TXI3=0x83,IPR_SCI3_TEI3=0x83, +IPR_SCI5_ERI5=0x85,IPR_SCI5_RXI5=0x85,IPR_SCI5_TXI5=0x85,IPR_SCI5_TEI5=0x85, +IPR_SCI6_ERI6=0x86,IPR_SCI6_RXI6=0x86,IPR_SCI6_TXI6=0x86,IPR_SCI6_TEI6=0x86, +IPR_RIIC0_ICEEI0=0x88,IPR_RIIC0_ICRXI0=0x89,IPR_RIIC0_ICTXI0=0x8A,IPR_RIIC0_ICTEI0=0x8B, +IPR_RIIC1_ICEEI1=0x8C,IPR_RIIC1_ICRXI1=0x8D,IPR_RIIC1_ICTXI1=0x8E,IPR_RIIC1_ICTEI1=0x8F, +IPR_BSC_=0x00, +IPR_CMT0_=0x04, +IPR_CMT1_=0x05, +IPR_CMT2_=0x06, +IPR_CMT3_=0x07, +IPR_ETHER_=0x08, +IPR_RSPI0_=0x14, +IPR_RSPI1_=0x15, +IPR_CAN0_=0x18, +IPR_WDT_=0x40, +IPR_AD0_=0x44, +IPR_AD1_=0x45, +IPR_S12AD_=0x48, +IPR_MTU1_TGI=0x53, +IPR_MTU1_TCI=0x54, +IPR_MTU2_TGI=0x55, +IPR_MTU2_TCI=0x56, +IPR_MTU3_TGI=0x57, +IPR_MTU4_TGI=0x59, +IPR_MTU5_=0x5B, +IPR_MTU5_TGI=0x5B, +IPR_MTU7_TGI=0x5E, +IPR_MTU7_TCI=0x5F, +IPR_MTU8_TGI=0x60, +IPR_MTU8_TCI=0x61, +IPR_MTU9_TGI=0x62, +IPR_MTU10_TGI=0x64, +IPR_MTU11_=0x66, +IPR_MTU11_TGI=0x66, +IPR_POE_=0x67, +IPR_POE_OEI=0x67, +IPR_TMR0_=0x68, +IPR_TMR1_=0x69, +IPR_TMR2_=0x6A, +IPR_TMR3_=0x6B, +IPR_SCI0_=0x80, +IPR_SCI1_=0x81, +IPR_SCI2_=0x82, +IPR_SCI3_=0x83, +IPR_SCI5_=0x85, +IPR_SCI6_=0x86 +}; + +#define IEN_BSC_BUSERR IEN0 +#define IEN_FCU_FIFERR IEN5 +#define IEN_FCU_FRDYI IEN7 +#define IEN_ICU_SWINT IEN3 +#define IEN_CMT0_CMI0 IEN4 +#define IEN_CMT1_CMI1 IEN5 +#define IEN_CMT2_CMI2 IEN6 +#define IEN_CMT3_CMI3 IEN7 +#define IEN_ETHER_EINT IEN0 +#define IEN_USB0_D0FIFO0 IEN4 +#define IEN_USB0_D1FIFO0 IEN5 +#define IEN_USB0_USBI0 IEN6 +#define IEN_USB1_D0FIFO1 IEN0 +#define IEN_USB1_D1FIFO1 IEN1 +#define IEN_USB1_USBI1 IEN2 +#define IEN_RSPI0_SPEI0 IEN4 +#define IEN_RSPI0_SPRI0 IEN5 +#define IEN_RSPI0_SPTI0 IEN6 +#define IEN_RSPI0_SPII0 IEN7 +#define IEN_RSPI1_SPEI1 IEN0 +#define IEN_RSPI1_SPRI1 IEN1 +#define IEN_RSPI1_SPTI1 IEN2 +#define IEN_RSPI1_SPII1 IEN3 +#define IEN_CAN0_ERS0 IEN0 +#define IEN_CAN0_RXF0 IEN1 +#define IEN_CAN0_TXF0 IEN2 +#define IEN_CAN0_RXM0 IEN3 +#define IEN_CAN0_TXM0 IEN4 +#define IEN_RTC_PRD IEN6 +#define IEN_RTC_CUP IEN7 +#define IEN_ICU_IRQ0 IEN0 +#define IEN_ICU_IRQ1 IEN1 +#define IEN_ICU_IRQ2 IEN2 +#define IEN_ICU_IRQ3 IEN3 +#define IEN_ICU_IRQ4 IEN4 +#define IEN_ICU_IRQ5 IEN5 +#define IEN_ICU_IRQ6 IEN6 +#define IEN_ICU_IRQ7 IEN7 +#define IEN_ICU_IRQ8 IEN0 +#define IEN_ICU_IRQ9 IEN1 +#define IEN_ICU_IRQ10 IEN2 +#define IEN_ICU_IRQ11 IEN3 +#define IEN_ICU_IRQ12 IEN4 +#define IEN_ICU_IRQ13 IEN5 +#define IEN_ICU_IRQ14 IEN6 +#define IEN_ICU_IRQ15 IEN7 +#define IEN_USB_USBR0 IEN2 +#define IEN_USB_USBR1 IEN3 +#define IEN_RTC_ALM IEN4 +#define IEN_WDT_WOVI IEN0 +#define IEN_AD0_ADI0 IEN2 +#define IEN_AD1_ADI1 IEN3 +#define IEN_S12AD_ADI IEN6 +#define IEN_MTU0_TGIA0 IEN2 +#define IEN_MTU0_TGIB0 IEN3 +#define IEN_MTU0_TGIC0 IEN4 +#define IEN_MTU0_TGID0 IEN5 +#define IEN_MTU0_TCIV0 IEN6 +#define IEN_MTU0_TGIE0 IEN7 +#define IEN_MTU0_TGIF0 IEN0 +#define IEN_MTU1_TGIA1 IEN1 +#define IEN_MTU1_TGIB1 IEN2 +#define IEN_MTU1_TCIV1 IEN3 +#define IEN_MTU1_TCIU1 IEN4 +#define IEN_MTU2_TGIA2 IEN5 +#define IEN_MTU2_TGIB2 IEN6 +#define IEN_MTU2_TCIV2 IEN7 +#define IEN_MTU2_TCIU2 IEN0 +#define IEN_MTU3_TGIA3 IEN1 +#define IEN_MTU3_TGIB3 IEN2 +#define IEN_MTU3_TGIC3 IEN3 +#define IEN_MTU3_TGID3 IEN4 +#define IEN_MTU3_TCIV3 IEN5 +#define IEN_MTU4_TGIA4 IEN6 +#define IEN_MTU4_TGIB4 IEN7 +#define IEN_MTU4_TGIC4 IEN0 +#define IEN_MTU4_TGID4 IEN1 +#define IEN_MTU4_TCIV4 IEN2 +#define IEN_MTU5_TGIU5 IEN3 +#define IEN_MTU5_TGIV5 IEN4 +#define IEN_MTU5_TGIW5 IEN7 +#define IEN_MTU6_TGIA6 IEN6 +#define IEN_MTU6_TGIB6 IEN7 +#define IEN_MTU6_TGIC6 IEN0 +#define IEN_MTU6_TGID6 IEN1 +#define IEN_MTU6_TCIV6 IEN2 +#define IEN_MTU6_TGIE6 IEN3 +#define IEN_MTU6_TGIF6 IEN4 +#define IEN_MTU7_TGIA7 IEN5 +#define IEN_MTU7_TGIB7 IEN6 +#define IEN_MTU7_TCIV7 IEN7 +#define IEN_MTU7_TCIU7 IEN0 +#define IEN_MTU8_TGIA8 IEN1 +#define IEN_MTU8_TGIB8 IEN2 +#define IEN_MTU8_TCIV8 IEN3 +#define IEN_MTU8_TCIU8 IEN4 +#define IEN_MTU9_TGIA9 IEN5 +#define IEN_MTU9_TGIB9 IEN6 +#define IEN_MTU9_TGIC9 IEN7 +#define IEN_MTU9_TGID9 IEN0 +#define IEN_MTU9_TCIV9 IEN1 +#define IEN_MTU10_TGIA10 IEN2 +#define IEN_MTU10_TGIB10 IEN3 +#define IEN_MTU10_TGIC10 IEN4 +#define IEN_MTU10_TGID10 IEN5 +#define IEN_MTU10_TCIV10 IEN6 +#define IEN_MTU11_TGIU11 IEN7 +#define IEN_MTU11_TGIV11 IEN0 +#define IEN_MTU11_TGIW11 IEN1 +#define IEN_POE_OEI1 IEN2 +#define IEN_POE_OEI2 IEN3 +#define IEN_POE_OEI3 IEN4 +#define IEN_POE_OEI4 IEN5 +#define IEN_TMR0_CMIA0 IEN6 +#define IEN_TMR0_CMIB0 IEN7 +#define IEN_TMR0_OVI0 IEN0 +#define IEN_TMR1_CMIA1 IEN1 +#define IEN_TMR1_CMIB1 IEN2 +#define IEN_TMR1_OVI1 IEN3 +#define IEN_TMR2_CMIA2 IEN4 +#define IEN_TMR2_CMIB2 IEN5 +#define IEN_TMR2_OVI2 IEN6 +#define IEN_TMR3_CMIA3 IEN7 +#define IEN_TMR3_CMIB3 IEN0 +#define IEN_TMR3_OVI3 IEN1 +#define IEN_DMAC_DMAC0I IEN6 +#define IEN_DMAC_DMAC1I IEN7 +#define IEN_DMAC_DMAC2I IEN0 +#define IEN_DMAC_DMAC3I IEN1 +#define IEN_EXDMAC_EXDMAC0I IEN2 +#define IEN_EXDMAC_EXDMAC1I IEN3 +#define IEN_SCI0_ERI0 IEN6 +#define IEN_SCI0_RXI0 IEN7 +#define IEN_SCI0_TXI0 IEN0 +#define IEN_SCI0_TEI0 IEN1 +#define IEN_SCI1_ERI1 IEN2 +#define IEN_SCI1_RXI1 IEN3 +#define IEN_SCI1_TXI1 IEN4 +#define IEN_SCI1_TEI1 IEN5 +#define IEN_SCI2_ERI2 IEN6 +#define IEN_SCI2_RXI2 IEN7 +#define IEN_SCI2_TXI2 IEN0 +#define IEN_SCI2_TEI2 IEN1 +#define IEN_SCI3_ERI3 IEN2 +#define IEN_SCI3_RXI3 IEN3 +#define IEN_SCI3_TXI3 IEN4 +#define IEN_SCI3_TEI3 IEN5 +#define IEN_SCI5_ERI5 IEN2 +#define IEN_SCI5_RXI5 IEN3 +#define IEN_SCI5_TXI5 IEN4 +#define IEN_SCI5_TEI5 IEN5 +#define IEN_SCI6_ERI6 IEN6 +#define IEN_SCI6_RXI6 IEN7 +#define IEN_SCI6_TXI6 IEN0 +#define IEN_SCI6_TEI6 IEN1 +#define IEN_RIIC0_ICEEI0 IEN6 +#define IEN_RIIC0_ICRXI0 IEN7 +#define IEN_RIIC0_ICTXI0 IEN0 +#define IEN_RIIC0_ICTEI0 IEN1 +#define IEN_RIIC1_ICEEI1 IEN2 +#define IEN_RIIC1_ICRXI1 IEN3 +#define IEN_RIIC1_ICTXI1 IEN4 +#define IEN_RIIC1_ICTEI1 IEN5 + +#define VECT_BSC_BUSERR 16 +#define VECT_FCU_FIFERR 21 +#define VECT_FCU_FRDYI 23 +#define VECT_ICU_SWINT 27 +#define VECT_CMT0_CMI0 28 +#define VECT_CMT1_CMI1 29 +#define VECT_CMT2_CMI2 30 +#define VECT_CMT3_CMI3 31 +#define VECT_ETHER_EINT 32 +#define VECT_USB0_D0FIFO0 36 +#define VECT_USB0_D1FIFO0 37 +#define VECT_USB0_USBI0 38 +#define VECT_USB1_D0FIFO1 40 +#define VECT_USB1_D1FIFO1 41 +#define VECT_USB1_USBI1 42 +#define VECT_RSPI0_SPEI0 44 +#define VECT_RSPI0_SPRI0 45 +#define VECT_RSPI0_SPTI0 46 +#define VECT_RSPI0_SPII0 47 +#define VECT_RSPI1_SPEI1 48 +#define VECT_RSPI1_SPRI1 49 +#define VECT_RSPI1_SPTI1 50 +#define VECT_RSPI1_SPII1 51 +#define VECT_CAN0_ERS0 56 +#define VECT_CAN0_RXF0 57 +#define VECT_CAN0_TXF0 58 +#define VECT_CAN0_RXM0 59 +#define VECT_CAN0_TXM0 60 +#define VECT_RTC_PRD 62 +#define VECT_RTC_CUP 63 +#define VECT_ICU_IRQ0 64 +#define VECT_ICU_IRQ1 65 +#define VECT_ICU_IRQ2 66 +#define VECT_ICU_IRQ3 67 +#define VECT_ICU_IRQ4 68 +#define VECT_ICU_IRQ5 69 +#define VECT_ICU_IRQ6 70 +#define VECT_ICU_IRQ7 71 +#define VECT_ICU_IRQ8 72 +#define VECT_ICU_IRQ9 73 +#define VECT_ICU_IRQ10 74 +#define VECT_ICU_IRQ11 75 +#define VECT_ICU_IRQ12 76 +#define VECT_ICU_IRQ13 77 +#define VECT_ICU_IRQ14 78 +#define VECT_ICU_IRQ15 79 +#define VECT_USB_USBR0 90 +#define VECT_USB_USBR1 91 +#define VECT_RTC_ALM 92 +#define VECT_WDT_WOVI 96 +#define VECT_AD0_ADI0 98 +#define VECT_AD1_ADI1 99 +#define VECT_S12AD_ADI 102 +#define VECT_MTU0_TGIA0 114 +#define VECT_MTU0_TGIB0 115 +#define VECT_MTU0_TGIC0 116 +#define VECT_MTU0_TGID0 117 +#define VECT_MTU0_TCIV0 118 +#define VECT_MTU0_TGIE0 119 +#define VECT_MTU0_TGIF0 120 +#define VECT_MTU1_TGIA1 121 +#define VECT_MTU1_TGIB1 122 +#define VECT_MTU1_TCIV1 123 +#define VECT_MTU1_TCIU1 124 +#define VECT_MTU2_TGIA2 125 +#define VECT_MTU2_TGIB2 126 +#define VECT_MTU2_TCIV2 127 +#define VECT_MTU2_TCIU2 128 +#define VECT_MTU3_TGIA3 129 +#define VECT_MTU3_TGIB3 130 +#define VECT_MTU3_TGIC3 131 +#define VECT_MTU3_TGID3 132 +#define VECT_MTU3_TCIV3 133 +#define VECT_MTU4_TGIA4 134 +#define VECT_MTU4_TGIB4 135 +#define VECT_MTU4_TGIC4 136 +#define VECT_MTU4_TGID4 137 +#define VECT_MTU4_TCIV4 138 +#define VECT_MTU5_TGIU5 139 +#define VECT_MTU5_TGIV5 140 +#define VECT_MTU5_TGIW5 141 +#define VECT_MTU6_TGIA6 142 +#define VECT_MTU6_TGIB6 143 +#define VECT_MTU6_TGIC6 144 +#define VECT_MTU6_TGID6 145 +#define VECT_MTU6_TCIV6 146 +#define VECT_MTU6_TGIE6 147 +#define VECT_MTU6_TGIF6 148 +#define VECT_MTU7_TGIA7 149 +#define VECT_MTU7_TGIB7 150 +#define VECT_MTU7_TCIV7 151 +#define VECT_MTU7_TCIU7 152 +#define VECT_MTU8_TGIA8 153 +#define VECT_MTU8_TGIB8 154 +#define VECT_MTU8_TCIV8 155 +#define VECT_MTU8_TCIU8 156 +#define VECT_MTU9_TGIA9 157 +#define VECT_MTU9_TGIB9 158 +#define VECT_MTU9_TGIC9 159 +#define VECT_MTU9_TGID9 160 +#define VECT_MTU9_TCIV9 161 +#define VECT_MTU10_TGIA10 162 +#define VECT_MTU10_TGIB10 163 +#define VECT_MTU10_TGIC10 164 +#define VECT_MTU10_TGID10 165 +#define VECT_MTU10_TCIV10 166 +#define VECT_MTU11_TGIU11 167 +#define VECT_MTU11_TGIV11 168 +#define VECT_MTU11_TGIW11 169 +#define VECT_POE_OEI1 170 +#define VECT_POE_OEI2 171 +#define VECT_POE_OEI3 172 +#define VECT_POE_OEI4 173 +#define VECT_TMR0_CMIA0 174 +#define VECT_TMR0_CMIB0 175 +#define VECT_TMR0_OVI0 176 +#define VECT_TMR1_CMIA1 177 +#define VECT_TMR1_CMIB1 178 +#define VECT_TMR1_OVI1 179 +#define VECT_TMR2_CMIA2 180 +#define VECT_TMR2_CMIB2 181 +#define VECT_TMR2_OVI2 182 +#define VECT_TMR3_CMIA3 183 +#define VECT_TMR3_CMIB3 184 +#define VECT_TMR3_OVI3 185 +#define VECT_DMAC_DMAC0I 198 +#define VECT_DMAC_DMAC1I 199 +#define VECT_DMAC_DMAC2I 200 +#define VECT_DMAC_DMAC3I 201 +#define VECT_EXDMAC_EXDMAC0I 202 +#define VECT_EXDMAC_EXDMAC1I 203 +#define VECT_SCI0_ERI0 214 +#define VECT_SCI0_RXI0 215 +#define VECT_SCI0_TXI0 216 +#define VECT_SCI0_TEI0 217 +#define VECT_SCI1_ERI1 218 +#define VECT_SCI1_RXI1 219 +#define VECT_SCI1_TXI1 220 +#define VECT_SCI1_TEI1 221 +#define VECT_SCI2_ERI2 222 +#define VECT_SCI2_RXI2 223 +#define VECT_SCI2_TXI2 224 +#define VECT_SCI2_TEI2 225 +#define VECT_SCI3_ERI3 226 +#define VECT_SCI3_RXI3 227 +#define VECT_SCI3_TXI3 228 +#define VECT_SCI3_TEI3 229 +#define VECT_SCI5_ERI5 234 +#define VECT_SCI5_RXI5 235 +#define VECT_SCI5_TXI5 236 +#define VECT_SCI5_TEI5 237 +#define VECT_SCI6_ERI6 238 +#define VECT_SCI6_RXI6 239 +#define VECT_SCI6_TXI6 240 +#define VECT_SCI6_TEI6 241 +#define VECT_RIIC0_ICEEI0 246 +#define VECT_RIIC0_ICRXI0 247 +#define VECT_RIIC0_ICTXI0 248 +#define VECT_RIIC0_ICTEI0 249 +#define VECT_RIIC1_ICEEI1 250 +#define VECT_RIIC1_ICRXI1 251 +#define VECT_RIIC1_ICTXI1 252 +#define VECT_RIIC1_ICTEI1 253 + +#define MSTP_EXDMAC SYSTEM.MSTPCRA.BIT.MSTPA29 +#define MSTP_DMAC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC0 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC1 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC2 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC3 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_AD0 SYSTEM.MSTPCRA.BIT.MSTPA23 +#define MSTP_AD1 SYSTEM.MSTPCRA.BIT.MSTPA22 +#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19 +#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17 +#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_CMT3 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_PPG0 SYSTEM.MSTPCRA.BIT.MSTPA11 +#define MSTP_PPG1 SYSTEM.MSTPCRA.BIT.MSTPA10 +#define MSTP_MTUA SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTUB SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_MTU6 SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_MTU7 SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_MTU8 SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_MTU9 SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_MTU10 SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_MTU11 SYSTEM.MSTPCRA.BIT.MSTPA8 +#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_SCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SMCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SMCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SCI3 SYSTEM.MSTPCRB.BIT.MSTPB28 +#define MSTP_SMCI3 SYSTEM.MSTPCRB.BIT.MSTPB28 +#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23 +#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21 +#define MSTP_RIIC1 SYSTEM.MSTPCRB.BIT.MSTPB20 +#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19 +#define MSTP_USB1 SYSTEM.MSTPCRB.BIT.MSTPB18 +#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17 +#define MSTP_RSPI1 SYSTEM.MSTPCRB.BIT.MSTPB16 +#define MSTP_EDMAC SYSTEM.MSTPCRB.BIT.MSTPB15 +#define MSTP_CAN0 SYSTEM.MSTPCRB.BIT.MSTPB0 +#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC1 +#define MSTP_RAM1 SYSTEM.MSTPCRC.BIT.MSTPC0 + +#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR +#define _IR( x ) __IR( x ) +#define IR( x , y ) _IR( _ ## x ## _ ## y ) +#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE +#define _DTCE( x ) __DTCE( x ) +#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y ) +#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x +#define _IEN( x ) __IEN( x ) +#define IEN( x , y ) _IEN( _ ## x ## _ ## y ) +#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR +#define _IPR( x ) __IPR( x ) +#define IPR( x , y ) _IPR( _ ## x ## _ ## y ) +#define __VECT( x ) VECT ## x +#define _VECT( x ) __VECT( x ) +#define VECT( x , y ) _VECT( _ ## x ## _ ## y ) +#define __MSTP( x ) MSTP ## x +#define _MSTP( x ) __MSTP( x ) +#define MSTP( x ) _MSTP( _ ## x ) + +#define AD0 (*(volatile struct st_ad *)0x88040) +#define AD1 (*(volatile struct st_ad *)0x88060) +#define BSC (*(volatile struct st_bsc *)0x81300) +#define CAN0 (*(volatile struct st_can *)0x90200) +#define CMT (*(volatile struct st_cmt *)0x88000) +#define CMT0 (*(volatile struct st_cmt0 *)0x88002) +#define CMT1 (*(volatile struct st_cmt0 *)0x88008) +#define CMT2 (*(volatile struct st_cmt0 *)0x88012) +#define CMT3 (*(volatile struct st_cmt0 *)0x88018) +#define CRC (*(volatile struct st_crc *)0x88280) +#define DA (*(volatile struct st_da *)0x880C0) +#define DMAC (*(volatile struct st_dmac *)0x82200) +#define DMAC0 (*(volatile struct st_dmac0 *)0x82000) +#define DMAC1 (*(volatile struct st_dmac1 *)0x82040) +#define DMAC2 (*(volatile struct st_dmac1 *)0x82080) +#define DMAC3 (*(volatile struct st_dmac1 *)0x820C0) +#define DTC (*(volatile struct st_dtc *)0x82400) +#define EDMAC (*(volatile struct st_edmac *)0xC0000) +#define ETHERC (*(volatile struct st_etherc *)0xC0100) +#define EXDMAC (*(volatile struct st_exdmac *)0x82A00) +#define EXDMAC0 (*(volatile struct st_exdmac0 *)0x82800) +#define EXDMAC1 (*(volatile struct st_exdmac1 *)0x82840) +#define FLASH (*(volatile struct st_flash *)0x8C288) +#define ICU (*(volatile struct st_icu *)0x87000) +#define IOPORT (*(volatile struct st_ioport *)0x8C100) +#define IWDT (*(volatile struct st_iwdt *)0x88030) +#define MTU0 (*(volatile struct st_mtu0 *)0x88700) +#define MTU1 (*(volatile struct st_mtu1 *)0x88780) +#define MTU2 (*(volatile struct st_mtu2 *)0x88800) +#define MTU3 (*(volatile struct st_mtu3 *)0x88600) +#define MTU4 (*(volatile struct st_mtu4 *)0x88600) +#define MTU5 (*(volatile struct st_mtu5 *)0x88880) +#define MTU6 (*(volatile struct st_mtu0 *)0x88B00) +#define MTU7 (*(volatile struct st_mtu1 *)0x88B80) +#define MTU8 (*(volatile struct st_mtu2 *)0x88C00) +#define MTU9 (*(volatile struct st_mtu3 *)0x88A00) +#define MTU10 (*(volatile struct st_mtu4 *)0x88A00) +#define MTU11 (*(volatile struct st_mtu5 *)0x88C80) +#define MTUA (*(volatile struct st_mtua *)0x8860A) +#define MTUB (*(volatile struct st_mtua *)0x88A0A) +#define POE (*(volatile struct st_poe *)0x88900) +#define PORT0 (*(volatile struct st_port0 *)0x8C000) +#define PORT1 (*(volatile struct st_port1 *)0x8C001) +#define PORT2 (*(volatile struct st_port2 *)0x8C002) +#define PORT3 (*(volatile struct st_port3 *)0x8C003) +#define PORT4 (*(volatile struct st_port4 *)0x8C004) +#define PORT5 (*(volatile struct st_port5 *)0x8C005) +#define PORT6 (*(volatile struct st_port6 *)0x8C006) +#define PORT7 (*(volatile struct st_port7 *)0x8C007) +#define PORT8 (*(volatile struct st_port8 *)0x8C008) +#define PORT9 (*(volatile struct st_port9 *)0x8C009) +#define PORTA (*(volatile struct st_porta *)0x8C00A) +#define PORTB (*(volatile struct st_portb *)0x8C00B) +#define PORTC (*(volatile struct st_portc *)0x8C00C) +#define PORTD (*(volatile struct st_portd *)0x8C00D) +#define PORTE (*(volatile struct st_porte *)0x8C00E) +#define PORTF (*(volatile struct st_portf *)0x8C00F) +#define PORTG (*(volatile struct st_portg *)0x8C010) +#define PPG0 (*(volatile struct st_ppg0 *)0x881E6) +#define PPG1 (*(volatile struct st_ppg1 *)0x881F0) +#define RIIC0 (*(volatile struct st_riic *)0x88300) +#define RIIC1 (*(volatile struct st_riic *)0x88320) +#define RSPI0 (*(volatile struct st_rspi *)0x88380) +#define RSPI1 (*(volatile struct st_rspi *)0x883A0) +#define RTC (*(volatile struct st_rtc *)0x8C400) +#define S12AD (*(volatile struct st_s12ad *)0x89000) +#define SCI0 (*(volatile struct st_sci *)0x88240) +#define SCI1 (*(volatile struct st_sci *)0x88248) +#define SCI2 (*(volatile struct st_sci *)0x88250) +#define SCI3 (*(volatile struct st_sci *)0x88258) +#define SCI5 (*(volatile struct st_sci *)0x88268) +#define SCI6 (*(volatile struct st_sci *)0x88270) +#define SMCI0 (*(volatile struct st_smci *)0x88240) +#define SMCI1 (*(volatile struct st_smci *)0x88248) +#define SMCI2 (*(volatile struct st_smci *)0x88250) +#define SMCI3 (*(volatile struct st_smci *)0x88258) +#define SMCI5 (*(volatile struct st_smci *)0x88268) +#define SMCI6 (*(volatile struct st_smci *)0x88270) +#define SYSTEM (*(volatile struct st_system *)0x80000) +#define TMR0 (*(volatile struct st_tmr0 *)0x88200) +#define TMR1 (*(volatile struct st_tmr1 *)0x88201) +#define TMR2 (*(volatile struct st_tmr0 *)0x88210) +#define TMR3 (*(volatile struct st_tmr1 *)0x88211) +#define TMR01 (*(volatile struct st_tmr01 *)0x88204) +#define TMR23 (*(volatile struct st_tmr01 *)0x88214) +#define USB (*(volatile struct st_usb *)0xA0400) +#define USB0 (*(volatile struct st_usb0 *)0xA0000) +#define USB1 (*(volatile struct st_usb0 *)0xA0200) +#define WDT (*(volatile union un_wdt *)0x88028) +#endif + diff --git a/os/hal/platforms/Rx62n/mac_lld.c b/os/hal/platforms/Rx62n/mac_lld.c new file mode 100644 index 000000000..23788244d --- /dev/null +++ b/os/hal/platforms/Rx62n/mac_lld.c @@ -0,0 +1,667 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RX62N/mac_lld.c + * @brief RX62N low level MAC driver code. + * + * @addtogroup MAC + * @{ + */ + +#include + +#include "ch.h" +#include "hal.h" +#include "mii.h" +#include "rx62n_mii.h" + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief Ethernet driver 1. + */ +MACDriver ETHD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +static const uint8_t default_mac_address[] = {0xAA, 0x55, 0x13, + 0x37, 0x01, 0x10}; + +__attribute__((aligned(16))) +static rx62n_eth_rx_descriptor_t rd[EDMAC_RECEIVE_DESCRIPTORS]; +__attribute__((aligned(16))) +static rx62n_eth_tx_descriptor_t td[EDMAC_TRANSMIT_DESCRIPTORS]; + +__attribute__((aligned(32))) +static uint8_t rb[EDMAC_RECEIVE_DESCRIPTORS * EDMAC_RECEIVE_BUFFERS_SIZE]; +__attribute__((aligned(32))) +static uint8_t tb[EDMAC_TRANSMIT_DESCRIPTORS * EDMAC_TRANSMIT_BUFFERS_SIZE]; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +#if !defined(BOARD_PHY_ADDRESS) +/** + * @brief PHY address detection. + * + * @param[in] macp pointer to the @p MACDriver object + */ +static void mii_find_phy(MACDriver *macp) { + uint32_t i; +#if RX62N_MAC_PHY_TIMEOUT > 0 + halrtcnt_t start = halGetCounterValue(); + halrtcnt_t timeout = start + MS2RTT(RX62N_MAC_PHY_TIMEOUT); + while (halIsCounterWithin(start, timeout)) { +#endif + for (i = 0; i < 31; i++) { + if ((miiGet(macp, MII_PHYSID1) == (BOARD_PHY_ID >> 16)) && + ((miiGet(macp, MII_PHYSID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) { + return; + } + } +#if RX62N_MAC_PHY_TIMEOUT > 0 + } +#endif + /* Wrong or defective board.*/ + chSysHalt(); +} +#endif + +/** + * @brief MAC address setup. + * + * @param[in] p pointer to a six bytes buffer containing the MAC + * address + */ +static void mac_lld_set_address(const uint8_t *p) { + + /* MAC address configuration, only a single address comparator is used, + hash table not used.*/ + ETHERC.MAHR = ((uint32_t)p[0] << 24) | + ((uint32_t)p[1] << 16) | + ((uint32_t)p[2] << 8) | + ((uint32_t)p[3] << 0); + ETHERC.MALR.LONG = ((uint32_t)p[4] << 8) | + ((uint32_t)p[5] << 0); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +static void serve_interrupt_ether1(void) { + uint32_t eesr = EDMAC.EESR.LONG; + + if (eesr & (1<<18)) { + /* Frame received.*/ + chSysLockFromIsr(); + chSemResetI(ÐD1.rdsem, 0); +#if MAC_USE_EVENTS + chEvtBroadcastI(ÐD1.rdevent); +#endif + chSysUnlockFromIsr(); + } + if (eesr & (1<<21)) { + /* Frame transmitted.*/ + chSysLockFromIsr(); + chSemResetI(ÐD1.tdsem, 0); + chSysUnlockFromIsr(); + } + EDMAC.EESR.LONG = 0x47FF0F9F; +} + +CH_IRQ_HANDLER(Excep_ETHER_EINT) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt_ether1(); + + CH_IRQ_EPILOGUE(); +} + + + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level MAC initialization. + * + * @notapi + */ +void mac_lld_init(void) { + + macObjectInit(ÐD1); + ETHD1.link_up = FALSE; + + /* Selection of the RMII or MII mode based on info exported by board.h.*/ +#if defined(BOARD_PHY_RMII) + IOPORT.PFENET.BYTE = (1<<7)|(0<<4)|(1<<1); +#else + IOPORT.PFENET.BYTE = (1<<7)|(1<<4)|(1<<1); +#endif + + /* MAC clocks temporary activation.*/ + MSTP(EDMAC) = 0; + + /* Reset of the MAC core.*/ + EDMAC.EDMR.BIT.SWR = 1; + /* TODO: wait 64 cycles, here is 1ms delay */ + asm volatile ("mov.l #24000,r2 \n\t" + "1: \n\t" + "sub #1,r2 \n\t" + "bne.b 1b \n\t"); + EDMAC.EDMR.BIT.DE = 1; + /* Clear registers not affected by reset */ + EDMAC.RMFCR.LONG = 0; + EDMAC.TFUCR.LONG = 0; + EDMAC.RFOCR.LONG = 0; + + /* PHY address setup.*/ +#if defined(BOARD_PHY_ADDRESS) + ETHD1.phyaddr = BOARD_PHY_ADDRESS; +#else + mii_find_phy(ÐD1); +#endif + +#if defined(BOARD_PHY_RESET) + /* PHY board-specific reset procedure.*/ + BOARD_PHY_RESET(); +#else + /* PHY soft reset procedure.*/ + miiPut(ÐD1, MII_BMCR, BMCR_RESET); +#if defined(BOARD_PHY_RESET_DELAY) + halPolledDelay(BOARD_PHY_RESET_DELAY); +#endif + while (miiGet(ÐD1, MII_BMCR) & BMCR_RESET) + ; +#endif + +#if RX62N_MAC_ETH1_CHANGE_PHY_STATE + /* PHY in power down mode until the driver will be started.*/ + miiPut(ÐD1, MII_BMCR, miiGet(ÐD1, MII_BMCR) | BMCR_PDOWN); +#endif + + /* MAC clocks stopped again.*/ + MSTP(EDMAC) = 1; +} + +/** + * @brief Configures and activates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @notapi + */ +void mac_lld_start(MACDriver *macp) { + unsigned i; + + /* Resets the state of all descriptors.*/ + for (i = 0; i < EDMAC_RECEIVE_DESCRIPTORS; i++) { + rd[i].rd0 = /*RX62N_RD0_RFP_ONE|*/RX62N_RD0_RACT; + rd[i].rd1 = EDMAC_RECEIVE_BUFFERS_SIZE<<16; + rd[i].rd2 = (uint32_t)&rb[i * EDMAC_RECEIVE_BUFFERS_SIZE]; + } + rd[i-1].rd0 |= RX62N_RD0_RDLE; + macp->rxptr = (rx62n_eth_rx_descriptor_t *)rd; + for (i = 0; i < EDMAC_TRANSMIT_DESCRIPTORS; i++) { + td[i].td0 = RX62N_TD0_TFP_ONE; + td[i].td1 = EDMAC_TRANSMIT_BUFFERS_SIZE<<16; + td[i].td2 = (uint32_t)&tb[i * EDMAC_TRANSMIT_BUFFERS_SIZE]; + } + td[i-1].td0 |= RX62N_TD0_TDLE; + macp->txptr = (rx62n_eth_tx_descriptor_t *)td; + + /* MAC clocks activation.*/ + MSTP(EDMAC) = 0; + +#if RX62N_MAC_ETH1_CHANGE_PHY_STATE + /* PHY in power up mode.*/ + miiPut(macp, MII_BMCR, miiGet(macp, MII_BMCR) & ~BMCR_PDOWN); +#endif + + /* MAC configuration.*/ + ETHERC.RFLR.LONG = RX62N_MAC_BUFFERS_SIZE; + /* Clear all status flags.*/ + ETHERC.ECSR.LONG = 0x37; + ETHERC.ECSIPR.LONG = 0; + ETHERC.IPGR.LONG = 0x14; /* Initial value.*/ + + /* MAC address setup.*/ + if (macp->config->mac_address == NULL) + mac_lld_set_address(default_mac_address); + else + mac_lld_set_address(macp->config->mac_address); + + /* Transmitter and receiver enabled. + Note that the complete setup of the MAC is performed when the link + status is detected.*/ + ETHERC.ECMR.LONG |= (ETHERC_ECMR_RE | ETHERC_ECMR_TE); + + /* ISR vector enabled.*/ + IEN(ETHER,EINT) = 1; + IPR(ETHER,EINT) = RX62N_MAC_ETH1_IRQ_PRIORITY; + + /* DMA configuration: + Descriptor list pointers.*/ + EDMAC.RDLAR = (void *)rd; + EDMAC.TDLAR = (void *)td; + + /* Clear all status flags.*/ + EDMAC.EESR.LONG = 0x47FF0F9F; + EDMAC.TFTR.LONG = 0; + /* Set FIFO size to 2048.*/ + EDMAC.FDR.LONG = 0x707; + EDMAC.RMCR.LONG = 1; + EDMAC.RPADIR.LONG = 0; + + EDMAC.EESIPR.LONG = (1<<21)|(1<<18); + + EDMAC.EDRRR.BIT.RR = 1; +} + +/** + * @brief Deactivates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @notapi + */ +void mac_lld_stop(MACDriver *macp) { + + if (macp->state != MAC_STOP) { +#if RX62N_MAC_ETH1_CHANGE_PHY_STATE + /* PHY in power down mode until the driver will be restarted.*/ + miiPut(macp, MII_BMCR, miiGet(macp, MII_BMCR) | BMCR_PDOWN); +#endif + + /* MAC and DMA stopped.*/ + ETHERC.ECMR.LONG = 0; + + /* MAC clocks stopped.*/ + MSTP(EDMAC) = 1; + + /* ISR vector disabled.*/ + IEN(ETHER,EINT) = 0; + } +} + +/** + * @brief Returns a transmission descriptor. + * @details One of the available transmission descriptors is locked and + * returned. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[out] tdp pointer to a @p MACTransmitDescriptor structure + * @return The operation status. + * @retval RDY_OK the descriptor has been obtained. + * @retval RDY_TIMEOUT descriptor not available. + * + * @notapi + */ +msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, + MACTransmitDescriptor *tdp) { + rx62n_eth_tx_descriptor_t *tdes; + + if (!macp->link_up) + return RDY_TIMEOUT; + + chSysLock(); + + /* Get Current TX descriptor.*/ + tdes = macp->txptr; + + /* Ensure that descriptor isn't owned by the Ethernet DMA or locked by + another thread.*/ + if ( (tdes->td0 & RX62N_TD0_TACT) || (tdes->td0 & RX62N_TD0_TLOCKED) ) { + chSysUnlock(); + return RDY_TIMEOUT; + } + + /* Marks the current descriptor as locked using a reserved bit.*/ + tdes->td0 |= RX62N_TD0_TLOCKED; + + /* Next TX descriptor to use.*/ + if (++macp->txptr >= &td[RX62N_MAC_TRANSMIT_BUFFERS]) { + macp->txptr = &td[0]; + } + + chSysUnlock(); + + /* Set the buffer size and configuration.*/ + tdp->offset = 0; + tdp->size = RX62N_MAC_BUFFERS_SIZE; + tdp->physdesc = tdes; + + return RDY_OK; +} + +/** + * @brief Releases a transmit descriptor and starts the transmission of the + * enqueued data as a single frame. + * + * @param[in] tdp the pointer to the @p MACTransmitDescriptor structure + * + * @notapi + */ +void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) { + + chSysLock(); + + /* Unlocks the descriptor and returns it to the DMA engine.*/ + tdp->physdesc->td1 = tdp->offset<<16; + tdp->physdesc->td0 &= ~RX62N_TD0_TLOCKED; + tdp->physdesc->td0 |= RX62N_TD0_TACT; + if (EDMAC.EDTRR.BIT.TR == 0) + EDMAC.EDTRR.BIT.TR = 1; + + chSysUnlock(); +} + +/** + * @brief Cleans an incomplete frame. + * + * @param[in] from the start position of the incomplete frame + */ +static void cleanup(MACDriver *macp, rx62n_eth_rx_descriptor_t *from) { + + while (from != macp->rxptr) { + from->rd0 = (from->rd0 & RX62N_RD0_RDLE) | RX62N_RD0_RACT; + if (++from >= &rd[EDMAC_RECEIVE_DESCRIPTORS]) + from = rd; + } +} + +/** + * @brief Returns a receive descriptor. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[out] rdp pointer to a @p MACReceiveDescriptor structure + * @return The operation status. + * @retval RDY_OK the descriptor has been obtained. + * @retval RDY_TIMEOUT descriptor not available. + * + * @notapi + */ +msg_t mac_lld_get_receive_descriptor(MACDriver *macp, + MACReceiveDescriptor *rdp) { + + unsigned n; + rx62n_eth_rx_descriptor_t *edp; + n = EDMAC_RECEIVE_DESCRIPTORS; + chSysLock(); + + /* + * Skips active buffers, if any. + */ +skip: + while ((n > 0) && (macp->rxptr->rd0 & RX62N_RD0_RACT)) { + if (++macp->rxptr >= &rd[EDMAC_RECEIVE_DESCRIPTORS]) + macp->rxptr = rd; + n--; + } +#if 0 + /* + * Skips fragments, if any, cleaning them up. + */ + while ((n > 0) && !(macp->rxptr->rd0 & RX62N_RD0_RACT) && + !(macp->rxptr->rd0 & RX62N_RD0_RFP_SOF)) { + macp->rxptr->rd0 = (macp->rxptr->rd0 & RX62N_RD0_RDLE) | RX62N_RD0_RACT; + if (++macp->rxptr >= &rd[EDMAC_RECEIVE_DESCRIPTORS]) + macp->rxptr = rd; + n--; + } +#endif + /* + * Now compute the total frame size skipping eventual incomplete frames + * or holes... + */ +restart: + edp = macp->rxptr; + while (n > 0) { + + if (macp->rxptr->rd0 & RX62N_RD0_RACT) { + /* Empty buffer for some reason... cleaning up the incomplete frame.*/ + cleanup(macp, edp); + goto skip; + } + if ( ( macp->rxptr->rd0 & (RX62N_RD0_RFP_EOF|RX62N_RD0_RFE) ) + == (RX62N_RD0_RFP_EOF|RX62N_RD0_RFE) ) { + /* End Of Frame found, but erroneous, so cleaning.*/ + if (++macp->rxptr >= &rd[EDMAC_RECEIVE_DESCRIPTORS]) + macp->rxptr = rd; + n++; + cleanup(macp, edp); + goto skip; + } + /* + * End Of Frame found. + */ + if (macp->rxptr->rd0 & RX62N_RD0_RFP_EOF) { + rdp->offset = 0; + rdp->size = macp->rxptr->rd1 & 0xFFFF; + rdp->physdesc = edp; + if (++macp->rxptr >= &rd[EDMAC_RECEIVE_DESCRIPTORS]) + macp->rxptr = rd; + if (EDMAC.EDRRR.BIT.RR == 0) + EDMAC.EDRRR.BIT.RR = 1; + chSysUnlock(); + return RDY_OK; + } + + if ( (macp->rxptr != edp) && (macp->rxptr->rd0 & RX62N_RD0_RFP_MASK) ) { + /* Found another start or ... cleaning up the incomplete frame.*/ + cleanup(macp, edp); + goto restart; /* Another start buffer for some reason... */ + } + + if (++macp->rxptr >= &rd[EDMAC_RECEIVE_DESCRIPTORS]) + macp->rxptr = rd; + n--; + } + if (EDMAC.EDRRR.BIT.RR == 0) + EDMAC.EDRRR.BIT.RR = 1; + chSysUnlock(); + return RDY_TIMEOUT; +} + +/** + * @brief Releases a receive descriptor. + * @details The descriptor and its buffer are made available for more incoming + * frames. + * + * @param[in] rdp the pointer to the @p MACReceiveDescriptor structure + * + * @notapi + */ +void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) { + + bool_t done; + rx62n_eth_rx_descriptor_t *edp = rdp->physdesc; + + unsigned n = EDMAC_RECEIVE_DESCRIPTORS; + chSysLock(); + do { + done = ((edp->rd0 & RX62N_RD0_RFP_EOF) != 0); + edp->rd1 = EDMAC_RECEIVE_BUFFERS_SIZE<<16; + edp->rd0 = (edp->rd0 & RX62N_RD0_RDLE) | RX62N_RD0_RACT; + if (++edp >= &rd[EDMAC_RECEIVE_DESCRIPTORS]) + edp = rd; + n--; + } + while ((n > 0) && !done); + chSysUnlock(); +} + +/** + * @brief Updates and returns the link status. + * + * @param[in] macp pointer to the @p MACDriver object + * @return The link status. + * @retval TRUE if the link is active. + * @retval FALSE if the link is down. + * + * @notapi + */ +bool_t mac_lld_poll_link_status(MACDriver *macp) { + uint32_t ecmr, bmsr, bmcr; + + ecmr = ETHERC.ECMR.LONG; + + /* PHY CR and SR registers read.*/ + (void)miiGet(macp, MII_BMSR); + bmsr = miiGet(macp, MII_BMSR); + bmcr = miiGet(macp, MII_BMCR); + + /* Check on auto-negotiation mode.*/ + if (bmcr & BMCR_ANENABLE) { + uint32_t lpa; + /* Auto-negotiation must be finished without faults and link established.*/ + if ((bmsr & (BMSR_LSTATUS | BMSR_RFAULT | BMSR_ANEGCOMPLETE)) != + (BMSR_LSTATUS | BMSR_ANEGCOMPLETE)) + return macp->link_up = FALSE; + + /* Auto-negotiation enabled, checks the LPA register.*/ + lpa = miiGet(macp, MII_LPA); + + /* Check on link speed.*/ + if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4)) + ecmr |= ETHERC_ECMR_RTM; + else + ecmr &= ~ETHERC_ECMR_RTM; + + /* Check on link mode.*/ + if (lpa & (LPA_10FULL | LPA_100FULL)) + ecmr |= ETHERC_ECMR_DM; + else + ecmr &= ~ETHERC_ECMR_DM; + } + else { + /* Link must be established.*/ + if (!(bmsr & BMSR_LSTATUS)) + return macp->link_up = FALSE; + + /* Check on link speed.*/ + if (bmcr & BMCR_SPEED100) + ecmr |= ETHERC_ECMR_RTM; + else + ecmr &= ~ETHERC_ECMR_RTM; + + /* Check on link mode.*/ + if (bmcr & BMCR_FULLDPLX) + ecmr |= ETHERC_ECMR_DM; + else + ecmr &= ~ETHERC_ECMR_DM; + } + + /* Changes the mode in the MAC.*/ + ETHERC.ECMR.LONG = ecmr; + + /* Returns the link status.*/ + return macp->link_up = TRUE; +} + +/** + * @brief Writes to a transmit descriptor's stream. + * + * @param[in] tdp pointer to a @p MACTransmitDescriptor structure + * @param[in] buf pointer to the buffer containing the data to be + * written + * @param[in] size number of bytes to be written + * @return The number of bytes written into the descriptor's + * stream, this value can be less than the amount + * specified in the parameter @p size if the maximum + * frame size is reached. + * + * @notapi + */ +size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, + uint8_t *buf, + size_t size) { + + chDbgAssert(!(tdp->physdesc->td0 & RX62N_TD0_TACT), + "mac_lld_write_transmit_descriptor(), #1", + "attempt to write descriptor already owned by DMA"); + + if (size > tdp->size - tdp->offset) + size = tdp->size - tdp->offset; + + if (size > 0) { + memcpy((uint8_t *)(tdp->physdesc->td2) + tdp->offset, buf, size); + tdp->offset += size; + } + + return size; +} + +/** + * @brief Reads from a receive descriptor's stream. + * + * @param[in] rdp pointer to a @p MACReceiveDescriptor structure + * @param[in] buf pointer to the buffer that will receive the read data + * @param[in] size number of bytes to be read + * @return The number of bytes read from the descriptor's + * stream, this value can be less than the amount + * specified in the parameter @p size if there are + * no more bytes to read. + * + * @notapi + */ +size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, + uint8_t *buf, + size_t size) { +/* + chDbgAssert(!(rdp->physdesc->rd0 & RX62N_RD0_RACT), + "mac_lld_read_receive_descriptor(), #1", + "attempt to read descriptor already owned by DMA"); +*/ + if (size > rdp->size - rdp->offset) + size = rdp->size - rdp->offset; + if (size > 0) { + uint8_t *src = (uint8_t *)(rdp->physdesc->rd2) + + rdp->offset; + uint8_t *limit = (uint8_t *)&rb[EDMAC_RECEIVE_DESCRIPTORS * EDMAC_RECEIVE_BUFFERS_SIZE]; + if (src >= limit) { + src -= EDMAC_RECEIVE_DESCRIPTORS * EDMAC_RECEIVE_BUFFERS_SIZE; + } + if (src + size > limit ) { + memcpy(buf, src, (size_t)(limit - src)); + memcpy(buf + (size_t)(limit - src), rb, size - (size_t)(limit - src)); + } + else + memcpy(buf, src, size); + rdp->offset += size; + } + return size; + +} + +#endif /* HAL_USE_MAC */ + +/** @} */ diff --git a/os/hal/platforms/Rx62n/mac_lld.h b/os/hal/platforms/Rx62n/mac_lld.h new file mode 100644 index 000000000..66e41dad4 --- /dev/null +++ b/os/hal/platforms/Rx62n/mac_lld.h @@ -0,0 +1,340 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RX62N/mac_lld.h + * @brief RX62N low level MAC driver header. + * + * @addtogroup MAC + * @{ + */ + +#ifndef _MAC_LLD_H_ +#define _MAC_LLD_H_ + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief This implementation supports the zero-copy mode API. + */ +#define MAC_SUPPORTS_ZERO_COPY FALSE + +/** + * @brief Every receive buffer must by aligned on 32-bytes boundary + * if multiple buffers used. + */ +#define EDMAC_RECEIVE_BUFFERS_SIZE (256) /* Do not modify */ + +/** + * @brief Every transmit buffer must by aligned on 32-bytes boundary + * if multiple buffers used. + */ +#define EDMAC_TRANSMIT_BUFFERS_SIZE \ + (((RX62N_MAC_BUFFERS_SIZE - 1) | (32 - 1)) + 1) + +#define EDMAC_RECEIVE_DESCRIPTORS \ + (((((RX62N_MAC_BUFFERS_SIZE - 1) | (EDMAC_RECEIVE_BUFFERS_SIZE - 1)) + 1) \ + / EDMAC_RECEIVE_BUFFERS_SIZE) * RX62N_MAC_RECEIVE_BUFFERS) + +#define EDMAC_TRANSMIT_DESCRIPTORS RX62N_MAC_TRANSMIT_BUFFERS + +/** + * @name RD0 constants + * @{ + */ +#define RX62N_RD0_RFS_MASK ((1<<27)-1) +#define RX62N_RD0_RFE (1<<27) +#define RX62N_RD0_RFP_COF (0<<28) +#define RX62N_RD0_RFP_EOF (1<<28) +#define RX62N_RD0_RFP_SOF (2<<28) +#define RX62N_RD0_RFP_ONE (3<<28) +#define RX62N_RD0_RFP_MASK (3<<28) +#define RX62N_RD0_RDLE (1<<30) +#define RX62N_RD0_RACT (1<<31) +/** @} */ + +/** + * @name RD1 constants + * @{ + */ +#define RX62N_RD1_RBL(x) (x>>16) +#define RX62N_RD1_RFL(x) (x&0xFFFF) +/** @} */ + +/** + * @name TD0 constants + * @{ + */ +#define RX62N_TD0_TLOCKED (1<<9) /* Not an EDMAC flag.*/ +#define RX62N_TD0_TFS_MASK ((1<<26)-1) +#define RX62N_TD0_TWBI (1<<26) +#define RX62N_TD0_TFE (1<<27) +#define RX62N_TD0_TFP_COF (0<<28) +#define RX62N_TD0_TFP_EOF (1<<28) +#define RX62N_TD0_TFP_SOF (2<<28) +#define RX62N_TD0_TFP_ONE (3<<28) +#define RX62N_TD0_TDLE (1<<30) +#define RX62N_TD0_TACT (1<<31) +/** @} */ + +/** + * @name TDES1 constants + * @{ + */ +/** @} */ + +#define ETHERC_ECMR_RE (1<<6) +#define ETHERC_ECMR_TE (1<<5) +#define ETHERC_ECMR_ILB (1<<3) +#define ETHERC_ECMR_RTM (1<<2) +#define ETHERC_ECMR_DM (1<<1) +#define ETHERC_ECMR_PRM (1<<0) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Number of available transmit buffers. + */ +#if !defined(RX62N_MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__) +#define RX62N_MAC_TRANSMIT_BUFFERS 2 +#endif + +/** + * @brief Number of available receive buffers. + */ +#if !defined(RX62N_MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__) +#define RX62N_MAC_RECEIVE_BUFFERS 2 +#endif + +/** + * @brief Maximum supported frame size. + */ +#if !defined(RX62N_MAC_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define RX62N_MAC_BUFFERS_SIZE 1536 +#endif + + +/** + * @brief PHY detection timeout. + * @details Timeout, in milliseconds, for PHY address detection, if a PHY + * is not detected within the timeout then the driver halts during + * initialization. This setting applies only if the PHY address is + * not explicitly set in the board header file using + * @p BOARD_PHY_ADDRESS. A zero value disables the timeout and a + * single search path is performed. + */ +#if !defined(RX62N_MAC_PHY_TIMEOUT) || defined(__DOXYGEN__) +#define RX62N_MAC_PHY_TIMEOUT 100 +#endif + +/** + * @brief Change the PHY power state inside the driver. + */ +#if !defined(RX62N_MAC_ETH1_CHANGE_PHY_STATE) || defined(__DOXYGEN__) +#define RX62N_MAC_ETH1_CHANGE_PHY_STATE TRUE +#endif + +/** + * @brief ETHD1 interrupt priority level setting. + */ +#if !defined(RX62N_MAC_ETH1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define RX62N_MAC_ETH1_IRQ_PRIORITY 5 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (RX62N_MAC_PHY_TIMEOUT > 0) && !HAL_IMPLEMENTS_COUNTERS +#error "RX62N_MAC_PHY_TIMEOUT requires the realtime counter service" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of an RX62N Ethernet receive descriptor. + */ +typedef struct { + volatile uint32_t rd0; + volatile uint32_t rd1; + volatile uint32_t rd2; + volatile uint32_t pad; +} rx62n_eth_rx_descriptor_t; + +/** + * @brief Type of an RX62N Ethernet transmit descriptor. + */ +typedef struct { + volatile uint32_t td0; + volatile uint32_t td1; + volatile uint32_t td2; + volatile uint32_t pad; +} rx62n_eth_tx_descriptor_t; + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief MAC address. + */ + uint8_t *mac_address; + /* End of the mandatory fields.*/ +} MACConfig; + +/** + * @brief Structure representing a MAC driver. + */ +struct MACDriver { + /** + * @brief Driver state. + */ + macstate_t state; + /** + * @brief Current configuration data. + */ + const MACConfig *config; + /** + * @brief Transmit semaphore. + */ + Semaphore tdsem; + /** + * @brief Receive semaphore. + */ + Semaphore rdsem; +#if MAC_USE_EVENTS || defined(__DOXYGEN__) + /** + * @brief Receive event. + */ + EventSource rdevent; +#endif + /* End of the mandatory fields.*/ + /** + * @brief Link status flag. + */ + bool_t link_up; + /** + * @brief PHY address. + */ + uint8_t phyaddr; + /** + * @brief Receive next frame pointer. + */ + rx62n_eth_rx_descriptor_t *rxptr; + /** + * @brief Transmit next frame pointer. + */ + rx62n_eth_tx_descriptor_t *txptr; +}; + +/** + * @brief Structure representing a transmit descriptor. + */ +typedef struct { + /** + * @brief Current write offset. + */ + size_t offset; + /** + * @brief Available space size. + */ + size_t size; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the physical descriptor. + */ + rx62n_eth_tx_descriptor_t *physdesc; +} MACTransmitDescriptor; + +/** + * @brief Structure representing a receive descriptor. + */ +typedef struct { + /** + * @brief Current read offset. + */ + size_t offset; + /** + * @brief Available data size. + */ + size_t size; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the physical descriptor. + */ + rx62n_eth_rx_descriptor_t *physdesc; +} MACReceiveDescriptor; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern MACDriver ETHD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void mac_lld_init(void); + void mac_lld_start(MACDriver *macp); + void mac_lld_stop(MACDriver *macp); + msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, + MACTransmitDescriptor *tdp); + void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp); + msg_t mac_lld_get_receive_descriptor(MACDriver *macp, + MACReceiveDescriptor *rdp); + void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp); + bool_t mac_lld_poll_link_status(MACDriver *macp); + size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, + uint8_t *buf, + size_t size); + size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, + uint8_t *buf, + size_t size); +#if MAC_USE_ZERO_COPY + uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp, + size_t size, + size_t *sizep); + const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp, + size_t *sizep); +#endif /* MAC_USE_ZERO_COPY */ +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_MAC */ + +#endif /* _MAC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/Rx62n/pal_lld.c b/os/hal/platforms/Rx62n/pal_lld.c new file mode 100644 index 000000000..2e8f48ffe --- /dev/null +++ b/os/hal/platforms/Rx62n/pal_lld.c @@ -0,0 +1,310 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RX62N/pal_lld.c + * @brief RX62N GPIO low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void odrset(ioportid_t port, ioportmask_t mask) { + +#if defined(RX62N_HAS_PORT0_OD) + if ( port == (ioportid_t)&PORT0 ) + { + port->ODR |= mask; + return; + } +#endif +#if defined(RX62N_HAS_PORT1_OD) + if ( port == (ioportid_t)&PORT1 ) + { + port->ODR |= mask; + return; + } +#endif +#if defined(RX62N_HAS_PORT2_OD) + if ( port == (ioportid_t)&PORT2 ) + { + port->ODR |= mask; + return; + } +#endif +#if defined(RX62N_HAS_PORT3_OD) + if ( port == (ioportid_t)&PORT3 ) + { + port->ODR |= mask; + return; + } +#endif +#if defined(RX62N_HAS_PORTC_OD) + if ( port == (ioportid_t)&PORTC ) + { + port->ODR |= mask; + return; + } +#endif +} + +static void odrclear(ioportid_t port, ioportmask_t mask) { + +#if defined(RX62N_HAS_PORT0_OD) + if ( port == (ioportid_t)&PORT0 ) + { + port->ODR &= ~mask; + return; + } +#endif +#if defined(RX62N_HAS_PORT1_OD) + if ( port == (ioportid_t)&PORT1 ) + { + port->ODR &= ~mask; + return; + } +#endif +#if defined(RX62N_HAS_PORT2_OD) + if ( port == (ioportid_t)&PORT2 ) + { + port->ODR &= ~mask; + return; + } +#endif +#if defined(RX62N_HAS_PORT3_OD) + if ( port == (ioportid_t)&PORT3 ) + { + port->ODR &= ~mask; + return; + } +#endif +#if defined(RX62N_HAS_PORTC_OD) + if ( port == (ioportid_t)&PORTC ) + { + port->ODR &= ~mask; + return; + } +#endif +} + +static void pcrset(ioportid_t port, ioportmask_t mask) { +#if defined(RX62N_HAS_PORTA_PU) + if ( port == (ioportid_t)&PORTA ) + { + port->PCR |= mask; + return; + } +#endif +#if defined(RX62N_HAS_PORTB_PU) + if ( port == (ioportid_t)&PORTB ) + { + port->PCR |= mask; + return; + } +#endif +#if defined(RX62N_HAS_PORTC_PU) + if ( port == (ioportid_t)&PORTC ) + { + port->PCR |= mask; + return; + } +#endif +#if defined(RX62N_HAS_PORTD_PU) + if ( port == (ioportid_t)&PORTD ) + { + port->PCR |= mask; + return; + } +#endif +#if defined(RX62N_HAS_PORTE_PU) + if ( port == (ioportid_t)&PORTE ) + { + port->PCR |= mask; + return; + } +#endif +} + +static void pcrclear(ioportid_t port, ioportmask_t mask) { +#if defined(RX62N_HAS_PORTA_PU) + if ( port == (ioportid_t)&PORTA ) + { + port->PCR &= ~mask; + return; + } +#endif +#if defined(RX62N_HAS_PORTB_PU) + if ( port == (ioportid_t)&PORTB ) + { + port->PCR &= ~mask; + return; + } +#endif +#if defined(RX62N_HAS_PORTC_PU) + if ( port == (ioportid_t)&PORTC ) + { + port->PCR &= ~mask; + return; + } +#endif +#if defined(RX62N_HAS_PORTD_PU) + if ( port == (ioportid_t)&PORTD ) + { + port->PCR &= ~mask; + return; + } +#endif +#if defined(RX62N_HAS_PORTE_PU) + if ( port == (ioportid_t)&PORTE ) + { + port->PCR &= ~mask; + return; + } +#endif +} + +static void initgpio(GPIO_TypeDef *gpiop, const rx62n_gpio_setup_t *config) { + + gpiop->DDR = config->ddr; + gpiop->DR = config->dr; + gpiop->ICR = config->icr; +/* + gpiop->ODR = config->odr; + gpiop->PCR = config->pcr; +*/ + odrset(gpiop, config->odr); + pcrset(gpiop, config->pcr); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief RX62N I/O ports configuration. + * @param[in] config the RX62N ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + + /* + * Enables the GPIO related clocks (always enabled). + */ + + /* + * Initial GPIO setup. + */ + initgpio((GPIO_TypeDef *)&PORT0, &config->P0Data); + initgpio((GPIO_TypeDef *)&PORT1, &config->P1Data); + initgpio((GPIO_TypeDef *)&PORT2, &config->P2Data); + initgpio((GPIO_TypeDef *)&PORT3, &config->P3Data); + initgpio((GPIO_TypeDef *)&PORT4, &config->P4Data); + initgpio((GPIO_TypeDef *)&PORT5, &config->P5Data); +#if RX62N_HAS_PORT6 + initgpio((GPIO_TypeDef *)&PORT6, &config->P6Data); +#endif +#if RX62N_HAS_PORT7 + initgpio((GPIO_TypeDef *)&PORT7, &config->P7Data); +#endif +#if RX62N_HAS_PORT8 + initgpio((GPIO_TypeDef *)&PORT8, &config->P8Data); +#endif +#if RX62N_HAS_PORT9 + initgpio((GPIO_TypeDef *)&PORT9, &config->P9Data); +#endif + initgpio((GPIO_TypeDef *)&PORTA, &config->PAData); + initgpio((GPIO_TypeDef *)&PORTB, &config->PBData); + initgpio((GPIO_TypeDef *)&PORTC, &config->PCData); + initgpio((GPIO_TypeDef *)&PORTD, &config->PDData); +#if RX62N_HAS_PORTE + initgpio((GPIO_TypeDef *)&PORTE, &config->PEData); +#endif +#if RX62N_HAS_PORTF + initgpio((GPIO_TypeDef *)&PORTF, &config->PFData); +#endif +#if RX62N_HAS_PORTG + initgpio((GPIO_TypeDef *)&PORTG, &config->PGData); +#endif +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as input (needs external + pull-up or pull-down resistor). + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + switch (mode) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT: + case PAL_MODE_UNCONNECTED: + port->DDR &= ~mask; + pcrclear(port, mask); + break; + case PAL_MODE_INPUT_PULLUP: + port->DDR &= ~mask; + pcrset(port, mask); + break; + case PAL_MODE_OUTPUT_PUSHPULL: + port->DDR |= mask; + odrclear(port, mask); + break; + case PAL_MODE_OUTPUT_OPENDRAIN: + port->DDR |= mask; + odrset(port, mask); + break; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/platforms/Rx62n/pal_lld.h b/os/hal/platforms/Rx62n/pal_lld.h new file mode 100644 index 000000000..86c60a9e2 --- /dev/null +++ b/os/hal/platforms/Rx62n/pal_lld.h @@ -0,0 +1,452 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RX62N/pal_lld.h + * @brief RX62N GPIO low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_ANALOG +#undef PAL_MODE_INPUT_PULLDOWN + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief RX62N GPIO registers block. + */ +typedef struct { + volatile uint8_t DDR; + uint8_t wk0[31]; + union { + volatile uint8_t DR; + struct { + volatile unsigned char B0:1; + volatile unsigned char B1:1; + volatile unsigned char B2:1; + volatile unsigned char B3:1; + volatile unsigned char B4:1; + volatile unsigned char B5:1; + volatile unsigned char B6:1; + volatile unsigned char B7:1; + } BIT; + }; + uint8_t wk1[31]; + volatile uint8_t PORT; + uint8_t wk2[31]; + volatile uint8_t ICR; + uint8_t wk3[31]; + volatile uint8_t ODR; + uint8_t wk4[63]; + volatile uint8_t PCR; +} GPIO_TypeDef; + +/** + * @brief GPIO port setup info. + */ +typedef struct { + /** Initial value for DDR register.*/ + uint8_t ddr; + /** Initial value for DR register.*/ + uint8_t dr; + /** Initial value for ICR register.*/ + uint8_t icr; + /** Initial value for ODR register.*/ + uint8_t odr; + /** Initial value for PCR register.*/ + uint8_t pcr; +} rx62n_gpio_setup_t; + +/** + * @brief RX62N GPIO static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialize the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { + /** @brief Port 0 setup data.*/ + rx62n_gpio_setup_t P0Data; + /** @brief Port 1 setup data.*/ + rx62n_gpio_setup_t P1Data; + /** @brief Port 2 setup data.*/ + rx62n_gpio_setup_t P2Data; + /** @brief Port 3 setup data.*/ + rx62n_gpio_setup_t P3Data; + /** @brief Port 4 setup data.*/ + rx62n_gpio_setup_t P4Data; + /** @brief Port 5 setup data.*/ + rx62n_gpio_setup_t P5Data; +#if RX62N_HAS_PORT6 + /** @brief Port 6 setup data.*/ + rx62n_gpio_setup_t P6Data; +#endif +#if RX62N_HAS_PORT7 + /** @brief Port 7 setup data.*/ + rx62n_gpio_setup_t P7Data; +#endif +#if RX62N_HAS_PORT8 + /** @brief Port 8 setup data.*/ + rx62n_gpio_setup_t P8Data; +#endif +#if RX62N_HAS_PORT9 + /** @brief Port 9 setup data.*/ + rx62n_gpio_setup_t P9Data; +#endif + /** @brief Port A setup data.*/ + rx62n_gpio_setup_t PAData; + /** @brief Port B setup data.*/ + rx62n_gpio_setup_t PBData; + /** @brief Port C setup data.*/ + rx62n_gpio_setup_t PCData; + /** @brief Port D setup data.*/ + rx62n_gpio_setup_t PDData; +#if RX62N_HAS_PORTE + /** @brief Port E setup data.*/ + rx62n_gpio_setup_t PEData; +#endif +#if RX62N_HAS_PORTx + /** @brief Port x setup data.*/ +/* rx62n_gpio_setup_t PxData;*/ +#endif +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 8 + +/** + * @brief Whole port mask. + * @details This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ( (ioportmask_t)( ( 1 << PAL_IOPORTS_WIDTH ) - 1 ) ) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint8_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint8_t iomode_t; + +/** + * @brief Port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ +typedef GPIO_TypeDef * ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/* The low level driver wraps the definitions already present in the RX62N */ +/* iodefine_gcc62n.h. */ +/*===========================================================================*/ + +/** + * @brief GPIO port 0 identifier. + */ +#if RX62N_HAS_PORT0 || defined(__DOXYGEN__) +#define GPIO0 ((GPIO_TypeDef *)(&PORT0)) +#define IOPORT1 ((GPIO_TypeDef *)(&PORT0)) +#endif + +/** + * @brief GPIO port 1 identifier. + */ +#if RX62N_HAS_PORT1 || defined(__DOXYGEN__) +#define GPIO1 ((GPIO_TypeDef *)(&PORT1)) +#define IOPORT2 ((GPIO_TypeDef *)(&PORT1)) +#endif + +/** + * @brief GPIO port 2 identifier. + */ +#if RX62N_HAS_PORT2 || defined(__DOXYGEN__) +#define GPIO2 ((GPIO_TypeDef *)(&PORT2)) +#define IOPORT3 ((GPIO_TypeDef *)(&PORT2)) +#endif + +/** + * @brief GPIO port 3 identifier. + */ +#if RX62N_HAS_PORT3 || defined(__DOXYGEN__) +#define GPIO3 ((GPIO_TypeDef *)(&PORT3)) +#define IOPORT4 ((GPIO_TypeDef *)(&PORT3)) +#endif + +/** + * @brief GPIO port 4 identifier. + */ +#if RX62N_HAS_PORT4 || defined(__DOXYGEN__) +#define GPIO4 ((GPIO_TypeDef *)(&PORT4)) +#define IOPORT5 ((GPIO_TypeDef *)(&PORT4)) +#endif + +/** + * @brief GPIO port 5 identifier. + */ +#if RX62N_HAS_PORT5 || defined(__DOXYGEN__) +#define GPIO5 ((GPIO_TypeDef *)(&PORT5)) +#define IOPORT6 ((GPIO_TypeDef *)(&PORT5)) +#endif + +/** + * @brief GPIO port 6 identifier. + */ +#if RX62N_HAS_PORT6 || defined(__DOXYGEN__) +#define GPIO6 ((GPIO_TypeDef *)(&PORT6)) +#define IOPORT7 ((GPIO_TypeDef *)(&PORT6)) +#endif + +/** + * @brief GPIO port 7 identifier. + */ +#if RX62N_HAS_PORT7 || defined(__DOXYGEN__) +#define GPIO7 ((GPIO_TypeDef *)(&PORT7)) +#define IOPORT8 ((GPIO_TypeDef *)(&PORT7)) +#endif + +/** + * @brief GPIO port 8 identifier. + */ +#if RX62N_HAS_PORT8 || defined(__DOXYGEN__) +#define GPIO8 ((GPIO_TypeDef *)(&PORT8)) +#define IOPORT9 ((GPIO_TypeDef *)(&PORT8)) +#endif + +/** + * @brief GPIO port 9 identifier. + */ +#if RX62N_HAS_PORT9 || defined(__DOXYGEN__) +#define GPIO9 ((GPIO_TypeDef *)(&PORT9)) +#define IOPORT10 ((GPIO_TypeDef *)(&PORT9)) +#endif + +/** + * @brief GPIO port 10 identifier. + */ +#if RX62N_HAS_PORTA || defined(__DOXYGEN__) +#define GPIO10 ((GPIO_TypeDef *)(&PORTA)) +#define IOPORT11 ((GPIO_TypeDef *)(&PORTA)) +#endif + +/** + * @brief GPIO port 11 identifier. + */ +#if RX62N_HAS_PORTB || defined(__DOXYGEN__) +#define GPIO11 ((GPIO_TypeDef *)(&PORTB)) +#define IOPORT12 ((GPIO_TypeDef *)(&PORTB)) +#endif + +/** + * @brief GPIO port 12 identifier. + */ +#if RX62N_HAS_PORTC || defined(__DOXYGEN__) +#define GPIO12 ((GPIO_TypeDef *)(&PORTC)) +#define IOPORT13 ((GPIO_TypeDef *)(&PORTC)) +#endif + +/** + * @brief GPIO port 13 identifier. + */ +#if RX62N_HAS_PORTD || defined(__DOXYGEN__) +#define GPIO13 ((GPIO_TypeDef *)(&PORTD)) +#define IOPORT14 ((GPIO_TypeDef *)(&PORTD)) +#endif + +/** + * @brief GPIO port 14 identifier. + */ +#if RX62N_HAS_PORTE || defined(__DOXYGEN__) +#define GPIO14 ((GPIO_TypeDef *)(&PORTE)) +#define IOPORT15 ((GPIO_TypeDef *)(&PORTE)) +#endif + +/** + * @brief GPIO port 15 identifier. + */ +#if RX62N_HAS_PORTF || defined(__DOXYGEN__) +#define GPIO15 ((GPIO_TypeDef *)(&PORTF)) +#define IOPORT16 ((GPIO_TypeDef *)(&PORTF)) +#endif + +/** + * @brief GPIO port 16 identifier. + */ +#if RX62N_HAS_PORTG || defined(__DOXYGEN__) +#define GPIO16 ((GPIO_TypeDef *)(&PORTG)) +#define IOPORT17 ((GPIO_TypeDef *)(&PORTG)) +#endif + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief GPIO ports subsystem initialization. + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads an I/O port. + * @details This function is implemented by reading the GPIO IDR register, the + * implementation has no side effects. + * @note This function is not meant to be invoked directly by the application + * code. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->PORT) + +/** + * @brief Reads the output latch. + * @details This function is implemented by reading the GPIO ODR register, the + * implementation has no side effects. + * @note This function is not meant to be invoked directly by the application + * code. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->DR) + +/** + * @brief Writes on a I/O port. + * @details This function is implemented by writing the GPIO ODR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->DR = (bits)) + +/** + * @brief Sets a bits mask on a I/O port. + * @details This function is implemented by writing the GPIO BSRR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +/* +#define pal_lld_setport(port, bits) +*/ + +/** + * @brief Clears a bits mask on a I/O port. + * @details This function is implemented by writing the GPIO BSRR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +/* +#define pal_lld_clearport(port, bits) +*/ + +/** + * @brief Writes a group of bits. + * @details This function is implemented by writing the GPIO BSRR register, the + * implementation has no side effects. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset the group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group + * width are masked. + * + * @notapi + */ +/* +#define pal_lld_writegroup(port, mask, offset, bits) +*/ + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Writes a logical state on an output pad. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit) + +extern const PALConfig pal_default_config; + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/Rx62n/rx62n_mii.c b/os/hal/platforms/Rx62n/rx62n_mii.c new file mode 100644 index 000000000..5f3496480 --- /dev/null +++ b/os/hal/platforms/Rx62n/rx62n_mii.c @@ -0,0 +1,259 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RX62N/rx62n_mii.c + * @brief RX62N low level MII driver code. + * + * @addtogroup RX62N_MII + * @{ + */ + +#include "ch.h" +#include "hal.h" +#include "rx62n_mii.h" + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +#if (RX62N_SYSCLK == 96000000) +__attribute__((always_inline)) +static inline void delay200ns(void) { + + asm volatile ("mov.l #5,r2 \n\t" + "1: \n\t" + "sub #1,r2 \n\t" + "bne.b 1b \n\t"); +} + +__attribute__((always_inline)) +static inline void delay1ms(void) { + + asm volatile ("mov.l #24000,r2 \n\t" + "1: \n\t" + "sub #1,r2 \n\t" + "bne.b 1b \n\t"); +} +#else +#error Adjust delay200ns and delay1ms for RX62N_SYSCLK other than 96MHz. +#endif + +/** + * @brief Write 1 bit to SMI bus. + * + * @param[in] b the bit value + */ +static void smi_bit_w(uint32_t b) { + uint32_t pir = PIR_MMD; + + if (b) + pir |= PIR_MDO; + ETHERC.PIR.LONG = pir; + /* wait 10ns */ + asm volatile("nop"); + ETHERC.PIR.LONG = pir | PIR_MDC; + delay200ns(); + ETHERC.PIR.LONG = pir; + delay200ns(); +} + +/** + * @brief Read 1 bit from SMI bus. + * + * @return The bit value. + */ +static uint32_t smi_bit_r(void) { + uint32_t pir = 0; + + ETHERC.PIR.LONG = PIR_MDC; + delay200ns(); + ETHERC.PIR.LONG = 0; + delay200ns(); + if (ETHERC.PIR.LONG & PIR_MDI) + pir = 1; + return pir; +} + +/** + * @brief Release SMI bus. + */ +static void smi_z0(void) { + + ETHERC.PIR.LONG = PIR_MDC; + delay200ns(); + ETHERC.PIR.LONG = 0; + delay200ns(); +} + +/** + * @brief Write up to 32 bits to SMI bus (MSB first). + * + * @note Writing starts from len-1 bit. + * @param[in] value value to write + * @param[in] len number of bits + */ +static void smi_write(uint32_t value, uint8_t len) { + + while (len--) + smi_bit_w(value & (1<phyaddr, regaddr); +} + +/** + * @brief Writes a PHY register through the MII interface. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[in] addr the register address + * @param[in] value the new register value + * + * @notapi + */ +void miiPut(MACDriver *macp, phyaddr_t regaddr, phyreg_t value) { + + (void)macp; + mii_write_reg(macp->phyaddr, regaddr, value); +} + +#endif /* HAL_USE_MAC */ + +/** @} */ diff --git a/os/hal/platforms/Rx62n/rx62n_mii.h b/os/hal/platforms/Rx62n/rx62n_mii.h new file mode 100644 index 000000000..1c7cfdf58 --- /dev/null +++ b/os/hal/platforms/Rx62n/rx62n_mii.h @@ -0,0 +1,87 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RX62N/rx62n_mii.h + * @brief RX62N low level MII driver header. + * + * @addtogroup RX62N_MII + * @{ + */ + +#ifndef _RX62N_MII_H_ +#define _RX62N_MII_H_ + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/* + * PIR bit definitions. + */ +#define PIR_MDC (1<<0) +#define PIR_MMD (1<<1) +#define PIR_MDO (1<<2) +#define PIR_MDI (1<<3) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a PHY register value. + */ +typedef uint16_t phyreg_t; + +/** + * @brief Type of a PHY register address. + */ +typedef uint8_t phyaddr_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void miiInit(void); + void miiReset(MACDriver *macp); + phyreg_t miiGet(MACDriver *macp, phyaddr_t addr); + void miiPut(MACDriver *macp, phyaddr_t addr, phyreg_t value); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_MAC */ + +#endif /* _RX62N_MII_H_ */ + +/** @} */ diff --git a/os/hal/platforms/Rx62n/serial_lld.c b/os/hal/platforms/Rx62n/serial_lld.c new file mode 100644 index 000000000..fc0e5eca2 --- /dev/null +++ b/os/hal/platforms/Rx62n/serial_lld.c @@ -0,0 +1,306 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RX62N/serial_lld.c + * @brief RX62N low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if RX62N_SERIAL_USE_UART0 || defined(__DOXYGEN__) +/** @brief UART0 serial driver identifier.*/ +SerialDriver SD1; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** @brief Driver default configuration.*/ +static const SerialConfig default_config = { + .sc_speed = SERIAL_DEFAULT_BITRATE, + .sc_scr = 0, /* only bits 0-1 used */ + .sc_smr = 0, + .sc_semr = 0, +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief UART initialization. + * + * @param[in] sdp communication channel associated to the UART + * @param[in] config the architecture-dependent serial driver configuration + * @todo Test all possible SMR and SEMR clock settings + */ +static void uart_init(SerialDriver *sdp, const SerialConfig *config) { + volatile struct st_sci *u = sdp->uart; + + uint32_t brr; + + u->SCR.BYTE = config->sc_scr & 0x03; + u->SMR.BYTE = config->sc_smr; + u->SEMR.BYTE = config->sc_semr; + brr = ( 32 << ( 2 * ( config->sc_smr & 3 ) ) ) >> ( ( config->sc_semr & 0x10 ) ? 1 : 0 ); + brr = RX62N_PERCLK / ( brr * config->sc_speed ) - 1; + u->BRR = brr; + /* TODO: delay 1-bit interval */ + u->SCR.BYTE |= 0x70; +} + +/** + * @brief UART de-initialization. + * + * @param[in] u pointer to an UART I/O block + */ +static void uart_deinit(volatile struct st_sci *u) { + + u->SCR.BYTE = 0; + u->SMR.BYTE = 0; + u->SEMR.BYTE = 0; + u->BRR = 0; +} + +/** + * @brief Error handling routine. + * + * @param[in] sdp communication channel associated to the UART + * @param[in] err UART LSR register value + */ +static void set_error(SerialDriver *sdp, uint32_t err) { + + flagsmask_t sts = 0; + + if (err & SSR_ORER) + sts |= SD_OVERRUN_ERROR; + if (err & SSR_PER) + sts |= SD_PARITY_ERROR; + if (err & SSR_FER) + sts |= SD_FRAMING_ERROR; + chSysLockFromIsr(); + chnAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); + +} + +#if RX62N_SERIAL_USE_UART0 || defined(__DOXYGEN__) +/** + * @brief Error IRQ handler. + * + * @param[in] sdp communication channel associated to the UART + */ +static void serve_interrupt_eri(SerialDriver *sdp) { + volatile struct st_sci *u = sdp->uart; + + set_error(sdp, u->SSR.BYTE); + u->SSR.BYTE &= ~((1<<3)|(1<<4)|(1<<5)); /* clear error flags */ +} + +/** + * @brief Receive IRQ handler. + * + * @param[in] sdp communication channel associated to the UART + */ +static void serve_interrupt_rxi(SerialDriver *sdp) { + volatile struct st_sci *u = sdp->uart; + + chSysLockFromIsr(); + sdIncomingDataI(sdp, u->RDR); + chSysUnlockFromIsr(); +} + +/** + * @brief Transmit IRQ handler. + * + * @param[in] sdp communication channel associated to the UART + */ +static void serve_interrupt_txi(SerialDriver *sdp) { + volatile struct st_sci *u = sdp->uart; + msg_t b; + + chSysLockFromIsr(); + if (!u->SSR.BIT.TDRE) { + /* forced by notify */ + chSysUnlockFromIsr(); + return; + } + b = chOQGetI(&sdp->oqueue); + chSysUnlockFromIsr(); + if (b < Q_OK) { + u->SCR.BIT.TIE = 0; + chSysLockFromIsr(); + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + chSysUnlockFromIsr(); + return; + } + u->TDR = b; +} + +/** + * @brief Transmission end IRQ handler. + * + * @param[in] sdp communication channel associated to the UART + */ +static void serve_interrupt_tei(SerialDriver *sdp) { + + chSysLockFromIsr(); + chnAddFlagsI(sdp, CHN_TRANSMISSION_END); + chSysUnlockFromIsr(); +} + +/** + * @brief Driver SD1 output notification. + */ +static void notify1(GenericQueue *qp) { + + (void)qp; + SD1.uart->SCR.BIT.TIE = 1; + IR(SCI0,TXI0) = 1; /* Set Interrupt Enable Register */ +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief UART0 IRQ handler. + * + * @isr + */ +#if RX62N_SERIAL_USE_UART0 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(Excep_SCI0_ERI0) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt_eri(&SD1); + + CH_IRQ_EPILOGUE(); +} +CH_IRQ_HANDLER(Excep_SCI0_RXI0) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt_rxi(&SD1); + + CH_IRQ_EPILOGUE(); +} +CH_IRQ_HANDLER(Excep_SCI0_TXI0) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt_txi(&SD1); + + CH_IRQ_EPILOGUE(); +} +CH_IRQ_HANDLER(Excep_SCI0_TEI0) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt_tei(&SD1); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if RX62N_SERIAL_USE_UART0 + sdObjectInit(&SD1, NULL, notify1); + SD1.uart = &SCI0; + PORT2.ICR.BIT.B1 = 1; +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + + if (sdp->state == SD_STOP) { +#if RX62N_SERIAL_USE_UART0 + if (&SD1 == sdp) { + MSTP(SCI0) = 0; /* Enable SCI0 (cancel module stop state) */ + IEN(SCI0,RXI0) = 1; + IEN(SCI0,TXI0) = 1; + IEN(SCI0,ERI0) = 1; + IPR(SCI0,TXI0) = RX62N_SERIAL_UART0_IRQ_PRIORITY; + } +#endif + } + uart_init(sdp, config); +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the UART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + + if (sdp->state == SD_READY) { + uart_deinit(sdp->uart); +#if RX62N_SERIAL_USE_UART0 + if (&SD1 == sdp) { + IEN(SCI0,RXI0) = 0; + IEN(SCI0,TXI0) = 0; + IEN(SCI0,ERI0) = 0; + MSTP(SCI0) = 1; /* Disable SCI0 (enter module stop state) */ + return; + } +#endif + } +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/platforms/Rx62n/serial_lld.h b/os/hal/platforms/Rx62n/serial_lld.h new file mode 100644 index 000000000..d8ef0c974 --- /dev/null +++ b/os/hal/platforms/Rx62n/serial_lld.h @@ -0,0 +1,142 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RX62N/serial_lld.h + * @brief RX62N low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define SSR_ORER (1<<5) +#define SSR_FER (1<<4) +#define SSR_PER (1<<3) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief UART0 driver enable switch. + * @details If set to @p TRUE the support for UART0 is included. + * @note The default is @p TRUE . + */ +#if !defined(RX62N_SERIAL_USE_UART0) || defined(__DOXYGEN__) +#define RX62N_SERIAL_USE_UART0 FALSE +#endif + +/** + * @brief UART0 PCLK divider. + */ +#if !defined(RX62N_SERIAL_UART0CLKDIV) || defined(__DOXYGEN__) +#define RX62N_SERIAL_UART0CLKDIV 1 +#endif + +/** + * @brief UART0 interrupt priority level setting. + */ +#if !defined(RX62N_SERIAL_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define RX62N_SERIAL_UART0_IRQ_PRIORITY 3 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief RX62N8 Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + */ +typedef struct { + /** + * @brief Bit rate. + */ + uint32_t sc_speed; + /** + * @brief Initialization value for the SCR register. + */ + uint8_t sc_scr; + /** + * @brief Initialization value for the SMR register. + */ + uint8_t sc_smr; + /** + * @brief Initialization value for the SEMR register. + */ + uint8_t sc_semr; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Pointer to the USART registers block.*/ \ + volatile struct st_sci *uart; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if RX62N_SERIAL_USE_UART0 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/Rx62n/usb_lld.c b/os/hal/platforms/Rx62n/usb_lld.c new file mode 100644 index 000000000..f5b7a965f --- /dev/null +++ b/os/hal/platforms/Rx62n/usb_lld.c @@ -0,0 +1,983 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RX62N/usb_lld.c + * @brief RX62N USB Driver subsystem low level driver source. + * + * @addtogroup USB + * @{ + */ + +#include "ch.h" +#include "hal.h" + + +#if HAL_USE_USB || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief PIPEnCTR register union. + */ +typedef union { + unsigned short WORD; + struct { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; +} pipectr_t;; + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief USB1 driver identifier.*/ +#if RX62N_USE_USB0 || defined(__DOXYGEN__) +USBDriver USBD1; +#endif + +/** @brief USB2 driver identifier.*/ +#if RX62N_USE_USB1 || defined(__DOXYGEN__) +USBDriver USBD2; +#error "USBD2 is not supported yet" +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** + * @brief EP0 state. + * @note It is an union because IN and OUT endpoints are never used at the + * same time for EP0. + */ +static union { + /** + * @brief IN EP0 state. + */ + USBInEndpointState in; + /** + * @brief OUT EP0 state. + */ + USBOutEndpointState out; +} ep0_state; + +/** + * @brief Buffer for the EP0 setup packets. + */ +static uint8_t ep0setup_buffer[8]; + +/** + * @brief EP0 initialization structure. + */ +static const USBEndpointConfig ep0config = { + USB_EP_MODE_TYPE_CTRL, + _usb_ep0setup, + _usb_ep0in, + _usb_ep0out, + USB_EP0_PACKET_SIZE, + USB_EP0_PACKET_SIZE, + &ep0_state.in, + &ep0_state.out, + 1, + ep0setup_buffer +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +pipectr_t usb_pipectr_read(USBDriver *usbp, usbep_t ep) { + volatile pipectr_t *pipe = (pipectr_t *)&usbp->usb->PIPE1CTR; + + return pipe[ep-1]; +} + +void usb_pipectr_write(USBDriver *usbp, usbep_t ep, uint16_t p) { + volatile pipectr_t *pipe = (pipectr_t *)&usbp->usb->PIPE1CTR; + + pipe[ep-1].WORD = p; +} + +/** + * @brief Reads from a dedicated packet buffer. + * + * @param[in] udp pointer to a @p stm32_usb_descriptor_t + * @param[out] buf buffer where to copy the packet data + * @param[in] n maximum number of bytes to copy. This value must + * not exceed the maximum packet size for this endpoint. + * + * @notapi + */ +static void usb_packet_read_to_buffer(USBDriver *usbp, usbep_t ep, + uint8_t *buf, size_t n) { + uint32_t i; + + usbp->epc[ep]->in_state->transmitted = n; + if (ep == 0) { + for (i = 0; i < n; i++) + usbp->epc[ep]->out_state->mode.linear.rxbuf[i] = usbp->usb->CFIFO.BYTE.L; + } + else { + for (i = 0; i < n; i++) + usbp->epc[ep]->out_state->mode.linear.rxbuf[i] = usbp->usb->D0FIFO.BYTE.L; + } +} + +/** + * @brief Reads from a dedicated packet buffer. + * + * @param[in] udp pointer to a @p stm32_usb_descriptor_t + * @param[in] iqp pointer to an @p InputQueue object + * @param[in] n maximum number of bytes to copy. This value must + * not exceed the maximum packet size for this endpoint. + * + * @notapi + */ +static void usb_packet_read_to_queue(USBDriver *usbp, usbep_t ep, InputQueue *iqp, size_t n) { + size_t nhw = n; + uint8_t c; + + while (nhw > 0) { + if (ep == 0) { + c = usbp->usb->CFIFO.BYTE.L; + } + else { + /* ep 1..9 */ + c = usbp->usb->D0FIFO.BYTE.L;; + } + *iqp->q_wrptr++ = c; + if (iqp->q_wrptr >= iqp->q_top) + iqp->q_wrptr = iqp->q_buffer; + nhw--; + } + + /* Updating queue.*/ + chSysLockFromIsr(); + iqp->q_counter += n; + while (notempty(&iqp->q_waiting)) + chSchReadyI(fifo_remove(&iqp->q_waiting))->p_u.rdymsg = Q_OK; + chSysUnlockFromIsr(); +} + +/** + * @brief Writes to a dedicated packet buffer. + * + * @param[in] buf buffer where to fetch the packet data + * @param[in] n maximum number of bytes to copy. This value must + * not exceed the maximum packet size for this endpoint. + * + * @notapi + */ +static void usb_packet_write_from_buffer(USBDriver *usbp, usbep_t ep, + const uint8_t *buf, size_t n) { + + usbp->epc[ep]->in_state->transmitted = n; + if (ep == 0) { + while (n--) { + usbp->usb->CFIFO.BYTE.L = *buf++; + } + } + else { + /* ep 1..9 */ + usbp->usb->D1FIFO.BYTE.L = *buf++; + } +} + +/** + * @brief Writes to a dedicated packet buffer. + * + * @param[in] udp pointer to a @p stm32_usb_descriptor_t + * @param[in] buf buffer where to fetch the packet data + * @param[in] n maximum number of bytes to copy. This value must + * not exceed the maximum packet size for this endpoint. + * + * @notapi + */ +static void usb_packet_write_from_queue(USBDriver *usbp, usbep_t ep, + OutputQueue *oqp, size_t n) { + size_t nhw = n; + uint8_t c; + + usbp->epc[ep]->in_state->transmitted = n; + while (nhw > 0) { + c = *oqp->q_rdptr++;; + if (ep == 0) { + usbp->usb->CFIFO.BYTE.L = c; + } + else { + /* ep 1..9 */ + usbp->usb->D1FIFO.BYTE.L = c; + } + c = c; + if (oqp->q_rdptr >= oqp->q_top) + oqp->q_rdptr = oqp->q_buffer; + nhw--; + } + + /* Updating queue. Note, the lock is done in this unusual way because this + function can be called from both ISR and thread context so the kind + of lock function to be invoked cannot be decided beforehand.*/ + + /* + TODO: port_lock() doesn't work.*/ + if (port_enabled()) { + dbg_enter_lock(); + chSysLock(); + + oqp->q_counter += n; + while (notempty(&oqp->q_waiting)) + chSchReadyI(fifo_remove(&oqp->q_waiting))->p_u.rdymsg = Q_OK; + + chSysUnlock(); + dbg_leave_lock(); + } + else { + oqp->q_counter += n; + while (notempty(&oqp->q_waiting)) + chSchReadyI(fifo_remove(&oqp->q_waiting))->p_u.rdymsg = Q_OK; + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if RX62N_USE_USB0 || defined(__DOXYGEN__) +void usb_lld_serve_interrupt(USBDriver *usbp) { + uint16_t sts0, sts0clr; + uint16_t ep = 0; + + sts0 = usbp->usb->INTSTS0.WORD; + sts0clr = (~(sts0 & usbp->usb->INTENB0.WORD))| + INTSTS0_VALID|INTSTS0_DVST|INTSTS0_CTRT; + + if (sts0 & INTSTS0_RESM) { +/* _usb_isr_invoke_event_cb(usbp, USB_EVENT_RESUME);*/ + } + + /* USB bus WAKEUP condition handling.*/ +/* + if (isr & AT91C_UDP_WAKEUP) { + _usb_isr_invoke_event_cb(usbp, USB_EVENT_WAKEUP); + } +*/ + /* SOF handling.*/ +/* + if (isr & AT91C_UDP_SOFINT) { + _usb_isr_invoke_sof_cb(usbp); + } +*/ + if (sts0 & INTSTS0_DVST) { + usbp->usb->INTSTS0.BIT.DVST = 0; + switch (INTSTS0_DVSQ(sts0)) { + case DVSQ_POWERED: + break; + case DVSQ_DEFAULT: + if ( !(sts0 & INTSTS0_RESM) && (usbp->last_dvst != DVSQ_ADDRESS) && + (usbp->last_dvst != DVSQ_SUSPENDED_DEF)) { + _usb_reset(usbp); + _usb_isr_invoke_event_cb(usbp, USB_EVENT_RESET); + } + break; + case DVSQ_ADDRESS: + break; + case DVSQ_CONFIGURED: + break; + default: + /* Default is suspened state */ + _usb_isr_invoke_event_cb(usbp, USB_EVENT_SUSPEND); + break; + } + usbp->last_dvst = INTSTS0_DVSQ(sts0); + } + + if (sts0 & INTSTS0_CTRT) { + switch (INTSTS0_CTSQ(sts0)) { + case CTSQ_IDLE_OR_SETUP: + if (usbp->last_ctsq == CTSQ_READ_STATUS) { + _usb_isr_invoke_out_cb(usbp, ep); + } + else if (usbp->last_ctsq == CTSQ_WRITE_STATUS) { + _usb_isr_invoke_in_cb(usbp, ep); + } + else if (usbp->last_ctsq == CTSQ_NODATA_STATUS) { + _usb_isr_invoke_in_cb(usbp, ep); + } + break; + default: + break; + } + usbp->last_ctsq = INTSTS0_CTSQ(sts0); + usbp->usb->INTSTS0.BIT.CTRT = 0; + } + + if (sts0 & INTSTS0_VALID) { + usbp->usb->INTSTS0.BIT.VALID = 0; + _usb_isr_invoke_setup_cb(usbp, ep); + if (INTSTS0_CTSQ(sts0) == CTSQ_NODATA_STATUS) { + usbp->usb->DCPCTR.BIT.PID = PID_BUF; + usbp->usb->DCPCTR.BIT.CCPL = 1; + } + } + + if (sts0 & INTSTS0_BRDY) { + /* BRDY */ + uint16_t brdysts = usbp->usb->BRDYSTS.WORD; + const USBEndpointConfig *epcp; + size_t n; + for (ep=0; epepc[ep]; + if (ep == 0) { + n = usbp->usb->CFIFOCTR.BIT.DTLN; + } + else { + if (epcp->out_state) { + usbp->usb->PIPESEL.BIT.PIPESEL = ep; + do { + usbp->usb->D0FIFOSEL.WORD = ep; + } while (usbp->usb->D0FIFOSEL.WORD != ep); + while (!usbp->usb->D0FIFOCTR.BIT.FRDY); + n = usbp->usb->D0FIFOCTR.BIT.DTLN; + } + else { + /* in_state */ + usbp->usb->PIPESEL.BIT.PIPESEL = ep; + do { + usbp->usb->D1FIFOSEL.WORD = ep; + } while (usbp->usb->D1FIFOSEL.WORD != ep); + while (!usbp->usb->D1FIFOCTR.BIT.FRDY); + n = 0; /* Omit compiler warning */ + } + } + if (epcp->out_state) { + /* Reads the packet into the defined buffer.*/ + if (epcp->out_state->rxqueued) { + usb_packet_read_to_queue(usbp, ep, + epcp->out_state->mode.queue.rxqueue, n); + } + else { + usb_packet_read_to_buffer(usbp, ep, + epcp->out_state->mode.linear.rxbuf, n); + epcp->out_state->mode.linear.rxbuf += n; + } + /* Transaction data updated.*/ + epcp->out_state->rxcnt += n; + epcp->out_state->rxsize -= n; + epcp->out_state->rxpkts -= 1; + if (epcp->out_state->rxpkts > 0) { + /* Transfer not completed, there are more packets to receive.*/ + } + else { + /* Transfer completed, invokes the callback.*/ + /* Set pipe to NAK */ + usb_pipectr_write(usbp, ep, PID_NAK); + _usb_isr_invoke_out_cb(usbp, ep); + } + } + else { + epcp->in_state->txcnt += epcp->in_state->transmitted; + epcp->in_state->txsize -= epcp->in_state->transmitted; + if (epcp->in_state->txsize > 0) { + /* Transfer not completed, there are more packets to send.*/ + if (epcp->in_state->txsize > epcp->in_maxsize) + n = epcp->in_maxsize; + else + n = epcp->in_state->txsize; + + if (epcp->in_state->txqueued) { + usb_packet_write_from_queue(usbp, ep, + epcp->in_state->mode.queue.txqueue, n); + } + else { + epcp->in_state->mode.linear.txbuf += epcp->in_state->transmitted; + usb_packet_write_from_buffer(usbp, ep, + epcp->in_state->mode.linear.txbuf, n); + } + chSysLockFromIsr(); + usb_lld_start_in(usbp, ep); + chSysUnlockFromIsr(); + } + else { + /* Transfer completed, invokes the callback.*/ + _usb_isr_invoke_in_cb(usbp, ep); + } + } + } + } + usbp->usb->BRDYSTS.WORD = ~brdysts; + } + if (sts0 & INTSTS0_BEMP) { + /* BEMP */ + uint16_t bempsts = usbp->usb->BEMPSTS.WORD; + const USBEndpointConfig *epcp; + size_t n; + ep = 0; + epcp = usbp->epc[ep]; + epcp->in_state->txcnt += epcp->in_state->transmitted; + epcp->in_state->txsize -= epcp->in_state->transmitted; + if (epcp->in_state->txsize > 0) { + /* Transfer not completed, there are more packets to send.*/ + if (epcp->in_state->txsize > epcp->in_maxsize) + n = epcp->in_maxsize; + else + n = epcp->in_state->txsize; + if (epcp->in_state->txqueued) { + usb_packet_write_from_queue(usbp, ep, + epcp->in_state->mode.queue.txqueue, n); + } + else { + epcp->in_state->mode.linear.txbuf += epcp->in_state->transmitted; + usb_packet_write_from_buffer(usbp, ep, + epcp->in_state->mode.linear.txbuf, n); + } + chSysLockFromIsr(); + usb_lld_start_in(usbp, ep); + chSysUnlockFromIsr(); + } + else { + /* Transfer completed, invokes the callback.*/ + _usb_isr_invoke_in_cb(usbp, ep); + } + usbp->usb->BEMPSTS.WORD = ~bempsts; + } + usbp->usb->INTSTS0.WORD = sts0clr; +} +#endif + +/** + * @brief USB interrupt handler. + * + * @isr + */ +#if RX62N_USE_USB0 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(Excep_USB0_USBI0) { + + CH_IRQ_PROLOGUE(); + usb_lld_serve_interrupt(&USBD1); + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level USB driver initialization. + * + * @notapi + */ +void usb_lld_init(void) { + +#if RX62N_USE_USB0 || defined(__DOXYGEN__) + usbObjectInit(&USBD1); + USBD1.usb = &USB0; +#endif +#if RX62N_USE_USB1 || defined(__DOXYGEN__) + usbObjectInit(&USBD2); + USBD2.usb = &USB1; +#endif +} + +/** + * @brief Configures and activates the USB peripheral. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_start(USBDriver *usbp) { + + if (usbp->state == USB_STOP) { + /* Enable USB peripheral. */ + if (usbp == &USBD1) { + MSTP(USB0) = 0; + /* Enable GPIO Pull-up */ + PORT1.DDR.BIT.B4 = 1; + /* Enable USB0 pins functions */ + IOPORT.PFKUSB.BYTE = 0x14; + } + /* USB clock activation. */ + usbp->usb->SYSCFG.BIT.SCKE = 1; + /* Select function. */ + usbp->usb->SYSCFG.BIT.DCFM = 0; + /* Enable module operation. */ + usbp->usb->SYSCFG.BIT.USBE = 1; + + /* Default as powered state */ + usbp->last_dvst = 0; + /* Default as idle stage */ + usbp->last_ctsq = 0; + /* Current FIFO */ + usbp->current_fifo = 0; + + /* Reset procedure enforced on driver start.*/ + _usb_reset(usbp); + } + /* Configuration.*/ +} + +/** + * @brief Deactivates the USB peripheral. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_stop(USBDriver *usbp) { + + /* If in ready state then disables the USB clock.*/ + if (usbp->state != USB_STOP) { +/* IEN(USB0,USBI0) = 0;*/ + /* Disable module operation. */ + usbp->usb->SYSCFG.BIT.USBE = 0; + /* Disable USB clock.*/ + usbp->usb->SYSCFG.BIT.SCKE = 0; + /* Disable USB peripheral.*/ + if (usbp == &USBD1) { + MSTP(USB0) = 1; + } + } +} + +/** + * @brief USB low level reset routine. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_reset(USBDriver *usbp) { + uint16_t ien = 0; + + if (usbp == &USBD1) { + IEN(USB0,USBI0) = 0; + } + /* Disable interrupts */ + usbp->usb->INTENB0.WORD = 0; + usbp->usb->INTENB1.WORD = 0; + usbp->usb->BRDYENB.WORD = 0; + usbp->usb->NRDYENB.WORD = 0; + usbp->usb->BEMPENB.WORD = 0; + /* Clear interrupt status bits */ + usbp->usb->INTSTS0.WORD = (uint16_t)(~(INTSTS0_VALID|INTSTS0_BRDY| + INTSTS0_BEMP|INTSTS0_CTRT|INTSTS0_DVST|INTSTS0_SOFR|INTSTS0_RESM| + INTSTS0_VBINT)); + usbp->usb->INTSTS1.WORD = (uint16_t)(~((1<<4)|(1<<5)|(1<<6)|(1<<11)|(1<<12)| + (1<<14)|(1<<15))); + + if (usbp->config->sof_cb != NULL) { + ien = INTENB0_SOFE; + } + + /* EP0 initialization.*/ + usbp->epc[0] = &ep0config; + usbp->usb->DCPCFG.WORD = 0; + usbp->usb->DCPMAXP.WORD = USB_EP0_PACKET_SIZE; + usbp->usb->CFIFOSEL.WORD = 0; + + /* Enable the USB interrupts - other interrupts get enabled as the + enumeration process progresses. */ + if (usbp == &USBD1) { + IEN(USB0,USBI0) = 1; + IPR(USB0,USBI0) = RX62N_USB0_IRQ_PRIORITY; + } + usbp->usb->INTENB0.WORD = + INTENB0_BRDYE| + INTENB0_BEMPE| + INTENB0_CTRE| + INTENB0_DVSE| + INTENB0_RSME| + ien| + 0; + usbp->usb->BRDYENB.BIT.PIPE0BRDYE = 1; + usbp->usb->BEMPENB.BIT.PIPE0BEMPE = 1; +} + +/** + * @brief Sets the USB address. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_set_address(USBDriver *usbp) { + + (void)usbp; +} + +/** + * @brief Finalizes the USB configuration process. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_end_configuration(USBDriver *usbp) { + + (void)usbp; +} + +/** + * @brief Enables an endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) { + uint16_t pipecfg; + const USBEndpointConfig *epcp = usbp->epc[ep]; + + chDbgAssert(ep > 0, "usb_lld_init_endpoint(), #1", "invalid endpoint"); + if (ep == 0) + return; + +/* usbp->usb->CFIFOSEL.BIT.CURPIPE = 0;*/ + usbp->usb->PIPESEL.WORD = ep; + + /* Set PID to NAK */ + usb_pipectr_write(usbp, ep, 0); + while (usb_pipectr_read(usbp, ep).BIT.PBUSY); + usb_pipectr_write(usbp, ep, PIPECTR_SQCLR|PIPECTR_ACLRM); + usb_pipectr_write(usbp, ep, 0); +/* + if (epcp->out_cb != NULL) + epcp->out_state->currentBank = 0; +*/ + /* Setting the endpoint type.*/ + switch (epcp->ep_mode & USB_EP_MODE_TYPE) { + case USB_EP_MODE_TYPE_ISOC: + pipecfg = PIPECFG_TYPE_ISO; + break; + case USB_EP_MODE_TYPE_BULK: + pipecfg = PIPECFG_TYPE_BULK; + break; + case USB_EP_MODE_TYPE_INTR: + pipecfg = PIPECFG_TYPE_INT; + break; + default: + /* No control type allowed */ + chDbgAssert((epcp->ep_mode & USB_EP_MODE_TYPE) != USB_EP_MODE_TYPE_CTRL, + "usb_lld_init_endpoint(), #2", "invalid endpoint"); + return; + } + + /* Set direction */ + if (epcp->in_cb != NULL) { + usbp->usb->PIPEMAXP.BIT.MXPS = epcp->in_maxsize; + pipecfg |= PIPECFG_DIR_IN; + } + else { + usbp->usb->PIPEMAXP.BIT.MXPS = epcp->out_maxsize; + pipecfg |= PIPECFG_DIR_OUT; + } + pipecfg |= ep; + usbp->usb->PIPECFG.WORD = pipecfg; + + /* Clear interrupt status flag */ + usbp->usb->BRDYSTS.WORD &= ~(1<usb->BRDYENB.WORD |= (1<usb->PIPESEL.WORD = 0; +} + +/** + * @brief Disables all the active endpoints except the endpoint zero. + * + * @param[in] usbp pointer to the @p USBDriver object + * + * @notapi + */ +void usb_lld_disable_endpoints(USBDriver *usbp) { + usbep_t i; + + /* Disable endpoints interrupt */ + usbp->usb->BRDYENB.WORD = 1; + usbp->usb->BRDYSTS.WORD = ~1; + /* Disable endpoints */ + for (i=0; iusb->PIPESEL.WORD = i+1; + usbp->usb->PIPECFG.BIT.EPNUM = 0; + } + usbp->usb->PIPESEL.WORD = 0; + /* Clear FIFO */ +} + +/** + * @brief Returns the status of an OUT endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The endpoint status. + * @retval EP_STATUS_DISABLED The endpoint is not active. + * @retval EP_STATUS_STALLED The endpoint is stalled. + * @retval EP_STATUS_ACTIVE The endpoint is active. + * + * @notapi + */ +usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) { + usbep_t epPrev = usbp->usb->PIPESEL.BIT.PIPESEL; + + if (ep == 0) + return EP_STATUS_ACTIVE; + usbp->usb->PIPESEL.BIT.PIPESEL = ep; + usbep_t epNum = usbp->usb->PIPECFG.BIT.EPNUM; + usbp->usb->PIPESEL.BIT.PIPESEL = epPrev; + if (epNum) { + if (usb_pipectr_read(usbp, ep).BIT.PID & 2) + return EP_STATUS_STALLED; + } + return EP_STATUS_DISABLED; +} + +/** + * @brief Returns the status of an IN endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return The endpoint status. + * @retval EP_STATUS_DISABLED The endpoint is not active. + * @retval EP_STATUS_STALLED The endpoint is stalled. + * @retval EP_STATUS_ACTIVE The endpoint is active. + * + * @notapi + */ +usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) { + + return usb_lld_get_status_out(usbp, ep); +} + +/** + * @brief Reads a setup packet from the dedicated packet buffer. + * @details This function must be invoked in the context of the @p setup_cb + * callback in order to read the received setup packet. + * @pre In order to use this function the endpoint must have been + * initialized as a control endpoint. + * @post The endpoint is ready to accept another packet. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @param[out] buf buffer where to copy the packet data + * + * @notapi + */ +void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) { + + buf[0] = usbp->usb->USBREQ.WORD & 0xFF; + buf[1] = (usbp->usb->USBREQ.WORD >> 8) & 0xFF; + buf[2] = usbp->usb->USBVAL & 0xFF; + buf[3] = (usbp->usb->USBVAL >> 8) & 0xFF; + buf[4] = usbp->usb->USBINDX & 0xFF; + buf[5] = (usbp->usb->USBINDX >> 8) & 0xFF; + buf[6] = usbp->usb->USBLENG & 0xFF; + buf[7] = (usbp->usb->USBLENG >> 8) & 0xFF; +} + +/** + * @brief Prepares for a receive operation. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep) { + USBOutEndpointState *osp = usbp->epc[ep]->out_state; + + /* Transfer initialization.*/ + if (ep == 0) { + do { + usbp->usb->CFIFOSEL.BIT.ISEL = 0; + } while (usbp->usb->CFIFOSEL.BIT.ISEL); + usbp->usb->DCPCTR.BIT.PID = PID_BUF; + while (!usbp->usb->CFIFOCTR.BIT.FRDY); + } + if (osp->rxsize == 0) /* Special case for zero sized packets.*/ + osp->rxpkts = 1; + else + osp->rxpkts = (uint16_t)((osp->rxsize + usbp->epc[ep]->out_maxsize - 1) / + usbp->epc[ep]->out_maxsize); +} + +/** + * @brief Prepares for a transmit operation. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep) { + size_t n; + USBInEndpointState *isp = usbp->epc[ep]->in_state; + + /* Transfer initialization.*/ + n = isp->txsize; + if (n > (size_t)usbp->epc[ep]->in_maxsize) + n = (size_t)usbp->epc[ep]->in_maxsize; + if (ep == 0) { + do { + usbp->usb->CFIFOSEL.BIT.ISEL = 1; + } while (!usbp->usb->CFIFOSEL.BIT.ISEL); + usbp->usb->DCPCTR.BIT.PID = PID_BUF; + while (!usbp->usb->CFIFOCTR.BIT.FRDY); + if (n == 0) + usbp->usb->CFIFOCTR.BIT.BCLR = 1; + } + else { + usbp->usb->PIPESEL.BIT.PIPESEL = ep; + do { + usbp->usb->D1FIFOSEL.WORD = ep; + } while (usbp->usb->D1FIFOSEL.WORD != ep); + while (!usbp->usb->D1FIFOCTR.BIT.FRDY); + do { + usb_pipectr_write(usbp, ep, PID_BUF); + } while (usb_pipectr_read(usbp, ep).BIT.PID != PID_BUF); + } + if (isp->txqueued) { + usb_packet_write_from_queue(usbp, ep, isp->mode.queue.txqueue, n); + } + else { + usb_packet_write_from_buffer(usbp, ep, isp->mode.linear.txbuf, n); + } +} + +/** + * @brief Starts a receive operation on an OUT endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_start_out(USBDriver *usbp, usbep_t ep) { + + if (ep) + usb_pipectr_write(usbp, ep, PID_BUF); +} + +/** + * @brief Starts a transmit operation on an IN endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_start_in(USBDriver *usbp, usbep_t ep) { + + if (ep == 0) { + if (usbp->epc[ep]->in_state->transmitted < usbp->epc[ep]->in_maxsize) + usbp->usb->CFIFOCTR.BIT.BVAL = 1; + } + else { + if (usbp->epc[ep]->in_state->transmitted < usbp->epc[ep]->in_maxsize) + usbp->usb->D1FIFOCTR.BIT.BVAL = 1; + } +} + +/** + * @brief Brings an OUT endpoint in the stalled state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) { + + if (ep == 0) { + if (usbp->usb->DCPCTR.BIT.PID == PID_NAK) + usbp->usb->DCPCTR.BIT.PID = PID_STALL10; + else + usbp->usb->DCPCTR.BIT.PID = PID_STALL11; + } + else { + if ( usb_pipectr_read(usbp, ep).BIT.PID == PID_NAK) + usb_pipectr_write(usbp, ep, PID_STALL10); + else + usb_pipectr_write(usbp, ep, PID_STALL11); + } +} + +/** + * @brief Brings an IN endpoint in the stalled state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) { + + usb_lld_stall_out(usbp, ep); +} + +/** + * @brief Brings an OUT endpoint in the active state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) { + + if (ep == 0) { + if (usbp->usb->DCPCTR.BIT.PID == PID_STALL11) + usbp->usb->DCPCTR.BIT.PID = PID_STALL10; + usbp->usb->DCPCTR.BIT.PID = PID_NAK; + } + else { + if ( usb_pipectr_read(usbp, ep).BIT.PID == PID_STALL11) + usb_pipectr_write(usbp, ep, PID_STALL10); + usb_pipectr_write(usbp, ep, PID_NAK); + } +} + +/** + * @brief Brings an IN endpoint in the active state. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) { + + usb_lld_clear_out(usbp, ep); +} + +#endif /* HAL_USE_USB */ + +/** @} */ diff --git a/os/hal/platforms/Rx62n/usb_lld.h b/os/hal/platforms/Rx62n/usb_lld.h new file mode 100644 index 000000000..5482fab50 --- /dev/null +++ b/os/hal/platforms/Rx62n/usb_lld.h @@ -0,0 +1,534 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file RX62N/usb_lld.h + * @brief RX62N USB Driver subsystem low level driver header. + * + * @addtogroup USB + * @{ + */ + +#ifndef _USB_LLD_H_ +#define _USB_LLD_H_ + +#if HAL_USE_USB || defined(__DOXYGEN__) + +#include "iodefine_gcc62n.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Maximum endpoint address. + * @details This value does not include the endpoint 0 which is always present. + */ +#define USB_MAX_ENDPOINTS 9 + +/** + * @brief Maximum endpoint 0 size. + */ +#define USB_EP0_PACKET_SIZE 64 /* other values doesn't work ? */ + +/** + * @brief Status stage handling method. + */ +#define USB_EP0_STATUS_STAGE USB_EP0_STATUS_STAGE_HW + +/** + * @brief SET_ADDRESS ack handling method. + */ +#define USB_SET_ADDRESS_ACK_HANDLING USB_SET_ADDRESS_ACK_HW + +/** + * @brief This device requires the address change after the status packet. + */ +#define USB_SET_ADDRESS_MODE USB_EARLY_SET_ADDRESS + +/** + * @brief INTSTS0 bit values. + */ +#define INTSTS0_VBINT (1<<15) +#define INTSTS0_RESM (1<<14) +#define INTSTS0_SOFR (1<<13) +#define INTSTS0_DVST (1<<12) +#define INTSTS0_CTRT (1<<11) +#define INTSTS0_BEMP (1<<10) +#define INTSTS0_NRDY (1<<9) +#define INTSTS0_BRDY (1<<8) +#define INTSTS0_VBSTS (1<<7) +#define INTSTS0_VALID (1<<3) +#define INTSTS0_DVSQ(x) ((x>>4)&7) +#define INTSTS0_CTSQ(x) (x&7) + +/** + * @brief INTENB0 bit values. + */ +#define INTENB0_VBSE (1<<15) +#define INTENB0_RSME (1<<14) +#define INTENB0_SOFE (1<<13) +#define INTENB0_DVSE (1<<12) +#define INTENB0_CTRE (1<<11) +#define INTENB0_BEMPE (1<<10) +#define INTENB0_NRDYE (1<<9) +#define INTENB0_BRDYE (1<<8) + +/** + * @brief PID values. + */ +#define PID_NAK 0 +#define PID_BUF 1 +#define PID_STALL10 2 +#define PID_STALL11 3 +#define PID_MASK 3 + +/** + * @brief CTSQ state values. + */ +#define CTSQ_IDLE_OR_SETUP 0 +#define CTSQ_READ_DATA 1 +#define CTSQ_READ_STATUS 2 +#define CTSQ_WRITE_DATA 3 +#define CTSQ_WRITE_STATUS 4 +#define CTSQ_NODATA_STATUS 5 +#define CTSQ_SEQ_ERROR 6 + +/** + * @brief DVSQ state values. + */ +#define DVSQ_POWERED 0 +#define DVSQ_DEFAULT 1 +#define DVSQ_ADDRESS 2 +#define DVSQ_CONFIGURED 3 +#define DVSQ_SUSPENDED_PWR 4 +#define DVSQ_SUSPENDED_DEF 5 +#define DVSQ_SUSPENDED_ADR 6 +#define DVSQ_SUSPENDED_CFG 7 + +/** + * @brief PIPECFG bit values. + */ +#define PIPECFG_TYPE_BULK (1<<14) +#define PIPECFG_TYPE_INT (2<<14) +#define PIPECFG_TYPE_ISO (3<<14) +#define PIPECFG_DIR_OUT (0<<4) +#define PIPECFG_DIR_IN (1<<4) + +/** + * @brief PIPEnCTR bit values. + */ +#define PIPECTR_SQSET (1<<7) +#define PIPECTR_SQCLR (1<<8) +#define PIPECTR_ACLRM (1<<9) +#define PIPECTR_ATREPM (1<<10) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of an IN endpoint state structure. + */ +typedef struct { + /** + * @brief Buffer mode, queue or linear. + */ + bool_t txqueued; + /** + * @brief Requested transmit transfer size. + */ + size_t txsize; + /** + * @brief Transmitted bytes so far. + */ + size_t txcnt; + /** + * @brief Transmitted bytes in last transaction (interrupt). + */ + size_t transmitted; + union { + struct { + /** + * @brief Pointer to the transmission linear buffer. + */ + const uint8_t *txbuf; + } linear; + struct { + /** + * @brief Pointer to the output queue. + */ + OutputQueue *txqueue; + } queue; + /* End of the mandatory fields.*/ + } mode; +} USBInEndpointState; + +/** + * @brief Type of an OUT endpoint state structure. + */ +typedef struct { + /** + * @brief Buffer mode, queue or linear. + */ + bool_t rxqueued; + /** + * @brief Requested receive transfer size. + */ + size_t rxsize; + /** + * @brief Received bytes so far. + */ + size_t rxcnt; + union { + struct { + /** + * @brief Pointer to the receive linear buffer. + */ + uint8_t *rxbuf; + } linear; + struct { + /** + * @brief Pointer to the input queue. + */ + InputQueue *rxqueue; + } queue; + } mode; + /* End of the mandatory fields.*/ + /** + * @brief Number of packets to receive. + */ + uint16_t rxpkts; + /** + * @brief Number of bytes last received. + */ + uint16_t rxlast; +} USBOutEndpointState; + +/** + * @brief Type of an USB endpoint configuration structure. + * @note Platform specific restrictions may apply to endpoints. + */ +typedef struct { + /** + * @brief Type and mode of the endpoint. + */ + uint32_t ep_mode; + /** + * @brief Setup packet notification callback. + * @details This callback is invoked when a setup packet has been + * received. + * @post The application must immediately call @p usbReadPacket() in + * order to access the received packet. + * @note This field is only valid for @p USB_EP_MODE_TYPE_CTRL + * endpoints, it should be set to @p NULL for other endpoint + * types. + */ + usbepcallback_t setup_cb; + /** + * @brief IN endpoint notification callback. + * @details This field must be set to @p NULL if the IN endpoint is not + * used. + */ + usbepcallback_t in_cb; + /** + * @brief OUT endpoint notification callback. + * @details This field must be set to @p NULL if the OUT endpoint is not + * used. + */ + usbepcallback_t out_cb; + /** + * @brief IN endpoint maximum packet size. + * @details This field must be set to zero if the IN endpoint is not + * used. + */ + uint16_t in_maxsize; + /** + * @brief OUT endpoint maximum packet size. + * @details This field must be set to zero if the OUT endpoint is not + * used. + */ + uint16_t out_maxsize; + /** + * @brief @p USBEndpointState associated to the IN endpoint. + * @details This structure maintains the state of the IN endpoint. + */ + USBInEndpointState *in_state; + /** + * @brief @p USBEndpointState associated to the OUT endpoint. + * @details This structure maintains the state of the OUT endpoint. + */ + USBOutEndpointState *out_state; + /* End of the mandatory fields.*/ + /** + * @brief Reserved field, not currently used. + * @note Initialize this field to 1 in order to be forward compatible. + */ + uint16_t ep_buffers; + /** + * @brief Pointer to a buffer for setup packets. + * @details Setup packets require a dedicated 8-bytes buffer, set this + * field to @p NULL for non-control endpoints. + */ + uint8_t *setup_buf; +} USBEndpointConfig; + +/** + * @brief Type of an USB driver configuration structure. + */ +typedef struct { + /** + * @brief USB events callback. + * @details This callback is invoked when an USB driver event is registered. + */ + usbeventcb_t event_cb; + /** + * @brief Device GET_DESCRIPTOR request callback. + * @note This callback is mandatory and cannot be set to @p NULL. + */ + usbgetdescriptor_t get_descriptor_cb; + /** + * @brief Requests hook callback. + * @details This hook allows to be notified of standard requests or to + * handle non standard requests. + */ + usbreqhandler_t requests_hook_cb; + /** + * @brief Start Of Frame callback. + */ + usbcallback_t sof_cb; + /* End of the mandatory fields.*/ +} USBConfig; + +/** + * @brief Structure representing an USB driver. + */ +struct USBDriver { + /** + * @brief Driver state. + */ + usbstate_t state; + /** + * @brief Current configuration data. + */ + const USBConfig *config; + /** + * @brief Field available to user, it can be used to associate an + * application-defined handler to the USB driver. + */ + void *param; + /** + * @brief Bit map of the transmitting IN endpoints. + */ + uint16_t transmitting; + /** + * @brief Bit map of the receiving OUT endpoints. + */ + uint16_t receiving; + /** + * @brief Active endpoints configurations. + */ + const USBEndpointConfig *epc[USB_MAX_ENDPOINTS + 1]; + /** + * @brief Fields available to user, it can be used to associate an + * application-defined handler to an IN endpoint. + * @note The base index is one, the endpoint zero does not have a + * reserved element in this array. + */ + void *in_params[USB_MAX_ENDPOINTS]; + /** + * @brief Fields available to user, it can be used to associate an + * application-defined handler to an OUT endpoint. + * @note The base index is one, the endpoint zero does not have a + * reserved element in this array. + */ + void *out_params[USB_MAX_ENDPOINTS]; + /** + * @brief Endpoint 0 state. + */ + usbep0state_t ep0state; + /** + * @brief Next position in the buffer to be transferred through endpoint 0. + */ + uint8_t *ep0next; + /** + * @brief Number of bytes yet to be transferred through endpoint 0. + */ + size_t ep0n; + /** + * @brief Endpoint 0 end transaction callback. + */ + usbcallback_t ep0endcb; + /** + * @brief Setup packet buffer. + */ + uint8_t setup[8]; + /** + * @brief Current USB device status. + */ + uint16_t status; + /** + * @brief Assigned USB address. + */ + uint8_t address; + /** + * @brief Current USB device configuration. + */ + uint8_t configuration; +#if defined(USB_DRIVER_EXT_FIELDS) + USB_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief USB hardware registers pointer. + */ + volatile struct st_usb0 *usb; + /** + * @brief Last USB device status. + */ + uint8_t last_dvst; + /** + * @brief Last USB control stage. + */ + uint8_t last_ctsq; + /** + * @brief Current FIFO number (D0 or D1). + */ + uint8_t current_fifo; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the current frame number. + * + * @param[in] usbp pointer to the @p USBDriver object + * @return The current frame number. + * + * @notapi + */ +#define usb_lld_get_frame_number(usbp) ((usbp)->usb->FRMNUM.BIT.FRNM) + +/** + * @brief Returns the exact size of a receive transaction. + * @details The received size can be different from the size specified in + * @p usbStartReceiveI() because the last packet could have a size + * different from the expected one. + * @pre The OUT endpoint must have been configured in transaction mode + * in order to use this function. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return Received data size. + * + * @notapi + */ +#define usb_lld_get_transaction_size(usbp, ep) \ + ((usbp)->epc[ep]->out_state->rxcnt) + +/** + * @brief Triggers status stage for control endpoint. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * + * @notapi + */ +#define usb_lld_end_transaction(usbp, ep) \ + ((usbp)->usb->DCPCTR.BIT.CCPL=1) + +/** + * @brief Returns the exact size of a received packet. + * @pre The OUT endpoint must have been configured in packet mode + * in order to use this function. + * + * @param[in] usbp pointer to the @p USBDriver object + * @param[in] ep endpoint number + * @return Received data size. + * + * @notapi + */ +#define usb_lld_get_packet_size(usbp, ep) \ + ((size_t)((usbp)->epc[ep]->out_state->rxlast) + + +/** + * @brief Connects the USB device. + * + * @api + */ +#define usb_lld_connect_bus(usbp) ((usbp)->usb->SYSCFG.BIT.DPRPU=1) + +/** + * @brief Disconnect the USB device. + * + * @api + */ +#define usb_lld_disconnect_bus(usbp) ((usbp)->usb->SYSCFG.BIT.DPRPU=0) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if RX62N_USE_USB0 || defined(__DOXYGEN__) +extern USBDriver USBD1; +#endif + +#if RX62N_USE_USB1 || defined(__DOXYGEN__) +extern USBDriver USBD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void usb_lld_init(void); + void usb_lld_start(USBDriver *usbp); + void usb_lld_stop(USBDriver *usbp); + void usb_lld_reset(USBDriver *usbp); + void usb_lld_set_address(USBDriver *usbp); + void usb_lld_end_configuration(USBDriver *usbp); + void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep); + void usb_lld_disable_endpoints(USBDriver *usbp); + usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep); + usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep); + void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf); + void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep); + void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep); + void usb_lld_start_out(USBDriver *usbp, usbep_t ep); + void usb_lld_start_in(USBDriver *usbp, usbep_t ep); + void usb_lld_stall_out(USBDriver *usbp, usbep_t ep); + void usb_lld_stall_in(USBDriver *usbp, usbep_t ep); + void usb_lld_clear_out(USBDriver *usbp, usbep_t ep); + void usb_lld_clear_in(USBDriver *usbp, usbep_t ep); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_USB */ + +#endif /* _USB_LLD_H_ */ + +/** @} */ diff --git a/os/hal/src/usb.c b/os/hal/src/usb.c index 1da532abf..55ae89d84 100644 --- a/os/hal/src/usb.c +++ b/os/hal/src/usb.c @@ -627,7 +627,13 @@ void _usb_ep0setup(USBDriver *usbp, usbep_t ep) { return; } } - +#if (USB_SET_ADDRESS_ACK_HANDLING == USB_SET_ADDRESS_ACK_HW) + if (usbp->setup[1] == USB_REQ_SET_ADDRESS) + { + /* Zero-length packet sent by hardware */ + return; + } +#endif /* Transfer preparation. The request handler must have populated correctly the fields ep0next, ep0n and ep0endcb using the macro usbSetupTransfer().*/ @@ -649,10 +655,14 @@ void _usb_ep0setup(USBDriver *usbp, usbep_t ep) { /* No transmission phase, directly receiving the zero sized status packet.*/ usbp->ep0state = USB_EP0_WAITING_STS; +#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW) usbPrepareReceive(usbp, 0, NULL, 0); chSysLockFromIsr(); usbStartReceiveI(usbp, 0); chSysUnlockFromIsr(); +#else + usbSetupEnd(usbp, ep); +#endif } } else { @@ -669,10 +679,14 @@ void _usb_ep0setup(USBDriver *usbp, usbep_t ep) { /* No receive phase, directly sending the zero sized status packet.*/ usbp->ep0state = USB_EP0_SENDING_STS; +#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW) usbPrepareTransmit(usbp, 0, NULL, 0); chSysLockFromIsr(); usbStartTransmitI(usbp, 0); chSysUnlockFromIsr(); +#else + usbSetupEnd(usbp, ep); +#endif } } } @@ -709,10 +723,14 @@ void _usb_ep0in(USBDriver *usbp, usbep_t ep) { case USB_EP0_WAITING_TX0: /* Transmit phase over, receiving the zero sized status packet.*/ usbp->ep0state = USB_EP0_WAITING_STS; +#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW) usbPrepareReceive(usbp, 0, NULL, 0); chSysLockFromIsr(); usbStartReceiveI(usbp, 0); chSysUnlockFromIsr(); +#else + usbSetupEnd(usbp, ep); +#endif return; case USB_EP0_SENDING_STS: /* Status packet sent, invoking the callback if defined.*/ @@ -749,16 +767,22 @@ void _usb_ep0out(USBDriver *usbp, usbep_t ep) { case USB_EP0_RX: /* Receive phase over, sending the zero sized status packet.*/ usbp->ep0state = USB_EP0_SENDING_STS; +#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW) usbPrepareTransmit(usbp, 0, NULL, 0); chSysLockFromIsr(); usbStartTransmitI(usbp, 0); chSysUnlockFromIsr(); +#else + usbSetupEnd(usbp, ep); +#endif return; case USB_EP0_WAITING_STS: /* Status packet received, it must be zero sized, invoking the callback if defined.*/ +#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW) if (usbGetReceiveTransactionSizeI(usbp, 0) != 0) break; +#endif if (usbp->ep0endcb != NULL) usbp->ep0endcb(usbp); usbp->ep0state = USB_EP0_WAITING_SETUP; diff --git a/os/ports/GCC/RX/RX62N/ld/R5F562N8xxxx_ram.ld b/os/ports/GCC/RX/RX62N/ld/R5F562N8xxxx_ram.ld new file mode 100644 index 000000000..edaa3a52b --- /dev/null +++ b/os/ports/GCC/RX/RX62N/ld/R5F562N8xxxx_ram.ld @@ -0,0 +1,167 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/* + * R5F562N8xxxx memory setup (code executed from RAM) + */ +__user_stack_size__ = 0x0; /* not used */ +__irq_stack_size__ = 0x0400; + +MEMORY +{ + ramjumps : org = 0x00000000, len = 0x20 + flash : org = 0x00000020, len = 64k-0x20 + ram : org = 0x00010000, len = 32k + fvectors : org = 0xFFFFFF80, len = 0x80 +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; +__flash_start__ = ORIGIN(flash); +__flash_size__ = LENGTH(flash); + +SECTIONS +{ + . = 0; + _text = .; + + ramjumps : ALIGN(4) + { + KEEP(*(.ramjumps)) + } > ramjumps + + rvectors : ALIGN(4) + { + KEEP(*(.rvectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(4) + { +/* KEEP(*(.text.startup.*))*/ + *(.text P .stub .text.* .gnu.linkonce.t.*) + *(.rodata C C_2 C_1 .rodata.* .gnu.linkonce.r.*) + *(.rodata1) + } > flash +/* + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash +*/ + . = ALIGN(4); + _etext = .; + _textdata = _etext; + + .noinit (NOLOAD) : + { + } > ram + + .stacks : + { + . = ALIGN(4); + __user_stack_base__ = .; + . += __user_stack_size__; + . = ALIGN(4); + __user_stack_end__ = .; + __irq_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __irq_stack_size__; + . = ALIGN(4); + __main_thread_stack_end__ = .; + PROVIDE(__irq_stack_end__ = .); + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data D .data.* .gnu.linkonce.d.*) + . = ALIGN(4); + *(.data1) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + *(.sdata .sdata.* .gnu.linkonce.s.* D_2 D_1) + . = ALIGN(4); + PROVIDE(_edata = .); +/* } > flash*/ + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.sbss .sbss.*) + *(.bss B B_2 B_1 .bss.* .gnu.linkonce.b.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + + . = ALIGN(32); + *(.etherdesc) + PROVIDE(_bss_end = .); + } > ram + + PROVIDE(end = .); + _end = .; + + ___heap_base__ = _end; + ___heap_end__ = __ram_end__; + + fvectors : ALIGN(4) + { + KEEP(*(.fvectors)) + } > fvectors + +} diff --git a/os/ports/GCC/RX/RX62N/rxparams.h b/os/ports/GCC/RX/RX62N/rxparams.h new file mode 100644 index 000000000..26843f63d --- /dev/null +++ b/os/ports/GCC/RX/RX62N/rxparams.h @@ -0,0 +1,59 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file GCC/RX/RX62N/rxparams.h + * @brief Renesas RX parameters for the RX62N. + * + * @defgroup RX_RX62N Specific Parameters + * @ingroup RX_SPECIFIC + * @details This file contains the RX specific parameters for the + * RX62N platform. + * @{ + */ + +#ifndef _RXPARAMS_H_ +#define _RXPARAMS_H_ + +/** + * @brief RX core model. + */ +#define RX_MODEL RX62N + +/** + * @brief Memory Protection unit presence. + */ +#define RX_HAS_MPU TRUE + +/** + * @brief Floating Point unit presence. + */ +#define RX_HAS_FPU TRUE + +#endif /* _RXPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/GCC/RX/RX62N/vectors.c b/os/ports/GCC/RX/RX62N/vectors.c new file mode 100644 index 000000000..1ea079dc0 --- /dev/null +++ b/os/ports/GCC/RX/RX62N/vectors.c @@ -0,0 +1,519 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/RX/RX62N/vectors.c + * @brief Interrupt vectors for the RX family. + * + * @defgroup RX_RX62N_VECTORS RX62N Interrupt Vectors + * @ingroup RX_SPECIFIC + * @details Interrupt vectors for the RX family. + * @{ + */ +#include "ch.h" +#include "hal.h" + + +/** + * @brief Unhandled exceptions handler. + * @details Any undefined exception vector points to this function by default. + * This function simply stops the system into an infinite loop. + * + * @notapi + */ +#if !defined(__DOXYGEN__) +__attribute__ ((naked)) +#endif +void _unhandled_exception(void) { + + while (1); +} + +#if !defined(__DOXYGEN__) +/* hardware vectors */ +extern void ResetHandler(void); +void NMIHandler(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void UndefHandler(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void FPUHandler(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void SVHandler(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +/* relocatable vectors */ +void Excep_BRK(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_BUSERR(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_FCU_FCUERR(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_FCU_FRDYI(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_ICU_SWINT(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_CMTU0_CMT0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_CMTU0_CMT1(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_CMTU1_CMT2(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_CMTU1_CMT3(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_ETHER_EINT(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_USB0_D0FIFO0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_USB0_D1FIFO0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_USB0_USBI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_USB1_D0FIFO1(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_USB1_D1FIFO1(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_USB1_USBI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_RSPI0_SPEI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_RSPI0_SPRI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_RSPI0_SPTI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_RSPI0_SPII0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_RSPI1_SPEI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_RSPI1_SPRI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_RSPI1_SPTI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_RSPI1_SPII1(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_CAN0_ERS0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_CAN0_RXF0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_CAN0_TXF0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_CAN0_RXM0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_CAN0_TXM0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_RTC_PRD(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_RTC_CUP(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_IRQ0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_IRQ1(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_IRQ2(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_IRQ3(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_IRQ4(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_IRQ5(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_IRQ6(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_IRQ7(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_IRQ8(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_IRQ9(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_IRQ10(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_IRQ11(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_IRQ12(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_IRQ13(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_IRQ14(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_IRQ15(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_USB_USBR0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_USB_USBR1(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_RTC_ALM(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_WDT_WOVI(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_AD0_ADI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_AD1_ADI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_S12AD_ADI12(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU0_TGIA0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU0_TGIB0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU0_TGIC0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU0_TGID0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU0_TCIV0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU0_TGIE0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU0_TGIF0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU1_TGIA1(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU1_TGIB1(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU1_TCIV1(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU1_TCIU1(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU2_TGIA2(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU2_TGIB2(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU2_TCIV2(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU2_TCIU2(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU3_TGIA3(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU3_TGIB3(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU3_TGIC3(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU3_TGID3(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU3_TCIV3(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU4_TGIA4(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU4_TGIB4(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU4_TGIC4(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU4_TGID4(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU4_TCIV4(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU5_TCIU5(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU5_TCIV5(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU5_TCIW5(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU6_TGIA6(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU6_TGIB6(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU6_TGIC6(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU6_TGID6(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU6_TCIV6(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU6_TGIE6(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU6_TGIF6(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU7_TGIA7(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU7_TGIB7(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU7_TCIV7(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU7_TCIU7(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU8_TGIA8(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU8_TGIB8(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU8_TCIV8(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU8_TCIU8(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU9_TGIA9(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU9_TGIB9(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU9_TGIC9(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU9_TGID9(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU9_TCIV9(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU10_TGIA10(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU10_TGIB10(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU10_TGIC10(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU10_TGID10(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU10_TCIV10(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU11_TCIU11(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU11_TCIV11(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_MTU11_TCIW11(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_POE_OEI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_POE_OEI2(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_POE_OEI3(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_POE_OEI4(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_TMR0_CMI0A(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_TMR0_CMI0B(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_TMR0_OV0I(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_TMR1_CMI1A(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_TMR1_CMI1B(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_TMR1_OV1I(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_TMR2_CMI2A(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_TMR2_CMI2B(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_TMR2_OV2I(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_TMR3_CMI3A(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_TMR3_CMI3B(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_TMR3_OV3I(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_DMACA_DMAC0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_DMACA_DMAC1(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_DMACA_DMAC2(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_DMACA_DMAC3(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_EXDMAC_DMAC0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_EXDMAC_DMAC1(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_SCI0_ERI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_SCI0_RXI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_SCI0_TXI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_SCI0_TEI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_SCI1_ERI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_SCI1_RXI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_SCI1_TXI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_SCI1_TEI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_SCI2_ERI2(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_SCI2_RXI2(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_SCI2_TXI2(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_SCI2_TEI2(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_SCI3_ERI3(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_SCI3_RXI3(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_SCI3_TXI3(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_SCI3_TEI3(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_SCI5_ERI5(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_SCI5_RXI5(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_SCI5_TXI5(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_SCI5_TEI5(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_SCI6_ERI6(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_SCI6_RXI6(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_SCI6_TXI6(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_SCI6_TEI6(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_RIIC0_EEI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_RIIC0_RXI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_RIIC0_TXI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_RIIC0_TEI0(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_RIIC1_EEI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_RIIC1_RXI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_RIIC1_TXI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +void Excep_RIIC1_TEI1(void)__attribute__((interrupt, weak, alias("_unhandled_exception"))); +#endif + +#if defined(RAMRUN) +__attribute__((naked,section(".ramjumps"))) +void ramjumps(void) +{ + asm volatile ("bra.a _ResetHandler\n\t\ + bra.a _NMIHandler\n\t\ + bra.a _UndefHandler\n\t\ + bra.a _FPUHandler\n\t\ + bra.a _SVHandler\n\t"); +} +#endif + +const unsigned long _hardwareVectors[] __attribute__ ((section (".fvectors"))) = { +/* 0xFFFFFF80 - reserved */ + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, +/* 0xFFFFFFD0 - Supervisor Instruction */ + 16, +/* 0xFFFFFFD4 - reserved */ + 0, 0, +/* 0xFFFFFFDC Undefined Instruction */ + 8, +/* 0xFFFFFFE0 - reserved */ + 0, +/* 0xFFFFFFE4 - Floating Point */ + 12, +/* 0xFFFFFFE8 - reserved */ + 0, 0, 0, 0, +/* 0xFFFFFFF8 - NMI */ + 4, +/* 0xFFFFFFFC - RESET */ + 0 +}; + +void (*_relocatableVectors[256])(void) __attribute__ ((section (".rvectors"))) = { + Excep_BRK, // 0 + _unhandled_exception, // 1 + _unhandled_exception, // 2 + _unhandled_exception, // 3 + _unhandled_exception, // 4 + _unhandled_exception, // 5 + _unhandled_exception, // 6 + _unhandled_exception, // 7 + _unhandled_exception, // 8 + _unhandled_exception, // 9 + _unhandled_exception, // 10 + _unhandled_exception, // 11 + _unhandled_exception, // 12 + _unhandled_exception, // 13 + _unhandled_exception, // 14 + _unhandled_exception, // 15 + Excep_BUSERR, // 16 + _unhandled_exception, // 17 + _unhandled_exception, // 18 + _unhandled_exception, // 19 + _unhandled_exception, // 20 + Excep_FCU_FCUERR, // 21 + _unhandled_exception, // 22 + Excep_FCU_FRDYI, // 23 + _unhandled_exception, // 24 + _unhandled_exception, // 25 + _unhandled_exception, // 26 + Excep_ICU_SWINT, // 27 + Excep_CMTU0_CMT0, // 28 + Excep_CMTU0_CMT1, // 29 + Excep_CMTU1_CMT2, // 30 + Excep_CMTU1_CMT3, // 31 + Excep_ETHER_EINT, // 32 + _unhandled_exception, // 33 + _unhandled_exception, // 34 + _unhandled_exception, // 35 + Excep_USB0_D0FIFO0, // 36 + Excep_USB0_D1FIFO0, // 37 + Excep_USB0_USBI0, // 38 + _unhandled_exception, // 39 + Excep_USB1_D0FIFO1, // 40 + Excep_USB1_D1FIFO1, // 41 + Excep_USB1_USBI1, // 42 + _unhandled_exception, // 43 + Excep_RSPI0_SPEI0, // 44 + Excep_RSPI0_SPRI0, // 45 + Excep_RSPI0_SPTI0, // 46 + Excep_RSPI0_SPII0, // 47 + Excep_RSPI1_SPEI1, // 48 + Excep_RSPI1_SPRI1, // 49 + Excep_RSPI1_SPTI1, // 50 + Excep_RSPI1_SPII1, // 51 + _unhandled_exception, // 52 + _unhandled_exception, // 53 + _unhandled_exception, // 54 + _unhandled_exception, // 55 + Excep_CAN0_ERS0, // 56 + Excep_CAN0_RXF0, // 57 + Excep_CAN0_TXF0, // 58 + Excep_CAN0_RXM0, // 59 + Excep_CAN0_TXM0, // 60 + _unhandled_exception, // 61 + Excep_RTC_PRD, // 62 + Excep_RTC_CUP, // 63 + Excep_IRQ0, // 64 + Excep_IRQ1, // 65 + Excep_IRQ2, // 66 + Excep_IRQ3, // 67 + Excep_IRQ4, // 68 + Excep_IRQ5, // 69 + Excep_IRQ6, // 70 + Excep_IRQ7, // 71 + Excep_IRQ8, // 72 + Excep_IRQ9, // 73 + Excep_IRQ10, // 74 + Excep_IRQ11, // 75 + Excep_IRQ12, // 76 + Excep_IRQ13, // 77 + Excep_IRQ14, // 78 + Excep_IRQ15, // 79 + _unhandled_exception, // 80 + _unhandled_exception, // 81 + _unhandled_exception, // 82 + _unhandled_exception, // 83 + _unhandled_exception, // 84 + _unhandled_exception, // 85 + _unhandled_exception, // 86 + _unhandled_exception, // 87 + _unhandled_exception, // 88 + _unhandled_exception, // 89 + Excep_USB_USBR0, // 90 + Excep_USB_USBR1, // 91 + Excep_RTC_ALM, // 92 + _unhandled_exception, // 93 + _unhandled_exception, // 94 + _unhandled_exception, // 95 + Excep_WDT_WOVI, // 96 + _unhandled_exception, // 97 + Excep_AD0_ADI0, // 98 + Excep_AD1_ADI1, // 99 + _unhandled_exception, // 100 + _unhandled_exception, // 101 + Excep_S12AD_ADI12, // 102 + _unhandled_exception, // 103 + _unhandled_exception, // 104 + _unhandled_exception, // 105 + _unhandled_exception, // 106 + _unhandled_exception, // 107 + _unhandled_exception, // 108 + _unhandled_exception, // 109 + _unhandled_exception, // 110 + _unhandled_exception, // 111 + _unhandled_exception, // 112 + _unhandled_exception, // 113 + Excep_MTU0_TGIA0, // 114 + Excep_MTU0_TGIB0, // 115 + Excep_MTU0_TGIC0, // 116 + Excep_MTU0_TGID0, // 117 + Excep_MTU0_TCIV0, // 118 + Excep_MTU0_TGIE0, // 119 + Excep_MTU0_TGIF0, // 120 + Excep_MTU1_TGIA1, // 121 + Excep_MTU1_TGIB1, // 122 + Excep_MTU1_TCIV1, // 123 + Excep_MTU1_TCIU1, // 124 + Excep_MTU2_TGIA2, // 125 + Excep_MTU2_TGIB2, // 126 + Excep_MTU2_TCIV2, // 127 + Excep_MTU2_TCIU2, // 128 + Excep_MTU3_TGIA3, // 129 + Excep_MTU3_TGIB3, // 130 + Excep_MTU3_TGIC3, // 131 + Excep_MTU3_TGID3, // 132 + Excep_MTU3_TCIV3, // 133 + Excep_MTU4_TGIA4, // 134 + Excep_MTU4_TGIB4, // 135 + Excep_MTU4_TGIC4, // 136 + Excep_MTU4_TGID4, // 137 + Excep_MTU4_TCIV4, // 138 + Excep_MTU5_TCIU5, // 139 + Excep_MTU5_TCIV5, // 140 + Excep_MTU5_TCIW5, // 141 + Excep_MTU6_TGIA6, // 142 + Excep_MTU6_TGIB6, // 143 + Excep_MTU6_TGIC6, // 144 + Excep_MTU6_TGID6, // 145 + Excep_MTU6_TCIV6, // 146 + Excep_MTU6_TGIE6, // 147 + Excep_MTU6_TGIF6, // 148 + Excep_MTU7_TGIA7, // 149 + Excep_MTU7_TGIB7, // 150 + Excep_MTU7_TCIV7, // 151 + Excep_MTU7_TCIU7, // 152 + Excep_MTU8_TGIA8, // 153 + Excep_MTU8_TGIB8, // 154 + Excep_MTU8_TCIV8, // 155 + Excep_MTU8_TCIU8, // 156 + Excep_MTU9_TGIA9, // 157 + Excep_MTU9_TGIB9, // 158 + Excep_MTU9_TGIC9, // 159 + Excep_MTU9_TGID9, // 160 + Excep_MTU9_TCIV9, // 161 + Excep_MTU10_TGIA10, // 162 + Excep_MTU10_TGIB10, // 163 + Excep_MTU10_TGIC10, // 164 + Excep_MTU10_TGID10, // 165 + Excep_MTU10_TCIV10, // 166 + Excep_MTU11_TCIU11, // 167 + Excep_MTU11_TCIV11, // 168 + Excep_MTU11_TCIW11, // 169 + Excep_POE_OEI1, // 170 + Excep_POE_OEI2, // 171 + Excep_POE_OEI3, // 172 + Excep_POE_OEI4, // 173 + Excep_TMR0_CMI0A, // 174 + Excep_TMR0_CMI0B, // 175 + Excep_TMR0_OV0I, // 176 + Excep_TMR1_CMI1A, // 177 + Excep_TMR1_CMI1B, // 178 + Excep_TMR1_OV1I, // 179 + Excep_TMR2_CMI2A, // 180 + Excep_TMR2_CMI2B, // 181 + Excep_TMR2_OV2I, // 182 + Excep_TMR3_CMI3A, // 183 + Excep_TMR3_CMI3B, // 184 + Excep_TMR3_OV3I, // 185 + _unhandled_exception, // 186 + _unhandled_exception, // 187 + _unhandled_exception, // 188 + _unhandled_exception, // 189 + _unhandled_exception, // 190 + _unhandled_exception, // 191 + _unhandled_exception, // 192 + _unhandled_exception, // 193 + _unhandled_exception, // 194 + _unhandled_exception, // 195 + _unhandled_exception, // 196 + _unhandled_exception, // 197 + Excep_DMACA_DMAC0, // 198 + Excep_DMACA_DMAC1, // 199 + Excep_DMACA_DMAC2, // 200 + Excep_DMACA_DMAC3, // 201 + Excep_EXDMAC_DMAC0, // 202 + Excep_EXDMAC_DMAC1, // 203 + _unhandled_exception, // 204 + _unhandled_exception, // 205 + _unhandled_exception, // 206 + _unhandled_exception, // 207 + _unhandled_exception, // 208 + _unhandled_exception, // 209 + _unhandled_exception, // 210 + _unhandled_exception, // 211 + _unhandled_exception, // 212 + _unhandled_exception, // 213 + Excep_SCI0_ERI0, // 214 + Excep_SCI0_RXI0, // 215 + Excep_SCI0_TXI0, // 216 + Excep_SCI0_TEI0, // 217 + Excep_SCI1_ERI1, // 218 + Excep_SCI1_RXI1, // 219 + Excep_SCI1_TXI1, // 220 + Excep_SCI1_TEI1, // 221 + Excep_SCI2_ERI2, // 222 + Excep_SCI2_RXI2, // 223 + Excep_SCI2_TXI2, // 224 + Excep_SCI2_TEI2, // 225 + Excep_SCI3_ERI3, // 226 + Excep_SCI3_RXI3, // 227 + Excep_SCI3_TXI3, // 228 + Excep_SCI3_TEI3, // 229 + _unhandled_exception, // 230 + _unhandled_exception, // 231 + _unhandled_exception, // 232 + _unhandled_exception, // 233 + Excep_SCI5_ERI5, // 234 + Excep_SCI5_RXI5, // 235 + Excep_SCI5_TXI5, // 236 + Excep_SCI5_TEI5, // 237 + Excep_SCI6_ERI6, // 238 + Excep_SCI6_RXI6, // 239 + Excep_SCI6_TXI6, // 240 + Excep_SCI6_TEI6, // 241 + _unhandled_exception, // 242 + _unhandled_exception, // 243 + _unhandled_exception, // 244 + _unhandled_exception, // 245 + Excep_RIIC0_EEI0, // 246 + Excep_RIIC0_RXI0, // 247 + Excep_RIIC0_TXI0, // 248 + Excep_RIIC0_TEI0, // 249 + Excep_RIIC1_EEI1, // 250 + Excep_RIIC1_RXI1, // 251 + Excep_RIIC1_TXI1, // 252 + Excep_RIIC1_TEI1, // 253 + _unhandled_exception, // 254 + _unhandled_exception, // 255 +}; + +/** @} */ diff --git a/os/ports/GCC/RX/chcore.c b/os/ports/GCC/RX/chcore.c new file mode 100644 index 000000000..004fdf36e --- /dev/null +++ b/os/ports/GCC/RX/chcore.c @@ -0,0 +1,150 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file GCC/RX/chcore.c + * @brief Renesas RX architecture port code. + * + * @addtogroup RX_CORE + * @{ + */ + +#include "ch.h" + +/** + * @brief RX initialization code. + * + * @note This function is usually empty. + */ +void port_init(void){ +} + +/** + * @brief Disables all the interrupt sources. + * + * @note Of course non maskable interrupt sources are not included. + */ +void port_disable() { + + asm volatile ("clrpsw I \n\t"); +} + +/** + * @brief Disables the interrupt sources that are not supposed to preempt the kernel. + */ +void port_suspend(void) { + + asm volatile ("clrpsw I \n\t"); +} + +/** + * @brief Enables all the interrupt sources. + */ +void port_enable(void) { + + asm volatile ("setpsw I \n\t"); +} + +/** + * @brief Check if interrupts are enabled. + */ +bool_t port_enabled(void) { + uint32_t psw; + + asm volatile("mvfc PSW,%0 \n\t" + : "=r" (psw) : : ); + return psw & (1<<16) ? true : false; +} + +/** + * @brief Halts the system. + * @details This function is invoked by the operating system when an + * unrecoverable error is detected (for example because a programming + * error in the application code that triggers an assertion while in + * debug mode). + * @note The function is declared as a weak symbol, it is possible to + * redefine it in your application code. + */ +#if !defined(__DOXYGEN__) +__attribute__((weak)) +#endif +void port_halt(void) { + + port_disable(); + while (TRUE) { + } +} + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * + * @param ntp the thread to be switched in + * @param otp the thread to be switched out + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + */ +#if !defined(__DOXYGEN__) +__attribute__((naked, weak)) +#endif +void port_switch(Thread *ntp, Thread *otp) { +/* + register struct intctx *sp asm ("sp"); + asm volatile ("pushm r6-r13 \n\t"); + otp->p_ctx.sp = sp; + sp = ntp->p_ctx.sp; + asm volatile ("popm r6-r13 \n\t"); +*/ +#if !defined(CH_CURRP_REGISTER_CACHE) + asm volatile ("pushm r6-r13 \n\t" + "mov.l r0,12[r2] \n\t" + "mov.l 12[r1],r0 \n\t" + "popm r6-r13 \n\t"); +#else + asm volatile ("pushm r6-r12 \n\t" + "mov r0,12[r2] \n\t" + "mov 12[r1],r0 \n\t" + "popm r6-r12 \n\t"); +#endif + asm volatile ("rts \n\t"); +} + +/** + * @brief Start a thread by invoking its work function. + * @details If the work function returns @p chThdExit() is automatically + * invoked. + */ +void _port_thread_start(void) { + + chSysUnlock(); + asm volatile ("mov.l r11,r1 \n\t" + "jsr r12 \n\t" + "bsr _chThdExit \n\t"); +} + +/** @} */ diff --git a/os/ports/GCC/RX/chcore.h b/os/ports/GCC/RX/chcore.h new file mode 100644 index 000000000..849f2fcca --- /dev/null +++ b/os/ports/GCC/RX/chcore.h @@ -0,0 +1,356 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file RX/chcore.h + * @brief Renesas RX port macros and structures. + * + * @addtogroup RX_CORE + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +/*===========================================================================*/ +/* Port constants. */ +/*===========================================================================*/ + +/* Inclusion of the RX implementation specific parameters.*/ +#include "rxparams.h" + +/* RX model check, only RX62N is supported right now.*/ +#if (RX_MODEL == RX62N) +#else +#error "unknown or unsupported RX model" +#endif + +/*===========================================================================*/ +/* Port statically derived parameters. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port configurable parameters. */ +/*===========================================================================*/ + +/** + * If enabled allows the idle thread to enter a low power mode. + */ +#ifndef RX_ENABLE_WFI_IDLE +#define RX_ENABLE_WFI_IDLE FALSE +#endif + +/*===========================================================================*/ +/* Port exported info. */ +/*===========================================================================*/ + +/** + * Macro defining a generic RX architecture. + */ +#define CH_ARCHITECTURE_RX + +/** + * @brief Name of the implemented architecture. + * @note The value is for documentation only, the real value changes + * depending on the selected architecture, the possible values are: + * - "ARM7". + * - "ARM9". + * . + */ +#define CH_ARCHITECTURE_NAME "RX" + +/** + * @brief Name of the compiler supported by this port. + */ +#define CH_COMPILER_NAME "GCC " __VERSION__ + +/*===========================================================================*/ +/* Port implementation part (common). */ +/*===========================================================================*/ + +/** + * @brief 32 bits stack and memory alignment enforcement. + */ +typedef uint32_t stkalign_t; + +/** + * @brief Generic RX register. + */ +typedef void *regrx_t; + +/** + * @brief Interrupt saved context. + * @details This structure represents the stack frame saved during a + * preemption-capable interrupt handler. These registers are caller-saved in GCC. + */ +struct extctx { +#if defined(RX_USE_FPU) + regrx_t fpsw; +#endif + regrx_t acc_hi; + regrx_t acc_lo; + regrx_t r1; + regrx_t r2; + regrx_t r3; + regrx_t r4; + regrx_t r5; + regrx_t r14; + regrx_t r15; + regrx_t psw; + regrx_t pc; +}; + +/** + * @brief System saved context. + * @details This structure represents the inner stack frame during a context + * switching. These registers are callee-saved in GCC. + */ +struct intctx { + regrx_t r6; + regrx_t r7; + regrx_t r8; + regrx_t r9; + regrx_t r10; + regrx_t r11; + regrx_t r12; +#ifndef CH_CURRP_REGISTER_CACHE +/* -mint-register=1 - reserves R13 */ + regrx_t r13; +#else +#warning CH_CURRP_REGISTER_CACHE feature is not tested. +#endif + regrx_t pc; +}; + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details In this port the structure just holds a pointer to the @p intctx + * structure representing the stack pointer at context switch time. + */ +struct context { + struct intctx *sp; +}; + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.sp = (struct intctx *)((uint8_t *)workspace + \ + wsize - sizeof(struct intctx)); \ + tp->p_ctx.sp->r11 = arg; \ + tp->p_ctx.sp->r12 = pf; \ + tp->p_ctx.sp->pc = _port_thread_start; \ +} + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + */ +#ifndef PORT_IDLE_THREAD_STACK_SIZE +#define PORT_IDLE_THREAD_STACK_SIZE 20 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * This value can be zero on those architecture where there is a + * separate interrupt stack and the stack space between @p intctx and + * @p extctx is known to be zero. + */ +#ifndef PORT_INT_REQUIRED_STACK +/*#define PORT_INT_REQUIRED_STACK 64*/ +#define PORT_INT_REQUIRED_STACK 256 +#endif + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (PORT_INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]; + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#if !defined(RX_USE_FPU) +#define PORT_IRQ_PROLOGUE() { \ + asm volatile ("pushm r14-r15 \n\t" \ + "pushm r1-r5 \n\t" \ + "mvfaclo r1 \n\t" \ + "push r1 \n\t" \ + "mvfachi r1 \n\t" \ + "push r1 \n\t"); \ +} +#else +#define PORT_IRQ_PROLOGUE() { \ + asm volatile ("pushm r14-r15 \n\t" \ + "pushm r1-r5 \n\t" \ + "mvfaclo r1 \n\t" \ + "push r1 \n\t" \ + "mvfachi r1 \n\t" \ + "push r1 \n\t" \ + "pushc FPSW \n\t"); \ +} +#endif +/* #define PORT_IRQ_PROLOGUE() */ + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#if !defined(RX_USE_FPU) +#define PORT_IRQ_EPILOGUE() { \ + dbg_check_lock(); \ + if (chSchIsPreemptionRequired()) { \ + asm volatile ("mvtipl #0 \n\t"); \ + chSchDoReschedule(); \ + } \ + dbg_check_unlock(); \ + asm volatile ("pop r1 \n\t" \ + "mvtachi r1 \n\t" \ + "pop r1 \n\t" \ + "mvtaclo r1 \n\t" \ + "popm r1-r5 \n\t" \ + "popm r14-r15 \n\t" \ + "rte \n\t"); \ +} +#else +#define PORT_IRQ_EPILOGUE() { \ + dbg_check_lock(); \ + if (chSchIsPreemptionRequired()) { \ + asm volatile ("mvtipl #0 \n\t"); \ + chSchDoReschedule(); \ + } \ + asm volatile ("popc FPSW \n\t" \ + "pop r1 \n\t" \ + "mvtachi r1 \n\t" \ + "pop r1 \n\t" \ + "mvtaclo r1 \n\t" \ + "popm r1-r5 \n\t" \ + "popm r14-r15 \n\t" \ + "rte \n\t"); \ +} +#endif + +/** + * IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) void __attribute__((naked)) id(void) + +/** + * @brief Kernel-unlock action. + * @details Usually this function just disables interrupts but may perform more + * actions. + */ +#define port_lock() asm volatile ("clrpsw I \n\t") + +/** + * @brief Kernel-unlock action. + * @details Usually this function just disables interrupts but may perform more + * actions. + */ +#define port_unlock() asm volatile ("setpsw I \n\t") + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details This function is invoked before invoking I-class APIs from + * interrupt handlers. The implementation is architecture dependent, in its + * simplest form it is void. + */ +#define port_lock_from_isr() + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details This function is invoked after invoking I-class APIs from interrupt + * handlers. The implementation is architecture dependent, in its simplest form + * it is void. + */ +#define port_unlock_from_isr() + +/** + * @brief Enters an architecture-dependent IRQ-waiting mode. + * @details The function is meant to return when an interrupt becomes pending. + * The simplest implementation is an empty function or macro but this + * would not take advantage of architecture-specific power saving + * modes. + * @note This port function is implemented as inlined code for performance + * reasons. + */ +#if RX_ENABLE_WFI_IDLE == TRUE +#define port_wait_for_interrupt() { \ + asm volatile ("wait"); \ +} +#else +#define port_wait_for_interrupt() +#endif + + +#ifdef __cplusplus +extern "C" { +#endif + void port_init(void); + void port_disable(void); + void port_suspend(void); + void port_enable(void); + bool_t port_enabled(void); + void port_halt(void); + void port_switch(Thread *ntp, Thread *otp); + void _port_thread_start(void); +#ifdef __cplusplus +} +#endif + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/os/ports/GCC/RX/chtypes.h b/os/ports/GCC/RX/chtypes.h new file mode 100644 index 000000000..35a21e13d --- /dev/null +++ b/os/ports/GCC/RX/chtypes.h @@ -0,0 +1,87 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + + --- + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes ChibiOS/RT, without being obliged to provide + the source code for any proprietary components. See the file exception.txt + for full details of how and when the exception can be applied. +*/ + +/** + * @file RX/chtypes.h + * @brief RX architecture port system types. + * + * @addtogroup RX_CORE + * @{ + */ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +#include +#include +#include + +typedef bool bool_t; /**< Fast boolean type. */ +typedef uint8_t tmode_t; /**< Thread flags. */ +typedef uint8_t tstate_t; /**< Thread state. */ +typedef uint8_t trefs_t; /**< Thread references counter. */ +typedef uint8_t tslices_t; /**< Thread time slices counter. */ +typedef uint32_t tprio_t; /**< Thread priority. */ +typedef int32_t msg_t; /**< Inter-thread message. */ +typedef int32_t eventid_t; /**< Event Id. */ +typedef uint32_t eventmask_t; /**< Event mask. */ +typedef uint32_t flagsmask_t; /**< Event flags. */ +typedef uint32_t systime_t; /**< System time. */ +typedef int32_t cnt_t; /**< Resources counter. */ + +/** + * @brief Inline function modifier. + */ +#define INLINE inline + +/** + * @brief ROM constant modifier. + * @note It is set to use the "const" keyword in this port. + */ +#define ROMCONST const + +/** + * @brief Packed structure modifier (within). + * @note It uses the "packed" GCC attribute. + */ +#define PACK_STRUCT_STRUCT __attribute__((packed)) + +/** + * @brief Packed structure modifier (before). + * @note Empty in this port. + */ +#define PACK_STRUCT_BEGIN + +/** + * @brief Packed structure modifier (after). + * @note Empty in this port. + */ +#define PACK_STRUCT_END + +#endif /* _CHTYPES_H_ */ + +/** @} */ diff --git a/os/ports/GCC/RX/crt0.c b/os/ports/GCC/RX/crt0.c new file mode 100644 index 000000000..13d823df7 --- /dev/null +++ b/os/ports/GCC/RX/crt0.c @@ -0,0 +1,302 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file RX/crt0.c + * @brief Generic RX600 startup file for ChibiOS/RT. + * + * @addtogroup RX_STARTUP + * @{ + */ + +#include "ch.h" + +typedef void (*funcp_t)(void); +typedef funcp_t * funcpp_t; +extern void (*_relocatableVectors[256])(void) __attribute__ ((section (".rvectors"))); +extern void __early_init(void); + +#define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0)) + +/*===========================================================================*/ +/** + * @name Startup settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Stack segments initialization switch. + */ +#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__) +#define CRT0_STACKS_FILL_PATTERN 0x55555555 +#endif + +/** + * @brief Stack segments initialization switch. + */ +#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__) +#define CRT0_INIT_STACKS TRUE +#endif + +/** + * @brief DATA segment initialization switch. + */ +#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__) +#define CRT0_INIT_DATA TRUE +#endif + +/** + * @brief BSS segment initialization switch. + */ +#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__) +#define CRT0_INIT_BSS TRUE +#endif + +/** + * @brief Constructors invocation switch. + */ +#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__) +#define CRT0_CALL_CONSTRUCTORS FALSE +#endif + +/** + * @brief Destructors invocation switch. + */ +#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__) +#define CRT0_CALL_DESTRUCTORS FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Symbols from the scatter file + */ +/*===========================================================================*/ + +/** + * @brief Main stack lower boundary. + * @details This symbol must be exported by the linker script and represents + * the main stack lower boundary. + */ +extern uint32_t __user_stack_base__; + +/** + * + * @brief Main stack initial position. + * @details This symbol must be exported by the linker script and represents + * the main stack initial position. + */ +extern uint32_t __user_stack_end__; + +/** + * @brief Process stack lower boundary. + * @details This symbol must be exported by the linker script and represents + * the process stack lower boundary. + */ +extern uint32_t __irq_stack_base__; + +/** + * @brief Process stack initial position. + * @details This symbol must be exported by the linker script and represents + * the process stack initial position. + */ +extern uint32_t __irq_stack_end__; + +/** + * @brief ROM image of the data segment start. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern uint32_t _textdata; + +/** + * @brief Data segment start. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern uint32_t _data; + +/** + * @brief Data segment end. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern uint32_t _edata; + +/** + * @brief BSS segment start. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern uint32_t _bss_start; + +/** + * @brief BSS segment end. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern uint32_t _bss_end; + +/** + * @brief Constructors table start. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern funcp_t __init_array_start; + +/** + * @brief Constructors table end. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern funcp_t __init_array_end; + +/** + * @brief Destructors table start. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern funcp_t __fini_array_start; + +/** + * @brief Destructors table end. + * @pre The symbol must be aligned to a 32 bits boundary. + */ +extern funcp_t __fini_array_end; + +/** @} */ + +/** + * @brief Application @p main() function. + */ +extern void main(void); + +/** + * @brief Early initialization. + * @details This hook is invoked immediately after the stack initialization + * and before the DATA and BSS segments initialization. The + * default behavior is to do nothing. + * @note This function is a weak symbol. + */ +#if !defined(__DOXYGEN__) +__attribute__((weak)) +#endif +void __early_init(void) {} + +/** + * @brief Late initialization. + * @details This hook is invoked after the DATA and BSS segments + * initialization and before any static constructor. The + * default behavior is to do nothing. + * @note This function is a weak symbol. + */ +#if !defined(__DOXYGEN__) +__attribute__((weak)) +#endif +void __late_init(void) {} + +/** + * @brief Default @p main() function exit handler. + * @details This handler is invoked or the @p main() function exit. The + * default behavior is to enter an infinite loop. + * @note This function is a weak symbol. + */ +#if !defined(__DOXYGEN__) +__attribute__((weak, naked)) +#endif +void _default_exit(void) { + while (1) + ; +} + +/** + * @brief Reset vector. + */ +#if !defined(__DOXYGEN__) +__attribute__((naked)) +#endif +void ResetHandler(void) { + + /* Disable interrupts, ipl=0, supervisor mode, select USP stack */ + asm volatile ("mvtc #0x00000000, PSW"); + + /* Set interrupt stack pointer */ + asm volatile ("mvtc #__irq_stack_end__, ISP"); + /* Set relocatable vectors base */ + asm volatile ("mvtc #__relocatableVectors, INTB"); + + __early_init(); + +#if RX_USE_FPU + asm volatile ("mvtc #0x100, FPSW"); +#endif + +#if defined(CRT0_INIT_STACKS) + /* Stack initialization.*/ + asm volatile ("mov %0, R2" : : "i" (CRT0_STACKS_FILL_PATTERN)); + asm volatile ("mov #__irq_stack_base__, R1"); + asm volatile ("mov #__irq_stack_end__-__irq_stack_base__, R3"); + asm volatile ("sstr.b"); +#endif + + /* copy initialized data */ +#if defined(CRT0_INIT_DATA) + asm volatile ("mov #_data, R1"); + asm volatile ("mov #_textdata, R2"); + asm volatile ("mov #_edata-_data, R3"); + asm volatile ("smovf"); +#endif + +#if defined(CRT0_INIT_BSS) + /* clear bss section */ + asm volatile ("mov #0, R2"); + asm volatile ("mov #_bss_start, R1"); + asm volatile ("mov #_bss_end-_bss_start, R3"); + asm volatile ("sstr.b"); +#endif + +#if CRT0_CALL_CONSTRUCTORS + /* Constructors invocation.*/ + { + funcpp_t fpp = &__init_array_start; + while (fpp < &__init_array_end) { + (*fpp)(); + fpp++; + } + } +#endif + + /* Enable interrupts */ + asm volatile ("setpsw I"); + + /* Invoking application main() function.*/ + main(); + + +#if CRT0_CALL_DESTRUCTORS + /* Destructors invocation.*/ + { + funcpp_t fpp = &__fini_array_start; + while (fpp < &__fini_array_end) { + (*fpp)(); + fpp++; + } + } +#endif + + /* Invoking the exit handler.*/ + _default_exit(); +} + +/** @} */ -- cgit v1.2.3