From 1134fe2a87e70cad601394793f0f01cfef066b70 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 30 Mar 2010 17:04:51 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1814 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/adc_lld.c | 3 +- os/hal/platforms/STM32/adc_lld.h | 4 +- os/hal/platforms/STM32/can_lld.c | 12 ++- os/hal/platforms/STM32/can_lld.h | 4 +- os/hal/platforms/STM32/hal_lld.c | 3 - os/hal/platforms/STM32/pwm_lld.c | 15 ++- os/hal/platforms/STM32/pwm_lld.h | 16 +-- os/hal/platforms/STM32/serial_lld.c | 15 ++- os/hal/platforms/STM32/serial_lld.h | 20 +--- os/hal/platforms/STM32/spi_lld.c | 12 ++- os/hal/platforms/STM32/spi_lld.h | 6 +- os/ports/GCC/ARMCM3/STM32F103/cmparams.h | 65 ------------ os/ports/GCC/ARMCM3/chcore.h | 163 ++++++++++++++++++++++++++++--- os/ports/GCC/ARMCMx/chcore.h | 3 +- 14 files changed, 201 insertions(+), 140 deletions(-) (limited to 'os') diff --git a/os/hal/platforms/STM32/adc_lld.c b/os/hal/platforms/STM32/adc_lld.c index c543b2c73..020b3c688 100644 --- a/os/hal/platforms/STM32/adc_lld.c +++ b/os/hal/platforms/STM32/adc_lld.c @@ -155,7 +155,8 @@ void adc_lld_start(ADCDriver *adcp) { #if USE_STM32_ADC1 if (&ADCD1 == adcp) { dmaEnable(DMA1_ID); /* NOTE: Must be enabled before the IRQs.*/ - NVICEnableVector(DMA1_Channel1_IRQn, STM32_ADC1_IRQ_PRIORITY); + NVICEnableVector(DMA1_Channel1_IRQn, + CORTEX_PRIORITY_MASK(STM32_ADC1_IRQ_PRIORITY)); DMA1_Channel1->CPAR = (uint32_t)&ADC1->DR; RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; } diff --git a/os/hal/platforms/STM32/adc_lld.h b/os/hal/platforms/STM32/adc_lld.h index 134fb9ba4..2b9ac2dd7 100644 --- a/os/hal/platforms/STM32/adc_lld.h +++ b/os/hal/platforms/STM32/adc_lld.h @@ -77,11 +77,9 @@ /** * @brief ADC1 interrupt priority level setting. - * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_ADC1_IRQ_PRIORITY > - * @p CORTEX_PRIORITY_PENDSV. */ #if !defined(STM32_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC1_IRQ_PRIORITY CORTEX_PRIORITY(5) +#define STM32_ADC1_IRQ_PRIORITY 5 #endif /** diff --git a/os/hal/platforms/STM32/can_lld.c b/os/hal/platforms/STM32/can_lld.c index 4b24ec810..6fe3cf30d 100644 --- a/os/hal/platforms/STM32/can_lld.c +++ b/os/hal/platforms/STM32/can_lld.c @@ -174,10 +174,14 @@ void can_lld_start(CANDriver *canp) { /* Clock activation.*/ #if USE_STM32_CAN1 if (&CAND1 == canp) { - NVICEnableVector(USB_HP_CAN1_TX_IRQn, STM32_CAN1_IRQ_PRIORITY); - NVICEnableVector(USB_LP_CAN1_RX0_IRQn, STM32_CAN1_IRQ_PRIORITY); - NVICEnableVector(CAN1_RX1_IRQn, STM32_CAN1_IRQ_PRIORITY); - NVICEnableVector(CAN1_SCE_IRQn, STM32_CAN1_IRQ_PRIORITY); + NVICEnableVector(USB_HP_CAN1_TX_IRQn, + CORTEX_PRIORITY_MASK(STM32_CAN1_IRQ_PRIORITY)); + NVICEnableVector(USB_LP_CAN1_RX0_IRQn, + CORTEX_PRIORITY_MASK(STM32_CAN1_IRQ_PRIORITY)); + NVICEnableVector(CAN1_RX1_IRQn, + CORTEX_PRIORITY_MASK(STM32_CAN1_IRQ_PRIORITY)); + NVICEnableVector(CAN1_SCE_IRQn, + CORTEX_PRIORITY_MASK(STM32_CAN1_IRQ_PRIORITY)); RCC->APB1ENR |= RCC_APB1ENR_CAN1EN; } #endif diff --git a/os/hal/platforms/STM32/can_lld.h b/os/hal/platforms/STM32/can_lld.h index 0e1d0fee0..85d86b0cb 100644 --- a/os/hal/platforms/STM32/can_lld.h +++ b/os/hal/platforms/STM32/can_lld.h @@ -83,11 +83,9 @@ /** * @brief CAN1 interrupt priority level setting. - * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_SPI1_IRQ_PRIORITY > - * @p CORTEX_PRIORITY_PENDSV. */ #if !defined(STM32_CAN1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_CAN1_IRQ_PRIORITY CORTEX_PRIORITY(11) +#define STM32_CAN1_IRQ_PRIORITY 11 #endif /*===========================================================================*/ diff --git a/os/hal/platforms/STM32/hal_lld.c b/os/hal/platforms/STM32/hal_lld.c index b28795ad9..817147026 100644 --- a/os/hal/platforms/STM32/hal_lld.c +++ b/os/hal/platforms/STM32/hal_lld.c @@ -76,9 +76,6 @@ void hal_lld_init(void) { /* Note: PRIGROUP 4:0 (4:4).*/ SCB->AIRCR = (0x05FA << SCB_AIRCR_VECTKEY_Pos) | (3 << SCB_AIRCR_PRIGROUP_Pos); - NVICSetSystemHandlerPriority(HANDLER_SVCALL, CORTEX_PRIORITY_SVCALL); - NVICSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK); - NVICSetSystemHandlerPriority(HANDLER_PENDSV, CORTEX_PRIORITY_PENDSV); /* SysTick initialization using the system clock.*/ SysTick->LOAD = SYSCLK / CH_FREQUENCY - 1; diff --git a/os/hal/platforms/STM32/pwm_lld.c b/os/hal/platforms/STM32/pwm_lld.c index 7e39964c3..ab0649b70 100644 --- a/os/hal/platforms/STM32/pwm_lld.c +++ b/os/hal/platforms/STM32/pwm_lld.c @@ -271,26 +271,31 @@ void pwm_lld_start(PWMDriver *pwmp) { /* Clock activation.*/ #if USE_STM32_PWM1 if (&PWMD1 == pwmp) { - NVICEnableVector(TIM1_UP_IRQn, STM32_PWM1_IRQ_PRIORITY); - NVICEnableVector(TIM1_CC_IRQn, STM32_PWM1_IRQ_PRIORITY); + NVICEnableVector(TIM1_UP_IRQn, + CORTEX_PRIORITY_MASK(STM32_PWM1_IRQ_PRIORITY)); + NVICEnableVector(TIM1_CC_IRQn, + CORTEX_PRIORITY_MASK(STM32_PWM1_IRQ_PRIORITY); RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; } #endif #if USE_STM32_PWM2 if (&PWMD2 == pwmp) { - NVICEnableVector(TIM2_IRQn, STM32_PWM2_IRQ_PRIORITY); + NVICEnableVector(TIM2_IRQn, + CORTEX_PRIORITY_MASK(STM32_PWM2_IRQ_PRIORITY)); RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; } #endif #if USE_STM32_PWM3 if (&PWMD3 == pwmp) { - NVICEnableVector(TIM3_IRQn, STM32_PWM3_IRQ_PRIORITY); + NVICEnableVector(TIM3_IRQn, + CORTEX_PRIORITY_MASK(STM32_PWM3_IRQ_PRIORITY)); RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; } #endif #if USE_STM32_PWM4 if (&PWMD4 == pwmp) { - NVICEnableVector(TIM4_IRQn, STM32_PWM4_IRQ_PRIORITY); + NVICEnableVector(TIM4_IRQn, + CORTEX_PRIORITY_MASK(STM32_PWM4_IRQ_PRIORITY)); RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; } #endif diff --git a/os/hal/platforms/STM32/pwm_lld.h b/os/hal/platforms/STM32/pwm_lld.h index a16b248b1..4249a8514 100644 --- a/os/hal/platforms/STM32/pwm_lld.h +++ b/os/hal/platforms/STM32/pwm_lld.h @@ -80,38 +80,30 @@ /** * @brief PWM1 interrupt priority level setting. - * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_PWM1_IRQ_PRIORITY > - * @p CORTEX_PRIORITY_PENDSV. */ #if !defined(STM32_PWM1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_PWM1_IRQ_PRIORITY CORTEX_PRIORITY(7) +#define STM32_PWM1_IRQ_PRIORITY 7 #endif /** * @brief PWM2 interrupt priority level setting. - * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_PWM2_IRQ_PRIORITY > - * @p CORTEX_PRIORITY_PENDSV. */ #if !defined(STM32_PWM2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_PWM2_IRQ_PRIORITY CORTEX_PRIORITY(7) +#define STM32_PWM2_IRQ_PRIORITY 7 #endif /** * @brief PWM3 interrupt priority level setting. - * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_PWM3_IRQ_PRIORITY > - * @p CORTEX_PRIORITY_PENDSV. */ #if !defined(STM32_PWM3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_PWM3_IRQ_PRIORITY CORTEX_PRIORITY(7) +#define STM32_PWM3_IRQ_PRIORITY 7 #endif /** * @brief PWM4 interrupt priority level setting. - * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_PWM4_IRQ_PRIORITY > - * @p CORTEX_PRIORITY_PENDSV. */ #if !defined(STM32_PWM4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_PWM4_IRQ_PRIORITY CORTEX_PRIORITY(7) +#define STM32_PWM4_IRQ_PRIORITY 7 #endif /*===========================================================================*/ diff --git a/os/hal/platforms/STM32/serial_lld.c b/os/hal/platforms/STM32/serial_lld.c index 33ccd44c1..99a8653ca 100644 --- a/os/hal/platforms/STM32/serial_lld.c +++ b/os/hal/platforms/STM32/serial_lld.c @@ -327,32 +327,37 @@ void sd_lld_start(SerialDriver *sdp) { #if USE_STM32_USART1 if (&SD1 == sdp) { RCC->APB2ENR |= RCC_APB2ENR_USART1EN; - NVICEnableVector(USART1_IRQn, STM32_USART1_PRIORITY); + NVICEnableVector(USART1_IRQn, + CORTEX_PRIORITY_MASK(STM32_USART1_PRIORITY)); } #endif #if USE_STM32_USART2 if (&SD2 == sdp) { RCC->APB1ENR |= RCC_APB1ENR_USART2EN; - NVICEnableVector(USART2_IRQn, STM32_USART2_PRIORITY); + NVICEnableVector(USART2_IRQn, + CORTEX_PRIORITY_MASK(STM32_USART2_PRIORITY)); } #endif #if USE_STM32_USART3 if (&SD3 == sdp) { RCC->APB1ENR |= RCC_APB1ENR_USART3EN; - NVICEnableVector(USART3_IRQn, STM32_USART3_PRIORITY); + NVICEnableVector(USART3_IRQn, + CORTEX_PRIORITY_MASK(STM32_USART3_PRIORITY)); } #endif #if defined(STM32F10X_HD) || defined(STM32F10X_CL) #if USE_STM32_UART4 if (&SD4 == sdp) { RCC->APB1ENR |= RCC_APB1ENR_UART4EN; - NVICEnableVector(UART4_IRQn, STM32_UART4_PRIORITY); + NVICEnableVector(UART4_IRQn, + CORTEX_PRIORITY_MASK(STM32_UART4_PRIORITY)); } #endif #if USE_STM32_UART5 if (&SD5 == sdp) { RCC->APB1ENR |= RCC_APB1ENR_UART5EN; - NVICEnableVector(UART5_IRQn, STM32_UART5_PRIORITY); + NVICEnableVector(UART5_IRQn, + CORTEX_PRIORITY_MASK(STM32_UART5_PRIORITY)); } #endif #endif diff --git a/os/hal/platforms/STM32/serial_lld.h b/os/hal/platforms/STM32/serial_lld.h index eb625230b..861582d54 100644 --- a/os/hal/platforms/STM32/serial_lld.h +++ b/os/hal/platforms/STM32/serial_lld.h @@ -87,48 +87,38 @@ /** * @brief USART1 interrupt priority level setting. - * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_USART1_PRIORITY > - * @p CORTEX_PRIORITY_PENDSV. */ #if !defined(STM32_USART1_PRIORITY) || defined(__DOXYGEN__) -#define STM32_USART1_PRIORITY CORTEX_PRIORITY(12) +#define STM32_USART1_PRIORITY 12 #endif /** * @brief USART2 interrupt priority level setting. - * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_USART2_PRIORITY > - * @p CORTEX_PRIORITY_PENDSV. */ #if !defined(STM32_USART2_PRIORITY) || defined(__DOXYGEN__) -#define STM32_USART2_PRIORITY CORTEX_PRIORITY(12) +#define STM32_USART2_PRIORITY 12) #endif /** * @brief USART3 interrupt priority level setting. - * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_USART3_PRIORITY > - * @p CORTEX_PRIORITY_PENDSV. */ #if !defined(STM32_USART3_PRIORITY) || defined(__DOXYGEN__) -#define STM32_USART3_PRIORITY CORTEX_PRIORITY(12) +#define STM32_USART3_PRIORITY 12 #endif #if defined(STM32F10X_HD) || defined(STM32F10X_CL) || defined(__DOXYGEN__) /** * @brief UART4 interrupt priority level setting. - * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_USART2_PRIORITY > - * @p CORTEX_PRIORITY_PENDSV. */ #if !defined(STM32_UART4_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART4_PRIORITY CORTEX_PRIORITY(12) +#define STM32_UART4_PRIORITY 12 #endif /** * @brief UART5 interrupt priority level setting. - * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_USART2_PRIORITY > - * @p CORTEX_PRIORITY_PENDSV. */ #if !defined(STM32_UART5_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART5_PRIORITY CORTEX_PRIORITY(12) +#define STM32_UART5_PRIORITY 12 #endif #endif diff --git a/os/hal/platforms/STM32/spi_lld.c b/os/hal/platforms/STM32/spi_lld.c index 37961c2a7..af4fdfc3d 100644 --- a/os/hal/platforms/STM32/spi_lld.c +++ b/os/hal/platforms/STM32/spi_lld.c @@ -218,16 +218,20 @@ void spi_lld_start(SPIDriver *spip) { #if USE_STM32_SPI1 if (&SPID1 == spip) { dmaEnable(DMA1_ID); /* NOTE: Must be enabled before the IRQs.*/ - NVICEnableVector(DMA1_Channel2_IRQn, STM32_SPI1_IRQ_PRIORITY); - NVICEnableVector(DMA1_Channel3_IRQn, STM32_SPI1_IRQ_PRIORITY); + NVICEnableVector(DMA1_Channel2_IRQn, + CORTEX_PRIORITY_MASK(STM32_SPI1_IRQ_PRIORITY)); + NVICEnableVector(DMA1_Channel3_IRQn, + CORTEX_PRIORITY_MASK(STM32_SPI1_IRQ_PRIORITY)); RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; } #endif #if USE_STM32_SPI2 if (&SPID2 == spip) { dmaEnable(DMA1_ID); /* NOTE: Must be enabled before the IRQs.*/ - NVICEnableVector(DMA1_Channel4_IRQn, STM32_SPI2_IRQ_PRIORITY); - NVICEnableVector(DMA1_Channel5_IRQn, STM32_SPI2_IRQ_PRIORITY); + NVICEnableVector(DMA1_Channel4_IRQn, + CORTEX_PRIORITY_MASK(STM32_SPI2_IRQ_PRIORITY)); + NVICEnableVector(DMA1_Channel5_IRQn, + CORTEX_PRIORITY_MASK(STM32_SPI2_IRQ_PRIORITY)); RCC->APB1ENR |= RCC_APB1ENR_SPI2EN; } #endif diff --git a/os/hal/platforms/STM32/spi_lld.h b/os/hal/platforms/STM32/spi_lld.h index 8afe01e93..a6ccb8467 100644 --- a/os/hal/platforms/STM32/spi_lld.h +++ b/os/hal/platforms/STM32/spi_lld.h @@ -78,18 +78,16 @@ /** * @brief SPI1 interrupt priority level setting. - * @note @p BASEPRI_KERNEL >= @p STM32_SPI1_IRQ_PRIORITY > @p PRIORITY_PENDSV. */ #if !defined(STM32_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI1_IRQ_PRIORITY CORTEX_PRIORITY(10) +#define STM32_SPI1_IRQ_PRIORITY 10 #endif /** * @brief SPI2 interrupt priority level setting. - * @note @p BASEPRI_KERNEL >= @p STM32_SPI2_IRQ_PRIORITY > @p PRIORITY_PENDSV. */ #if !defined(STM32_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI2_IRQ_PRIORITY CORTEX_PRIORITY(10) +#define STM32_SPI2_IRQ_PRIORITY 10 #endif /** diff --git a/os/ports/GCC/ARMCM3/STM32F103/cmparams.h b/os/ports/GCC/ARMCM3/STM32F103/cmparams.h index a3b481037..a5aed8126 100644 --- a/os/ports/GCC/ARMCM3/STM32F103/cmparams.h +++ b/os/ports/GCC/ARMCM3/STM32F103/cmparams.h @@ -31,13 +31,6 @@ #ifndef _CMPARAMS_H_ #define _CMPARAMS_H_ -/*===========================================================================*/ -/* Constants parameters. */ -/*===========================================================================*/ - -#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */ -#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */ - /** * @brief Cortex core model. */ @@ -55,67 +48,9 @@ /** * @brief Number of bits in priority masks. - * @details The available number of priority levels is equal to - * (1 << @p CORTEX_PRIORITY_BITS). */ #define CORTEX_PRIORITY_BITS 4 -/** - * @brief Priority to priority mask conversion macro. - */ -#define CORTEX_PRIORITY(n) ((n) << (8 - CORTEX_PRIORITY_BITS)) - -/*===========================================================================*/ -/* Configurable parameters. */ -/*===========================================================================*/ - -/** - * @brief BASEPRI user level, 0 = disabled. - */ -#ifndef CORTEX_BASEPRI_USER -#define CORTEX_BASEPRI_USER CORTEX_PRIORITY(0) -#endif - -/** - * @brief BASEPRI level within kernel lock. - * @details Priority levels higher than this one (lower values) are unaffected - * by the OS activity and can be classified as fast interrupt sources, - * see @ref interrupt_classes. - */ -#ifndef CORTEX_BASEPRI_KERNEL -#define CORTEX_BASEPRI_KERNEL CORTEX_PRIORITY(4) -#endif - -/** - * @brief SVCALL handler priority. - * @note This priority must always be one level above the @p BASEPRI_KERNEL - * value. - * @note It is recommended, but not mandatory, to leave this priority level - * for this handler alone. - */ -#ifndef CORTEX_PRIORITY_SVCALL -#define CORTEX_PRIORITY_SVCALL CORTEX_PRIORITY(3) -#endif - -/** - * @brief SYSTICK handler priority. - */ -#ifndef CORTEX_PRIORITY_SYSTICK -#define CORTEX_PRIORITY_SYSTICK CORTEX_PRIORITY(8) -#endif - -/** - * @brief PENDSV handler priority. - * @note It is recommended to leave this priority level for this handler - * alone. - * @note This is a reserved handler and its priority must always be the - * lowest priority in the system in order to be always executed last - * in the interrupt servicing chain. - */ -#ifndef CORTEX_PRIORITY_PENDSV -#define CORTEX_PRIORITY_PENDSV CORTEX_PRIORITY(15) -#endif - #endif /* _CMPARAMS_H_ */ /** @} */ diff --git a/os/ports/GCC/ARMCM3/chcore.h b/os/ports/GCC/ARMCM3/chcore.h index 8c7c5fd69..a720d9ffb 100644 --- a/os/ports/GCC/ARMCM3/chcore.h +++ b/os/ports/GCC/ARMCM3/chcore.h @@ -28,6 +28,8 @@ #ifndef _CHCORE_H_ #define _CHCORE_H_ +#include "nvic.h" + /*===========================================================================*/ /* Port constants. */ /*===========================================================================*/ @@ -39,44 +41,171 @@ */ #define CORTEX_PORT_MODE_ENDOSWITCH +#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */ +#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */ +#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */ +#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */ + +/* Inclusion of the Cortex-Mx implementation specific parameters.*/ +#include "cmparams.h" + +/* Cortex model check, only M3 right now.*/ +#if (CORTEX_MODEL == CORTEX_M3) +#else +#error "unknown or unsupported Cortex-M model" +#endif + + +/*===========================================================================*/ +/* Port derived parameters. */ +/*===========================================================================*/ + +/** + * @brief Priority masking support. + */ +#if defined(CH_ARCHITECTURE_ARM_v7M) || defined(__DOXYGEN__) +#define CORTEX_SUPPORTS_BASEPRI TRUE +#else +#define CORTEX_SUPPORTS_BASEPRI FALSE +#endif + +/** + * @brief Total priority levels. + */ +#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS) + +/** + * @brief Minimum priority level. + * @details This minimum priority level is calculated from the number of + * priority bits supported by the specific Cortex-Mx implementation. + */ +#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1) + +/** + * @brief Maximum priority level. + * @details The maximum allowed priority level is always zero. + */ +#define CORTEX_MAXIMUM_PRIORITY 0 + +/*===========================================================================*/ +/* Port macros. */ +/*===========================================================================*/ + +/** + * @brief Priority level verification macro. + */ +#define CORTEX_IS_VALID_PRIORITY(n) \ + (((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS)) + +/** + * @brief Priority level to priority mask conversion macro. + */ +#define CORTEX_PRIORITY_MASK(n) ((n) << (8 - CORTEX_PRIORITY_BITS)) + /*===========================================================================*/ /* Port configurable parameters. */ /*===========================================================================*/ /** - * @brief Enables the use of the WFI ins. + * @brief Enables the use of the WFI instruction in the idle thread loop. */ #ifndef CORTEX_ENABLE_WFI_IDLE #define CORTEX_ENABLE_WFI_IDLE FALSE #endif +/** + * @brief SYSTICK handler priority. + * @note The default is calculated as the priority level in the middle + * of the priority range. + */ +#ifndef CORTEX_PRIORITY_SYSTICK +#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1) +#else +/* If it is externally redefined then better perform a validity check on it.*/ +#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK) +#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK" +#endif +#endif + +/** + * @brief BASEPRI user level. + */ +#ifndef CORTEX_BASEPRI_USER +#define CORTEX_BASEPRI_USER CORTEX_PRIORITY_MASK(0) +#endif + +/** + * @brief BASEPRI level within kernel lock. + * @details Priority levels higher than this one (lower values) are unaffected + * by the OS activity and can be classified as fast interrupt sources, + * see @ref interrupt_classes. + */ +#ifndef CORTEX_BASEPRI_KERNEL +#define CORTEX_BASEPRI_KERNEL CORTEX_PRIORITY_MASK(CORTEX_MAXIMUM_PRIORITY+4) +#endif + +/** + * @brief PENDSV handler priority. + * @note This priority must always be the lowest one. + * @note It is recommended, but not mandatory, to leave this priority level + * for this handler alone. + */ +#ifndef CORTEX_PRIORITY_PENDSV +#define CORTEX_PRIORITY_PENDSV CORTEX_MINIMUM_PRIORITY +#endif + +/** + * @brief SVCALL handler priority. + * @note This priority must always be one level above the + * @p CORTEX_MAXIMUM_PRIORITY value. + * @note It is recommended, but not mandatory, to leave this priority level + * for this handler alone. + */ +#ifndef CORTEX_PRIORITY_SVCALL +#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 3) +#endif + /*===========================================================================*/ /* Port exported info. */ /*===========================================================================*/ +#if defined(__DOXYGEN__) /** - * @brief Name of the implemented architecture. + * @brief Macro defining the ARM architecture. */ -#define CH_ARCHITECTURE_NAME "ARM" +#define CH_ARCHITECTURE_ARM_vxm -/* Inclusion of the Cortex-M3 implementation specific parameters.*/ -#include "cmparams.h" - -/* Generating model-dependent info.*/ -#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__) /** - * @brief Macro defining the ARM Cortex-M3 architecture. + * @brief Name of the implemented architecture. */ -#define CH_ARCHITECTURE_ARMCM3 +#define CH_ARCHITECTURE_NAME "ARMvx-M" /** * @brief Name of the architecture variant (optional). */ +#define CH_CORE_VARIANT_NAME "Cortex-Mx" +#elif CORTEX_MODEL == CORTEX_M4 +#define CH_ARCHITECTURE_ARM_v7M +#define CH_ARCHITECTURE_NAME "ARMv7-M" +#define CH_CORE_VARIANT_NAME "Cortex-M4" +#elif CORTEX_MODEL == CORTEX_M3 +#define CH_ARCHITECTURE_ARM_v7M +#define CH_ARCHITECTURE_NAME "ARMv7-M" #define CH_CORE_VARIANT_NAME "Cortex-M3" -#else -#error "this ports only supports the Cortex-M3 architecture" +#elif CORTEX_MODEL == CORTEX_M1 +#define CH_ARCHITECTURE_ARM_v6M +#define CH_ARCHITECTURE_NAME "ARMv6-M" +#define CH_CORE_VARIANT_NAME "Cortex-M1" +#elif CORTEX_MODEL == CORTEX_M0 +#define CH_ARCHITECTURE_ARM_v6M +#define CH_ARCHITECTURE_NAME "ARMv6-M" +#define CH_CORE_VARIANT_NAME "Cortex-M0" #endif +/*===========================================================================*/ +/* Port implementation part. */ +/*===========================================================================*/ + /** * @brief 32 bits stack and memory alignment enforcement. */ @@ -231,9 +360,15 @@ struct context { /** * @brief Port-related initialization code. - * @note This function is empty in this port. */ -#define port_init() +#define port_init() { \ + NVICSetSystemHandlerPriority(HANDLER_SVCALL, \ + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); \ + NVICSetSystemHandlerPriority(HANDLER_PENDSV, \ + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \ + NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \ + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \ +} /** * @brief Kernel-lock action. diff --git a/os/ports/GCC/ARMCMx/chcore.h b/os/ports/GCC/ARMCMx/chcore.h index 779485385..d858a806d 100644 --- a/os/ports/GCC/ARMCMx/chcore.h +++ b/os/ports/GCC/ARMCMx/chcore.h @@ -60,8 +60,7 @@ /** * @brief Priority masking support. */ -#if (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4) || \ - defined(__DOXYGEN__) +#if defined(CH_ARCHITECTURE_ARM_v7M) || defined(__DOXYGEN__) #define CORTEX_SUPPORTS_BASEPRI TRUE #else #define CORTEX_SUPPORTS_BASEPRI FALSE -- cgit v1.2.3