From 10e2b91f3ecf6f85f8f4806bd99507e985c01cfe Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 7 Dec 2012 11:52:13 +0000 Subject: GPT, ICU, PWM tested on STM32F3xx. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4882 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/SAM4L/hal_lld.c | 69 ++++++++++++++++++-- os/hal/platforms/SAM4L/hal_lld.h | 99 ++++++++++++++++++++++++++++- os/hal/platforms/STM32/USARTv2/serial_lld.c | 19 +++--- os/hal/platforms/STM32/USARTv2/serial_lld.h | 4 +- os/hal/platforms/STM32F3xx/hal_lld.h | 10 +-- os/hal/platforms/STM32F3xx/platform.mk | 3 + os/hal/platforms/STM32F3xx/stm32_rcc.h | 54 ++++++++++++++++ 7 files changed, 234 insertions(+), 24 deletions(-) (limited to 'os') diff --git a/os/hal/platforms/SAM4L/hal_lld.c b/os/hal/platforms/SAM4L/hal_lld.c index 745da4686..608fb6fe7 100644 --- a/os/hal/platforms/SAM4L/hal_lld.c +++ b/os/hal/platforms/SAM4L/hal_lld.c @@ -33,6 +33,9 @@ /* Driver local definitions. */ /*===========================================================================*/ +#define SAM_PM_UNLOCK(addr) \ + PM->PM_UNLOCK = BPM_UNLOCK_KEY(0xAAu) | BPM_UNLOCK_ADDR(addr) + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -53,17 +56,71 @@ /* Driver exported functions. */ /*===========================================================================*/ -void sam4l_clock_init(void) { +/** + * @brief Enables a module on one of the PBx buses. + * @note PB bridges are assumed to be already enabled. + * + * @param[in] bus_id id of the bus + * @param[in] module module address + */ +void sam_enable_module(uint32_t bus_id, uint32_t module) { + uint32_t mask; + + mask = *(&PM->PM_CPUMASK + bus_id); + mask |= 1U << module; + SAM_PM_UNLOCK(((uint32_t)&PM->PM_CPUMASK - (uint32_t)PM) + (4 * bus_id)); + *(&PM->PM_CPUMASK + bus_id) |= mask; +} + +/** + * @brief Disables a module on one of the PBx buses. + * @note PB bridges are assumed to be already enabled. + * + * @param[in] bus_id id of the bus + * @param[in] module module index + */ +void sam_disable_module(uint32_t bus_id, uint32_t module) { + uint32_t mask; + + mask = *(&PM->PM_CPUMASK + bus_id); + mask &= ~(1U << module); + SAM_PM_UNLOCK(((uint32_t)&PM->PM_CPUMASK - (uint32_t)PM) + (4 * bus_id)); + *(&PM->PM_CPUMASK + bus_id) = mask; +} + +/** + * @brief Clock initialization. + */ +void sam_clock_init(void) { #if SAM_NO_INIT + /* Enables bridges.*/ + sam_enable_module(SAM_CLK_GRP_HSB, SAM_HSB_PBA_BRIDGE); + sam_enable_module(SAM_CLK_GRP_HSB, SAM_HSB_PBB_BRIDGE); + sam_enable_module(SAM_CLK_GRP_HSB, SAM_HSB_PBC_BRIDGE); + sam_enable_module(SAM_CLK_GRP_HSB, SAM_HSB_PBD_BRIDGE); + #if SAM_USE_PICOCACHE - /* Enable the PicoCache.*/ - sysclk_enable_peripheral_clock(HCACHE); - HCACHE->HCACHE_CTRL = HCACHE_CTRL_CEN_YES; - while ((HCACHE->HCACHE_SR & HCACHE_SR_CSTS_EN) == 0) - ; + /* Enable the PicoCache.*/ + sam_enable_module(SAM_CLK_GRP_PBB, SAM_PBB_HRAMC1_DATA); + sam_enable_module(SAM_CLK_GRP_PBB, SAM_PBB_HRAMC1_REGS); + HCACHE->HCACHE_CTRL = HCACHE_CTRL_CEN_YES; + while ((HCACHE->HCACHE_SR & HCACHE_SR_CSTS_EN) == 0) + ; #endif + /* Setting up prescalers.*/ + SAM_PM_UNLOCK((uint32_t)&PM->PM_CPUSEL); + PM->PM_CPUSEL = SAM_CPUSEL; + SAM_PM_UNLOCK((uint32_t)&PM->PM_PBASEL); + PM->PM_PBASEL = SAM_PBASEL; + SAM_PM_UNLOCK((uint32_t)&PM->PM_PBBSEL); + PM->PM_PBBSEL = SAM_PBBSEL; + SAM_PM_UNLOCK((uint32_t)&PM->PM_PBCSEL); + PM->PM_PBCSEL = SAM_PBCSEL; + SAM_PM_UNLOCK((uint32_t)&PM->PM_PBDSEL); + PM->PM_PBDSEL = SAM_PBDSEL; + #endif /* SAM_NO_INIT */ } diff --git a/os/hal/platforms/SAM4L/hal_lld.h b/os/hal/platforms/SAM4L/hal_lld.h index 52e1fd2ec..fe4b7230f 100644 --- a/os/hal/platforms/SAM4L/hal_lld.h +++ b/os/hal/platforms/SAM4L/hal_lld.h @@ -41,10 +41,103 @@ #define HAL_IMPLEMENTS_COUNTERS TRUE /** - * @brief Platform name. + * @brief Platform name */ #define PLATFORM_NAME "SAM4L Series" +/** + * @name BUS IDs + * @{ + */ +#define SAM_CLK_GRP_CPU 0 +#define SAM_CLK_GRP_HSB 1 +#define SAM_CLK_GRP_PBA 2 +#define SAM_CLK_GRP_PBB 3 +#define SAM_CLK_GRP_PBC 4 +#define SAM_CLK_GRP_PBD 5 +/** @} */ + +/** + * @name Clocks derived from the HSB clock + * @{ + */ +#define SAM_HSB_PDCA_HSB 0 +#define SAM_HSB_HFLASHC_DATA 1 +#define SAM_HSB_HRAMC1_DATA 2 +#define SAM_HSB_USBC_DATA 3 +#define SAM_HSB_CRCCU_DATA 4 +#define SAM_HSB_PBA_BRIDGE 5 +#define SAM_HSB_PBB_BRIDGE 6 +#define SAM_HSB_PBC_BRIDGE 7 +#define SAM_HSB_PBD_BRIDGE 8 +#define SAM_HSB_AESA_HSB 9 +/** @} */ + +/** + * @name Clocks derived from the PBA clock + * @{ + */ +#define SAM_PBA_IISC 0 +#define SAM_PBA_SPI 1 +#define SAM_PBA_TC0 2 +#define SAM_PBA_TC1 3 +#define SAM_PBA_TWIM0 4 +#define SAM_PBA_TWIS0 5 +#define SAM_PBA_TWIM1 6 +#define SAM_PBA_TWIS1 7 +#define SAM_PBA_USART0 8 +#define SAM_PBA_USART1 9 +#define SAM_PBA_USART2 10 +#define SAM_PBA_USART3 11 +#define SAM_PBA_ADCIFE 12 +#define SAM_PBA_DACC 13 +#define SAM_PBA_ACIFC 14 +#define SAM_PBA_GLOC 15 +#define SAM_PBA_ABDACB 16 +#define SAM_PBA_TRNG 17 +#define SAM_PBA_PARC 18 +#define SAM_PBA_CATB 19 +#define SAM_PBA_TWIM2 21 +#define SAM_PBA_TWIM3 22 +#define SAM_PBA_LCDCA 23 +/** @} */ + +/** + * @name Clocks derived from the PBB clock + * @{ + */ +#define SAM_PBB_HFLASHC_REGS 0 +#define SAM_PBB_HRAMC1_REGS 1 +#define SAM_PBB_HMATRIX 2 +#define SAM_PBB_PDCA_PB 3 +#define SAM_PBB_CRCCU_REGS 4 +#define SAM_PBB_USBC_REGS 5 +#define SAM_PBB_PEVC 6 +/** @} */ + +/** + * @name Clocks derived from the PBC clock + * @{ + */ +#define SAM_PBC_PM 0 +#define SAM_PBC_CHIPID 1 +#define SAM_PBC_SCIF 2 +#define SAM_PBC_FREQM 3 +#define SAM_PBC_GPIO 4 +/* @} */ + +/** + * @name Clocks derived from the PBD clock + * @{ + */ +#define SAM_PBD_BPM 0 +#define SAM_PBD_BSCIF 1 +#define SAM_PBD_AST 2 +#define SAM_PBD_WDT 3 +#define SAM_PBD_EIC 4 +#define SAM_PBD_PICOUART 5 +/** @} */ + /** * @name MCCTRL register bits definitions * @{ @@ -203,7 +296,9 @@ typedef uint32_t halrtcnt_t; #ifdef __cplusplus extern "C" { #endif - void sam4l_clock_init(void); + void sam_enable_module(uint32_t bus_id, uint32_t module); + void sam_disable_module(uint32_t bus_id, uint32_t module); + void sam_clock_init(void); void hal_lld_init(void); #ifdef __cplusplus } diff --git a/os/hal/platforms/STM32/USARTv2/serial_lld.c b/os/hal/platforms/STM32/USARTv2/serial_lld.c index 6d44d7d23..a97f52b3f 100644 --- a/os/hal/platforms/STM32/USARTv2/serial_lld.c +++ b/os/hal/platforms/STM32/USARTv2/serial_lld.c @@ -88,14 +88,12 @@ static const SerialConfig default_config = * * @param[in] sdp pointer to a @p SerialDriver object * @param[in] config the architecture-dependent serial driver configuration - * @param[in] clock clock in Hz for the specified USART/UART */ -static void usart_init(SerialDriver *sdp, const SerialConfig *config, - uint32_t clock) { +static void usart_init(SerialDriver *sdp, const SerialConfig *config) { USART_TypeDef *u = sdp->usart; /* Baud rate setting.*/ - u->BRR = clock / config->sc_speed; + u->BRR = (uint16_t)(sdp->clock / config->sc_speed); /* Note that some bits are enforced.*/ u->CR2 = config->sc_cr2 | USART_CR2_LBDIE; @@ -372,31 +370,37 @@ void sd_lld_init(void) { #if STM32_SERIAL_USE_USART1 sdObjectInit(&SD1, NULL, notify1); SD1.usart = USART1; + SD1.clock = STM32_USART1CLK; #endif #if STM32_SERIAL_USE_USART2 sdObjectInit(&SD2, NULL, notify2); SD2.usart = USART2; + SD2.clock = STM32_USART2CLK; #endif #if STM32_SERIAL_USE_USART3 sdObjectInit(&SD3, NULL, notify3); SD3.usart = USART3; + SD3.clock = STM32_USART3CLK; #endif #if STM32_SERIAL_USE_UART4 sdObjectInit(&SD4, NULL, notify4); SD4.usart = UART4; + SD4.clock = STM32_UART4CLK; #endif #if STM32_SERIAL_USE_UART5 sdObjectInit(&SD5, NULL, notify5); SD5.usart = UART5; + SD5.clock = STM32_UART5CLK; #endif #if STM32_SERIAL_USE_USART6 sdObjectInit(&SD6, NULL, notify6); SD6.usart = USART6; + SD6.clock = STM32_USART6CLK; #endif } @@ -421,7 +425,6 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { rccEnableUSART1(FALSE); nvicEnableVector(STM32_USART1_NUMBER, CORTEX_PRIORITY_MASK(STM32_SERIAL_USART1_PRIORITY)); - usart_init(sdp, config, STM32_USART1CLK); } #endif #if STM32_SERIAL_USE_USART2 @@ -429,7 +432,6 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { rccEnableUSART2(FALSE); nvicEnableVector(STM32_USART2_NUMBER, CORTEX_PRIORITY_MASK(STM32_SERIAL_USART2_PRIORITY)); - usart_init(sdp, config, STM32_USART2CLK); } #endif #if STM32_SERIAL_USE_USART3 @@ -437,7 +439,6 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { rccEnableUSART3(FALSE); nvicEnableVector(STM32_USART3_NUMBER, CORTEX_PRIORITY_MASK(STM32_SERIAL_USART3_PRIORITY)); - usart_init(sdp, config, STM32_USART3CLK); } #endif #if STM32_SERIAL_USE_UART4 @@ -445,7 +446,6 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { rccEnableUART4(FALSE); nvicEnableVector(STM32_UART4_NUMBER, CORTEX_PRIORITY_MASK(STM32_SERIAL_UART4_PRIORITY)); - usart_init(sdp, config, STM32_UART4CLK); } #endif #if STM32_SERIAL_USE_UART5 @@ -453,7 +453,6 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { rccEnableUART5(FALSE); nvicEnableVector(STM32_UART5_NUMBER, CORTEX_PRIORITY_MASK(STM32_SERIAL_UART5_PRIORITY)); - usart_init(sdp, config, STM32_UART5CLK); } #endif #if STM32_SERIAL_USE_USART6 @@ -461,10 +460,10 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { rccEnableUSART6(FALSE); nvicEnableVector(STM32_USART6_NUMBER, CORTEX_PRIORITY_MASK(STM32_SERIAL_USART6_PRIORITY)); - usart_init(sdp, config, STM32_USART6CLK); } #endif } + usart_init(sdp, config); } /** diff --git a/os/hal/platforms/STM32/USARTv2/serial_lld.h b/os/hal/platforms/STM32/USARTv2/serial_lld.h index d3b3a9352..054e89194 100644 --- a/os/hal/platforms/STM32/USARTv2/serial_lld.h +++ b/os/hal/platforms/STM32/USARTv2/serial_lld.h @@ -252,7 +252,9 @@ typedef struct { uint8_t ob[SERIAL_BUFFERS_SIZE]; \ /* End of the mandatory fields.*/ \ /* Pointer to the USART registers block.*/ \ - USART_TypeDef *usart; + USART_TypeDef *usart; \ + /* Clock frequency for the associated USART/UART.*/ \ + uint32_t clock; /*===========================================================================*/ /* Driver macros. */ diff --git a/os/hal/platforms/STM32F3xx/hal_lld.h b/os/hal/platforms/STM32F3xx/hal_lld.h index 348bba45c..270664abd 100644 --- a/os/hal/platforms/STM32F3xx/hal_lld.h +++ b/os/hal/platforms/STM32F3xx/hal_lld.h @@ -170,11 +170,11 @@ #define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */ #define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */ -#define STM32_PPRE2_DIV1 (0 << 8) /**< HCLK divided by 1. */ -#define STM32_PPRE2_DIV2 (4 << 8) /**< HCLK divided by 2. */ -#define STM32_PPRE2_DIV4 (5 << 8) /**< HCLK divided by 4. */ -#define STM32_PPRE2_DIV8 (6 << 8) /**< HCLK divided by 8. */ -#define STM32_PPRE2_DIV16 (7 << 8) /**< HCLK divided by 16. */ +#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */ +#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */ +#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */ +#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */ +#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */ #define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI/2. */ #define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is diff --git a/os/hal/platforms/STM32F3xx/platform.mk b/os/hal/platforms/STM32F3xx/platform.mk index becb7986c..0401a8ddf 100644 --- a/os/hal/platforms/STM32F3xx/platform.mk +++ b/os/hal/platforms/STM32F3xx/platform.mk @@ -1,6 +1,9 @@ # List of all the STM32F3xx platform files. PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F3xx/stm32_dma.c \ ${CHIBIOS}/os/hal/platforms/STM32F3xx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/SPIv2/spi_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c diff --git a/os/hal/platforms/STM32F3xx/stm32_rcc.h b/os/hal/platforms/STM32F3xx/stm32_rcc.h index 229333104..2144ee041 100644 --- a/os/hal/platforms/STM32F3xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F3xx/stm32_rcc.h @@ -422,6 +422,33 @@ * @name TIM peripherals specific RCC operations * @{ */ +/** + * @brief Enables the TIM1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp) + +/** + * @brief Disables the TIM1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp) + +/** + * @brief Resets the TIM1 peripheral. + * + * @api + */ +#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST) + /** * @brief Enables the TIM2 peripheral clock. * @@ -496,6 +523,33 @@ * @api */ #define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST) + +/** + * @brief Enables the TIM8 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp) + +/** + * @brief Disables the TIM8 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp) + +/** + * @brief Resets the TIM8 peripheral. + * + * @api + */ +#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST) /** @} */ /** -- cgit v1.2.3