From 014b752b76039952754a9285d2af9c0125b50e33 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 12 Nov 2013 10:05:39 +0000
Subject: Fixed bug #439.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6461 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/ports/STM32F0xx/stm32_dma.c | 10 +++++-----
 os/hal/ports/STM32F1xx/stm32_dma.c | 28 ++++++++++++++--------------
 os/hal/ports/STM32F30x/stm32_dma.c | 24 ++++++++++++------------
 os/hal/ports/STM32F37x/stm32_dma.c | 24 ++++++++++++------------
 os/hal/ports/STM32F4xx/stm32_dma.c | 32 ++++++++++++++++----------------
 os/hal/ports/STM32L1xx/stm32_dma.c | 14 +++++++-------
 6 files changed, 66 insertions(+), 66 deletions(-)

(limited to 'os')

diff --git a/os/hal/ports/STM32F0xx/stm32_dma.c b/os/hal/ports/STM32F0xx/stm32_dma.c
index f803f0506..65419feba 100644
--- a/os/hal/ports/STM32F0xx/stm32_dma.c
+++ b/os/hal/ports/STM32F0xx/stm32_dma.c
@@ -114,7 +114,7 @@ OSAL_IRQ_HANDLER(Vector64) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 0;
+  DMA1->IFCR = flags << 0;
   if (dma_isr_redir[0].dma_func)
     dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
 
@@ -134,7 +134,7 @@ OSAL_IRQ_HANDLER(Vector68) {
   /* Check on channel 2.*/
   flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
   if (flags & STM32_DMA_ISR_MASK) {
-    DMA1->IFCR = STM32_DMA_ISR_MASK << 4;
+    DMA1->IFCR = flags << 4;
     if (dma_isr_redir[1].dma_func)
       dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
   }
@@ -142,7 +142,7 @@ OSAL_IRQ_HANDLER(Vector68) {
   /* Check on channel 3.*/
   flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
   if (flags & STM32_DMA_ISR_MASK) {
-    DMA1->IFCR = STM32_DMA_ISR_MASK << 8;
+    DMA1->IFCR = flags << 8;
     if (dma_isr_redir[2].dma_func)
       dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
   }
@@ -163,7 +163,7 @@ OSAL_IRQ_HANDLER(Vector6C) {
   /* Check on channel 4.*/
   flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
   if (flags & STM32_DMA_ISR_MASK) {
-    DMA1->IFCR = STM32_DMA_ISR_MASK << 12;
+    DMA1->IFCR = flags << 12;
     if (dma_isr_redir[3].dma_func)
       dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
   }
@@ -171,7 +171,7 @@ OSAL_IRQ_HANDLER(Vector6C) {
   /* Check on channel 5.*/
   flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
   if (flags & STM32_DMA_ISR_MASK) {
-    DMA1->IFCR = STM32_DMA_ISR_MASK << 16;
+    DMA1->IFCR = flags << 16;
     if (dma_isr_redir[4].dma_func)
       dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
   }
diff --git a/os/hal/ports/STM32F1xx/stm32_dma.c b/os/hal/ports/STM32F1xx/stm32_dma.c
index f8cee45ad..c3b39d37c 100644
--- a/os/hal/ports/STM32F1xx/stm32_dma.c
+++ b/os/hal/ports/STM32F1xx/stm32_dma.c
@@ -128,7 +128,7 @@ OSAL_IRQ_HANDLER(Vector6C) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 0;
+  DMA1->IFCR = flags << 0;
   if (dma_isr_redir[0].dma_func)
     dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
 
@@ -146,7 +146,7 @@ OSAL_IRQ_HANDLER(Vector70) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 4;
+  DMA1->IFCR = flags << 4;
   if (dma_isr_redir[1].dma_func)
     dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
 
@@ -164,7 +164,7 @@ OSAL_IRQ_HANDLER(Vector74) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 8;
+  DMA1->IFCR = flags << 8;
   if (dma_isr_redir[2].dma_func)
     dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
 
@@ -182,7 +182,7 @@ OSAL_IRQ_HANDLER(Vector78) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 12;
+  DMA1->IFCR = flags << 12;
   if (dma_isr_redir[3].dma_func)
     dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
 
@@ -200,7 +200,7 @@ OSAL_IRQ_HANDLER(Vector7C) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 16;
+  DMA1->IFCR = flags << 16;
   if (dma_isr_redir[4].dma_func)
     dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
 
@@ -218,7 +218,7 @@ OSAL_IRQ_HANDLER(Vector80) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 20;
+  DMA1->IFCR = flags << 20;
   if (dma_isr_redir[5].dma_func)
     dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
 
@@ -236,7 +236,7 @@ OSAL_IRQ_HANDLER(Vector84) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 24;
+  DMA1->IFCR = flags << 24;
   if (dma_isr_redir[6].dma_func)
     dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
 
@@ -255,7 +255,7 @@ OSAL_IRQ_HANDLER(Vector120) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 0;
+  DMA2->IFCR = flags << 0;
   if (dma_isr_redir[7].dma_func)
     dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
 
@@ -273,7 +273,7 @@ OSAL_IRQ_HANDLER(Vector124) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 4;
+  DMA2->IFCR = flags << 4;
   if (dma_isr_redir[8].dma_func)
     dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
 
@@ -291,7 +291,7 @@ OSAL_IRQ_HANDLER(Vector128) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 8;
+  DMA2->IFCR = flags << 8;
   if (dma_isr_redir[9].dma_func)
     dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
 
@@ -310,7 +310,7 @@ OSAL_IRQ_HANDLER(Vector12C) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 12;
+  DMA2->IFCR = flags << 12;
   if (dma_isr_redir[10].dma_func)
     dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
 
@@ -328,7 +328,7 @@ OSAL_IRQ_HANDLER(Vector130) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 16;
+  DMA2->IFCR = flags << 16;
   if (dma_isr_redir[11].dma_func)
     dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
 
@@ -350,7 +350,7 @@ OSAL_IRQ_HANDLER(DMA2_Ch4_5_IRQHandler) {
   /* Check on channel 4.*/
   flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
   if (flags & STM32_DMA_ISR_MASK) {
-    DMA2->IFCR = STM32_DMA_ISR_MASK << 12;
+    DMA2->IFCR = flags << 12;
     if (dma_isr_redir[10].dma_func)
       dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
   }
@@ -358,7 +358,7 @@ OSAL_IRQ_HANDLER(DMA2_Ch4_5_IRQHandler) {
   /* Check on channel 5.*/
   flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
   if (flags & STM32_DMA_ISR_MASK) {
-    DMA2->IFCR = STM32_DMA_ISR_MASK << 16;
+    DMA2->IFCR = flags << 16;
     if (dma_isr_redir[11].dma_func)
       dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
   }
diff --git a/os/hal/ports/STM32F30x/stm32_dma.c b/os/hal/ports/STM32F30x/stm32_dma.c
index 9b912e8fb..e18f2f4e1 100644
--- a/os/hal/ports/STM32F30x/stm32_dma.c
+++ b/os/hal/ports/STM32F30x/stm32_dma.c
@@ -121,7 +121,7 @@ OSAL_IRQ_HANDLER(Vector6C) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 0;
+  DMA1->IFCR = flags << 0;
   if (dma_isr_redir[0].dma_func)
     dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
 
@@ -139,7 +139,7 @@ OSAL_IRQ_HANDLER(Vector70) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 4;
+  DMA1->IFCR = flags << 4;
   if (dma_isr_redir[1].dma_func)
     dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
 
@@ -157,7 +157,7 @@ OSAL_IRQ_HANDLER(Vector74) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 8;
+  DMA1->IFCR = flags << 8;
   if (dma_isr_redir[2].dma_func)
     dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
 
@@ -175,7 +175,7 @@ OSAL_IRQ_HANDLER(Vector78) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 12;
+  DMA1->IFCR = flags << 12;
   if (dma_isr_redir[3].dma_func)
     dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
 
@@ -193,7 +193,7 @@ OSAL_IRQ_HANDLER(Vector7C) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 16;
+  DMA1->IFCR = flags << 16;
   if (dma_isr_redir[4].dma_func)
     dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
 
@@ -211,7 +211,7 @@ OSAL_IRQ_HANDLER(Vector80) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 20;
+  DMA1->IFCR = flags << 20;
   if (dma_isr_redir[5].dma_func)
     dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
 
@@ -229,7 +229,7 @@ OSAL_IRQ_HANDLER(Vector84) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 24;
+  DMA1->IFCR = flags << 24;
   if (dma_isr_redir[6].dma_func)
     dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
 
@@ -247,7 +247,7 @@ OSAL_IRQ_HANDLER(Vector120) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 0;
+  DMA2->IFCR = flags << 0;
   if (dma_isr_redir[7].dma_func)
     dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
 
@@ -265,7 +265,7 @@ OSAL_IRQ_HANDLER(Vector124) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 4;
+  DMA2->IFCR = flags << 4;
   if (dma_isr_redir[8].dma_func)
     dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
 
@@ -283,7 +283,7 @@ OSAL_IRQ_HANDLER(Vector128) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 8;
+  DMA2->IFCR = flags << 8;
   if (dma_isr_redir[9].dma_func)
     dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
 
@@ -301,7 +301,7 @@ OSAL_IRQ_HANDLER(Vector12C) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 12;
+  DMA2->IFCR = flags << 12;
   if (dma_isr_redir[10].dma_func)
     dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
 
@@ -319,7 +319,7 @@ OSAL_IRQ_HANDLER(Vector130) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 16;
+  DMA2->IFCR = flags << 16;
   if (dma_isr_redir[11].dma_func)
     dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
 
diff --git a/os/hal/ports/STM32F37x/stm32_dma.c b/os/hal/ports/STM32F37x/stm32_dma.c
index 688d43dfc..4e9052ab1 100644
--- a/os/hal/ports/STM32F37x/stm32_dma.c
+++ b/os/hal/ports/STM32F37x/stm32_dma.c
@@ -121,7 +121,7 @@ OSAL_IRQ_HANDLER(Vector6C) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 0;
+  DMA1->IFCR = flags << 0;
   if (dma_isr_redir[0].dma_func)
     dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
 
@@ -139,7 +139,7 @@ OSAL_IRQ_HANDLER(Vector70) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 4;
+  DMA1->IFCR = flags << 4;
   if (dma_isr_redir[1].dma_func)
     dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
 
@@ -157,7 +157,7 @@ OSAL_IRQ_HANDLER(Vector74) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 8;
+  DMA1->IFCR = flags << 8;
   if (dma_isr_redir[2].dma_func)
     dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
 
@@ -175,7 +175,7 @@ OSAL_IRQ_HANDLER(Vector78) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 12;
+  DMA1->IFCR = flags << 12;
   if (dma_isr_redir[3].dma_func)
     dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
 
@@ -193,7 +193,7 @@ OSAL_IRQ_HANDLER(Vector7C) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 16;
+  DMA1->IFCR = flags << 16;
   if (dma_isr_redir[4].dma_func)
     dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
 
@@ -211,7 +211,7 @@ OSAL_IRQ_HANDLER(Vector80) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 20;
+  DMA1->IFCR = flags << 20;
   if (dma_isr_redir[5].dma_func)
     dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
 
@@ -229,7 +229,7 @@ OSAL_IRQ_HANDLER(Vector84) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 24;
+  DMA1->IFCR = flags << 24;
   if (dma_isr_redir[6].dma_func)
     dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
 
@@ -247,7 +247,7 @@ OSAL_IRQ_HANDLER(Vector120) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 0;
+  DMA2->IFCR = flags << 0;
   if (dma_isr_redir[7].dma_func)
     dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
 
@@ -265,7 +265,7 @@ OSAL_IRQ_HANDLER(Vector124) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 4;
+  DMA2->IFCR = flags << 4;
   if (dma_isr_redir[8].dma_func)
     dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
 
@@ -283,7 +283,7 @@ OSAL_IRQ_HANDLER(Vector128) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 8;
+  DMA2->IFCR = flags << 8;
   if (dma_isr_redir[9].dma_func)
     dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
 
@@ -301,7 +301,7 @@ OSAL_IRQ_HANDLER(Vector12C) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 12;
+  DMA2->IFCR = flags << 12;
   if (dma_isr_redir[10].dma_func)
     dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
 
@@ -319,7 +319,7 @@ OSAL_IRQ_HANDLER(Vector130) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = STM32_DMA_ISR_MASK << 16;
+  DMA2->IFCR = flags << 16;
   if (dma_isr_redir[11].dma_func)
     dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
 
diff --git a/os/hal/ports/STM32F4xx/stm32_dma.c b/os/hal/ports/STM32F4xx/stm32_dma.c
index af3513954..f64e34b4f 100644
--- a/os/hal/ports/STM32F4xx/stm32_dma.c
+++ b/os/hal/ports/STM32F4xx/stm32_dma.c
@@ -130,7 +130,7 @@ OSAL_IRQ_HANDLER(Vector6C) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->LISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA1->LIFCR = STM32_DMA_ISR_MASK << 0;
+  DMA1->LIFCR = flags << 0;
   if (dma_isr_redir[0].dma_func)
     dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
 
@@ -148,7 +148,7 @@ OSAL_IRQ_HANDLER(Vector70) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->LISR >> 6) & STM32_DMA_ISR_MASK;
-  DMA1->LIFCR = STM32_DMA_ISR_MASK << 6;
+  DMA1->LIFCR = flags << 6;
   if (dma_isr_redir[1].dma_func)
     dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
 
@@ -166,7 +166,7 @@ OSAL_IRQ_HANDLER(Vector74) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->LISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA1->LIFCR = STM32_DMA_ISR_MASK << 16;
+  DMA1->LIFCR = flags << 16;
   if (dma_isr_redir[2].dma_func)
     dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
 
@@ -184,7 +184,7 @@ OSAL_IRQ_HANDLER(Vector78) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->LISR >> 22) & STM32_DMA_ISR_MASK;
-  DMA1->LIFCR = STM32_DMA_ISR_MASK << 22;
+  DMA1->LIFCR = flags << 22;
   if (dma_isr_redir[3].dma_func)
     dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
 
@@ -202,7 +202,7 @@ OSAL_IRQ_HANDLER(Vector7C) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->HISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA1->HIFCR = STM32_DMA_ISR_MASK << 0;
+  DMA1->HIFCR = flags << 0;
   if (dma_isr_redir[4].dma_func)
     dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
 
@@ -220,7 +220,7 @@ OSAL_IRQ_HANDLER(Vector80) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->HISR >> 6) & STM32_DMA_ISR_MASK;
-  DMA1->HIFCR = STM32_DMA_ISR_MASK << 6;
+  DMA1->HIFCR = flags << 6;
   if (dma_isr_redir[5].dma_func)
     dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
 
@@ -238,7 +238,7 @@ OSAL_IRQ_HANDLER(Vector84) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->HISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA1->HIFCR = STM32_DMA_ISR_MASK << 16;
+  DMA1->HIFCR = flags << 16;
   if (dma_isr_redir[6].dma_func)
     dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
 
@@ -256,7 +256,7 @@ OSAL_IRQ_HANDLER(VectorFC) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->HISR >> 22) & STM32_DMA_ISR_MASK;
-  DMA1->HIFCR = STM32_DMA_ISR_MASK << 22;
+  DMA1->HIFCR = flags << 22;
   if (dma_isr_redir[7].dma_func)
     dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
 
@@ -274,7 +274,7 @@ OSAL_IRQ_HANDLER(Vector120) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA2->LISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA2->LIFCR = STM32_DMA_ISR_MASK << 0;
+  DMA2->LIFCR = flags << 0;
   if (dma_isr_redir[8].dma_func)
     dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
 
@@ -292,7 +292,7 @@ OSAL_IRQ_HANDLER(Vector124) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA2->LISR >> 6) & STM32_DMA_ISR_MASK;
-  DMA2->LIFCR = STM32_DMA_ISR_MASK << 6;
+  DMA2->LIFCR = flags << 6;
   if (dma_isr_redir[9].dma_func)
     dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
 
@@ -310,7 +310,7 @@ OSAL_IRQ_HANDLER(Vector128) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA2->LISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA2->LIFCR = STM32_DMA_ISR_MASK << 16;
+  DMA2->LIFCR = flags << 16;
   if (dma_isr_redir[10].dma_func)
     dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
 
@@ -328,7 +328,7 @@ OSAL_IRQ_HANDLER(Vector12C) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA2->LISR >> 22) & STM32_DMA_ISR_MASK;
-  DMA2->LIFCR = STM32_DMA_ISR_MASK << 22;
+  DMA2->LIFCR = flags << 22;
   if (dma_isr_redir[11].dma_func)
     dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
 
@@ -346,7 +346,7 @@ OSAL_IRQ_HANDLER(Vector130) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA2->HISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA2->HIFCR = STM32_DMA_ISR_MASK << 0;
+  DMA2->HIFCR = flags << 0;
   if (dma_isr_redir[12].dma_func)
     dma_isr_redir[12].dma_func(dma_isr_redir[12].dma_param, flags);
 
@@ -364,7 +364,7 @@ OSAL_IRQ_HANDLER(Vector150) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA2->HISR >> 6) & STM32_DMA_ISR_MASK;
-  DMA2->HIFCR = STM32_DMA_ISR_MASK << 6;
+  DMA2->HIFCR = flags << 6;
   if (dma_isr_redir[13].dma_func)
     dma_isr_redir[13].dma_func(dma_isr_redir[13].dma_param, flags);
 
@@ -382,7 +382,7 @@ OSAL_IRQ_HANDLER(Vector154) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA2->HISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA2->HIFCR = STM32_DMA_ISR_MASK << 16;
+  DMA2->HIFCR = flags << 16;
   if (dma_isr_redir[14].dma_func)
     dma_isr_redir[14].dma_func(dma_isr_redir[14].dma_param, flags);
 
@@ -400,7 +400,7 @@ OSAL_IRQ_HANDLER(Vector158) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA2->HISR >> 22) & STM32_DMA_ISR_MASK;
-  DMA2->HIFCR = STM32_DMA_ISR_MASK << 22;
+  DMA2->HIFCR = flags << 22;
   if (dma_isr_redir[15].dma_func)
     dma_isr_redir[15].dma_func(dma_isr_redir[15].dma_param, flags);
 
diff --git a/os/hal/ports/STM32L1xx/stm32_dma.c b/os/hal/ports/STM32L1xx/stm32_dma.c
index 0b7623281..46faae429 100644
--- a/os/hal/ports/STM32L1xx/stm32_dma.c
+++ b/os/hal/ports/STM32L1xx/stm32_dma.c
@@ -116,7 +116,7 @@ OSAL_IRQ_HANDLER(Vector6C) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 0;
+  DMA1->IFCR = flags << 0;
   if (dma_isr_redir[0].dma_func)
     dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
 
@@ -134,7 +134,7 @@ OSAL_IRQ_HANDLER(Vector70) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 4;
+  DMA1->IFCR = flags << 4;
   if (dma_isr_redir[1].dma_func)
     dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
 
@@ -152,7 +152,7 @@ OSAL_IRQ_HANDLER(Vector74) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 8;
+  DMA1->IFCR = flags << 8;
   if (dma_isr_redir[2].dma_func)
     dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
 
@@ -170,7 +170,7 @@ OSAL_IRQ_HANDLER(Vector78) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 12;
+  DMA1->IFCR = flags << 12;
   if (dma_isr_redir[3].dma_func)
     dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
 
@@ -188,7 +188,7 @@ OSAL_IRQ_HANDLER(Vector7C) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 16;
+  DMA1->IFCR = flags << 16;
   if (dma_isr_redir[4].dma_func)
     dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
 
@@ -206,7 +206,7 @@ OSAL_IRQ_HANDLER(Vector80) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 20;
+  DMA1->IFCR = flags << 20;
   if (dma_isr_redir[5].dma_func)
     dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
 
@@ -224,7 +224,7 @@ OSAL_IRQ_HANDLER(Vector84) {
   OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = STM32_DMA_ISR_MASK << 24;
+  DMA1->IFCR = flags << 24;
   if (dma_isr_redir[6].dma_func)
     dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
 
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