From 3b0fd0fa92ec80455944ff3313b24df0644d73a9 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 14 Oct 2014 08:38:51 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7394 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/rt/ports/ARM/compilers/GCC/chcoreasm.s | 18 ++++++++++++++++++ os/rt/ports/ARM/compilers/GCC/mk/port_lpc214x.mk | 1 - 2 files changed, 18 insertions(+), 1 deletion(-) (limited to 'os/rt') diff --git a/os/rt/ports/ARM/compilers/GCC/chcoreasm.s b/os/rt/ports/ARM/compilers/GCC/chcoreasm.s index 3667a0e80..7c33135bf 100644 --- a/os/rt/ports/ARM/compilers/GCC/chcoreasm.s +++ b/os/rt/ports/ARM/compilers/GCC/chcoreasm.s @@ -26,7 +26,9 @@ * @{ */ +#define __FROM_ASM__ #include "chconf.h" +#include "armparams.h" #define FALSE 0 #define TRUE 1 @@ -136,6 +138,22 @@ _port_switch_arm: ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} #endif /* !defined(THUMB_PRESENT) */ +/* + * Common IRQ code. It expects a macro ARM_IRQ_VECTOR_REG with the address + * of a register holding the address of the ISR to be invoked, the IRS will + * then return in the common epilogue code where the context switch will + * be performed if required. + */ + .code 32 + .func + .global Irq_Handler +Irq_Handler: + stmfd sp!, {r0-r3, r12, lr} + ldr r0, =ARM_IRQ_VECTOR_REG + ldr r0, [r0] + ldr lr, =_port_irq_common + bx r0 + /* * Common exit point for all IRQ routines, it performs the rescheduling if * required. diff --git a/os/rt/ports/ARM/compilers/GCC/mk/port_lpc214x.mk b/os/rt/ports/ARM/compilers/GCC/mk/port_lpc214x.mk index 1f91d144d..68ea1cdf7 100644 --- a/os/rt/ports/ARM/compilers/GCC/mk/port_lpc214x.mk +++ b/os/rt/ports/ARM/compilers/GCC/mk/port_lpc214x.mk @@ -2,7 +2,6 @@ PORTSRC = ${CHIBIOS}/os/rt/ports/ARM/chcore.c PORTASM = $(CHIBIOS)/os/common/ports/ARM/compilers/GCC/vectors.s \ - $(CHIBIOS)/os/common/ports/ARM/compilers/GCC/irq.s \ $(CHIBIOS)/os/common/ports/ARM/compilers/GCC/crt0.s \ $(CHIBIOS)/os/rt/ports/ARM/compilers/GCC/chcoreasm.s -- cgit v1.2.3