From 4efde56cebd1b9164e3a44b8f6e0155b73ec6b9a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 22 Dec 2010 14:46:41 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2523 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/ports/RVCT/ARMCMx/STM32/cmparams.h | 2 +- os/ports/RVCT/ARMCMx/chcore.c | 4 +- os/ports/RVCT/ARMCMx/chcore.h | 4 +- os/ports/RVCT/ARMCMx/chcore_v7m.c | 4 +- os/ports/RVCT/ARMCMx/chcore_v7m.h | 4 +- os/ports/RVCT/ARMCMx/chtypes.h | 4 +- os/ports/RVCT/ARMCMx/nvic.c | 4 +- os/ports/RVCT/ARMCMx/nvic.h | 4 +- os/ports/RVCT/ARMCMx/port.dox | 211 ++++++++++++++++++++++++++++++++++ os/ports/ports.dox | 7 ++ 10 files changed, 233 insertions(+), 15 deletions(-) create mode 100644 os/ports/RVCT/ARMCMx/port.dox (limited to 'os/ports') diff --git a/os/ports/RVCT/ARMCMx/STM32/cmparams.h b/os/ports/RVCT/ARMCMx/STM32/cmparams.h index de07b7c67..1c068ecbe 100644 --- a/os/ports/RVCT/ARMCMx/STM32/cmparams.h +++ b/os/ports/RVCT/ARMCMx/STM32/cmparams.h @@ -18,7 +18,7 @@ */ /** - * @file STM32/cmparams.h + * @file RVCT/ARMCMx/STM32/cmparams.h * @brief ARM Cortex-M3 parameters for the STM32. * * @defgroup ARMCMx_STM32 STM32 Specific Parameters diff --git a/os/ports/RVCT/ARMCMx/chcore.c b/os/ports/RVCT/ARMCMx/chcore.c index 2f2122ae4..56ddcb6bc 100644 --- a/os/ports/RVCT/ARMCMx/chcore.c +++ b/os/ports/RVCT/ARMCMx/chcore.c @@ -18,10 +18,10 @@ */ /** - * @file IAR/ARMCMx/chcore.c + * @file RVCT/ARMCMx/chcore.c * @brief ARM Cortex-Mx port code. * - * @addtogroup IAR_ARMCMx_CORE + * @addtogroup RVCT_ARMCMx_CORE * @{ */ diff --git a/os/ports/RVCT/ARMCMx/chcore.h b/os/ports/RVCT/ARMCMx/chcore.h index d07d585a9..a8c8d7496 100644 --- a/os/ports/RVCT/ARMCMx/chcore.h +++ b/os/ports/RVCT/ARMCMx/chcore.h @@ -18,10 +18,10 @@ */ /** - * @file IAR/ARMCMx/chcore.h + * @file RVCT/ARMCMx/chcore.h * @brief ARM Cortex-Mx port macros and structures. * - * @addtogroup IAR_ARMCMx_CORE + * @addtogroup RVCT_ARMCMx_CORE * @{ */ diff --git a/os/ports/RVCT/ARMCMx/chcore_v7m.c b/os/ports/RVCT/ARMCMx/chcore_v7m.c index fe267b9e9..84d1c97a1 100644 --- a/os/ports/RVCT/ARMCMx/chcore_v7m.c +++ b/os/ports/RVCT/ARMCMx/chcore_v7m.c @@ -18,10 +18,10 @@ */ /** - * @file IAR/ARMCMx/chcore_v7m.c + * @file RVCT/ARMCMx/chcore_v7m.c * @brief ARMv7-M architecture port code. * - * @addtogroup IAR_ARMCMx_V7M_CORE + * @addtogroup RVCT_ARMCMx_V7M_CORE * @{ */ diff --git a/os/ports/RVCT/ARMCMx/chcore_v7m.h b/os/ports/RVCT/ARMCMx/chcore_v7m.h index 57b18f980..528144173 100644 --- a/os/ports/RVCT/ARMCMx/chcore_v7m.h +++ b/os/ports/RVCT/ARMCMx/chcore_v7m.h @@ -18,10 +18,10 @@ */ /** - * @file IAR/ARMCMx/chcore_v7m.h + * @file RVCT/ARMCMx/chcore_v7m.h * @brief ARMv7-M architecture port macros and structures. * - * @addtogroup IAR_ARMCMx_V7M_CORE + * @addtogroup RVCT_ARMCMx_V7M_CORE * @{ */ diff --git a/os/ports/RVCT/ARMCMx/chtypes.h b/os/ports/RVCT/ARMCMx/chtypes.h index 3386f5d4b..af8d64eb8 100644 --- a/os/ports/RVCT/ARMCMx/chtypes.h +++ b/os/ports/RVCT/ARMCMx/chtypes.h @@ -18,10 +18,10 @@ */ /** - * @file IAR/ARMCMx/chtypes.h + * @file RVCT/ARMCMx/chtypes.h * @brief ARM Cortex-Mx port system types. * - * @addtogroup IAR_ARMCMx_CORE + * @addtogroup RVCT_ARMCMx_CORE * @{ */ diff --git a/os/ports/RVCT/ARMCMx/nvic.c b/os/ports/RVCT/ARMCMx/nvic.c index 93dbd6ba4..568c4a23e 100644 --- a/os/ports/RVCT/ARMCMx/nvic.c +++ b/os/ports/RVCT/ARMCMx/nvic.c @@ -18,10 +18,10 @@ */ /** - * @file IAR/ARMCMx/nvic.c + * @file RVCT/ARMCMx/nvic.c * @brief Cortex-Mx NVIC support code. * - * @addtogroup IAR_ARMCMx_NVIC + * @addtogroup RVCT_ARMCMx_NVIC * @{ */ diff --git a/os/ports/RVCT/ARMCMx/nvic.h b/os/ports/RVCT/ARMCMx/nvic.h index 321a0ed7b..590deae24 100644 --- a/os/ports/RVCT/ARMCMx/nvic.h +++ b/os/ports/RVCT/ARMCMx/nvic.h @@ -18,10 +18,10 @@ */ /** - * @file IAR/ARMCMx/nvic.h + * @file RVCT/ARMCMx/nvic.h * @brief Cortex-Mx NVIC support macros and structures. * - * @addtogroup IAR_ARMCMx_NVIC + * @addtogroup RVCT_ARMCMx_NVIC * @{ */ diff --git a/os/ports/RVCT/ARMCMx/port.dox b/os/ports/RVCT/ARMCMx/port.dox new file mode 100644 index 000000000..0e65f8c2b --- /dev/null +++ b/os/ports/RVCT/ARMCMx/port.dox @@ -0,0 +1,211 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup RVCT_ARMCMx ARM Cortex-Mx + * @details ARM Cortex-Mx port for the RVCT compiler. + + * @section RVCT_ARMCMx_INTRO Introduction + * This port supports all the cores implementing the ARMv6-M and ARMv7-M + * architectures. + * + * @section RVCT_ARMCMx_STATES_A System logical states in ARMv6-M mode + * The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM + * Cortex-M0 port: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated. + * - Normal. This is the state the system has after executing + * @p chSysInit(). In this state interrupts are enabled. The processor + * is running in thread-privileged mode. + * - Suspended. In this state the interrupt sources are globally + * disabled. The processor is running in thread-privileged mode. In this + * mode this state is not different from the Disabled state. + * - Disabled. In this state the interrupt sources are globally + * disabled. The processor is running in thread-privileged mode. In this + * mode this state is not different from the Suspended state. + * - Sleep. This state is entered with the execution of the specific + * instruction @p wfi. + * - S-Locked. In this state the interrupt sources are globally + * disabled. The processor is running in thread-privileged mode. + * - I-Locked. In this state the interrupt sources are globally + * disabled. The processor is running in exception-privileged mode. + * - Serving Regular Interrupt. In this state the interrupt sources are + * not globally masked but only interrupts with higher priority can preempt + * the current handler. The processor is running in exception-privileged + * mode. + * - Serving Fast Interrupt. This state is not implemented in the + * ARMv6-M implementation. + * - Serving Non-Maskable Interrupt. The Cortex-M3 has a specific + * asynchronous NMI vector and several synchronous fault vectors that can + * be considered belonging to this category. + * - Halted. Implemented as an infinite loop after globally masking all + * the maskable interrupt sources. The ARM state is whatever the processor + * was running when @p chSysHalt() was invoked. + * + * @section RVCT_ARMCMx_STATES_B System logical states in ARMv7-M mode + * The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM + * Cortex-M3 port: + * - Init. This state is represented by the startup code and the + * initialization code before @p chSysInit() is executed. It has not a + * special hardware state associated. + * - Normal. This is the state the system has after executing + * @p chSysInit(). In this state the ARM Cortex-M3 has the BASEPRI register + * set at @p CORTEX_BASEPRI_USER level, interrupts are not masked. The + * processor is running in thread-privileged mode. + * - Suspended. In this state the interrupt sources are not globally + * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus + * masking any interrupt source with lower or equal priority. The processor + * is running in thread-privileged mode. + * - Disabled. Interrupt sources are globally masked. The processor + * is running in thread-privileged mode. + * - Sleep. This state is entered with the execution of the specific + * instruction @p wfi. + * - S-Locked. In this state the interrupt sources are not globally + * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus + * masking any interrupt source with lower or equal priority. The processor + * is running in thread-privileged mode. + * - I-Locked. In this state the interrupt sources are not globally + * masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus + * masking any interrupt source with lower or equal priority. The processor + * is running in exception-privileged mode. + * - Serving Regular Interrupt. In this state the interrupt sources are + * not globally masked but only interrupts with higher priority can preempt + * the current handler. The processor is running in exception-privileged + * mode. + * - Serving Fast Interrupt. It is basically the same of the SRI state + * but it is not possible to switch to the I-Locked state because fast + * interrupts can preempt the kernel critical zone. + * - Serving Non-Maskable Interrupt. The Cortex-M3 has a specific + * asynchronous NMI vector and several synchronous fault vectors that can + * be considered belonging to this category. + * - Halted. Implemented as an infinite loop after globally masking all + * the maskable interrupt sources. The ARM state is whatever the processor + * was running when @p chSysHalt() was invoked. + * . + * @section RVCT_ARMCMx_NOTES ARM Cortex-Mx/RVCT port notes + * The ARM Cortex-Mx port is organized as follow: + * - The @p main() function is invoked in thread-privileged mode. + * - Each thread has a private process stack, the system has a single main + * stack where all the interrupts and exceptions are processed. + * - The threads are started in thread-privileged mode. + * - Interrupt nesting and the other advanced core/NVIC features are supported. + * - When using an STM32 one of the following macros must be defined on the + * compiler command line or in a file named board.h: + * - @p STM32F10X_LD + * - @p STM32F10X_LD_VL + * - @p STM32F10X_MD + * - @p STM32F10X_MD_VL + * - @p STM32F10X_HD + * - @p STM32F10X_XL + * - @p STM32F10X_CL + * . + * This is required in order to include a vectors table with the correct + * length for the STM32 model, see the file + * ./os/ports/RVCT/ARMCMx/STM32/vectors.s. + * - The Cortex-Mx port is perfectly generic, support for more devices can be + * easily added by adding a subdirectory under ./os/ports/RVCT/ARMCMx + * and giving it the name of the new device, then copy the files from another + * device into the new directory and customize them for the new device. + * . + * @ingroup rvct + */ + +/** + * @defgroup RVCT_ARMCMx_CONF Configuration Options + * @details ARM Cortex-Mx Configuration Options. The ARMCMx port allows some + * architecture-specific configurations settings that can be overridden + * by redefining them in @p chconf.h. Usually there is no need to change + * the default values. + * - @p INT_REQUIRED_STACK, this value represent the amount of stack space used + * by an interrupt handler between the @p extctx and @p intctx + * structures. + * - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE + * thread. Usually there is no need to change this value unless inserting + * code in the IDLE thread using the @p IDLE_LOOP_HOOK hook macro. + * - @p CORTEX_BASEPRI_KERNEL, this is the @p BASEPRI value for the kernel lock + * code. Code running at higher priority levels must not invoke any OS API. + * This setting is specific to the ARMv7-M architecture. + * - @p CORTEX_PRIORITY_SYSTICK, priority of the SYSTICK handler. + * - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler. + * - @p CORTEX_PRIORITY_PENDSV, priority of the PENDSV handler. + * - @p CORTEX_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the + * @p wfi instruction from within the idle loop. This option is + * defaulted to FALSE because it can create problems with some debuggers. + * Setting this option to TRUE reduces the system power requirements. + * . + * @ingroup RVCT_ARMCMx + */ + +/** + * @defgroup RVCT_ARMCMx_CORE Core Port Implementation + * @details ARM Cortex-Mx specific port code, structures and macros. + * + * @ingroup RVCT_ARMCMx + */ + +/** + * @defgroup RVCT_ARMCMx_V6M_CORE ARMv6-M Specific Implementation + * @details ARMv6-M specific port code, structures and macros. + * + * @ingroup RVCT_ARMCMx_CORE + */ + +/** + * @defgroup RVCT_ARMCMx_V7M_CORE ARMv7-M Specific Implementation + * @details ARMv7-M specific port code, structures and macros. + * + * @ingroup RVCT_ARMCMx_CORE + */ + +/** + * @defgroup RVCT_ARMCMx_STARTUP Startup Support + * @details ChibiOS/RT provides its own generic startup file for the ARM + * Cortex-Mx port. + * Of course it is not mandatory to use it but care should be taken about the + * startup phase details. + * + * @section RVCT_ARMCMx_STARTUP_1 Startup Process + * The startup process, as implemented, is the following: + * -# Interrupts are masked globally. + * -# The two stacks are initialized by assigning them the sizes defined in the + * linker script (usually named @p ch.icf). + * -# The CPU state is switched to Privileged and the PSP stack is used. + * -# An early initialization routine @p __early_init() is invoked, if the + * symbol is not defined then an empty default routine is executed + * (weak symbol). + * -# Control is passed to the C runtime entry point @p __cmain that performs + * the required initializations before invoking the @p main() function. + * . + * @ingroup RVCT_ARMCMx + */ + +/** + * @defgroup RVCT_ARMCMx_NVIC NVIC Support + * @details ARM Cortex-Mx NVIC support. + * + * @ingroup RVCT_ARMCMx + */ + +/** + * @defgroup RVCT_ARMCMx_SPECIFIC Specific Implementations + * @details Platform-specific port code. + * + * @ingroup RVCT_ARMCMx + */ diff --git a/os/ports/ports.dox b/os/ports/ports.dox index 30d732504..8168fdbce 100644 --- a/os/ports/ports.dox +++ b/os/ports/ports.dox @@ -37,6 +37,13 @@ * @ingroup ports */ +/** + * @defgroup rvct RVCT Ports + * Ports for the RVCT compiler. + * + * @ingroup ports + */ + /** * @defgroup cosmic Cosmic Compiler Ports * Ports for the Compiler compiler. -- cgit v1.2.3