From ffc9dd5b3914fa24e149cf95cd34033feb33b5a3 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Fri, 13 Nov 2015 15:53:58 +0000 Subject: Extra checks. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8484 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/STM32L4xx/hal_lld.h | 57 ++++++++++++++++++++++++++++------ 1 file changed, 47 insertions(+), 10 deletions(-) (limited to 'os/hal') diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.h b/os/hal/ports/STM32/STM32L4xx/hal_lld.h index ff7bb614f..9c9bfc361 100644 --- a/os/hal/ports/STM32/STM32L4xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.h @@ -1758,7 +1758,7 @@ #endif /** - * @brief USART1 frequency. + * @brief USART1 clock frequency. */ #if (STM32_USART1SEL == STM32_USART1SEL_PCLK2) || defined(__DOXYGEN) #define STM32_USART1CLK STM32_PCLK2 @@ -1773,7 +1773,7 @@ #endif /** - * @brief USART2 frequency. + * @brief USART2 clock frequency. */ #if (STM32_USART2SEL == STM32_USART2SEL_PCLK1) || defined(__DOXYGEN) #define STM32_USART2CLK STM32_PCLK1 @@ -1788,7 +1788,7 @@ #endif /** - * @brief USART3 frequency. + * @brief USART3 clock frequency. */ #if (STM32_USART3SEL == STM32_USART3SEL_PCLK1) || defined(__DOXYGEN) #define STM32_USART3CLK STM32_PCLK1 @@ -1803,7 +1803,7 @@ #endif /** - * @brief UART4 frequency. + * @brief UART4 clock frequency. */ #if (STM32_UART4SEL == STM32_UART4SEL_PCLK1) || defined(__DOXYGEN) #define STM32_UART4CLK STM32_PCLK1 @@ -1818,7 +1818,7 @@ #endif /** - * @brief UART5 frequency. + * @brief UART5 clock frequency. */ #if (STM32_UART5SEL == STM32_UART5SEL_PCLK1) || defined(__DOXYGEN) #define STM32_UART5CLK STM32_PCLK1 @@ -1833,7 +1833,7 @@ #endif /** - * @brief I2C1 frequency. + * @brief I2C1 clock frequency. */ #if (STM32_I2C1SEL == STM32_I2C1SEL_PCLK1) || defined(__DOXYGEN) #define STM32_I2C1CLK STM32_PCLK1 @@ -1846,7 +1846,7 @@ #endif /** - * @brief I2C2 frequency. + * @brief I2C2 clock frequency. */ #if (STM32_I2C2SEL == STM32_I2C2SEL_PCLK1) || defined(__DOXYGEN) #define STM32_I2C2CLK STM32_PCLK1 @@ -1859,7 +1859,7 @@ #endif /** - * @brief I2C3 frequency. + * @brief I2C3 clock frequency. */ #if (STM32_I2C3SEL == STM32_I2C3SEL_PCLK1) || defined(__DOXYGEN) #define STM32_I2C3CLK STM32_PCLK1 @@ -1872,7 +1872,7 @@ #endif /** - * @brief LPTIM1 frequency. + * @brief LPTIM1 clock frequency. */ #if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PCLK1) || defined(__DOXYGEN) #define STM32_LPTIM1CLK STM32_PCLK1 @@ -1887,7 +1887,7 @@ #endif /** - * @brief LPTIM2 frequency. + * @brief LPTIM2 clock frequency. */ #if (STM32_LPTIM2SEL == STM32_LPTIM2SEL_PCLK1) || defined(__DOXYGEN) #define STM32_LPTIM2CLK STM32_PCLK1 @@ -1916,6 +1916,43 @@ #error "invalid source selected for 48CLK clock" #endif +/** + * @brief ADC clock frequency. + */ +#if (STM32_ADCSEL == STM32_ADCSEL_NOCLK) || defined(__DOXYGEN) +#define STM32_ADCCLK 0 +#elif STM32_ADCSEL == STM32_ADCSEL_PLLSAI1 +#define STM32_ADCCLK STM32_PLLSAI1_R_CLKOUT +#elif STM32_ADCSEL == STM32_ADCSEL_PLLSAI2 +#define STM32_ADCCLK STM32_PLLSAI2_R_CLKOUT +#elif STM32_ADCSEL == STM32_ADCSEL_SYSCLK +#define STM32_ADCCLK STM32_SYSCLK +#else +#error "invalid source selected for ADC clock" +#endif + +/** + * @brief SWPMI1 clock frequency. + */ +#if (STM32_SWPMI1SEL == STM32_SWPMI1SEL_PCLK1) || defined(__DOXYGEN) +#define STM32_SWPMI1CLK STM32_PCLK1 +#elif STM32_SWPMI1SEL == STM32_SWPMI1SEL_HSI16 +#define STM32_SWPMI1CLK STM32_HSI16CLK +#else +#error "invalid source selected for SWPMI1 clock" +#endif + +/** + * @brief DFSDM clock frequency. + */ +#if (STM32_DFSDMSEL == STM32_DFSDMSEL_PCLK1) || defined(__DOXYGEN) +#define STM32_SWPMI1CLK STM32_PCLK1 +#elif STM32_DFSDMSEL == STM32_DFSDMSEL_SYSCLK +#define STM32_SWPMI1CLK STM32_SYSCLK +#else +#error "invalid source selected for DFSDM clock" +#endif + /** * @brief SDMMC frequency. */ -- cgit v1.2.3