From b0b6214a6253eedb438e003dcfd408d52ed0a6c4 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 31 Mar 2013 10:37:06 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5522 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/I2Cv2/i2c_lld.c | 127 ++++++++++++++--- os/hal/platforms/STM32/I2Cv2/i2c_lld.h | 51 ++++--- os/hal/platforms/STM32F0xx/hal_lld.h | 210 +--------------------------- os/hal/platforms/STM32F0xx/stm32_isr.h | 34 +++-- os/hal/platforms/STM32F0xx/stm32_registry.h | 198 ++++++++++++++++++++++++++ os/hal/platforms/STM32F30x/stm32_isr.h | 13 ++ os/hal/platforms/STM32F37x/stm32_isr.h | 13 ++ 7 files changed, 382 insertions(+), 264 deletions(-) create mode 100644 os/hal/platforms/STM32F0xx/stm32_registry.h (limited to 'os/hal') diff --git a/os/hal/platforms/STM32/I2Cv2/i2c_lld.c b/os/hal/platforms/STM32/I2Cv2/i2c_lld.c index 81cc4d73c..69d35134d 100644 --- a/os/hal/platforms/STM32/I2Cv2/i2c_lld.c +++ b/os/hal/platforms/STM32/I2Cv2/i2c_lld.c @@ -57,12 +57,14 @@ #define I2C_MASTER_TC \ ((uint32_t)(I2C_ISR_BUSY|I2C_ISR_TC)) + #define I2C_ERROR_MASK \ - ((uint32_t)(I2C_ISR_BERR|I2C_ISR_ARLO|I2C_ISR_OVR|I2C_ISR_PECERR| \ - I2C_ISR_TIMEOUT|I2C_ISR_ALERT)) + ((uint32_t)(I2C_ISR_BERR | I2C_ISR_ARLO | I2C_ISR_OVR | I2C_ISR_PECERR | \ + I2C_ISR_TIMEOUT | I2C_ISR_ALERT)) + #define I2C_INT_MASK \ - ((uint32_t)(I2C_ISR_TCR|I2C_ISR_TC|I2C_ISR_STOPF|I2C_ISR_NACKF| \ - I2C_ISR_ADDR|I2C_ISR_RXNE|I2C_ISR_TXIS)) + ((uint32_t)(I2C_ISR_TCR | I2C_ISR_TC | I2C_ISR_STOPF | I2C_ISR_NACKF | \ + I2C_ISR_ADDR | I2C_ISR_RXNE | I2C_ISR_TXIS)) /*===========================================================================*/ /* Driver exported variables. */ @@ -212,6 +214,7 @@ static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp, uint32_t flags) { * @notapi */ static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp, uint32_t flags) { + /* DMA errors handling.*/ #if defined(STM32_I2C_DMA_ERROR_HOOK) if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { @@ -235,10 +238,8 @@ static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint32_t status) { i2cflags_t errors; /* Clears interrupt flags just to be safe.*/ - chSysLockFromIsr(); dmaStreamDisable(i2cp->dmatx); dmaStreamDisable(i2cp->dmarx); - chSysUnlockFromIsr(); errors = I2CD_NO_ERROR; @@ -279,14 +280,14 @@ static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint32_t status) { /*===========================================================================*/ #if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__) +#if defined(STM32_I2C1_GLOBAL_HANDLER) || defined(__DOXYGEN__) /** * @brief I2C1 event interrupt handler. * * @notapi */ -CH_IRQ_HANDLER(I2C1_IRQHandler) { - volatile I2C_TypeDef *dp = I2CD1.i2c; - uint32_t status = dp->ISR; +CH_IRQ_HANDLER(STM32_I2C1_GLOBAL_HANDLER) { + uint32_t status = I2CD1.i2c->ISR; CH_IRQ_PROLOGUE(); @@ -297,17 +298,42 @@ CH_IRQ_HANDLER(I2C1_IRQHandler) { CH_IRQ_EPILOGUE(); } + +#elif defined(STM32_I2C1_EVENT_HANDLER) && defined(STM32_I2C1_ERROR_HANDLER) +CH_IRQ_HANDLER(STM32_I2C1_EVENT_HANDLER) { + uint32_t status = I2CD1.i2c->ISR; + + CH_IRQ_PROLOGUE(); + + i2c_lld_serve_interrupt(&I2CD1, status); + + CH_IRQ_EPILOGUE(); +} + +CH_IRQ_HANDLER(STM32_I2C1_ERROR_HANDLER) { + uint32_t status = I2CD1.i2c->ISR; + + CH_IRQ_PROLOGUE(); + + i2c_lld_serve_error_interrupt(&I2CD1, status); + + CH_IRQ_EPILOGUE(); +} + +#else +#error "I2C1 interrupt handlers not defined" +#endif #endif /* STM32_I2C_USE_I2C1 */ #if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__) +#if defined(STM32_I2C2_GLOBAL_HANDLER) || defined(__DOXYGEN__) /** * @brief I2C2 event interrupt handler. * * @notapi */ -CH_IRQ_HANDLER(I2C2_IRQHandler) { - volatile I2C_TypeDef *dp = I2CD2.i2c; - uint32_t status = dp->ISR; +CH_IRQ_HANDLER(STM32_I2C2_GLOBAL_HANDLER) { + uint32_t status = I2CD2.i2c->ISR; CH_IRQ_PROLOGUE(); @@ -318,6 +344,31 @@ CH_IRQ_HANDLER(I2C2_IRQHandler) { CH_IRQ_EPILOGUE(); } + +#elif defined(STM32_I2C2_EVENT_HANDLER) && defined(STM32_I2C2_ERROR_HANDLER) +CH_IRQ_HANDLER(STM32_I2C2_EVENT_HANDLER) { + uint32_t status = I2CD2.i2c->ISR; + + CH_IRQ_PROLOGUE(); + + i2c_lld_serve_interrupt(&I2CD2, status); + + CH_IRQ_EPILOGUE(); +} + +CH_IRQ_HANDLER(STM32_I2C2_ERROR_HANDLER) { + uint32_t status = I2CD2.i2c->ISR; + + CH_IRQ_PROLOGUE(); + + i2c_lld_serve_error_interrupt(&I2CD2, status); + + CH_IRQ_EPILOGUE(); +} + +#else +#error "I2C2 interrupt handlers not defined" +#endif #endif /* STM32_I2C_USE_I2C2 */ /*===========================================================================*/ @@ -384,8 +435,18 @@ void i2c_lld_start(I2CDriver *i2cp) { (void *)i2cp); chDbgAssert(!b, "i2c_lld_start(), #2", "stream already allocated"); rccEnableI2C1(FALSE); - nvicEnableVector(I2C1_IRQn, - CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); + +#if defined(STM32_I2C1_GLOBAL_NUMBER) || defined(__DOXYGEN__) + nvicEnableVector(STM32_I2C1_GLOBAL_NUMBER, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); +#elif defined(STM32_I2C1_EVENT_NUMBER) && defined(STM32_I2C1_ERROR_NUMBER) + nvicEnableVector(STM32_I2C1_EVENT_NUMBER, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); + nvicEnableVector(STM32_I2C1_ERROR_NUMBER, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); +#else +#error "I2C1 interrupt numbers not defined" +#endif i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY); @@ -408,8 +469,18 @@ void i2c_lld_start(I2CDriver *i2cp) { (void *)i2cp); chDbgAssert(!b, "i2c_lld_start(), #4", "stream already allocated"); rccEnableI2C2(FALSE); - nvicEnableVector(I2C2_IRQn, - CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); + +#if defined(STM32_I2C2_GLOBAL_NUMBER) || defined(__DOXYGEN__) + nvicEnableVector(STM32_I2C2_GLOBAL_NUMBER, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); +#elif defined(STM32_I2C2_EVENT_NUMBER) && defined(STM32_I2C2_ERROR_NUMBER) + nvicEnableVector(STM32_I2C2_EVENT_NUMBER, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); + nvicEnableVector(STM32_I2C2_ERROR_NUMBER, + CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); +#else +#error "I2C2 interrupt numbers not defined" +#endif i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY); @@ -458,14 +529,30 @@ void i2c_lld_stop(I2CDriver *i2cp) { #if STM32_I2C_USE_I2C1 if (&I2CD1 == i2cp) { - nvicDisableVector(I2C1_IRQn); +#if defined(STM32_I2C1_GLOBAL_NUMBER) || defined(__DOXYGEN__) + nvicDisableVector(STM32_I2C1_GLOBAL_NUMBER); +#elif defined(STM32_I2C1_EVENT_NUMBER) && defined(STM32_I2C1_ERROR_NUMBER) + nvicDisableVector(STM32_I2C1_EVENT_NUMBER); + nvicDisableVector(STM32_I2C1_ERROR_NUMBER); +#else +#error "I2C1 interrupt numbers not defined" +#endif + rccDisableI2C1(FALSE); } #endif #if STM32_I2C_USE_I2C2 if (&I2CD2 == i2cp) { - nvicDisableVector(I2C2_IRQn); +#if defined(STM32_I2C2_GLOBAL_NUMBER) || defined(__DOXYGEN__) + nvicDisableVector(STM32_I2C2_GLOBAL_NUMBER); +#elif defined(STM32_I2C2_EVENT_NUMBER) && defined(STM32_I2C2_ERROR_NUMBER) + nvicDisableVector(STM32_I2C2_EVENT_NUMBER); + nvicDisableVector(STM32_I2C2_ERROR_NUMBER); +#else +#error "I2C2 interrupt numbers not defined" +#endif + rccDisableI2C2(FALSE); } #endif @@ -502,9 +589,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, VirtualTimer vt; uint32_t addr_cr2 = addr & I2C_CR2_SADD; -#if defined(STM32F0XX_I2C) chDbgCheck((rxbytes > 1), "i2c_lld_master_receive_timeout"); -#endif /* Global timeout for the whole operation.*/ if (timeout != TIME_INFINITE) @@ -594,10 +679,8 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, VirtualTimer vt; uint32_t addr_cr2 = addr & I2C_CR2_SADD; -#if defined(STM32F0XX_I2C) chDbgCheck(((rxbytes == 0) || ((rxbytes > 1) && (rxbuf != NULL))), "i2c_lld_master_transmit_timeout"); -#endif /* Global timeout for the whole operation.*/ if (timeout != TIME_INFINITE) diff --git a/os/hal/platforms/STM32/I2Cv2/i2c_lld.h b/os/hal/platforms/STM32/I2Cv2/i2c_lld.h index 96d9950dc..64f2f6fff 100644 --- a/os/hal/platforms/STM32/I2Cv2/i2c_lld.h +++ b/os/hal/platforms/STM32/I2Cv2/i2c_lld.h @@ -49,7 +49,7 @@ * @note The default is @p FALSE. */ #if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__) -#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C1 FALSE #endif /** @@ -58,39 +58,39 @@ * @note The default is @p FALSE. */ #if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__) -#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C2 FALSE #endif /** * @brief I2C1 interrupt priority level setting. */ #if !defined(STM32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 #endif /** * @brief I2C2 interrupt priority level setting. */ #if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 #endif /** -* @brief I2C1 DMA priority (0..3|lowest..highest). -* @note The priority level is used for both the TX and RX DMA streams but -* because of the streams ordering the RX stream has always priority -* over the TX stream. -*/ + * @brief I2C1 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA streams but + * because of the streams ordering the RX stream has always priority + * over the TX stream. + */ #if !defined(STM32_I2C_I2C1_DMA_PRIORITY) || defined(__DOXYGEN__) #define STM32_I2C_I2C1_DMA_PRIORITY 1 #endif /** -* @brief I2C2 DMA priority (0..3|lowest..highest). -* @note The priority level is used for both the TX and RX DMA streams but -* because of the streams ordering the RX stream has always priority -* over the TX stream. -*/ + * @brief I2C2 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA streams but + * because of the streams ordering the RX stream has always priority + * over the TX stream. + */ #if !defined(STM32_I2C_I2C2_DMA_PRIORITY) || defined(__DOXYGEN__) #define STM32_I2C_I2C2_DMA_PRIORITY 1 #endif @@ -101,21 +101,30 @@ * error can only happen because programming errors. */ #if !defined(STM32_I2C_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() #endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ /* Streams for the DMA peripheral.*/ +#if defined(STM32F0XX) #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32F0XX_I2C -/** @} */ +#elif defined(STM32F30X) || defined(STM32F37X) +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ +#else +#error "device unsupported by I2Cv2 driver" +#endif /** @brief error checks */ #if STM32_I2C_USE_I2C1 && !STM32_HAS_I2C1 @@ -188,7 +197,7 @@ typedef enum { */ typedef struct { i2copmode_t op_mode; /**< @brief Specifies the I2C mode. */ - uint32_t clock_timing; /**< @brief Specifies the clock timing + uint32_t clock_timing; /**< @brief Specifies the clock timing. @note See TRM for further info. */ uint32_t cr1; /**< @brief I2C register initialization data. */ diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h index 48a3be448..dcff57a5c 100644 --- a/os/hal/platforms/STM32F0xx/hal_lld.h +++ b/os/hal/platforms/STM32F0xx/hal_lld.h @@ -37,6 +37,7 @@ #define _HAL_LLD_H_ #include "stm32.h" +#include "stm32_registry.h" /*===========================================================================*/ /* Driver constants. */ @@ -208,215 +209,6 @@ #define STM32_ADCSW_PCLK (1 << 8) /**< ADC clock is PCLK/2|4. */ /** @} */ -/*===========================================================================*/ -/* Platform capabilities. */ -/*===========================================================================*/ - -/** - * @name STM32F0xx capabilities - * @{ - */ -/* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) | \ - STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_ADC1_DMA_CHN 0x00000000 - -#define STM32_HAS_ADC2 FALSE -#define STM32_ADC2_DMA_MSK 0x00000000 -#define STM32_ADC2_DMA_CHN 0x00000000 - -#define STM32_HAS_ADC3 FALSE -#define STM32_ADC3_DMA_MSK 0x00000000 -#define STM32_ADC3_DMA_CHN 0x00000000 - -#define STM32_HAS_ADC4 FALSE -#define STM32_ADC4_DMA_MSK 0x00000000 -#define STM32_ADC4_DMA_CHN 0x00000000 - -/* CAN attributes.*/ -#define STM32_HAS_CAN1 FALSE -#define STM32_HAS_CAN2 FALSE -#define STM32_CAN_MAX_FILTERS 0 - -/* DAC attributes.*/ -#define STM32_HAS_DAC TRUE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE - -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_CHANNELS 28 - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE FALSE -#define STM32_HAS_GPIOF TRUE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) -#define STM32_I2C1_RX_DMA_CHN 0x00000000 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_I2C1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_I2C2_RX_DMA_CHN 0x00000000 -#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_I2C2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C3 FALSE -#define STM32_I2C3_RX_DMA_MSK 0 -#define STM32_I2C3_RX_DMA_CHN 0x00000000 -#define STM32_I2C3_TX_DMA_MSK 0 -#define STM32_I2C3_TX_DMA_CHN 0x00000000 - -/* RTC attributes.*/ -#define STM32_HAS_RTC TRUE -#define STM32_RTC_HAS_SUBSECONDS FALSE -#define STM32_RTC_IS_CALENDAR TRUE - -/* SDIO attributes.*/ -#define STM32_HAS_SDIO FALSE - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_SPI1_RX_DMA_CHN 0x00000000 -#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI3 FALSE -#define STM32_SPI3_RX_DMA_MSK 0 -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK 0 -#define STM32_SPI3_TX_DMA_CHN 0x00000000 - -/* TIM attributes.*/ -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 FALSE -#define STM32_HAS_TIM5 FALSE -#define STM32_HAS_TIM6 TRUE -#define STM32_HAS_TIM7 FALSE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 TRUE -#define STM32_HAS_TIM15 TRUE -#define STM32_HAS_TIM16 TRUE -#define STM32_HAS_TIM17 TRUE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) | \ - STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00000000 -#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) | \ - STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART2_RX_DMA_CHN 0x00000000 -#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART3 FALSE -#define STM32_USART3_RX_DMA_MSK 0 -#define STM32_USART3_RX_DMA_CHN 0x00000000 -#define STM32_USART3_TX_DMA_MSK 0 -#define STM32_USART3_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART4 FALSE -#define STM32_UART4_RX_DMA_MSK 0 -#define STM32_UART4_RX_DMA_CHN 0x00000000 -#define STM32_UART4_TX_DMA_MSK 0 -#define STM32_UART4_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART5 FALSE -#define STM32_UART5_RX_DMA_MSK 0 -#define STM32_UART5_RX_DMA_CHN 0x00000000 -#define STM32_UART5_TX_DMA_MSK 0 -#define STM32_UART5_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART6 FALSE -#define STM32_USART6_RX_DMA_MSK 0 -#define STM32_USART6_RX_DMA_CHN 0x00000000 -#define STM32_USART6_TX_DMA_MSK 0 -#define STM32_USART6_TX_DMA_CHN 0x00000000 - -/* USB attributes.*/ -#define STM32_HAS_USB TRUE -#define STM32_HAS_OTG1 FALSE -#define STM32_HAS_OTG2 FALSE -/** @} */ - -/*===========================================================================*/ -/* Platform specific friendly IRQ names. */ -/*===========================================================================*/ - -/** - * @name IRQ VECTOR names - * @{ - */ -#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ -#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line - detect. */ -#define RTC_IRQHandler Vector48 /**< RTC through EXTI Line - Interrupt. */ -#define FLASH_IRQHandler Vector4C /**< Flash. */ -#define RCC_IRQHandler Vector50 /**< RCC. */ -#define EXTI0_1_IRQHandler Vector54 /**< EXTI Line 0..1. */ -#define EXTI2_3_IRQHandler Vector58 /**< EXTI Line 2..3. */ -#define EXTI4_15_IRQHandler Vector5C /**< EXTI Line 4..15. */ -#define TS_IRQHandler Vector60 /**< TS. */ -#define DMA1_Ch1_IRQHandler Vector64 /**< DMA1 Channel 1. */ -#define DMA1_Ch2_3_IRQHandler Vector68 /**< DMA1 Channels 2 and 3. */ -#define DMA1_Ch4_5_IRQHandler Vector6C /**< DMA1 Channels 4 and 5. */ -#define ADC1_COMP_IRQHandler Vector70 /**< ADC1 comparators 1 and 2. */ -#define TIM1_BRK_UP_TRG_COM_IRQHandler Vector74 /**< TIM1 common. */ -#define TIM1_CC_IRQHandler Vector78 /**< TIM1 Capture Compare. */ -#define TIM2_IRQHandler Vector7C /**< TIM2. */ -#define TIM3_IRQHandler Vector80 /**< TIM3. */ -#define TIM6_DAC_IRQHandler Vector84 /**< TIM6 and DAC. */ -#define TIM14_IRQHandler Vector8C /**< TIM14. */ -#define TIM15_IRQHandler Vector90 /**< TIM15. */ -#define TIM16_IRQHandler Vector94 /**< TIM16. */ -#define TIM17_IRQHandler Vector98 /**< TIM17. */ -#define I2C1_IRQHandler Vector9C /**< I2C1. */ -#define I2C2_IRQHandler VectorA0 /**< I2C2. */ -#define SPI1_IRQHandler VectorA4 /**< SPI1. */ -#define SPI2_IRQHandler VectorA8 /**< SPI2. */ -#define USART1_IRQHandler VectorAC /**< USART1. */ -#define USART2_IRQHandler VectorB0 /**< USART2. */ -#define CEC_IRQHandler VectorB8 /**< CEC. */ -/** @} */ - /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32F0xx/stm32_isr.h b/os/hal/platforms/STM32F0xx/stm32_isr.h index 745885f41..52421a4d5 100644 --- a/os/hal/platforms/STM32F0xx/stm32_isr.h +++ b/os/hal/platforms/STM32F0xx/stm32_isr.h @@ -33,27 +33,37 @@ * @name ISR names and numbers remapping * @{ */ + +/* + * I2C units. + */ +#define STM32_I2C1_GLOBAL_HANDLER Vector9C +#define STM32_I2C1_GLOBAL_NUMBER 23 + +#define STM32_I2C2_GLOBAL_HANDLER VectorA0 +#define STM32_I2C2_GLOBAL_NUMBER 24 + /* * TIM units. */ -#define STM32_TIM1_UP_HANDLER TIM1_BRK_UP_TRG_COM_IRQHandler -#define STM32_TIM1_CC_HANDLER TIM1_CC_IRQHandler -#define STM32_TIM2_HANDLER TIM2_IRQHandler -#define STM32_TIM3_HANDLER TIM3_IRQHandler +#define STM32_TIM1_UP_HANDLER Vector74 +#define STM32_TIM1_CC_HANDLER Vector78 +#define STM32_TIM2_HANDLER Vector7C +#define STM32_TIM3_HANDLER Vector80 -#define STM32_TIM1_UP_NUMBER TIM1_BRK_UP_TRG_COM_IRQn -#define STM32_TIM1_CC_NUMBER TIM1_CC_IRQn -#define STM32_TIM2_NUMBER TIM2_IRQn -#define STM32_TIM3_NUMBER TIM3_IRQn +#define STM32_TIM1_UP_NUMBER 13 +#define STM32_TIM1_CC_NUMBER 14 +#define STM32_TIM2_NUMBER 15 +#define STM32_TIM3_NUMBER 16 /* * USART units. */ -#define STM32_USART1_HANDLER USART1_IRQHandler -#define STM32_USART2_HANDLER USART2_IRQHandler +#define STM32_USART1_HANDLER VectorAC +#define STM32_USART2_HANDLER VectorB0 -#define STM32_USART1_NUMBER USART1_IRQn -#define STM32_USART2_NUMBER USART2_IRQn +#define STM32_USART1_NUMBER 27 +#define STM32_USART2_NUMBER 28 /** @} */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32F0xx/stm32_registry.h b/os/hal/platforms/STM32F0xx/stm32_registry.h new file mode 100644 index 000000000..ccef92730 --- /dev/null +++ b/os/hal/platforms/STM32F0xx/stm32_registry.h @@ -0,0 +1,198 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F0xx/stm32_registry.h + * @brief STM32F0xx capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _STM32_REGISTRY_H_ +#define _STM32_REGISTRY_H_ + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name STM32F0xx capabilities + * @{ + */ +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) | \ + STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_ADC1_DMA_CHN 0x00000000 + +#define STM32_HAS_ADC2 FALSE +#define STM32_ADC2_DMA_MSK 0x00000000 +#define STM32_ADC2_DMA_CHN 0x00000000 + +#define STM32_HAS_ADC3 FALSE +#define STM32_ADC3_DMA_MSK 0x00000000 +#define STM32_ADC3_DMA_CHN 0x00000000 + +#define STM32_HAS_ADC4 FALSE +#define STM32_ADC4_DMA_MSK 0x00000000 +#define STM32_ADC4_DMA_CHN 0x00000000 + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 FALSE +#define STM32_HAS_CAN2 FALSE +#define STM32_CAN_MAX_FILTERS 0 + +/* DAC attributes.*/ +#define STM32_HAS_DAC TRUE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 FALSE + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_CHANNELS 28 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE FALSE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_I2C2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_I2C3 FALSE +#define STM32_I2C3_RX_DMA_MSK 0 +#define STM32_I2C3_RX_DMA_CHN 0x00000000 +#define STM32_I2C3_TX_DMA_MSK 0 +#define STM32_I2C3_TX_DMA_CHN 0x00000000 + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS FALSE +#define STM32_RTC_IS_CALENDAR TRUE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 FALSE +#define STM32_SPI3_RX_DMA_MSK 0 +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK 0 +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +/* TIM attributes.*/ +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 FALSE +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 FALSE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 TRUE +#define STM32_HAS_TIM15 TRUE +#define STM32_HAS_TIM16 TRUE +#define STM32_HAS_TIM17 TRUE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) | \ + STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) | \ + STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART1_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART3 FALSE +#define STM32_USART3_RX_DMA_MSK 0 +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK 0 +#define STM32_USART3_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART4 FALSE +#define STM32_UART4_RX_DMA_MSK 0 +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK 0 +#define STM32_UART4_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_UART5 FALSE +#define STM32_UART5_RX_DMA_MSK 0 +#define STM32_UART5_RX_DMA_CHN 0x00000000 +#define STM32_UART5_TX_DMA_MSK 0 +#define STM32_UART5_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_USART6 FALSE +#define STM32_USART6_RX_DMA_MSK 0 +#define STM32_USART6_RX_DMA_CHN 0x00000000 +#define STM32_USART6_TX_DMA_MSK 0 +#define STM32_USART6_TX_DMA_CHN 0x00000000 + +/* USB attributes.*/ +#define STM32_HAS_USB TRUE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +/** @} */ + +#endif /* _STM32_REGISTRY_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32F30x/stm32_isr.h b/os/hal/platforms/STM32F30x/stm32_isr.h index 69f49acec..f3ec2112a 100644 --- a/os/hal/platforms/STM32F30x/stm32_isr.h +++ b/os/hal/platforms/STM32F30x/stm32_isr.h @@ -46,6 +46,19 @@ #define STM32_CAN1_RX1_NUMBER 21 #define STM32_CAN1_SCE_NUMBER 22 +/* + * I2C units. + */ +#define STM32_I2C1_EVENT_HANDLER VectorBC +#define STM32_I2C1_ERROR_HANDLER VectorC0 +#define STM32_I2C1_EVENT_NUMBER 31 +#define STM32_I2C1_ERROR_NUMBER 32 + +#define STM32_I2C2_EVENT_HANDLER VectorC4 +#define STM32_I2C2_ERROR_HANDLER VectorC8 +#define STM32_I2C2_EVENT_NUMBER 33 +#define STM32_I2C2_ERROR_NUMBER 34 + /* * TIM units. */ diff --git a/os/hal/platforms/STM32F37x/stm32_isr.h b/os/hal/platforms/STM32F37x/stm32_isr.h index 21ef387e6..0ef2679bb 100644 --- a/os/hal/platforms/STM32F37x/stm32_isr.h +++ b/os/hal/platforms/STM32F37x/stm32_isr.h @@ -46,6 +46,19 @@ #define STM32_CAN1_RX1_NUMBER 21 #define STM32_CAN1_SCE_NUMBER 22 +/* + * I2C units. + */ +#define STM32_I2C1_EVENT_HANDLER VectorBC +#define STM32_I2C1_ERROR_HANDLER VectorC0 +#define STM32_I2C1_EVENT_NUMBER 31 +#define STM32_I2C1_ERROR_NUMBER 32 + +#define STM32_I2C2_EVENT_HANDLER VectorC4 +#define STM32_I2C2_ERROR_HANDLER VectorC8 +#define STM32_I2C2_EVENT_NUMBER 33 +#define STM32_I2C2_ERROR_NUMBER 34 + /* * TIM units. */ -- cgit v1.2.3