From 45765c3f7671d99cccab31ceea52e300b07d2ecd Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 19 Jun 2011 11:35:07 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3062 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32L1xx/hal_lld.c | 3 +++ os/hal/platforms/STM32L1xx/hal_lld.h | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) (limited to 'os/hal') diff --git a/os/hal/platforms/STM32L1xx/hal_lld.c b/os/hal/platforms/STM32L1xx/hal_lld.c index c9d8a3914..9a8265365 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.c +++ b/os/hal/platforms/STM32L1xx/hal_lld.c @@ -90,6 +90,9 @@ void hal_lld_init(void) { void stm32_clock_init(void) { #if !STM32_NO_INIT + /* PWR clock enable.*/ + RCC->APB1ENR = RCC_APB1ENR_PWREN; + /* Core voltage setup.*/ while ((PWR->CSR & PWR_CSR_VOSF) != 0) ; /* Waits until regulator is stable. */ diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index 5e451409d..37dff216e 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -59,9 +59,9 @@ /* PWR_CR register bits definitions.*/ #define STM32_VOS_MASK (3 << 11) /**< Core voltage mask. */ -#define STM32_VOS_1P2 (1 << 11) /**< Core voltage 1.2 Volts. */ +#define STM32_VOS_1P8 (1 << 11) /**< Core voltage 1.8 Volts. */ #define STM32_VOS_1P5 (2 << 11) /**< Core voltage 1.5 Volts. */ -#define STM32_VOS_1P8 (3 << 11) /**< Core voltage 1.8 Volts. */ +#define STM32_VOS_1P2 (3 << 11) /**< Core voltage 1.2 Volts. */ /* RCC_CR register bits definitions.*/ #define STM32_RTCPRE_MASK (3 << 29) /**< RTCPRE mask. */ -- cgit v1.2.3