From 3f1cbf814e81930d859f43ea9e829e1702ce2f2d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 23 Mar 2012 13:12:56 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4053 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/include/i2s.h | 11 +++++++++++ os/hal/platforms/STM32/i2s_lld.h | 7 ++----- os/hal/platforms/STM32/mac_lld.c | 7 ++++++- os/hal/platforms/STM32/mac_lld.h | 17 ++++++++++++++++ os/hal/platforms/STM32F2xx/stm32_rcc.h | 36 ++++++++++++++++++++++++++++++++++ os/hal/platforms/STM32F4xx/stm32_rcc.h | 36 ++++++++++++++++++++++++++++++++++ 6 files changed, 108 insertions(+), 6 deletions(-) (limited to 'os/hal') diff --git a/os/hal/include/i2s.h b/os/hal/include/i2s.h index 241bb5ec7..d2dedf982 100644 --- a/os/hal/include/i2s.h +++ b/os/hal/include/i2s.h @@ -35,6 +35,17 @@ /* Driver constants. */ /*===========================================================================*/ +/** + * @name I2S modes + * @{ + */ +#define I2S_MODE_SLAVE 0 +#define I2S_MODE_MASTER 1 +#define I2S_MODE_TX 2 +#define I2S_MODE_RX 4 +#define I2S_MODE_TXRX (I2S_MODE_TX | I2S_MODE_RX) +/** @} */ + /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32/i2s_lld.h b/os/hal/platforms/STM32/i2s_lld.h index c56ab8ccb..52f00d2b7 100644 --- a/os/hal/platforms/STM32/i2s_lld.h +++ b/os/hal/platforms/STM32/i2s_lld.h @@ -189,10 +189,7 @@ /** * @brief I2S mode type. */ -typedef enum { - i2s_mode_master = 0, /**< Master mode. */ - i2s_mode_slave = 1 /**< Slave mode. */ -} i2smode_t; +typedef uint32_t i2smode_t; /** * @brief Type of a structure representing an I2S driver. @@ -214,7 +211,7 @@ typedef void (*i2scallback_t)(I2SDriver *i2sp, void *buffer, size_t n); */ typedef struct { /** - * @brief Slave mode selec + * @brief I2S mode selection. */ i2smode_t mode; /** diff --git a/os/hal/platforms/STM32/mac_lld.c b/os/hal/platforms/STM32/mac_lld.c index 849c7a39e..2918bb434 100644 --- a/os/hal/platforms/STM32/mac_lld.c +++ b/os/hal/platforms/STM32/mac_lld.c @@ -308,7 +308,11 @@ void mac_lld_start(MACDriver *macp) { /* Transmitter and receiver enabled. Note that the complete setup of the MAC is performed when the link status is detected.*/ +#if STM32_IP_CHECKSUM_OFFLOAD ETH->MACCR = ETH_MACCR_IPCO | ETH_MACCR_RE | ETH_MACCR_TE; +#else + ETH->MACCR = ETH_MACCR_RE | ETH_MACCR_TE; +#endif /* DMA configuration: Descriptor chains pointers.*/ @@ -457,7 +461,8 @@ void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) { /* Unlocks the descriptor and returns it to the DMA engine.*/ tdp->physdesc->tdes1 = tdp->offset; - tdp->physdesc->tdes0 = STM32_TDES0_IC | STM32_TDES0_LS | STM32_TDES0_FS | + tdp->physdesc->tdes0 = (STM32_IP_CHECKSUM_OFFLOAD << 22) | + STM32_TDES0_IC | STM32_TDES0_LS | STM32_TDES0_FS | STM32_TDES0_TCH | STM32_TDES0_OWN; /* If the DMA engine is stalled then a restart request is issued.*/ diff --git a/os/hal/platforms/STM32/mac_lld.h b/os/hal/platforms/STM32/mac_lld.h index 077ddd2ec..ffb187bba 100644 --- a/os/hal/platforms/STM32/mac_lld.h +++ b/os/hal/platforms/STM32/mac_lld.h @@ -146,6 +146,23 @@ #if !defined(STM32_ETH1_IRQ_PRIORITY) || defined(__DOXYGEN__) #define STM32_ETH1_IRQ_PRIORITY 13 #endif + +/** + * @brief IP checksum offload. + * @details The following modes are available: + * - 0 Function disabled. + * - 1 Only IP header checksum calculation and insertion are enabled. + * - 2 IP header checksum and payload checksum calculation and + * insertion are enabled, but pseudo-header checksum is not + * calculated in hardware. + * - 3 IP Header checksum and payload checksum calculation and + * insertion are enabled, and pseudo-header checksum is + * calculated in hardware. + * . + */ +#if !defined(STM32_IP_CHECKSUM_OFFLOAD) || defined(__DOXYGEN__) +#define STM32_IP_CHECKSUM_OFFLOAD 0 +#endif /** @} */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32F2xx/stm32_rcc.h b/os/hal/platforms/STM32F2xx/stm32_rcc.h index c624279ea..fefbf656b 100644 --- a/os/hal/platforms/STM32F2xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F2xx/stm32_rcc.h @@ -422,6 +422,42 @@ #define rccResetPWRInterface() rccResetAPB1(RCC_APB1ENR_BKPRST) /** @} */ +/** + * @name ETH peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the ETH peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableETH(lp) rccEnableAHB1(RCC_AHB1ENR_ETHMACEN | \ + RCC_AHB1ENR_ETHMACTXEN | \ + RCC_AHB1ENR_ETHMACRXEN, lp) + +/** + * @brief Disables the ETH peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableETH(lp) rccDisableAHB1(RCC_AHB1ENR_ETHMACEN | \ + RCC_AHB1ENR_ETHMACTXEN | \ + RCC_AHB1ENR_ETHMACRXEN, lp) + +/** + * @brief Resets the ETH peripheral. + * + * @api + */ +#define rccResetETH() rccResetAHB1(RCC_AHB1RSTR_ETHMACRST) +/** @} */ + /** * @name I2C peripherals specific RCC operations * @{ diff --git a/os/hal/platforms/STM32F4xx/stm32_rcc.h b/os/hal/platforms/STM32F4xx/stm32_rcc.h index c7f5c8a51..f459c192a 100644 --- a/os/hal/platforms/STM32F4xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F4xx/stm32_rcc.h @@ -422,6 +422,42 @@ #define rccResetPWRInterface() rccResetAPB1(RCC_APB1ENR_BKPRST) /** @} */ +/** + * @name ETH peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the ETH peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableETH(lp) rccEnableAHB1(RCC_AHB1ENR_ETHMACEN | \ + RCC_AHB1ENR_ETHMACTXEN | \ + RCC_AHB1ENR_ETHMACRXEN, lp) + +/** + * @brief Disables the ETH peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableETH(lp) rccDisableAHB1(RCC_AHB1ENR_ETHMACEN | \ + RCC_AHB1ENR_ETHMACTXEN | \ + RCC_AHB1ENR_ETHMACRXEN, lp) + +/** + * @brief Resets the ETH peripheral. + * + * @api + */ +#define rccResetETH() rccResetAHB1(RCC_AHB1RSTR_ETHMACRST) +/** @} */ + /** * @name I2C peripherals specific RCC operations * @{ -- cgit v1.2.3